Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a transistor structure; a plurality of first metal lines over the transistor structure; and a plurality of first vias respectively formed on selected first metal lines among the plurality of first metal lines; a second via formed on a first active via among the plurality of first vias; and a second metal line on the second via, where the first metal line is arranged in a first direction and extends in a second direction intersecting the first direction, and the second metal line extends in the first direction, where the plurality of first via includes at least one dummy via that is not connected to any metal line above it.

Description

Technical Field

[0001] Apparatus and methods consistent with example embodiments of the present disclosure relate to an interconnect structure including an active top via and a dummy top via. Background Art

[0002] The performance of a semiconductor device may be affected by how interconnect structures are formed in the semiconductor device. The interconnect structures may include back-end-of-line (BEOL) structures, such as metal lines and vias, which connect front-end-of-line (FEOL) structures to voltage sources or other circuit elements through middle-end (MOL) structures. The FEOL structures may include a channel structure, source / drain regions, and gate structures of a transistor, and the MOL structures may include contact plugs formed on the source / drain regions and the gate structures, respectively.

[0003] As semiconductor devices are developed to have high device density and performance, the design and formation of interconnect structures including metal lines and vias have become more difficult and complex, while semiconductor devices require improved resistance and capacitance (RC) characteristics.

[0004] The information disclosed in this background technology section is known to the inventors before implementing the embodiments of the present application, or is technical information acquired during the implementation of the embodiments described herein. Therefore, it may contain information that does not constitute prior art known to the public. Summary of the invention

[0005] The present disclosure provides example implementations of interconnect structures for semiconductor devices or integrated circuits.

[0006] According to one or more embodiments, a semiconductor device is provided, which may include: a transistor structure; a plurality of first metal lines above the transistor structure; and a plurality of first vias, which are respectively formed on selected first metal lines among the plurality of first metal lines; a second via formed on a first active via among the plurality of first vias; and a second metal line on the second via, wherein the first metal lines are arranged in a first direction and extend in a second direction intersecting the first direction, and the second metal line extends in the first direction, wherein the plurality of first vias include at least one dummy via that is not connected to any metal line above it.

[0007] According to one or more embodiments, each of the selected first metal lines and each of the plurality of first vias thereon are formed of ruthenium (Ru) and have no connecting surface, boundary, or interface therebetween.

[0008] According to one or more embodiments, a semiconductor device is provided, which may include: a transistor structure; a first metal wire on the transistor structure; a first via on the first metal wire; a first isolation layer surrounding the first metal wire and the first via; a second via on the first via; a second metal wire on the second via; and a second isolation layer surrounding the second via, wherein the first metal wire and the first via do not have a connecting surface, boundary or interface between them, wherein a diffusion barrier layer is formed between the second via and the second isolation layer, and wherein no diffusion barrier layer is formed between the first via and the first isolation layer.

[0009] According to one or more embodiments, a semiconductor device is provided, which may include: a transistor structure; and a plurality of first metal lines above the transistor structure, the plurality of first metal lines being arranged in a first direction and extending in a second direction intersecting the first direction; a plurality of first vias on selected first metal lines among the plurality of first metal lines; and a plurality of second metal lines above the plurality of first vias, the plurality of second metal lines being arranged in a second direction and extending in the first direction, wherein the plurality of first vias include: a first active via connected to a second metal line among the second metal lines; and a plurality of dummy vias that are not connected to any second metal line among the second metal lines, and wherein the plurality of first vias are arranged at a first pitch in the first direction and at a second pitch in the second direction.

[0010] According to one or more embodiments, a method for manufacturing a semiconductor device is provided. The method may include: forming a front-end process (FEOL) structure and an interconnect structure thereon, wherein forming the interconnect structure includes: forming a plurality of first metal lines; patterning a selected first metal line among the plurality of first metal lines to form a plurality of first vias from the selected first metal line; forming a first isolation layer to surround the first metal line and the plurality of first vias; planarizing or polishing the first isolation layer to expose the plurality of first vias; and forming a plurality of second metal lines and a second via connected to one of the plurality of second metal lines, so that the second via is formed on a first active via among the plurality of first vias, wherein a first via other than the first active via among the plurality of first vias is not connected to any second metal line among the second metal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figures 1A to 1C An interconnect structure for a semiconductor device according to one or more embodiments is shown, the interconnect structure including a plurality of metal lines and vias formed by a damascene process.

[0013] FIG. 2A to FIG. 2C A semiconductor device including an interconnect structure including a via formed by a top via process and a plurality of metal lines according to one or more embodiments is shown.

[0014] Figure 3A and Figure 3B An interconnect structure according to one or more embodiments is shown in which a top via is not properly formed.

[0015] Figure 4A and Figure 4B An interconnect structure is shown in accordance with one or more embodiments wherein overlying metal lines are improperly formed due to CMP recessing.

[0016] FIG. 5A to FIG. 5C A semiconductor device including a hybrid interconnect structure including vias and a plurality of metal lines formed by both a top via process and a damascene process according to one or more embodiments is illustrated.

[0017] Fig. 6A and Figure 6B According to one or more embodiments FIG. 2A to FIG. 2C The interconnect structure shown in FIG. 5A to FIG. 5C Plan view of the top via formation in the interconnect structure shown in FIG.

[0018] 7A to 7C A semiconductor device including a hybrid interconnect structure including vias and a plurality of metal lines formed by both a top via process and a damascene process according to one or more other embodiments is illustrated.

[0019] Figure 8 A flow chart of a method of manufacturing a semiconductor device including a hybrid interconnect structure through both a top via process and a damascene process according to one or more embodiments is shown.

[0020] Fig. 9 is a diagram showing a method including FIG. 5A to FIG. 5C and 7A to 7C Schematic block diagram of an electronic device having at least one of the interconnect structures shown in . DETAILED DESCRIPTION

[0021] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the matters described in a specific example or embodiment are not described in different examples or embodiments, these matters may also be understood to be related to or combined with different examples or embodiments, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described herein may be of different types or forms, as long as the present disclosure can be applied thereto.

[0022] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on," "over," "up," "under," "below," "connected to," or "connected to" another element of the semiconductor device, it may be directly on, over, over, under, under, under, connected to, or coupled to the other element, or intervening elements may be present. In contrast, when an element of a semiconductor device is referred to as being "directly on," "directly over," "directly on," "directly under," "directly under," "directly under," "directly connected to," or "directly coupled to" another element, there are no intervening elements. Like reference numerals refer to like elements throughout the present disclosure.

[0023] For ease of description, spatially relative terms such as "above", "above", "up", "above", "below", "below", "below", "below", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used herein to describe the relationship of one element to another element as shown in the figure. It will be understood that in addition to the orientations described in the drawings, the spatially relative terms are intended to include different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the drawings is flipped, the element described as "below" or "below" another element will be oriented "above" the other element. Therefore, the term "below" can include both above and below. The semiconductor device can be oriented in other ways (rotated 90 degrees or other directions), and the spatially relative descriptors used herein are interpreted accordingly. As another example, when the device or structure including these elements is oriented differently, the elements referred to as "left" elements and "right" elements can be "right" elements and "left" elements. Therefore, in the following description, the "left" element and the "right" element can also be referred to as "first" elements or "second" elements, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms “lower” element and “upper” element may be referred to as a “first” element and a “second” element, respectively, with the two elements distinguished by necessary description.

[0024] It will be understood that although the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0025] As used herein, expressions such as "at least one" when preceding a list of elements modify the entire list of elements but do not modify the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the term "same" or "equal" is used to compare the size of two or more elements, the term may encompass "substantially the same" or "substantially equal" sizes.

[0026] It will also be understood that even if a certain step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0027] Many embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments (and intermediate structures). As such, variations from the illustrated shapes are to be expected, for example as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments should not be interpreted as being limited to the specific shapes of the regions shown herein, but rather include shape deviations, for example, caused by manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0028] For the sake of brevity, conventional elements of semiconductor devices may or may not be described in detail herein or shown in the drawings. For example, when MOL or FEOL structures are not relevant to the concepts of the present disclosure, these structures may not be shown or described in detail.

[0029] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0030] Figures 1A to 1C An interconnect structure for a semiconductor device according to one or more embodiments is shown, the interconnect structure including a plurality of metal lines and vias formed by a damascene process. Figure 1A is a plan view of the interconnection structure, Figure 1B is the interconnect structure along Figure 1A A side cross-sectional view taken along line II' shown in FIG. Figure 1C is the interconnect structure along Figure 1A A side sectional view taken along line II-II' shown in FIG.

[0031] refer to Figures 1A to 1C The interconnect structure 10 may be formed on a base layer 100 , which may be another interconnect structure in a back-end-of-line (BEOL) layer including the interconnect structure 10 , a middle-of-line (MOL) layer, or a front-end-of-line (FEOL) layer.

[0032] The interconnect structure 10 may include a plurality of M1 metal lines M11-M15, vias DV, and a plurality of M2 metal lines M21-M23, respectively surrounded by intermetallic dielectric (IMD) layers 111, 112, and 113. The M1 metal lines may be arranged in the D1 direction and extend in the D2 direction, and the M2 metal lines formed above the M1 metal lines and having vias DV therebetween may be arranged in the D2 direction and extend in the D1 direction. The D1 direction and the D2 direction are each a horizontal direction and intersect each other. The D3 direction is a vertical direction intersecting the D1 direction and the D2 direction. The via DV may connect the M1 metal line M13 to the M2 metal line M22. Note here that the M1 metal lines do not necessarily indicate that these metal lines are formed in the lowest layer of the BEOL layer, and one or more other metal lines and vias may exist below the M1 metal lines on the MOL or FEOL layer 100 to form a semiconductor device.

[0033] The interconnect structure 10 may be formed by a damascene process, in which the IMD layers 111, 112, and 113 are patterned by photolithography / masking / etching operations to form trenches and vias in which the diffusion barrier layer B is stacked, and metals such as copper (Cu), aluminum (Al), tungsten (W), etc. or metal compounds are filled in the trenches and vias having the diffusion barrier layer B thereon to form the M1 metal line and the M2 metal line and the via DV. The diffusion barrier layer B may also be formed to ensure adhesion between the M1 metal line M13, the via DV, and the M2 metal line M22, which are connected to each other for current flow. The IMD layers 111, 112, and 113 may be made of a material such as silicon oxide (SiO 2 The diffusion barrier layer B may be formed of a low-k material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., but is not limited thereto, and isolates the M1 metal line and the M2 metal line and the via DV from each other or from another circuit element. The diffusion barrier layer B may be formed of a metal such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., but is not limited thereto, and prevents atoms of a metal (e.g., Cu) filled in the trenches and holes from migrating into the IMD layers 111, 112, and 113 to degrade the isolation performance of the IMD layers 111, 112, and 113. In addition, the diffusion barrier layer B may facilitate adhesion of the metal to the IMD layers 111, 112, and 113.

[0034] The via DV and the M2 metal line may be formed in the IMD layers 112 and 113 by a corresponding single damascene process, in which case a connection surface, interface, or boundary S1 may exist between the M2 metal line M22 and the via DV. However, when the M2 metal line M22 and the via DV are formed by a dual damascene process, there may be no connection surface, interface, or boundary S1 therebetween because the via DV may be a part of the M2 metal line M22, and the IMD layers 112 and 113 may be a single isolation layer.

[0035] Meanwhile, the interconnect structure 10 may be formed such that the M1 metal line has a predetermined fine pitch P1 that is smaller than a predetermined pitch P2 of the M2 metal line formed above the M1 metal line. Therefore, when the via DV is formed to be connected to the metal line M13 by a single or dual damascene operation, regardless of the IMD layers 111 and 112, there is a risk of misalignment between the via DV and the M1 metal line M12 or M14 adjacent to the M1 metal line M13 due to the fine pitch P1, such as Figure 1B Therefore, a short circuit or bridge between via DV and M1 metal line M12 or M14 may occur.

[0036] Therefore, in order to at least address the risk of short circuit or bridging that may occur in the interconnect structure 10 of the above embodiment, the following embodiment of the interconnect structure is provided.

[0037] FIG. 2A to FIG. 2C A semiconductor device including an interconnect structure including a via formed by a top via process and a plurality of metal lines according to one or more embodiments is shown. Figure 2A is a plan view of the interconnection structure, Figure 2B is the interconnect structure along Figure 2A A side cross-sectional view taken along line II' shown in FIG. Figure 2C is the interconnect structure along Figure 2A A side sectional view taken along line II-II' shown in FIG.

[0038] refer to FIG. 2A to FIG. 2C , the interconnect structure 20 may have Figures 1A to 1C The metal line and via arrangement of the interconnect structure 10 shown in FIG. 1 is the same as that of the metal line and via arrangement including fine metal pitches P1 and P2. In addition, the interconnect structure 20 may also be formed on a base layer 200, which may be another interconnect structure or MOL or FEOL layer 200 in a BEOL layer including the interconnect structure 20, similar to the interconnect structure 10. Therefore, a repeated description thereof may be omitted herein, and instead, different aspects of the interconnect structure 20 may be described below.

[0039] Similar to the interconnect structure 10, the interconnect structure 20 may also include a plurality of M1 metal lines M11-M15, a via TV, and a plurality of M2 metal lines M21-M23, respectively surrounded by the IMD layers 211 and 212. However, while the via DV in the interconnect structure 10 may be formed by a damascene process to connect the M1 metal line M13 with the M2 metal line M22, the corresponding via TV in the interconnect structure 20 may be formed from the M1 metal line M13 by a top via process. Here, the via TV formed on the M1 metal line M13 is a part of the M1 metal line M13 itself. In this document, a via formed by a top via process (such as the via TV of the interconnect structure 20) is referred to as a top via, and a via formed by a damascene process (such as the via DV of the interconnect structure 10) is referred to as a damascene via.

[0040] According to an embodiment, at least the M1 metal line of the interconnect structure 20, except for the top via TV, may be formed of a metal such as ruthenium (Ru), which provides a method for achieving fine pitches (eg, FIG. 2A to FIG. 2C The material properties and chemical properties (grain size, chemical resistance, thermal stability, etc.) required for the metal wire of the pitch P1 shown in FIG. According to another embodiment, molybdenum (Mo) or cobalt (Co) may also be considered as a substitute for Ru for the M1 metal wire. The M2 metal wire may also be formed of the same metal that forms the M1 metal wire, or of a different metal wire such as Cu, Al, W, etc.

[0041] A top via is introduced to reduce the contact resistance and capacitance existing between a metal line and a via formed thereon by a damascene process (which at least adversely affects the connection performance of a semiconductor device including the metal line and the via). In order to form a top via, a metal structure (e.g., Ru) may be first patterned, and the metal structure except for a mask region for via formation may be recessed by, for example, photolithography, fabrication, and etching operations. As a result, the recessed region of the metal structure forms the metal line below, and the mask region forms the via (i.e., the top via). Therefore, unlike a damascene via and a damascene metal line formed by a corresponding single damascene process, the top via and the metal line below may be a single continuum structure having no boundaries, connecting surfaces, or interfaces therebetween. After the metal line and the top via are patterned, an IMD layer may be formed to surround the metal line and the top via. Therefore, the risk of metal atoms diffusing into the IMD layer that occurs in a damascene process may not occur in a top via process, so that there is no need to form a diffusion barrier layer (such as a layer formed in the IMD layer) between the IMD layer and the metal line having the top via thereon. Figures 1A to 1C Therefore, the M1 metal line and the top via TV of the interconnect structure 20 may be formed in this manner, and no diffusion barrier layer may be formed between the IMD layer 211 and each of the M2 metal line and the top via TV.

[0042] Although Figures 1A to 1C The interconnect structure 10 is formed such that the damascene via DV is aligned with the M1 metal line M13 among the M1 metal lines having the fine pitch P1 to connect the M1 metal line M13 with the M2 metal line M22, but the interconnect structure 20 is formed such that the top via TV formed on the M1 metal line M13 is aligned with the M2 metal line M22 among the M2 metal lines having a pitch P2 larger than the fine pitch P1. Therefore, the risk of short circuit or bridge between the top via TV and the M2 metal line M21 or M23 not connected to the top via TV can be reduced. For example, the top via TV connected to the M2 metal line M22 can have a larger margin relative to the adjacent M2 metal lines M21 and M23 due to the pitch P2 (which is larger than the fine pitch P1), as shown in FIG. FIG. 2A to FIG. 2C As shown in FIG. 1 , the damascene via DV connected to the M1 metal line M13 has a shorter margin relative to the adjacent M1 metal lines M12 and M14, as shown in FIG. Figure 1B Therefore, with Figures 1A to 1C Compared with a semiconductor device including the interconnection structure 10 , the interconnection structure 20 may at least enhance the connection performance of the semiconductor device including the interconnection structure 20 .

[0043] However, since there is still a possibility of misalignment between the M2 metal line M22 and the top via TV when the M2 metal line is formed by photolithography / masking / etching / deposition operations, the risk of short circuit or bridge between the top via TV and the M2 metal line M21 or M23 may not be completely removed. In addition, the formation of the top via TV for the interconnect structure 20 presents various challenges, such as via loss and chemical mechanical polishing (CMP) recess, due to the difficulty in fine CMP operation of the IMD layer 211 surrounding the high-density M1 metal line.

[0044] Figure 3A and Figure 3B An interconnect structure according to one or more embodiments is shown in which a top via is not properly formed.

[0045] Respectively Figure 3A and Figure 3B The interconnect structures 20A and 20B shown in FIG. 1 are after forming the M1 metal line including the top via TV and before forming the M2 metal line thereover. FIG. 2A to FIG. 2C Therefore, the same reference numerals used in the above description of the interconnect structure 20 are used to describe the interconnect structures 20A and 20B below.

[0046] In the formation FIG. 2A to FIG. 2CIn the BEOL process of the interconnect structure 20 shown in FIG, after forming the underlying M1 metal lines M11-M15 including the top vias TV, an IMD layer 211 may be formed to surround the M1 metal lines including the top vias TV, and then a CMP operation may be performed to expose the top vias TV for connection with the overlying M2 metal lines M22. However, since the number of top vias TV formed on the underlying M1 metal lines in the interconnect structure 20 is too small, for example, FIG. 2A to FIG. 2C Only one is shown in FIG. 1 , so it may be very difficult to detect the top via TV for subsequent CMP operations. Therefore, the top via TV on the M1 metal line M13 may be over-CMPed, resulting in irregular via loss phenomena, such as Figure 3A In other cases, even when the top via TV is detected early and the CMP operation is stopped in time to expose the top via TV, due to the low-k dielectric material (e.g., SiO 2 ) and the metal of the top via TV (e.g., Ru), the IMD layer 311 may also suffer from CMP recessing, such as Figure 3B When CMP recess occurs, the IMD layer 311 may be overetched outward from the top via TV.

[0047] As a result of the irregular via loss, the height of the plurality of top vias (if any) including the top via TV may vary, and therefore, a subsequent operation of forming an overlying M2 metal line on the top via may become unstable. As a result of CMP recessing, the overlying metal line height may vary, or an unCMP phenomenon may subsequently occur.

[0048] Figure 4A and Figure 4B An interconnect structure is shown in accordance with one or more embodiments wherein overlying metal lines are improperly formed due to CMP recessing.

[0049] Figure 4A and Figure 4B The interconnect structures 20B-1 and 20B-2 shown in FIG. 1 and 2 are M2 metal lines formed on the Figure 3B After the interconnect structure 20B FIG. 2A to FIG. 2B Therefore, the same reference numerals used in the description of interconnect structures 20 and 20B are used to describe interconnect structures 20B-1 and 20B-2 below.

[0050] refer to Figure 4AWhen CMP recess occurs, the overlying M2 metal lines M21, M22, and M23 surrounded by the IMD layer 312 may have different heights, thereby making at least the estimation of metal resistance very difficult when manufacturing a semiconductor device including the interconnect structure 20B-1. Figure 4B , the non-CMP phenomenon caused by the CMP recess may cause a possible short circuit risk between the overlying M2 metal lines M21, M22, and M23 surrounded by the IMD layer 312. Therefore, when a semiconductor device is manufactured to include the interconnect structure 20B-1 or 20B-2, the connection performance of the semiconductor device may be deteriorated.

[0051] The embodiments presented below address the above-mentioned risks of over-CMP and CMP recess as well as shorts or bridges between metal lines and vias.

[0052] FIG. 5A to FIG. 5C A semiconductor device including a hybrid interconnect structure including vias and a plurality of metal lines formed by both a top via process and a damascene process according to one or more embodiments is illustrated. Figure 5A is a plan view of the interconnection structure, Figure 5B is the interconnect structure along Figure 5A A side cross-sectional view taken along line II' shown in FIG. Figure 5C is the interconnect structure along Figure 5A A side sectional view taken along line II-II' shown in FIG.

[0053] refer to FIG. 5A to FIG. 5C , the interconnect structure 50 may have FIG. 2A to FIG. 2C The metal line arrangement of the interconnect structure 20 shown in FIG. 5 includes the same metal line arrangement including metal pitches P1 and P2. In addition, the interconnect structure 50 may also be formed on a base layer 500, which may be another interconnect structure or a MOL or FEOL layer in a BEOL layer including the interconnect structure 50. Therefore, a repeated description thereof may be omitted herein, and instead, different aspects of the interconnect structure 50 may be described below.

[0054] Similar to interconnect structure 20 , interconnect structure 50 may also include a plurality of M1 metal lines M11-M15 and M2 metal lines M21-M23 . In addition, interconnect structure 50 may include a top via ATV formed from M1 metal line M13 to connect to M2 metal line M22 , as in interconnect structure 20 .

[0055] However, the interconnect structure 50 may include additional top vias dV formed on the M1 metal lines M11-M15. These additional top vias dV are dummy top vias that are not connected to any M2 metal lines above them (including M2 metal lines M21-M23), while the top vias ATV are active top vias connected to the M2 metal line M22. Instead of being connected to any of the M2 metal lines, the dummy top vias dV may be formed in the interconnect structure 20 to facilitate the CMP operation to expose the top vias ATV and dV. For example, the dummy top vias dV may enable easy and rapid detection of active top vias TV and dummy top vias dV by increasing the density of top vias in a unit area (e.g., the area of ​​the interconnect structure 50). The dummy top vias dV may also enable the CMP operation to have better planarity and uniformity, such as Fig. 6A and Figure 6B For these purposes, top vias including active top vias ATV and dummy top vias dV may be formed in the interconnect structure 50 at predetermined pitches P3 and P4 in the D1 direction and the D2 direction, respectively. In addition, the dummy top vias dV may be formed at the same level to facilitate CMP operations. For example, the top surfaces of the dummy top vias dV may be at the same level in the D3 direction.

[0056] Fig. 6A and Figure 6B According to one or more embodiments FIG. 2A to FIG. 2C The interconnect structure 20 and FIG. 5A to FIG. 5C A plan view of the top via formation in the interconnect structure 50.

[0057] In order to obtain FIG. 2A to FIG. 2C In the BEOL process of the interconnect structure 20, the M1 metal lines M11-M15 may be formed first, and the top via TV may be formed on the M1 metal line M13, and then the IMD layer 211 may be formed to surround the M1 metal lines and the top via TV to isolate the M1 metal lines from each other or from another circuit element. Subsequently, the IMD layer 211 may be planarized by a CMP operation to expose the top via TV (e.g., its top surface) for the next operation of forming the M2 metal line M22 on the top via TV.

[0058] refer to Fig. 6A , the interconnect structure 20 may have a very low density of top vias because the top via TV is the only top via included in the interconnect structure 20. Therefore, it may be very difficult to detect the top via TV during the CMP operation, which may result in the following problems: Figure 3A and Figure 3B The via loss or CMP recess.

[0059] In contrast, Figure 6BIt is shown that due to the multiple dummy top vias dV and active top vias ATV included in the interconnect structure 50, the interconnect structure 50 can have a greater density of top vias. In addition, these top vias can be arranged at predetermined pitches P3 and P4. Therefore, during the CMP operation, the detection of the active top vias ATV can be easy and fast, so that the CMP operation can be stopped in time and a planar and uniform IMD layer 511 can be formed, thereby preventing via loss and CMP recess.

[0060] Return to reference FIG. 5A to FIG. 5C , the interconnect structure 50 may further include a damascene via DV formed on the active top via ATV and below the M2 metal line M22 to connect the active top via ATV to the M2 metal line M22. The damascene via DV and the M2 metal line including the M2 metal line M22 may be formed in the IMD layers 512 and 513 by corresponding single damascene processes, and therefore, a diffusion barrier layer B may be stacked between the IMD layer 512 and the damascene via DV and between the IMD layer 513 and each of the M2 metal lines. In addition, there may be a connection surface, boundary, or interface S2 between the M2 metal line M22 and the damascene via DV, although the connection surface, boundary, or interface S2 may not exist when the M2 metal line and the active top via ATV are formed by a dual damascene process. Furthermore, in the interconnect structure 50, the active top via ATV and the dummy top via dV may be formed to have a thickness greater than FIG. 2A to FIG. 2C The top vias TV of the interconnect structure 20 shown in FIG. 5 is of a uniformly smaller height. Therefore, in the via layer VL of the interconnect structure 50, both active top vias ATV and damascene vias DV may be formed.

[0061] The aforementioned structural configuration of the interconnect structure 50 is provided to prevent the undesired connection of the dummy top via dV with the M2 metal lines M21-M23. For example, when the damascene via DV is not formed and all the dummy top vias dV and the active top vias ATV are formed to have the same FIG. 2A to FIG. 2C The dummy top via dV may also be connected to the overlying M2 metal line M22 when the top via TV in the interconnect structure 20 shown in FIG. Therefore, although the active top via ATV is formed to have a smaller height, an additional damascene via DV may be formed in the IMD layer 512 to connect the M22 metal line to the active top via ATV through a damascene process.

[0062] In addition, if FIG. 5A to FIG. 5C Both the active top via ATV and the damascene via DV are formed in the via layer VL of the interconnect structure 50, and Figures 1A to 1C and FIG. 2A to FIG. 2CWhen only one of the damascene vias DV or the top vias shown in the figure is formed in the corresponding via layer of the interconnect structure 10 or 20, an independent plane or surface IS may be formed between the underlying M1 metal line and the overlying M2 metal line. The independent plane or surface IS may be the same as the boundary between the IMD layers 511 and 512, and provide an isolation space for the metal line and the via. In addition, when the dummy top vias dV are formed to have predetermined pitches P3 and P4 in the D1 direction and the D2 direction, respectively, the dummy top vias dV may be formed such that the dummy top vias dV are not formed adjacent to the active top vias ATV. For example, no dummy top vias dV are formed on or from the M1 metal lines M12 and M14 adjacent to the M1 metal line M13 on which the active top vias ATV are formed.

[0063] Therefore, even if the damascene via DV is formed on the M2 metal line M22, sufficient space may be provided between the damascene via DV and the M1 metal lines M12 and M14. Therefore, there may be no risk of short circuit or bridge between the damascene via DV and each of the M1 metal lines M12 and M14, or the risk of short circuit or bridge may be small. In addition, as Figure 5C As shown in , since the height of the active top via ATV is smaller than that of the top via TV of the interconnect structure 20 , the risk of short circuit or bridge between the active top via ATV and each of the metal lines M21 and M23 can be more completely removed or reduced.

[0064] In addition, if Figure 5B When no dummy top via dV is formed adjacent to the active top via ATV as shown in , the damascene via DV can be formed to have a width W2 in the D1 direction that is greater than the width W1 of each of the active top via ATV and the M1 metal line in the D1 direction, and therefore, the damascene process of forming a space in which the damascene via DV is formed can be more easily performed, and the risk of misalignment with the underlying active top via ATV in the D1 direction is reduced. In addition, the active top via ATV and the dummy top via dV can each be formed to have a length L1 in the D2 direction that is greater than the length L2 of the damascene via DV in the D2 direction. Therefore, in a CMP operation, detection of the active top via ATV and the dummy top via dV can be easy and fast, and the risk of misalignment with the overlying damascene via DV in the D2 direction can also be reduced.

[0065] However, the sizes of the active top via ATV and the dummy top via dV are not limited to the above embodiments. According to one or more embodiments, the active top via ATV and the dummy top via dV may have different forms or shapes to have different sizes.

[0066] 7A to 7C A semiconductor device including a hybrid interconnect structure including vias and a plurality of metal lines formed by both a top via process and a damascene process according to one or more other embodiments is illustrated. Fig. 7A is a plan view of the interconnection structure, Figure 7B is the interconnect structure along Fig. 7A A side cross-sectional view taken along line II' shown in FIG. Figure 7C is the interconnect structure along Fig. 7A A side sectional view taken along line II-II' shown in FIG.

[0067] refer to 7A to 7C , the interconnect structure 70 may have FIG. 5A to FIG. 5C The metal line arrangement of the interconnect structure 50 shown in FIG. 7 is the same as the metal line arrangement including the metal pitches P1 and P2. In addition, the interconnect structure 70 may also be formed on a base layer 700, which may be another interconnect structure or a MOL or FEOL layer in a BEOL layer including the interconnect structure 70. Therefore, a repeated description thereof may be omitted herein, and instead, different aspects of the interconnect structure 70 may be described below.

[0068] Similar to FIG. 5A to FIG. 5C The interconnect structure 50 may also include a plurality of M1 metal lines M11-M15 and active top vias ATV and dummy top vias dV formed by a top via process and surrounded by an IMD layer 711. The interconnect structure 70 may also include a plurality of M2 metal lines M21-M23 and a damascene via DV, which are surrounded by IMD layers 713 and 712 and formed by corresponding single damascene processes.

[0069] However, each of the active top via ATV and the dummy top via dV in the interconnect structure 70 may be a line or strip type extending longer in the D2 direction across the M2 metal lines M21-M23. Such a structural configuration of the top vias ATV and dV may be achieved due to the smaller height of the active top via ATV and the formation of a damascene via DV between the active top via ATV and the M2 metal line M22.

[0070] like Figure 7C As shown in , the interconnect structure 70 can more completely avoid the possible misalignment of the damascene via DV with the underlying active top via ATV extending longer in the D2 direction, while providing sufficient space between the active top via ATV and the overlying M2 metal lines M21 and M23. Therefore, the interconnect structure 70 can also avoid the risk of short circuit or bridge between the active top via ATV and the overlying M2 metal lines M21 or M23. In addition, as shown in FIG. Figure 7BAs shown, as in the interconnect structure 70 , sufficient space may be provided between the damascene via DV and the M1 metal lines M12 and M14 , so that the risk of short circuits or bridges therebetween may also be avoided.

[0071] Furthermore, forming top vias ATV and dV with a predetermined pitch P3 in the D1 direction may also enable easy and rapid inspection of these top vias during a CMP operation as well as planar and uniform formation of the IMD layer 711 around the M1 metal lines and top vias ATV and dV.

[0072] In the following, a method of forming a hybrid interconnect structure, such as interconnect structure 50 , is provided.

[0073] Figure 8 A flow chart of a method of manufacturing a semiconductor device including a hybrid interconnect structure through both a top via process and a damascene process according to one or more embodiments is shown.

[0074] In step S10, a plurality of M1 metal lines may be formed in the BEOL layer. The M1 metal lines may be arranged in the D1 direction and extend in the D2 direction horizontally intersecting the D1 direction. The M1 metal lines may be formed of a metal such as Ru, which may enable the formation of M1 metal lines with very fine pitches. The M1 metal lines may be formed by, for example, photolithography, masking, etching and / or deposition operations (such as dry etching, wet etching, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.), but are not limited thereto.

[0075] Here, the M1 metal lines do not necessarily indicate that these metal lines are formed in the lowest layer of the BEOL layer, and there may be one or more other metal lines and vias below the M1 metal lines on the MOL or FEOL layer to form a semiconductor device.

[0076] In step S20, the selected M1 metal line may be patterned to form a plurality of top vias thereon. The top vias may be formed to have predetermined pitches in the D1 direction and the D2 direction, respectively, to facilitate easy and rapid detection of the top vias in a CMP operation in a later step. The top vias may include at least one active top via to be connected to an overlying M2 metal line and one or more dummy top vias not connected to any overlying M2 metal line. The formation of the top vias may be performed, for example, by photolithography, masking, and etching (such as dry etching or wet etching), but is not limited thereto.

[0077] Each top via is itself part of the corresponding M1 metal line below the top via, so unlike metal lines and damascene vias, there is no connecting surface, boundary, or interface between the top via and the underlying M1 metal line.

[0078] In step S30, a first IMD layer may be formed to surround the top via and the underlying M1 metal line to isolate these structural elements from each other or from another circuit element. The first IMD layer may be formed by, for example, depositing silicon oxide (e.g., SiO 2 ) can be performed with, but is not limited to, low-k materials.

[0079] In step S40, a planarization or polishing operation (such as CMP) may be performed on the first IMD layer to expose the top surface of the top via surrounded by the first IMD layer. Due to the dummy top via in addition to the active top via, the density of the top via has increased. In addition, the top via is formed in a uniform pattern (that is, at a predetermined pitch). Therefore, the detection of the top via can become easy and fast to avoid possible via loss and CMP recess phenomenon.

[0080] In step S50, a second IMD layer may be formed on the first IMD layer surrounding the top via and the underlying M1 metal line. The second IMD layer may be performed by depositing a low-k material, such as by PVD, CVD, PECVD, ALD, etc., which may be the same or similar to the low-k material forming the first IMD layer, but is not limited thereto.

[0081] In step S60, a plurality of M2 metal lines and at least one damascene via thereunder may be formed in the second IMD layer to be respectively connected to at least one active top via. When forming the damascene via on the active top via, sufficient space may be provided to avoid or reduce the possible risk of short circuit or bridge between the damascene via and the M1 metal line not connected to the M2 metal line and between the active top via and the M2 metal line not connected to the M1 metal line.

[0082] The formation of the M2 metal lines and damascene vias may be performed by a single damascene process or a dual damascene process.

[0083] Fig. 9 is a diagram showing a method including FIG. 5A to FIG. 5C and 7A to 7C Schematic block diagram of an electronic device having at least one of the interconnect structures 50 and 70 shown in FIG.

[0084] refer to Fig. 9 , the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a memory 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0085] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving an input and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The memory 1400 may be implemented to store user data, output signals, etc. input by the input / output module 1300. The memory 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, etc.

[0086] The buffer RAM module 1500 may temporarily store data used for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0087] although Fig. 9 Although not shown in the figure, the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0088] According to one or more embodiments, at least one component in the electronic device 1000 may include FIG. 5A to FIG. 5C and 7A to 7C At least one of the interconnect structures 50 and 70 shown in FIG.

[0089] The foregoing is a description of exemplary embodiments and should not be construed as limiting the present disclosure. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above-described embodiments without materially departing from the present disclosure.

[0090] This application is based on and claims priority from U.S. Provisional Application No. 63 / 544,341 filed in the U.S. Patent and Trademark Office on October 16, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Transistor structure; one or more first metal lines over the transistor structure; as well as one or more first vias formed on corresponding first metal lines among the one or more first metal lines; forming a second via on a first active via among the one or more first vias; as well as a second metal line on the second via, wherein the one or more first metal lines are arranged in a first direction and extend in a second direction intersecting the first direction, and the second metal line extends in the first direction, and The one or more first vias include at least one dummy via, and the at least one dummy via is not connected to any metal line thereon. 2 . The semiconductor device according to claim 1 , wherein each of the one or more first vias and each of the corresponding first metal lines have no connecting surface, boundary or interface therebetween. 3 . The semiconductor device according to claim 2 , wherein the second metal line and the second via have a connection surface, a boundary or an interface therebetween.

4. The semiconductor device according to claim 3, wherein the first metal line and the first via are formed of at least one of ruthenium (Ru), molybdenum (Mo), and cobalt (Co), and The second metal line and the second via are formed of at least one of copper (Cu), aluminum (Al) and tungsten (W). 5 . The semiconductor device according to claim 2 , wherein the second via and the second metal line have no connection surface, boundary or interface therebetween. 6 . The semiconductor device according to claim 1 , wherein a height of the at least one dummy via in a third direction intersecting the first direction and the second direction is the same as a height of the first active via in the third direction.

7. The semiconductor device according to claim 6, wherein one or more dummy vias including the at least one dummy via are not connected to any metal line thereover, wherein a height of the one or more dummy vias in the third direction is the same as the height of the first active via in the third direction.

8. The semiconductor device according to claim 7, wherein a first metal line among the one or more first metal lines that is adjacent to another first metal line among the one or more first metal lines in the first direction does not have a dummy path under the second metal line, and the first path is formed on the other first metal line. 9 . The semiconductor device according to claim 7 , wherein each of the one or more first vias and each of the corresponding first metal lines have no connecting surface, boundary or interface therebetween.

10. The semiconductor device according to claim 1, wherein a length of the second via in the first direction is greater than a length of the first via in the first direction, and a width of the second via in the second direction is smaller than a width of the first via in the second direction.

11. A semiconductor device comprising: Transistor structure; a first metal line on the transistor structure; a first via on the first metal line; a first isolation layer surrounding the first metal line and the first via; a second passage on the first passage; a second metal line on the second via; and a second insulating layer surrounding the second passage, wherein the first metal line and the first via have no connecting surface, boundary or interface, wherein a diffusion barrier layer is formed between the second via and the second isolation layer, and Wherein a diffusion barrier layer is not formed between the first via and the first isolation layer. 12 . The semiconductor device according to claim 11 , further comprising a third isolation layer surrounding the second metal line.

13. The semiconductor device according to claim 11, further comprising: one or more first metal lines including the first metal lines, the one or more first metal lines being arranged in a first direction and extending in a second direction intersecting the first direction; one or more first vias on corresponding first metal lines among the one or more first metal lines, the one or more first vias including a first active via and a dummy via having the same height; as well as one or more second metal lines, including the second metal line, arranged in the second direction and extending in the first direction, The dummy via is not connected to any of the second metal lines. 14 . The semiconductor device according to claim 11 , wherein the first metal line and the first via are formed of at least one of ruthenium (Ru), molybdenum (Mo), and cobalt (Co).

15. A semiconductor device comprising: Transistor structure; as well as one or more first metal lines over the transistor structure, the one or more first metal lines arranged in a first direction and extending in a second direction intersecting the first direction; one or more first vias on corresponding first metal lines among the one or more first metal lines; as well as one or more second metal lines over the one or more first vias, the one or more second metal lines arranged in the second direction and extending in the first direction, wherein the one or more first pathways include: a first active via connected to a second metal line among the one or more second metal lines; as well as one or more dummy vias not connected to any of the one or more second metal lines, and The one or more first vias are arranged in the first direction at a first pitch. 16 . The semiconductor device according to claim 15 , wherein the one or more dummy vias are of a line or stripe type and extend in the second direction across the one or more second metal lines. 17 . The semiconductor device according to claim 15 , wherein the one or more first vias are arranged in the second direction at a second pitch. 18 . The semiconductor device according to claim 15 , wherein the one or more first vias have the same height in a third direction intersecting the first direction and the second direction.

19. The semiconductor device according to claim 15, further comprising a second via on a second metal line among the one or more second metal lines, The length of the second passage in the first direction is greater than the length of the first passage in the first direction, and the width of the second passage in the second direction is less than the width of the first passage in the second direction.

20. A method of manufacturing a semiconductor device, the method comprising forming a front-end-of-line structure and an interconnect structure connected to the front-end-of-line structure, Wherein forming the interconnect structure comprises: forming one or more first metal lines; patterning a corresponding first metal line among the one or more first metal lines to form one or more first vias from the corresponding first metal line; forming a first isolation layer to surround the one or more first metal lines and the one or more first vias; planarizing or polishing the first isolation layer to expose the one or more first vias; as well as forming one or more second metal lines and a second via connected to one of the one or more second metal lines such that the second via is formed on a first active via among the one or more first vias, Wherein a first via other than the first active via among the one or more first vias is not connected to any second metal line among the second metal lines.

Images