Semiconductor device structure and forming method thereof

Abstract

Semiconductor device structures and methods of forming the same are described. The structure includes a through-silicon via disposed through the dielectric material, the interconnect structure, and the substrate. The through silicon via has a top surface having a first diameter and a portion having a second diameter in the substrate, and the first diameter is substantially greater than the second diameter. The structure also includes an alloy portion surrounding the through silicon via, a barrier layer surrounding the alloy portion, and a liner surrounding the barrier layer. The through-silicon via, the alloy portion, the barrier layer, and the liner together have a funnel-shaped cross-section.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor device structures and methods for forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from repeated reductions in the size of the smallest component, which allows more components to be integrated into a given area. With the recent growth in demand for even smaller electronic devices, the demand for smaller and more creative packaging technologies for semiconductor dies is also growing.

[0003] As semiconductor technology further develops, stacked semiconductor devices (e.g., 3D integrated circuit (3DIC) packages) have emerged as an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, etc. are manufactured on different semiconductor wafers. Two or more semiconductor components can be mounted on top of each other to further reduce the size specifications of the semiconductor device.

[0004] The high level of integration of advanced packaging technology enables the production of semiconductor devices with enhanced functionality and small footprints, which is advantageous for small form factor devices such as mobile phones, tablets, and digital music players. Another advantage is the shortened length of the conductive paths connecting the interoperating parts within the semiconductor device. This improves the electrical performance of the semiconductor device because the shorter wiring of the interconnections between circuits produces faster signal propagation and reduced noise and crosstalk. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor device structure, including: a through silicon via, which is arranged through a dielectric material, an interconnect structure and a substrate, wherein the through silicon via has: a top surface with a first diameter and a portion with a second diameter located in the substrate, and the first diameter is substantially larger than the second diameter; an alloy portion, surrounding the through silicon via; a barrier layer, surrounding the alloy portion; and a liner, surrounding the barrier layer, wherein the through silicon via, the alloy portion, the barrier layer and the liner together have a funnel-shaped cross-section.

[0006] Some other embodiments of the present application provide a semiconductor device structure, including: a through silicon via, which is arranged through a dielectric material, an interconnect structure and a substrate; a guard ring, which surrounds the through silicon via, wherein the guard ring includes: a first closed-loop structure, which has a first inner edge, a first outer edge and a first dimension between the first inner edge and the first outer edge, wherein the first distance is located between two opposite sides of the first inner edge; a second closed-loop structure, which is arranged above the first closed-loop structure, wherein the second closed-loop structure has a second inner edge, a second outer edge and a second dimension between the second inner edge and the second outer edge, wherein the second dimension is substantially smaller than the first dimension, a second distance is located between two opposite sides of the second inner edge, and the second distance is substantially larger than the first distance a third closed-loop structure disposed above the second closed-loop structure, wherein the third closed-loop structure has a third inner edge, a third outer edge, and a third dimension between the third inner edge and the third outer edge, wherein the third dimension is substantially the same as the first dimension, a third distance is located between two opposite sides of the third inner edge, and the third distance is substantially greater than the first distance; and a fourth closed-loop structure disposed above the third closed-loop structure, wherein the fourth closed-loop structure has a fourth inner edge, a fourth outer edge, and a fourth dimension between the fourth inner edge and the fourth outer edge, wherein the fourth dimension is substantially the same as the second dimension, the fourth distance is located between two opposite sides of the fourth inner edge, and the fourth distance is substantially greater than the second distance.

[0007] Some other embodiments of the present application provide a method, comprising: forming a protection ring in an interconnect structure, comprising: depositing a first closed-loop structure, wherein the first closed-loop structure has a first outer edge; depositing a second closed-loop structure above the first closed-loop structure, wherein the second closed-loop structure has a second outer edge laterally located outside the first outer edge; and depositing a third closed-loop structure above the second closed-loop structure, wherein the third closed-loop structure has a third outer edge laterally located outside the second outer edge; forming an opening surrounded by the protection ring in the interconnect structure, wherein the opening includes a bottom portion having a first critical dimension, a middle portion having a second critical dimension, and a top portion having a third critical dimension, wherein the first critical dimension and the third critical dimension are substantially constant, and the second critical dimension varies; and depositing a through-silicon via into the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figures 1A to 1D are cross-sectional side views of various stages in the fabrication of a semiconductor device structure in accordance with some embodiments.

[0010] Figure 2A and Figure 2B is a top view of a semiconductor device structure according to some embodiments.

[0011] FIG. 3A to FIG. 3C are cross-sectional side views of various stages in the fabrication of a semiconductor device structure according to an alternative embodiment.

[0012] FIG. 4A to FIG. 4C are cross-sectional side views of various stages in the fabrication of a semiconductor device structure according to an alternative embodiment.

[0013] Figure 5A and Figure 5B is a cross-sectional side view of a 3DIC package including through silicon vias (TSVs) of a semiconductor device structure according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "above," "on," "top," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] Figures 1A to 1D 1 is a cross-sectional side view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1A As shown in , the semiconductor device structure 100 includes a substrate 102, such as a semiconductor wafer or a semiconductor die. The substrate 102 can be a semiconductor substrate (such as doped or undoped silicon) or an active layer of a semiconductor on insulator (SOI) substrate. The substrate 102 can include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. Active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc., can be formed in and / or on the substrate 102.

[0017] In some embodiments, the substrate 102 has Figure 1A The first region and the second region (not shown) shown in FIG. 1 may be formed with different components in the first region and the second region. For example, a guard ring and a through silicon via (TSV) may be formed in the first region. No active or passive devices are formed in the first region, or at least in the region where the TSV is to be formed. The active and passive devices may be formed in the substrate 102 at Figure 1A Although only one first region is shown for clarity, those skilled in the art will appreciate that multiple such first regions with different configurations may be formed on a typical integrated circuit. For example, in some embodiments, the first region may be dispersed among multiple second regions, while in other embodiments, a single first region or an array of first regions may be formed near the periphery of the second region.

[0018] In some embodiments, Figure 1AAs shown in , the semiconductor device 100 includes an interconnect structure 104 above the substrate 102. The interconnect structure 104 may include metallization components in one or more dielectric layers 106. The metallization components may include metal lines (not shown) distributed in the dielectric layer 106 and through holes (not shown) connecting metal lines at different levels. The metal lines and through holes may be located in the second region for providing power and signals to active and passive devices. The metallization components may include copper, tungsten, cobalt, ruthenium, their alloys, or combinations thereof. In some embodiments, the metal lines and through holes may also include a diffusion barrier layer (not shown). The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the interconnect structure 104 may be formed by one or more single damascene processes, one or more dual damascene processes, or a combination thereof.

[0019] like Figure 1A As shown in FIG. 1 , a guard ring 108 is disposed in the interconnect structure 104 in the first region. The guard ring 108 includes a stack of closed ring structures 108a-108e. Figure 2A is along Figure 1A A top view of the semiconductor device structure 100 is taken along line AA. Figure 2A The dielectric layer 106 is omitted. Figure 1A and Figure 2A As shown in , each closed-loop structure 108a-108e is a frame-like structure. In some embodiments, each closed-loop structure 108a-108e is a ring-shaped structure. Figure 2A As shown in , the closed loop structure 108e is disposed on the closed loop structure 108d. Each closed loop structure 108d, 108e (as well as the closed loop structures 108a-108c) includes an inner edge 108i and an outer edge 108o. In some embodiments, the inner edge 108i and the outer edge 108o each include four sides forming a rectangular shape. In some embodiments, the inner edge 108i and the outer edge 108o each form a circular shape. Each closed loop structure 108d, 108e (as well as the closed loop structures 108a-108c) includes a dimension (W1-W5) from the inner edge 108i to the outer edge 108o along the X direction. The dimensions of the closed loop structures 108a-108e are different. In some embodiments, as Figure 1A and Figure 2AAs shown in , the size W1 of the closed-loop structure 108a is substantially larger than the size W2 of the closed-loop structure 108b located above the corresponding closed-loop structure 108a, the size W3 of the closed-loop structure 108d is substantially smaller than the size W4 of the closed-loop structure 108e located above the corresponding closed-loop structure 108d, and the size W5 of the closed-loop structure 108c is substantially larger than the sizes W1, W2, W3, and W4 of the closed-loop structures 108a, 108b, 108d, and 108e, respectively. In some embodiments, the guard ring 108 includes alternating closed-loop structures 108a and 108b, a closed-loop structure 108c disposed on the topmost closed-loop structure of the alternating closed-loop structures 108a and 108b, and alternating closed-loop structures 108d and 108e disposed on the closed-loop structure 108c. Figure 1A The number of closed-loop structures 108a-108e shown in is merely an example and is not intended to be limiting. In some embodiments, the guard ring 108 includes a plurality of alternating closed-loop structures 108a, 108b and a plurality of alternating closed-loop structures 108d, 108e. A plurality of alternating closed-loop structures 108a, 108b and a plurality of alternating closed-loop structures 108d, 108e are separated by a closed-loop structure 108c. In some embodiments, the size W1 of the closed-loop structure 108a is substantially the same as the size W4 of the closed-loop structure 108e, and the size W2 of the closed-loop structure 108b is substantially the same as the size W3 of the closed-loop structure 108d. In some embodiments, the closed-loop structures 108a, 108c, 108e are formed simultaneously with the metal lines in the second region, and the closed-loop structures 108b, 108d are formed simultaneously with the metal vias in the second region.

[0020] In some embodiments, distance D1 is located between two opposite sides of the inner edge 108i of the closed-loop structure 108a along the X direction (or along the Y direction), distance D2 is located between two opposite sides of the inner edge 108i of the closed-loop structure 108b along the X direction (or along the Y direction), distance D3 is located between two opposite sides of the inner edge 108i of the closed-loop structure 108d along the X direction (or along the Y direction), and distance D4 is located between two opposite sides of the inner edge 108i of the closed-loop structure 108e along the X direction (or along the Y direction). In some embodiments, the closed-loop structures 108a-108e are annular structures, and distances D1, D2, D3, and D4 are the inner diameters of the closed-loop structures 108a, 108b, 108d, and 108e, respectively. In some embodiments, distance D1 is smaller than distance D2, and distance D4 is smaller than distance D3. In some embodiments, in order to enlarge the top portion ( Figure 1D ), the distances D3 and D4 are substantially larger than the distances D2 and D1, respectively.

[0021] In some embodiments, the closed-loop structure 108a is aligned in the Z direction, the closed-loop structure 108b is aligned in the Z direction, the closed-loop structure 108d is aligned in the Z direction, and the closed-loop structure 108e is aligned in the Z direction. In other words, the outer edge 108o and the inner edge 108i of the closed-loop structure 108a are aligned, the outer edge 108o and the inner edge 108i of the closed-loop structure 108b are aligned, the outer edge 108o and the inner edge 108i of the closed-loop structure 108d are aligned, and the outer edge 108o and the inner edge 108i of the closed-loop structure 108e are aligned, as shown in FIG. Figure 1A As shown in . Due to the enlarged distance D3, the closed-loop structure 108d is not aligned with the closed-loop structure 108b, and due to the enlarged distance D4, the closed-loop structure 108e is not aligned with the closed-loop structure 108a. In other words, the closed-loop structure 108a and the closed-loop structure 108e are offset, and the closed-loop structure 108b and the closed-loop structure 108d are offset. In order to provide contact with the closed-loop structure 108b and the closed-loop structure 108e, the size W5 of the closed-loop structure 108c is enlarged. In some embodiments, the size W5 of the closed-loop structure 108c is larger than the sizes W1, W2, W3, and W4 of the closed-loop structures 108a, 108b, 108d, and 108e, respectively.

[0022] A dielectric material 110 is deposited on the interconnect structure 104, and a dielectric layer 112 is deposited on the dielectric material 110. In some embodiments, the dielectric material 110 is undoped silicate glass (USG), and the dielectric layer 112 is a SiC layer. The dielectric material 110 may have a thickness in a range from about 400 nm to about 1000 nm. In some embodiments, in the second region, a conductive feature such as a redistribution layer (RDL) is formed in the dielectric material 110.

[0023] like Figure 1BAs shown in , a resist layer 114 is deposited on a dielectric layer 112, and an opening 116 is formed in the resist layer 114, the dielectric layer 112, the dielectric material 110, the interconnect structure 104, and the substrate 102. In some embodiments, the opening 116 includes a bottom portion 116a, a middle portion 116b, and a top portion 116c. In some embodiments, the bottom portion 116a is defined by the side of the substrate 102 and the side of the dielectric layer 106 in which the closed loop structures 108a-108c are located. The middle portion 116b is defined by the side of the dielectric layer 106 in which the closed loop structures 108d-108e are located, the side of the dielectric material 110, and the side of the dielectric layer 112. The top portion 116c is defined by the side of the resist layer 114. In some embodiments, the bottom portion 116a has a substantially constant critical dimension CD1, the middle portion 116b has a varying critical dimension CD2, and the top portion 116c has a substantially constant critical dimension CD3. In some embodiments, the varying critical dimension CD2 increases in a direction away from the substrate 102, and the maximum critical dimension CD2 may be in a range of 1.15 times the critical dimension CD1 to about 2.5 times the critical dimension CD1. In some embodiments, the substantially constant critical dimension CD3 is substantially the same as the substantially constant critical dimension CD1.

[0024] The opening 116 having a bottom portion 116a, a middle portion 116b, and a top portion 116c can be formed by one or more processes, such as one or more etching processes. By using different etchants (such as SF6, CF4, or O2) and adjusting the plasma bias (such as from about 0V to about 900V), one or more etching processes can be more or less isotropic. Therefore, undercutting under the resist layer 114 may occur, and the opening 116 includes a middle portion 116b with a varying critical dimension CD2. For example, initially, one or more etching processes may be substantially anisotropic, so the opening 116 may have a constant critical dimension. Then, by changing the etchant and / or adjusting the plasma bias (e.g., reducing the plasma bias), one or more etching processes become more isotropic, and undercutting under the resist layer 114 may occur. In some embodiments, first, the top portion 116c of the opening 116 is formed using photolithography and one or more etching processes to expose a portion of the dielectric layer 112. The resist layer 114 may be a single layer of photoresist or a three-layer photoresist. An exemplary three-layer photoresist may include a bottom layer, an intermediate layer disposed above the bottom layer, and a photosensitive top layer disposed above the intermediate layer. The bottom layer may be a bottom anti-reflective coating (BARC) layer, the intermediate layer may be a silicon-containing inorganic polymer providing anti-reflective properties and / or hard mask properties for a photolithography process, and the photosensitive top layer may be a DUV (KrF) resist, an argon fluoride (ArF) resist, an EUV resist, an electron beam (e-beam) resist, or an ion beam resist. The photolithography process and one or more etching processes remove portions of the resist layer 114. Then, another one or more etching processes are implemented to form a middle portion 116b and a bottom portion 116a of the opening 116. The one or more etching processes that form the middle portion 116b and the bottom portion 116a may be selective etching processes that do not substantially affect the resist layer 114. In some embodiments, the one or more etching processes that form the middle portion 116b and the bottom portion 116a first form the bottom portion 116a and the middle portion 116b having the same critical dimension as the bottom portion 116a. Next, changes in process conditions, such as reducing the plasma bias and / or changes in the etchant, are implemented to make the etching process more isotropic. As a result, the critical dimension CD2 of the middle portion 116b is reduced by Figure 1B and Figure 1C In some embodiments, the increased critical dimension CD2 causes the opening 116 to have a funnel shape.

[0025] In some embodiments, the middle portion 116b of the opening 116 may be surrounded by the closed loop structures 108d, 108e. The increased distances D3 and D4 of the closed loop structures 108d, 108e, respectively, help accommodate the varying critical dimension CD2 that increases in the direction away from the substrate 102. The bottom portion 116a of the opening 116 may be surrounded by the closed loop structures 108a, 108b, 108c. Because the critical dimension CD1 is substantially constant, the distances D1 and D2 of the closed loop structures 108a, 108b do not need to be increased. Therefore, the area occupied by the closed loop structure 108a on the substrate 102 will not be expanded, and the number of active devices or passive devices in the second region may not be reduced.

[0026] In some embodiments, the side surface 106a of the dielectric layer 106 defining the bottom portion 116a of the opening 116 has a substantially linear cross-section, such as Figure 1B , and the side 106a and the main surface of the substrate 102 form an angle A. The side 106b of the middle portion 116b of the dielectric layer 106 defining the opening 116 has a substantially linear cross-section, and the side 106b and a plane substantially parallel to the main surface of the substrate 102 form an angle B. Angle A is substantially greater than angle B. In some embodiments, angle A is in a range from about 88 degrees to about 90 degrees, and angle B is in a range from about 80 degrees to about 87 degrees.

[0027] In some embodiments, the side surface 106b and the side surface of the dielectric material 110 exposed to the middle portion 116b of the opening 116 each have a substantially linear cross-section, such as Figure 1B Thus, in some embodiments, the varying critical dimension CD2 may increase at a constant rate in a direction away from the substrate 102. In other words, the relationship between the distance in the Z direction and the varying critical dimension CD2 is linear. In some embodiments, the side 106b and the side of the middle portion 116b of the dielectric material 110 exposed to the opening 116 each have a substantially curved cross-section, such as Figure 1C As shown in . For example, the side 106b and the side of the middle portion 116b of the dielectric material 110 exposed to the opening 116 together have a convex shape. Therefore, in some embodiments, the critical dimension CD2 of the change can increase at an exponential rate in the direction away from the substrate 102. In other words, the relationship between the distance in the Z direction and the critical dimension CD2 of the change is exponential. The shape of the side 106b and the side of the dielectric material 110 can be controlled by one or more etching processes. After forming the opening 116, the resist layer 114 can be removed. The resist layer 114 can be removed by a selective process that does not substantially affect other materials of the semiconductor device structure 100.

[0028] like Figure 1DAs shown in , a liner 118, a barrier layer 120, and a TSV 124 are formed in the opening 116. The liner 118 includes a dielectric material, such as an oxide or a nitride, and may be formed by a conformal process, such as atomic layer deposition (ALD). After the liner 118 is formed in the opening 116 to cover the side exposed to the opening 116, the barrier layer 120 is formed on the liner 118 in the opening 116. The barrier layer 120 includes a metal or a metal nitride, such as Ti, TiN, Ta, TaN, or other suitable materials. The TSV 124 includes a metal, such as copper. In some embodiments, during the annealing process, the barrier layer 120 and the TSV 124 react to form an alloy portion 122, such as Figure 1D and Figure 2B The alloy portion 122 may have a varying thickness, such as Figure 1D For example, due to the annealing process (heating from the top), the thickness of the alloy portion 122 decreases in the direction toward the substrate 102. Figure 2B is along Figure 1A A top view of the semiconductor device structure 100 is taken along line AA. Figure 2B The dielectric layer 106 is omitted. Figure 2B As shown in , when viewed from the top, TSV 124 may have a circular shape, when viewed from the top, alloy portion 122 may be annular, when viewed from the top, barrier layer 120 may be annular, and when viewed from the top, liner 118 may be annular. TSV 124, alloy portion 122, barrier layer 120, and liner 118 may have any suitable shape. In some embodiments, because opening 116 has a funnel shape, TSV 124, alloy portion 122, barrier layer 120, and liner 118 together may have a funnel-shaped cross-section. In some embodiments, TSV 124 has a funnel-shaped cross-section.

[0029] Return to reference Figure 1D In some embodiments, the alloy portion 122 includes a Cu / Ti alloy, and the contact resistance Rc of the CuTi alloy is substantially greater than the Rc of the copper of the TSV 124. Therefore, by increasing the distances D3 and D4 of the closed-loop structures 108d and 108e, respectively, the critical dimension CD2 of the middle portion 116b of the opening 116 is increased. Therefore, the area of ​​the top surface 124t of the TSV 124 is expanded, which in turn reduces the contact resistance Rc. In some embodiments, Rc is reduced by 20% compared to a conventional TSV. In some embodiments, the diameter Dt of the top surface 124t of the TSV 124 is substantially the same as or greater than the diameter Db of the portion of the TSV 124 located in the substrate 102, such as Figure 1D As shown in Figure 1D and Figure 2B As shown in , the top surface 122t of the alloy portion 122 has a width Wt. In some embodiments, the width Wt is about 3% to about 5% of the sum of the width Wt and the diameter Dt. In some embodiments, the top surfaces of the liner 118, the barrier layer 120, the alloy portion 122, and the TSV 124 have a total diameter Dtt, and the total diameter Dtt can be about 1.15 times to about 2.5 times the diameter Db of the portion of the TSV 124 located in the substrate 102.

[0030] Figure 1D The liner 118, barrier layer 120, alloy portion 122 and TSV 124 are shown formed on Figure 1B In some embodiments, the liner 118, the barrier layer 120, the alloy portion 122, and the TSV 124 are formed in the Figure 1C After forming TSV 124, dielectric layer 112 may be removed. In some embodiments, dielectric layer 112 may be removed by a planarization process, such as a chemical mechanical polishing (CMP) process.

[0031] FIG. 3A to FIG. 3C 1 is a cross-sectional side view of various stages of manufacturing a semiconductor device structure 100 according to an alternative embodiment. Figure 3AAs shown in , the guard ring 108 includes closed-loop structures 108a-108e. In some embodiments, the distances D3 and D4 of the closed-loop structures 108d and 108e increase in a direction away from the substrate 102, respectively. In other words, the distance D3 increases in a direction away from the substrate 102, and the distance D4 increases in a direction away from the substrate 102. For example, the closed-loop structure 108d disposed on the closed-loop structure 108c has a first distance D3, and the closed-loop structure 108d disposed on the closed-loop structure 108e (the closed-loop structure 108e is disposed on the closed-loop structure 108d having the first distance D3) has a second distance D3 substantially greater than the first distance D3. Similarly, the closed-loop structure 108e disposed on the closed-loop structure 108d (the closed-loop structure 108d is disposed on the closed-loop structure 108c) has a first distance D4, and the closed-loop structure 108e disposed on the closed-loop structure 108d (the closed-loop structure 108d is disposed on the closed-loop structure 108e having the first distance D4) has a second distance D4 substantially greater than the first distance D4. In some embodiments, the closed-loop structures 108a are aligned in the Z direction, the closed-loop structures 108b are aligned in the Z direction, the closed-loop structures 108d are not aligned in the Z direction, and the closed-loop structures 108e are not aligned in the Z direction. In other words, the outer edge 108o and the inner edge 108i of the closed-loop structure 108a are aligned, the outer edge 108o and the inner edge 108i of the closed-loop structure 108b are aligned, the outer edge 108o and the inner edge 108i of the closed-loop structure 108d are not aligned, and the outer edge 108o and the inner edge 108i of the closed-loop structure 108e are not aligned, as Figure 3A For example, the outer edge 108o of the closed-loop structure 108d expands laterally outward in a direction away from the substrate 102, and the inner edge 108i of the closed-loop structure 108d expands laterally outward in a direction away from the substrate 102. Similarly, the outer edge 108o of the closed-loop structure 108e expands laterally outward in a direction away from the substrate 102, and the inner edge 108i of the closed-loop structure 108e expands laterally outward in a direction away from the substrate 102. In some embodiments, Figure 3A The sizes W3 and W4 of the closed loop structures 108d and 108e shown in FIG. Figure 1A The closed-loop structures 108d and 108e shown in the figures are the same in size W3 and W4.

[0032] like Figure 3B As shown in FIG. 1 , a resist layer 114 is formed on a dielectric layer 112, and an opening 116 is formed in the resist layer 114, the dielectric layer 112, the dielectric material 110, the interconnect structure 104, and the substrate 102. The opening 116 may include a bottom portion 116a, a middle portion 116b, and a top portion 116c. Due to the location of the closed loop structures 108d, 108e, the opening 116 has an increased critical dimension CD2 ( Figure 1B ) does not expose the closed loop structures 108d, 108e. The opening 116 may have Figure 3B The shape shown in Figure 1C The shapes shown in .

[0033] like Figure 3C As shown in FIG. 1 , a liner 118, a barrier layer 120, an alloy portion 122, and a TSV 124 are formed in the opening 116. A diameter Dt of a top surface 124t of the TSV 124 is substantially the same as or larger than a diameter Db of a portion of the TSV 124 located in the substrate 102. With the large top surface 124t of the TSV 124, Rc is reduced.

[0034] FIG. 4A to FIG. 4C 1 is a cross-sectional side view of various stages of manufacturing a semiconductor device structure 100 according to an alternative embodiment. Figure 4A As shown in , the guard ring 108 includes alternating closed loop structures 108a, 108b. There are no closed loop structures 108c-108e in the guard ring 108. In some embodiments, the closed loop structures 108a are aligned in the Z direction, and the closed loop structures 108b are aligned in the Z direction. In other words, the outer edge 108o and the inner edge 108i of the closed loop structure 108a are aligned, and the outer edge 108o and the inner edge 108i of the closed loop structure 108b are aligned. The distance D1 and the distance D2 are substantially constant in the direction away from the substrate 102.

[0035] like Figure 4B As shown in , a resist layer 114 is deposited on a dielectric layer 112, and an opening 150 is formed in the resist layer 114, the dielectric layer 112, the dielectric material 110, the interconnect structure 104, and the substrate 102. In some embodiments, the opening 150 includes a bottom portion 150a, a middle portion 150b, and a top portion 150c. In some embodiments, the bottom portion 150a is defined by the sides of the substrate 102 and the dielectric layer 106. The middle portion 150b is defined by the sides of the dielectric material 110 and the dielectric layer 112. The top portion 150c is defined by the sides of the resist layer 114. In some embodiments, the bottom portion 150a has a substantially constant critical dimension CD4, the middle portion 150b has a varying critical dimension CD5, and the top portion 150c has a substantially constant critical dimension CD6. In some embodiments, the varying critical dimension CD5 increases in a direction away from the substrate 102 and may range from 1.15 times the critical dimension CD1 to about 2.5 times the critical dimension CD1. In some embodiments, the substantially constant critical dimension CD6 is substantially the same as the substantially constant critical dimension CD4.

[0036] In some embodiments, the critical dimension CD5 of the middle portion 150b of the opening 150 is increased, so that the top surface 124t ( Figure 4C ) is enlarged, which in turn reduces Rc. The increased critical dimension CD5 of the middle portion 150b of the opening 150 can cause the opening 150 to have a funnel shape. In some embodiments, the side 110s of the dielectric material 110 defining the middle portion 150b of the opening 150 has a substantially linear cross-section, such as Figure 4B , and the side surface 110s and the bottom surface 110b of the dielectric material 110 form an angle C. Angle C is an acute angle in a range from about 45 degrees to about 87 degrees. In some embodiments, the side surface 110s of the middle portion 150b of the dielectric material 110 defining the opening 150 has a curved cross-section, such as a convex cross-section.

[0037] The opening 150 may be formed by the same process as the opening 116. By adjusting the etchant and / or plasma bias, an undercut in the dielectric material 110 beneath the resist layer 114 may be formed. After the opening 150 is formed, the resist layer 114 is removed.

[0038] like Figure 4C As shown in FIG. 1 , the liner 118, the barrier layer 120, the alloy portion 122, and the TSV 124 are formed in the opening 150. The diameter Dt of the top surface 124t of the TSV 124 is substantially larger than the diameter Db of the portion of the TSV 124 located in the substrate 102. With the large top surface 124t of the TSV 124, Rc is reduced. In some embodiments, because the opening 150 has a funnel shape, the TSV 124, the alloy portion 122, the barrier layer 120, and the liner 118 together can have a funnel-shaped cross-section. In some embodiments, the TSV 124 has a funnel-shaped cross-section.

[0039] Figure 5A and Figure 5B 1 is a cross-sectional side view of a 3DIC package 160 including TSVs 124 of a semiconductor device structure 100 according to some embodiments. Figure 5A As shown in FIG. 1 , 3DIC package 160 is a system on integrated chip (SoIC) with face-to-back (F2B) bonding. 3DIC package 160 includes a first die 162 disposed above a second die 164. TSV 124 is used to electrically connect the first die 162 and the second die 164. TSV 124 is surrounded by guard ring 108. TSV 124 may be Figure 1D , Figure 3C , Figure 4C The TSV 124 shown in FIG. 1 and the guard ring 108 may be Figure 1D , Figure 3C , Figure 4CFor clarity, the protective ring 108 is shown in FIG. Figure 5A The alloy portion 122, the barrier layer 120 and the liner 118 may be omitted.

[0040] like Figure 5B As shown in FIG. 1 , 3DIC package 160 is a SoIC with surface-to-surface (F2F) bonding. 3DIC package 160 includes a first die 166 and a second die 168 disposed adjacent to first die 166 and a third die 170 disposed below first die 166 and second die 168. One or more TSVs 124 are used to electrically connect third die 170 to one or more microbumps 172, which are electrically connected to a package substrate (not shown). TSVs 124 are surrounded by guard ring 108. TSVs 124 may be Figure 1D , Figure 3C , Figure 4C The TSV 124 shown in FIG. 1 and the guard ring 108 may be Figure 1D , Figure 3C , Figure 4C For clarity, the protective ring 108 is shown in FIG. Figure 5B The alloy portion 122, the barrier layer 120 and the liner 118 may be omitted.

[0041] Embodiments of the present disclosure provide a semiconductor device structure 100 including a TSV 124 having a top surface 124t having a diameter Dt substantially the same as or greater than the diameter Db of the portion of the TSV 124 located in the substrate 102. In some embodiments, the closed loop structures 108d, 108e located at the top of the guard ring 108 may be modified so that the distance D3 or D4 between the opposite sides of the inner edge 108i of the closed loop structures 108d, 108e is increased. Some embodiments may achieve advantages. For example, the increased top surface 124t of the TSV 124 reduces contact resistance.

[0042] The embodiment is a semiconductor device structure. The structure includes a through silicon via disposed through a dielectric material, an interconnect structure, and a substrate. The through silicon via has: a top surface having a first diameter and a portion having a second diameter located in the substrate, and the first diameter is substantially greater than the second diameter. The structure also includes an alloy portion surrounding the through silicon via, a barrier layer surrounding the alloy portion, and a liner surrounding the barrier layer. The through silicon via, the alloy portion, the barrier layer, and the liner together have a funnel-shaped cross-section.

[0043] Another embodiment is a semiconductor device structure. The structure includes: a through silicon via, which is arranged through a dielectric material, an interconnect structure and a substrate; and a guard ring, which surrounds the through silicon via. The guard ring includes: a first closed loop structure, which has a first inner edge, a first outer edge and a first dimension between the first inner edge and the first outer edge. The first distance is located between two opposite sides of the first inner edge. The guard ring also includes: a second closed loop structure, which is arranged above the first closed loop structure, and the second closed loop structure has a second inner edge, a second outer edge and a second dimension between the second inner edge and the second outer edge. The second dimension is substantially smaller than the first dimension, the second distance is located between two opposite sides of the second inner edge, and the second distance is substantially greater than the first distance. The guard ring also includes: a third closed loop structure, which is arranged above the second closed loop structure, and the third closed loop structure has a third inner edge, a third outer edge and a third dimension between the third inner edge and the third outer edge. The third dimension is substantially the same as the first dimension, the third distance is located between two opposite sides of the third inner edge, and the third distance is substantially greater than the first distance. The guard ring further includes: a fourth closed loop structure disposed above the third closed loop structure, and the fourth closed loop structure has a fourth inner edge, a fourth outer edge, and a fourth dimension between the fourth inner edge and the fourth outer edge. The fourth dimension is substantially the same as the second dimension, a fourth distance is located between two opposite sides of the fourth inner edge, and the fourth distance is substantially greater than the second distance.

[0044] A further embodiment is a method. The method includes forming a guard ring in an interconnect structure. The formation of the guard ring includes depositing a first closed-loop structure, and the first closed-loop structure has a first outer edge. The formation of the guard ring also includes depositing a second closed-loop structure above the first closed-loop structure, and the second closed-loop structure has a second outer edge laterally located outside the first outer edge. The formation of the guard ring also includes depositing a third closed-loop structure above the second closed-loop structure, and the third closed-loop structure has a third outer edge laterally located outside the second outer edge. The method also includes forming an opening surrounded by the guard ring in the interconnect structure, the opening including a bottom portion having a first critical dimension, a middle portion having a second critical dimension, and a top portion having a third critical dimension. The first critical dimension and the third critical dimension are substantially constant, and the second critical dimension varies. The method also includes depositing a through silicon via into the opening.

[0045] Some embodiments of the present application provide a semiconductor device structure, including: a through silicon via, which is arranged through a dielectric material, an interconnect structure and a substrate, wherein the through silicon via has: a top surface with a first diameter and a portion with a second diameter located in the substrate, and the first diameter is substantially larger than the second diameter; an alloy portion, surrounding the through silicon via; a barrier layer, surrounding the alloy portion; and a liner, surrounding the barrier layer, wherein the through silicon via, the alloy portion, the barrier layer and the liner together have a funnel-shaped cross-section.

[0046] In some embodiments, the through silicon via comprises Cu, the barrier layer comprises Ti, and the alloy portion comprises a Cu / Ti alloy.

[0047] In some embodiments, the alloy portion has a top surface having a first width, and the first width is about 3% to about 5% of a sum of the first width and the first diameter.

[0048] In some embodiments, the liner, the barrier layer, the alloy portion, and a top surface of the through silicon via have a total diameter, and the total diameter is about 1.15 times to about 2.5 times the second diameter.

[0049] In some embodiments, the semiconductor device structure further includes a guard ring surrounding the through silicon via.

[0050] In some embodiments, the guard ring includes a plurality of closed loop structures.

[0051] In some embodiments, the multiple closed-loop structures include: a first closed-loop structure having a first inner edge, a first outer edge, and a first dimension between the first inner edge and the first outer edge; a second closed-loop structure disposed above the first closed-loop structure, wherein the second closed-loop structure has a second inner edge, a second outer edge, and a second dimension between the second inner edge and the second outer edge; and a third closed-loop structure disposed above the second closed-loop structure, wherein the third closed-loop structure has a third inner edge, a third outer edge, and a third dimension between the third inner edge and the third outer edge.

[0052] In some embodiments, the first size and the third size are substantially the same.

[0053] In some embodiments, the second dimension is substantially larger than the first dimension and the third dimension.

[0054] In some embodiments, a first distance between opposite sides of the first inner edge is substantially less than a second distance between opposite sides of the third inner edge.

[0055] In some embodiments, the first size, the second size, and the third size are substantially the same.

[0056] In some embodiments, a first distance between opposite sides of the first inner edge is substantially smaller than a second distance between opposite sides of the second inner edge, and the second distance is substantially smaller than a third distance between opposite sides of the third inner edge.

[0057] Some other embodiments of the present application provide a semiconductor device structure, including: a through silicon via, which is arranged through a dielectric material, an interconnect structure and a substrate; a guard ring, which surrounds the through silicon via, wherein the guard ring includes: a first closed-loop structure, which has a first inner edge, a first outer edge and a first dimension between the first inner edge and the first outer edge, wherein the first distance is located between two opposite sides of the first inner edge; a second closed-loop structure, which is arranged above the first closed-loop structure, wherein the second closed-loop structure has a second inner edge, a second outer edge and a second dimension between the second inner edge and the second outer edge, wherein the second dimension is substantially smaller than the first dimension, a second distance is located between two opposite sides of the second inner edge, and the second distance is substantially larger than the first distance a third closed-loop structure disposed above the second closed-loop structure, wherein the third closed-loop structure has a third inner edge, a third outer edge, and a third dimension between the third inner edge and the third outer edge, wherein the third dimension is substantially the same as the first dimension, a third distance is located between two opposite sides of the third inner edge, and the third distance is substantially greater than the first distance; and a fourth closed-loop structure disposed above the third closed-loop structure, wherein the fourth closed-loop structure has a fourth inner edge, a fourth outer edge, and a fourth dimension between the fourth inner edge and the fourth outer edge, wherein the fourth dimension is substantially the same as the second dimension, the fourth distance is located between two opposite sides of the fourth inner edge, and the fourth distance is substantially greater than the second distance.

[0058] In some embodiments, the semiconductor device structure further includes a fifth closed-loop structure disposed between the second closed-loop structure and the third closed-loop structure.

[0059] In some embodiments, the fifth closed loop structure has a fifth inner edge, a fifth outer edge, and a fifth dimension between the fifth inner edge and the fifth outer edge, wherein the fifth dimension is substantially greater than the first dimension.

[0060] In some embodiments, the semiconductor device structure further includes an alloy portion surrounding the through silicon via.

[0061] In some embodiments, the alloy portion includes a Cu / Ti alloy, and the through silicon via includes Cu.

[0062] Some other embodiments of the present application provide a method, comprising: forming a protection ring in an interconnect structure, comprising: depositing a first closed-loop structure, wherein the first closed-loop structure has a first outer edge; depositing a second closed-loop structure above the first closed-loop structure, wherein the second closed-loop structure has a second outer edge laterally located outside the first outer edge; and depositing a third closed-loop structure above the second closed-loop structure, wherein the third closed-loop structure has a third outer edge laterally located outside the second outer edge; forming an opening surrounded by the protection ring in the interconnect structure, wherein the opening includes a bottom portion having a first critical dimension, a middle portion having a second critical dimension, and a top portion having a third critical dimension, wherein the first critical dimension and the third critical dimension are substantially constant, and the second critical dimension varies; and depositing a through-silicon via into the opening.

[0063] In some embodiments, the method further includes depositing a liner in the opening and depositing a barrier layer on the liner in the opening, wherein the through silicon via is deposited on the barrier layer.

[0064] In some embodiments, the method further includes forming an alloy portion between the barrier layer and the through silicon via.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A through silicon via disposed through the dielectric material, the interconnect structure and the substrate, wherein the through silicon via has: a top surface having a first diameter and a portion located in the substrate having a second diameter, and the first diameter is substantially greater than the second diameter; an alloy portion surrounding the through silicon via; a barrier layer surrounding the alloy portion; and A liner surrounds the barrier layer, wherein the through silicon via, the alloy portion, the barrier layer and the liner together have a funnel-shaped cross-section.

2. The semiconductor device structure according to claim 1, wherein: The through silicon via includes Cu, the barrier layer includes Ti, and the alloy portion includes a Cu / Ti alloy.

3. The semiconductor device structure according to claim 1, wherein: The alloy portion has a top surface having a first width, and the first width is about 3% to about 5% of a sum of the first width and the first diameter.

4. The semiconductor device structure according to claim 1, wherein: The liner, the barrier layer, the alloy portion, and a top surface of the through silicon via have a total diameter, and the total diameter is about 1.15 times to about 2.5 times the second diameter. 5 . The semiconductor device structure according to claim 1 , further comprising a guard ring surrounding the through silicon via.

6. The semiconductor device structure according to claim 5, wherein: The protection ring includes a plurality of closed-loop structures.

7. The semiconductor device structure according to claim 6, wherein: The multiple closed-loop structures include: a first closed loop structure having a first inner edge, a first outer edge, and a first dimension between the first inner edge and the first outer edge; a second closed-loop structure disposed above the first closed-loop structure, wherein the second closed-loop structure has a second inner edge, a second outer edge, and a second dimension between the second inner edge and the second outer edge; and The third closed-loop structure is disposed above the second closed-loop structure, wherein the third closed-loop structure has a third inner edge, a third outer edge, and a third dimension between the third inner edge and the third outer edge.

8. The semiconductor device structure according to claim 7, wherein: The first dimension and the third dimension are substantially the same.

9. A semiconductor device structure, comprising: Through-silicon vias are provided through dielectric materials, interconnect structures, and substrates; A guard ring surrounding the through silicon via, wherein the guard ring comprises: a first closed loop structure having a first inner edge, a first outer edge, and a first dimension between the first inner edge and the first outer edge, wherein the first distance is between two opposing sides of the first inner edge; a second closed loop structure disposed above the first closed loop structure, wherein the second closed loop structure has a second inner edge, a second outer edge, and a second dimension between the second inner edge and the second outer edge, wherein the second dimension is substantially smaller than the first dimension, a second distance is located between two opposite sides of the second inner edge, and the second distance is substantially greater than the first distance; a third closed-loop structure disposed above the second closed-loop structure, wherein the third closed-loop structure has a third inner edge, a third outer edge, and a third dimension between the third inner edge and the third outer edge, wherein the third dimension is substantially the same as the first dimension, a third distance is located between two opposite sides of the third inner edge, and the third distance is substantially greater than the first distance; and A fourth closed-loop structure is arranged above the third closed-loop structure, wherein the fourth closed-loop structure has a fourth inner edge, a fourth outer edge and a fourth dimension between the fourth inner edge and the fourth outer edge, wherein the fourth dimension is substantially the same as the second dimension, the fourth distance is located between two opposite sides of the fourth inner edge, and the fourth distance is substantially greater than the second distance.

10. A method for forming a semiconductor device structure, comprising: Forming a guard ring in an interconnect structure includes: depositing a first closed loop structure, wherein the first closed loop structure has a first outer edge; depositing a second closed-loop structure over the first closed-loop structure, wherein the second closed-loop structure has a second outer edge laterally outside the first outer edge; and depositing a third closed-loop structure over the second closed-loop structure, wherein the third closed-loop structure has a third outer edge laterally located outside the second outer edge; forming an opening in the interconnect structure surrounded by the guard ring, wherein the opening includes a bottom portion having a first critical dimension, a middle portion having a second critical dimension, and a top portion having a third critical dimension, wherein the first critical dimension and the third critical dimension are substantially constant and the second critical dimension varies; and Through silicon vias are deposited into the openings.

Images