An automatic direction sensing level conversion circuit

Abstract

The present invention discloses an automatic direction-sensing level conversion circuit, comprising first and second voltage domain circuits of identical structure. The circuit can automatically input the input signal A of the first voltage domain circuit to the second level conversion module via the first voltage domain circuit driving input module, output a driving signal to the second voltage domain circuit driving output module to control weak drive, and simultaneously control a monostable circuit to generate a corresponding strong drive, outputting a second signal B of the same phase; or similarly, automatically convert the input signal B of the second voltage domain circuit into the same phase as the first signal A. The level conversion circuit of the present invention can automatically sense the direction of signal transmission without requiring additional signals, achieving bidirectional level conversion and simplifying the system structure. The monostable circuit also enables the strong drive output in a short period of time, improving the output drive capability and transmission speed, and disables the strong drive output on the other side via a feedback signal, avoiding the accidental activation of the bidirectional level conversion circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an automatic direction sensing level conversion circuit. Background Art

[0002] In modern integrated circuit design, many different functions are often integrated onto the same chip, creating a complex system-on-chip (SoC). To achieve a good compromise between circuit performance and power consumption, multi-voltage technology is often employed, allowing different functional modules to operate at different voltages to achieve optimal performance and power consumption. However, this multi-voltage design also brings new challenges: how to efficiently and reliably transmit information between two systems with different voltages.

[0003] To transfer information between systems operating at different voltages, a level shifter circuit is necessary to achieve data conversion between circuits with different supply voltages. The function of a level shifter circuit is to convert the signal level of one voltage domain to the signal level of another voltage domain while ensuring signal integrity and timing requirements. Traditional level shifters are mainly divided into two types: unidirectional level shifters and bidirectional level shifters.

[0004] Unidirectional level conversion circuits can only realize signal transmission in a single direction and are usually used in scenarios where the data transmission direction is fixed. However, in practical applications, bidirectional data transmission between two voltage domains is often required, which requires the use of bidirectional level conversion circuits. Existing bidirectional level conversion circuits usually adopt a direction detection mechanism based on control signals, that is, an additional control signal is used to indicate the direction of data transmission. However, this solution has the following problems: 1. Inaccurate transmission direction detection: Since the control signal may have delays or jitter, the direction detection is inaccurate, resulting in data transmission errors. 2. Weak driving capability: Traditional bidirectional level conversion circuits usually adopt a simple transmission gate structure with limited driving capability, which is difficult to meet the needs of high-speed data transmission. 3. High circuit complexity and power consumption: The additional control signal increases the circuit complexity and power consumption, which is not conducive to low-power design.

[0005] To address these issues, researchers have proposed a variety of improved solutions, such as direction detection circuits based on current sensing and those based on delay-locked loops. However, these solutions still suffer from complex circuits, high power consumption, and slow speeds, making them difficult to meet the high-performance, low-power requirements of modern integrated circuits.

[0006] Therefore, there is an urgent need for a new type of bidirectional level conversion circuit that can achieve automatic direction sensing, high driving capability, low power consumption and high-speed data transmission to meet the needs of modern integrated circuit design. Summary of the Invention

[0007] The problem to be solved by the present invention is to provide an automatic direction-sensing level conversion circuit, which can automatically detect the data transmission direction and complete the level conversion without the need for additional control signals, realize accurate bidirectional level conversion, and have a high transmission rate.

[0008] The present invention adopts the following technical solution: a level conversion circuit for automatic direction sensing, comprising: a first voltage domain circuit, a second voltage domain circuit, a first level conversion module, and a second level conversion module; the first voltage domain circuit and the second voltage domain circuit have the same structure, both including a drive input module and a drive output module; the first voltage domain circuit is connected to a first signal terminal, the second voltage domain circuit is connected to a second signal terminal, and the first signal terminal and the second signal terminal are bidirectional ports.

[0009] The level conversion circuit inputs the first signal A input to the first signal terminal into the second level conversion module through the drive input module of the first voltage domain circuit, generates a drive signal C2 at the output terminal of the second level conversion module, inputs the drive signal C2 to the drive output module of the second voltage domain circuit, controls the monostable circuit in the drive output module to generate a corresponding strong drive, and controls the weak drive at the same time, outputs a second signal B that is in phase with the first signal A to the second signal terminal; or inputs the second signal B input to the second signal terminal into the first level conversion module through the drive input module of the second voltage domain circuit, generates a drive signal D2 at the output terminal of the first level conversion module, inputs the drive signal D2 to the drive output module of the first voltage domain circuit, controls the monostable circuit in the drive output module to generate a corresponding strong drive, and controls the weak drive at the same time, outputs the first signal A that is in phase with the second signal B to the first signal terminal.

[0010] Preferably, the driving input module of the first voltage domain circuit includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a fourth rising edge monostable circuit;

[0011] The first voltage domain voltage signal is C1, the first input terminal of the first NOR gate NOR1 is connected to the first signal terminal, the second input terminal inputs the first voltage domain voltage signal C1, the output terminal is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 outputs the driving signal C2 through the second level conversion module;

[0012] The first voltage domain voltage signal C1 is also input to the first input terminal of the second NAND gate NAND2, the first signal terminal is connected to the second input terminal of the second NAND gate NAND2 through the fourth rising edge monostable circuit, and the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the first NAND gate NAND1;

[0013] The first input end of the first NAND gate NAND1 is connected to the output end of the first inverter INV1, the input end of the first inverter INV1 is connected to the drive signal D3 generated by the first voltage domain circuit drive output module, and the output end of the first NAND gate NAND1 is connected to the second input end of the first NOR gate NOR1 through the first voltage domain voltage signal C1.

[0014] Preferably, the driving output module of the first voltage domain circuit includes: a sixth inverter INV6, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first rising-edge monostable circuit, and a first falling-edge monostable circuit;

[0015] A drive signal D2 is input to the gate of the first PMOS transistor PM1 through a first rising-edge monostable circuit, and is simultaneously input to the gate of the first NMOS transistor NM1 through a first falling-edge monostable circuit. The source of the first PMOS transistor PM1 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is grounded. A strong drive is generated between the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1, and the strong drive is output to the first signal terminal.

[0016] The drive signal D2 is also input to the input terminal of the sixth inverter INV6, and a drive signal D3 is generated at the output terminal of the sixth inverter INV6. The drive signal D3 is input to the drain of the second PMOS transistor PM2 and the second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is grounded; a weak drive is generated between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2, and is output to the first signal terminal.

[0017] Preferably, the driving input module of the second voltage domain circuit includes: a fourth inverter INV4, a fifth inverter INV5, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third rising edge monostable circuit;

[0018] The second voltage domain voltage signal is D1, the first input terminal of the second NOR gate NOR2 is connected to the second signal terminal, the second input terminal is input with the second voltage domain voltage signal D1, the output terminal is connected to the input terminal of the fifth inverter INV5, and the output terminal of the fifth inverter INV5 outputs the driving signal D2 through the first level conversion module;

[0019] The second voltage domain voltage signal D1 is also input to the first input terminal of the third NAND gate NAND3, the second signal terminal is connected to the second input terminal of the third NAND gate NAND3 through the third rising edge monostable circuit, and the output terminal of the third NAND gate NAND3 is connected to the second input terminal of the fourth NAND gate NAND4;

[0020] The first input end of the fourth NAND gate NAND4 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the drive signal C3 generated by the second voltage domain circuit drive output module, and the output end of the fourth NAND gate NAND4 is connected to the second input end of the second NOR gate NOR2 through the second voltage domain voltage signal D1.

[0021] Preferably, the driving output module of the second voltage domain circuit includes: a third inverter INV3, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a second rising-edge monostable circuit, and a second falling-edge monostable circuit;

[0022] The drive signal C2 is input to the gate of the fourth PMOS transistor PM4 through the second rising-edge monostable circuit, and is simultaneously input to the gate of the fourth NMOS transistor NM4 through the second falling-edge monostable circuit. The source of the fourth PMOS transistor PM4 is connected to the second power supply voltage VCC2, and the drain is connected to the drain of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is grounded. A strong drive is generated between the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and the strong drive is output to the second signal terminal.

[0023] The drive signal C2 is also input to the input terminal of the third inverter INV3, and a drive signal C3 is generated at the output terminal of the third inverter INV3. The drive signal C3 is input to the drains of the third PMOS transistor PM3 and the third NMOS transistor NM3. The source of the third PMOS transistor PM3 is connected to the second power supply voltage VCC2, and the drain is connected to the drain of the third NMOS transistor NM3. The source of the third NMOS transistor NM3 is grounded. A weak drive is generated between the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 and is output to the second signal terminal.

[0024] Preferably, when the first signal terminal is an input terminal and the second signal terminal is an output terminal, the first voltage domain voltage signal C1 is at a low level, and the input first signal A passes through the first NOR gate NOR1, the second inverter INV2, and the second level conversion module in sequence to generate a drive signal C2 that is input to the drive output module of the second voltage domain circuit, controls the second rising edge monostable circuit and the second falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time, outputting a second signal B that is in phase with the first signal A;

[0025] The drive signal C2 simultaneously generates a drive signal C3 through the third inverter INV3, which is fed back to the input end of the fourth inverter INV4, and generates a second voltage domain voltage signal D1 with a phase opposite to the second signal B through the fourth NAND gate NAND4, which is input to the second input end of the second NOR gate NOR2. The two input signals of the second NOR gate NOR2 have opposite phases and output a low level. After passing through the fifth inverter INV5 and the first level conversion module, the drive signal D2 is generated to be a high level. The strong drive in the first voltage domain circuit driving output module is not turned on and the drive signal D3 remains at a low level, which does not affect the input of the first signal A at the first signal end.

[0026] Preferably, when the second signal terminal is the input terminal and the first signal terminal is the output terminal, the second voltage domain voltage signal D1 is at a low level, and the input second signal B passes through the second NOR gate NOR2, the fifth inverter INV5, and the first level conversion module in sequence to generate a drive signal D2 that is input to the drive output module of the first voltage domain circuit, controls the first rising edge monostable circuit and the first falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time, outputting a first signal A that is in phase with the second signal B;

[0027] The drive signal D2 simultaneously generates a drive signal D3 through the sixth inverter INV2, which is fed back to the input end of the first inverter INV1, and generates a first voltage domain voltage signal C1 with a phase opposite to the first signal A through the first NAND gate NAND1, which is input to the second input end of the first NOR gate NOR1. The two input signals of the first NOR gate NOR1 have opposite phases and output a low level. After passing through the second inverter INV2 and the second level conversion module, the drive signal C2 is generated to be a high level. The strong drive in the second voltage domain circuit driving output module is not turned on and the drive signal C3 remains at a low level, which does not affect the input of the second signal B at the second signal end.

[0028] Preferably, the first PMOS transistor PM1, the first NMOS transistor NM1, the third PMOS transistor PM3, and the third NMOS transistor NM3 are strong drive transistors; the second PMOS transistor PM2, the second NMOS transistor NM2, the fourth PMOS transistor PM4, and the fourth NMOS transistor NM4 are weak drive transistors.

[0029] Preferably, the first, second, third, and fourth rising-edge monostable circuits and the first and second falling-edge monostable circuits are all monostable circuits, and their working states include a steady state and a quasi-stable state; the monostable circuit flips from the steady state to the quasi-stable state through an external trigger pulse, and automatically returns to the steady state after maintaining the quasi-stable state for a period of time.

[0030] Preferably, the monostable circuit includes an RC circuit composed of a resistor R and a MOS capacitor NM, and the duration of the temporary stable state of the monostable circuit depends on the charging and discharging time of the RC circuit.

[0031] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0032] 1. The level conversion circuit of the present invention can not only realize bidirectional level conversion, but also automatically perform direction sensing and switch the transmission direction of the signal without the need for additional signals to control the transmission direction, thereby simplifying the system structure, reducing costs and power consumption, and improving data transmission speed.

[0033] 2. The level conversion circuit of the present invention uses a monostable circuit to turn on a strong drive output in a short time, thereby improving the output drive capability and transmission speed. At the same time, the strong drive output on the other side is turned off through a feedback signal, thereby avoiding the false start of the bidirectional level conversion circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a structural diagram of a level conversion circuit for automatic direction sensing of the present invention;

[0035] Figure 2 This is a structural diagram of the rising edge monostable circuit of the present invention;

[0036] Figure 3 This is a structural diagram of the falling edge monostable circuit of the present invention;

[0037] Figure 4 This is a level conversion timing waveform diagram of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the application are further elaborated in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in this field on this embodiment fall within the scope of protection of the present invention. At the same time, the step numbers in the embodiments of the present invention are only set for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] In one embodiment of the present invention, a level conversion circuit for automatic direction sensing, such as Figure 1 As shown, it includes: a first voltage domain circuit VCCA, a second voltage domain circuit VCCB, a first level conversion module, and a second level conversion module;

[0040] The first voltage domain circuit VCCA and the second voltage domain circuit VCCB have the same structure and both include a drive input module and a drive output module. The first voltage domain circuit VCCA is connected to the first signal terminal, and the second voltage domain circuit VCCB is connected to the second signal terminal. The first signal terminal and the second signal terminal are bidirectional ports, and the first level conversion module and the second level conversion module use conventional circuits.

[0041] Specifically, in the first voltage domain circuit VCCA, the drive input module includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a fourth rising-edge monostable circuit; the drive output module includes: a sixth inverter INV6, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first rising-edge monostable circuit, and a first falling-edge monostable circuit.

[0042] Specifically, in the second voltage domain circuit VCCB, the drive input module includes: a fourth inverter INV4, a fifth inverter INV5, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third rising-edge monostable circuit; the drive output module includes: a third inverter INV3, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a second rising-edge monostable circuit, and a second falling-edge monostable circuit.

[0043] Among them, the first PMOS transistor PM1, the first NMOS transistor NM1, the third PMOS transistor PM3, and the third NMOS transistor NM3 are strong drive transistors; the second PMOS transistor PM2, the second NMOS transistor NM2, the fourth PMOS transistor PM4, and the fourth NMOS transistor NM4 are weak drive transistors.

[0044] The initial state voltage of the first voltage domain circuit VCCA is the first voltage domain voltage signal C1, and the initial state voltage of the second voltage domain circuit VCCB is the second voltage domain voltage signal D1. Figure 1 Among them, C2, C3, C4, C5, D2, D3, D4, and D5 are all internal drive signals.

[0045] When the first signal terminal is an input terminal and the second signal terminal is an output terminal, Figure 4As shown, the first voltage domain voltage signal C1 remains at a low level, and the input first signal A passes through the first NOR gate NOR1, the second inverter INV2, and the second level conversion module in sequence to generate a drive signal C2 that is input to the second voltage domain circuit VCCB; the drive output module of the second voltage domain circuit VCCB controls the second rising edge monostable circuit to generate a drive signal C4 that is input to the gate of the fourth PMOS transistor PM4, and controls the second falling edge monostable circuit to generate a drive signal C5 that is input to the gate of the fourth NMOS transistor NM4, thereby generating a strong drive between the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and simultaneously controls the generation of a weak drive between the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3, thereby outputting a second signal B that is in phase with the first signal A.

[0046] At the same time, drive signal C2 is input to the third inverter INV3 to generate drive signal C3. Drive signal C3 is fed back to the input of the fourth inverter INV4. After passing through the fourth NAND gate NAND4, a second voltage domain voltage signal D1, which is opposite in phase to the second signal B, is generated and input to the second input of the second NOR gate NOR2. This causes the two input signals of the second NOR gate NOR2 to have opposite phases. The second NOR gate NOR2 maintains a low-level output. After passing through the fifth inverter INV5 and the first level conversion module, the generated drive signal D2 remains at a high level. Therefore, the strong drive in the driver output module of the first voltage domain circuit VCCA is not activated, preventing the bidirectional level conversion circuit from erroneously activating. Furthermore, drive signal D3 in the driver output module of the first voltage domain circuit VCCA remains at a low level, without affecting the input of the first signal A on the first signal terminal side.

[0047] Similarly, when the second signal terminal is the input terminal and the first signal terminal is the output terminal, the second voltage domain voltage signal D1 remains at a low level, and the input second signal B passes through the second NOR gate NOR2, the fifth inverter INV5, and the first level conversion module in sequence to generate a drive signal D2 that is input to the first voltage domain circuit VCCA; the drive output module of the first voltage domain circuit VCCA controls the first rising-edge monostable circuit to generate a drive signal D4 that is input to the gate of the first PMOS transistor PM1, and controls the first falling-edge monostable circuit to generate a drive signal D5 that is input to the gate of the first NMOS transistor NM1, thereby generating a strong drive between the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1, and simultaneously controls the generation of a weak drive between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2, thereby outputting a first signal A that is in phase with the second signal B.

[0048] At the same time, drive signal D2 is input to the sixth inverter INV6 to generate drive signal D3. Drive signal D3 is fed back to the input of the first inverter INV1 and passes through the first NAND gate NAND1 to generate a first voltage domain voltage signal C1 with a phase opposite to that of the first signal A. This signal is then input to the second input of the first NOR gate NOR1, causing the two input signals of the first NOR gate NOR1 to have opposite phases. The first NOR gate NOR1 maintains a low-level output. After passing through the second inverter INV2 and the second level shifter module, the generated drive signal C2 remains high. Therefore, the strong drive in the driver output module of the second voltage domain circuit VCCB is not activated, preventing the bidirectional level shifter circuit from erroneously activating. Furthermore, drive signal C3 in the driver output module of the second voltage domain circuit VCCB remains low, without affecting the input of the second signal B on the second signal terminal side.

[0049] In particular, in this embodiment, the first, second, third, and fourth rising-edge monostable circuits and the first and second falling-edge monostable circuits are all monostable circuits. The monostable circuit has two different working states: a stable state and a quasi-stable state. Under the action of an external trigger pulse, it can flip from the stable state to the quasi-stable state, and after maintaining the quasi-stable state for a period of time, it automatically returns to the steady state.

[0050] The duration of the transient state depends on the charging and discharging time of the RC circuit in the monostable circuit, and has nothing to do with the width and amplitude of the trigger pulse. Figure 1 The transient stable state time of the monostable circuit is short, which is used to start strong drive in a short time to improve the output driving capability and transmission speed.

[0051] Specifically, a rising edge triggered monostable circuit such as Figure 2 As shown, Figure 2 In the figure, R1 is a resistor, PM5~PM10 are PMOS tubes, and NM5~NM10 are NMOS tubes.

[0052] In steady state, the circuit's output signal OUT remains high. At the rising edge of the input signal IN, which transitions from low to high, the gate signals of the PMOS transistor PM10 and the NMOS transistor NM9 quickly transition to low. Due to the delay generated by the resistor R1 and the MOS capacitor NM6, the gates of the PMOS transistor PM9 and the NMOS transistor NM10 remain high temporarily. At this point, the output signal OUT briefly transitions to low, and the circuit enters a transient steady state. After a period of time, the gates of the PMOS transistor PM9 and the NMOS transistor NM10 transition to low, at which point the output signal OUT returns to high, and the circuit returns to steady state.

[0053] Specifically, a falling-edge-triggered monostable circuit, such as Figure 3 As shown, Figure 3In the figure, R2 is a resistor, PM11~PM16 are PMOS tubes, and NM11~NM16 are NMOS tubes. The principle is similar to the rising edge triggered monostable circuit.

[0054] In steady state, the output signal OUT of the circuit remains at a low level. At the falling edge of the input signal IN, which changes from a high level to a low level, the gate signals of the PMOS transistor PM16 and the NMOS transistor NM16 quickly change to a low level. Due to the delay generated by the resistor R2 and the MOS capacitor PM12, the gates of the PMOS transistor PM15 and the NMOS transistor NM15 temporarily remain at a low level. At this time, the output signal OUT briefly changes to a high level, and the circuit enters a transient steady state. After a period of time, the gates of the PMOS transistor PM15 and the NMOS transistor NM15 change to a high level. At this time, the output signal OUT changes to a low level, and the circuit returns to a steady state.

[0055] In summary, the automatic direction-sensing level conversion circuit of the present invention not only achieves bidirectional level conversion, but also automatically switches the signal transmission direction based on direction sensing, eliminating the need for additional signals to control the transmission direction, simplifying the system structure and reducing costs. Furthermore, the present invention utilizes a monostable circuit to enable a strong drive output within a short period of time, improving the output drive capability and transmission speed, and uses a feedback signal to disable the strong drive output on the other side, thus preventing the bidirectional level conversion circuit from being accidentally enabled.

[0056] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A level conversion circuit for automatic direction sensing, characterized in that: include: A first voltage domain circuit, a second voltage domain circuit, a first level conversion module, and a second level conversion module; The first voltage domain circuit and the second voltage domain circuit have the same structure, and both include a drive input module and a drive output module; The first voltage domain circuit is connected to the first signal terminal, the second voltage domain circuit is connected to the second signal terminal, and the first signal terminal and the second signal terminal are bidirectional ports; The level conversion circuit inputs the first signal A inputted at the first signal terminal into the second level conversion module through the driving input module of the first voltage domain circuit, generates a driving signal C2 at the output terminal of the second level conversion module, inputs the driving signal C2 into the driving output module of the second voltage domain circuit, controls the monostable circuit in the driving output module to generate a corresponding strong driving signal, and controls the weak driving signal at the same time, and outputs a second signal B in phase with the first signal A to the second signal terminal; or inputs the second signal B inputted at the second signal terminal into the first level conversion module through the driving input module of the second voltage domain circuit, generates a driving signal D2 at the output terminal of the first level conversion module, inputs the driving signal D2 into the driving output module of the first voltage domain circuit, controls the monostable circuit in the driving output module to generate a corresponding strong driving signal, and controls the weak driving signal at the same time, and outputs the first signal A in phase with the second signal B to the first signal terminal; The driving output module of the first voltage domain circuit includes: a sixth inverter INV6, a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, a second PMOS transistor PM2, a first rising edge monostable circuit, and a first falling edge monostable circuit; The drive signal D2 is input to the gate of the first PMOS transistor PM1 through a first rising-edge monostable circuit, and is simultaneously input to the gate of the first NMOS transistor NM1 through a first falling-edge monostable circuit; the source of the first PMOS transistor PM1 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the first NMOS transistor NM1; the source of the first NMOS transistor NM1 is grounded; a strong drive is generated between the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1, and the strong drive is output to the first signal terminal; The drive signal D2 is also input to the input end of the sixth inverter INV6, and the drive signal D3 is generated at the output end of the sixth inverter INV6. The drive signal D3 is input to the drain of the second PMOS transistor PM2 and the second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the first power supply voltage VCC1, and the drain is connected to the drain of the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is grounded; a weak drive is generated between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2, and is output to the first signal end.

2. The level conversion circuit for automatic direction sensing according to claim 1, characterized in that: The driving input module of the first voltage domain circuit includes: a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, a second NAND gate NAND2, a first NOR gate NOR1, and a fourth rising edge monostable circuit; The first voltage domain voltage signal is C1, the first input terminal of the first NOR gate NOR1 is connected to the first signal terminal, the second input terminal inputs the first voltage domain voltage signal C1, the output terminal is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 outputs the driving signal C2 through the second level conversion module; The first voltage domain voltage signal C1 is also input to the first input terminal of the second NAND gate NAND2, the first signal terminal is connected to the second input terminal of the second NAND gate NAND2 through the fourth rising edge monostable circuit, and the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the first NAND gate NAND1; The first input end of the first NAND gate NAND1 is connected to the output end of the first inverter INV1, the input end of the first inverter INV1 is connected to the drive signal D3 generated by the first voltage domain circuit drive output module, and the output end of the first NAND gate NAND1 is connected to the second input end of the first NOR gate NOR1 through the first voltage domain voltage signal C1.

3. The level conversion circuit for automatic direction sensing according to claim 2, characterized in that: The driving input module of the second voltage domain circuit includes: a fourth inverter INV4, a fifth inverter INV5, a third NAND gate NAND3, a fourth NAND gate NAND4, a second NOR gate NOR2, and a third rising edge monostable circuit; The second voltage domain voltage signal is D1, the first input terminal of the second NOR gate NOR2 is connected to the second signal terminal, the second input terminal is input with the second voltage domain voltage signal D1, the output terminal is connected to the input terminal of the fifth inverter INV5, and the output terminal of the fifth inverter INV5 outputs the driving signal D2 through the first level conversion module; The second voltage domain voltage signal D1 is also input to the first input terminal of the third NAND gate NAND3, the second signal terminal is connected to the second input terminal of the third NAND gate NAND3 through the third rising edge monostable circuit, and the output terminal of the third NAND gate NAND3 is connected to the second input terminal of the fourth NAND gate NAND4; The first input end of the fourth NAND gate NAND4 is connected to the output end of the fourth inverter INV4, the input end of the fourth inverter INV4 is connected to the drive signal C3 generated by the second voltage domain circuit drive output module, and the output end of the fourth NAND gate NAND4 is connected to the second input end of the second NOR gate NOR2 through the second voltage domain voltage signal D1.

4. The level conversion circuit for automatic direction sensing according to claim 3, characterized in that: The drive output module of the second voltage domain circuit includes: a third inverter INV3, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a second rising edge monostable circuit, and a second falling edge monostable circuit; The drive signal C2 is input into the gate of the fourth PMOS transistor PM4 through the second rising-edge monostable circuit, and is simultaneously input into the gate of the fourth NMOS transistor NM4 through the second falling-edge monostable circuit; the source of the fourth PMOS transistor PM4 is connected to the second power supply voltage VCC2, and the drain is connected to the drain of the fourth NMOS transistor NM4; the source of the fourth NMOS transistor NM4 is grounded; a strong drive is generated between the drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4, and is output to the second signal terminal; The drive signal C2 is also input to the input end of the third inverter INV3, and a drive signal C3 is generated at the output end of the third inverter INV3. The drive signal C3 is input to the drains of the third PMOS transistor PM3 and the third NMOS transistor NM3. The source of the third PMOS transistor PM3 is connected to the second power supply voltage VCC2, and the drain is connected to the drain of the third NMOS transistor NM3. The source of the third NMOS transistor NM3 is grounded. A weak drive is generated between the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 and is output to the second signal end.

5. The level conversion circuit for automatic direction sensing according to claim 4, characterized in that: When the first signal terminal is the input terminal and the second signal terminal is the output terminal, the first voltage domain voltage signal C1 is at a low level, and the input first signal A passes through the first NOR gate NOR1, the second inverter INV2, and the second level conversion module in sequence to generate a drive signal C2 which is input to the drive output module of the second voltage domain circuit, controls the second rising edge monostable circuit and the second falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time to output a second signal B which is in phase with the first signal A; The drive signal C2 simultaneously generates a drive signal C3 through the third inverter INV3, which is fed back to the input end of the fourth inverter INV4, and generates a second voltage domain voltage signal D1 with a phase opposite to the second signal B through the fourth NAND gate NAND4, which is input to the second input end of the second NOR gate NOR2. The two input signals of the second NOR gate NOR2 have opposite phases and output a low level. After passing through the fifth inverter INV5 and the first level conversion module, the drive signal D2 is generated to be a high level. The strong drive in the first voltage domain circuit driving output module is not turned on and the drive signal D3 remains at a low level, which does not affect the input of the first signal A at the first signal end.

6. The level conversion circuit for automatic direction sensing according to claim 4, characterized in that: When the second signal terminal is the input terminal and the first signal terminal is the output terminal, the second voltage domain voltage signal D1 is at a low level, and the input second signal B passes through the second NOR gate NOR2, the fifth inverter INV5, and the first level conversion module in sequence to generate a drive signal D2 which is input to the drive output module of the first voltage domain circuit, controls the first rising edge monostable circuit and the first falling edge monostable circuit to generate a strong drive, and controls the weak drive at the same time to output a first signal A which is in phase with the second signal B; The drive signal D2 simultaneously generates a drive signal D3 through the sixth inverter INV2, which is fed back to the input end of the first inverter INV1, and generates a first voltage domain voltage signal C1 with a phase opposite to the first signal A through the first NAND gate NAND1, which is input to the second input end of the first NOR gate NOR1. The two input signals of the first NOR gate NOR1 have opposite phases and output a low level. After passing through the second inverter INV2 and the second level conversion module, the drive signal C2 is generated to be a high level. The strong drive in the second voltage domain circuit driving output module is not turned on and the drive signal C3 remains at a low level, which does not affect the input of the second signal B at the second signal end.

7. The level conversion circuit for automatic direction sensing according to claim 4, characterized in that: The first PMOS transistor PM1, the first NMOS transistor NM1, and the third PMOS transistor PM3, the third NMOS transistor NM3 are strong drive transistors; the second PMOS transistor PM2, the second NMOS transistor NM2, the fourth PMOS transistor PM4, and the fourth NMOS transistor NM4 are weak drive transistors.

8. The level conversion circuit for automatic direction sensing according to claim 4, characterized in that: The first, second, third, and fourth rising-edge monostable circuits and the first and second falling-edge monostable circuits are all monostable circuits, and their working states include a steady state and a transient state. The monostable circuit flips from the steady state to the transient state through an external trigger pulse, and then automatically returns to the steady state.

9. The level conversion circuit for automatic direction sensing according to claim 8, characterized in that: The monostable circuit includes an RC circuit composed of a resistor R and a MOS capacitor NM. The duration of the monostable circuit's transient state depends on the charge and discharge time of the RC circuit.

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