Counter system and counting method thereof
By designing a counter system including input module, counter and latch module, the problems of complex peripheral hardware and state out-synchronization in traditional counter design are solved, and the counting effect of simplifying circuits and improving reliability is achieved.
Patent Information
- Application Number
- CN202411839880.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-18
AI Technical Summary
In traditional counter design, the peripheral hardware circuit is complex, and the state changes of the high-bit counter depend on the state changes of the low-bit counter, which may cause the state changes between different bits to be synchronized, resulting in counting errors, and low reliability.
Design a counter system, including input module, counter and latch module. When the counting window signal is the first level, the input module outputs the clock signal to the counter, and the counter counts. When the signal jumps to the second level, the first set time is delayed and the count value of the latch counter is used to latch the counter.
The counter circuit is simplified, the requirements for counter processing speed are reduced, the count value is ensured to be stored accurately, the reliability of the counter system is improved, and the accurate counting of discrete signals is achieved.
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Figure CN119853672A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog-to-digital converters, and in particular to a counter system and a counting method thereof. Background Art
[0002] As an important component of digital circuits, counters are widely used in various timing devices.
[0003] Traditional counters use a high-bit asynchronous and low-bit synchronous design, and use digital logic to achieve alignment delay. However, this design has complex peripheral hardware circuits, and the state change of the high-bit counter depends on the state change of the low-bit counter. This dependency may cause the state changes between different bits to be asynchronous, resulting in counting errors, that is, low reliability. Summary of the invention
[0004] The invention provides a counter system and a counting method thereof to realize counting of discrete signals.
[0005] According to one aspect of the present invention, there is provided a counter system, comprising: an input module, a counter, and a latch module;
[0006] The input module is connected to the input end of the counter, and is used to output a clock signal to the counter when the input counting window signal is at a first level; the counter is used to count the clock signal;
[0007] The latch module is connected to the output end of the counter, and is used to delay a first set time after the first level of the connected counting window signal jumps to a second level, and latch the count value output by the counter.
[0008] According to another aspect of the present invention, a counting method of a counter system is provided, the method comprising: when an input counting window signal connected thereto is at a first level, an input module outputs a clock signal to the counter;
[0009] When the counting window signal is at a first level, the counter receives a clock signal to count;
[0010] When the first level of the counting window signal jumps to the second level, the counter stops counting;
[0011] The latch module latches the count value of the output end of the counter after a first set time.
[0012] In the embodiment of the present invention, when the counting window signal is at the first level, the clock signal output by the input module is counted by the counter, and when the counting window signal jumps to the second level, the first set time is delayed, and then the count value of the counter is latched by the latch module. The counter system circuit provided by the present invention is simple, and by setting the first set time delay before latching, the requirements for the processing speed of the counter are reduced, and the count value can be ensured to be accurately saved, which is conducive to improving the reliability of the counter system. At the same time, the present invention can count and latch the events when the counting window signal is at the first level, that is, it can count the discrete signals.
[0013] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0015] Figure 1 A schematic diagram of the structure of a counter system provided by an embodiment of the present invention;
[0016] Figure 2 A schematic diagram of the structure of another counter system provided by an embodiment of the present invention;
[0017] Figure 3 A schematic diagram of the structure of another counter system provided by an embodiment of the present invention;
[0018] Figure 4 A signal waveform diagram of a counter system provided by an embodiment of the present invention;
[0019] Figure 5 A schematic diagram of the structure of a counter provided by an embodiment of the present invention;
[0020] Figure 6 A structural schematic diagram of a D-type flip-flop with a true single-phase clock structure provided by an embodiment of the present invention;
[0021] Figure 7 A flowchart of a counting method of a counter system provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0024] Figure 1 This is a schematic diagram of the structure of a counter system provided by an embodiment of the present invention. This embodiment is applicable to the case of counting events. The counter system can be configured in an electronic device with a counting function. Figure 1 As shown, the counter system includes: an input module 110, a counter 120, and a latch module 130; the input module 110 is connected to the input end of the counter 120, and is used to output a clock signal to the counter 120 when the connected counting window signal is at the first level; the counter 120 is used to count the clock signal; the latch module 130 is connected to the output end of the counter 120, and is used to delay a first set time after the first level of the connected counting window signal jumps to the second level, and latch the count value output by the counter 120.
[0025] Specifically, the input module 110 refers to the input part of the counter system provided in this embodiment, which is responsible for receiving external signals and converting them into a format that can be processed by the counter.
[0026] Counter 120 refers to a digital circuit used to record the number of times an event occurs, usually expressed in binary or decimal.
[0027] The counting window signal refers to a control signal for indicating when the counter 120 starts counting. When the counting window signal is at the first level, the input module 110 will output a clock signal to the counter 120 to ensure that the counter 120 records events at an appropriate time. When the counting window signal is at the second level, the input module 110 stops outputting the clock signal to the counter 120, and the counter 120 will maintain the current state and will not count.
[0028] The clock signal refers to a periodically changing electrical signal used to synchronize various components in a circuit. In the counter 120, the clock signal serves as a trigger signal to indicate when the counter 120 starts counting.
[0029] The latch module 130 refers to a storage element capable of maintaining the state of an input signal. After receiving the count window signal changing to the second level for a certain period of time, the latch module 130 stores the current count value of the counter 120.
[0030] The first setting time refers to the time period during which the latch module 130 delays saving the count value after the counting window signal changes to the second level. The first setting time is used to ensure the output stability of the counter and avoid erroneous latching due to instantaneous signal changes.
[0031] In the embodiment of the present invention, when the counting window signal connected to the input module 110 is at the first level, the input module 110 outputs a clock signal to the counter 120, and the counter 120 counts the clock signal. When the first level of the counting window signal jumps to the second level, the first set time is delayed, and then the latch module 130 latches the count value currently outputted by the output terminal of the counter 120.
[0032] In the embodiment of the present invention, when the counting window signal is at the first level, the clock signal output by the input module 110 is counted by the counter 120, and when the counting window signal jumps to the second level, the first set time is delayed, and then the count value of the counter 120 is latched by the latch module 130. The counter system circuit provided by the present invention is simple, and by setting the first set time delay before latching, the requirements for the processing speed of the counter 120 are reduced, and the count value can be ensured to be accurately saved, which is conducive to improving the reliability of the counter system. At the same time, the present invention can count and latch the events when the counting window signal is at the first level, that is, it can count the discrete signals.
[0033] Figure 2 A schematic diagram of the structure of another counter system provided by an embodiment of the present invention, based on the above embodiments, as Figure 2As shown, optionally, the latch module 130 includes a first delay unit 131, a first OR gate unit 132 and a latch unit 133, the output end of the first delay unit 131 is connected to the first input end of the first OR gate unit 132, the second input end of the first OR gate unit 132 is connected to the counting window signal, the output end of the first OR gate unit 132 is connected to the trigger end of the latch unit 133, and the input end of the latch unit 133 is connected to the output end of the counter 120. The first delay unit 131 is used to delay the connected counting window signal by a first set time to obtain a first delay signal. The first OR gate unit 132 is used to output a trigger signal after performing an OR operation on the first delay signal and the counting window signal. The latch unit 133 is used to latch the count value output by the counter 120 at the transition edge where the first level corresponding to the trigger signal jumps to the second level.
[0034] Specifically, the first delay unit 131 refers to a circuit component for introducing a specific time delay between its input signal and output signal. In the embodiment of the present invention, the first delay unit 131 can delay the counting window signal so that the subsequent first OR gate unit 132 receives the corresponding first delayed signal after the first set time. That is, the first delayed signal is the signal processed by the first delay unit 131, that is, the signal obtained by delaying the counting window signal backward by the first set time.
[0035] The first OR gate unit 132 refers to a basic logic gate having at least two inputs and one output. As long as one of the inputs is at a high level (logic 1), the output is at a high level. In the embodiment of the present invention, the first OR gate unit 132 performs a logic "OR" operation on the counting window signal and the first delay signal to obtain a trigger signal. The trigger signal refers to a signal used to activate the latch unit 133. In one cycle, the rising edge of the trigger signal is synchronized with the rising edge of the counting window signal, and the falling edge of the trigger signal is synchronized with the falling edge of the first delay signal.
[0036] The latch unit 133 refers to a storage element for maintaining the state of the input signal until a specific control signal is received to latch its state. Exemplarily, the latch unit 133 can be a trigger array composed of a plurality of triggers. In an embodiment of the present invention, during the first level time of the first delay signal, the counter 120 performs a counting function, and its output value changes with the input clock signal; before the first level of the first delay signal jumps to the second level, the count value at the output end of the counter 120 stabilizes; at the moment when the first level of the first delay signal jumps to the second level, the latch unit 133 latches the current count value of the counter 120.
[0037] A transition edge refers to the moment when a signal changes from one state to another, such as from a low level (0) to a high level (1) or from a high level (1) to a low level (0).
[0038] In the embodiment of the present invention, the first delay unit 131 delays the counting window signal by a first set time to obtain a first delay signal, and the first delay signal and the counting window signal are logically "OR" operated to obtain a trigger signal and input to the trigger end of the latch unit 133. At the transition edge where the first level of the trigger signal jumps to the second level, the latch unit 133 latches the count value output by the counter 120.
[0039] Continue to see Figure 2 Optionally, based on the above embodiments, the first delay unit 131 includes at least two cascaded inverters.
[0040] Specifically, an inverter refers to a basic digital logic circuit component, whose main function is to invert the logic state of the input signal, that is, a high level becomes a low level, and a low level becomes a high level. Each inverter introduces a fixed delay when processing its input signal. By cascading at least two inverters together, the delay time of the first delay unit 131 is the sum of the delay times of all inverters.
[0041] In the embodiment of the present invention, at least two cascaded inverters are used as components of the first delay unit 131, which can effectively implement signal delay, enhance signal quality, and improve circuit stability.
[0042] The embodiment of the present invention performs delay through the first delay unit 131, so that the latch unit 133 latches the value of the counter 120 after the first set time, thereby being able to accurately latch the counting result when the counter 120 is stable. The present invention can eliminate the potential unstable state that exists at the moment after the signal changes, thereby effectively improving the counting accuracy and reliability of the counter system.
[0043] Figure 3 A schematic diagram of the structure of another counter system provided by an embodiment of the present invention, based on the above embodiments, as Figure 3 As shown, optionally, the latch module 130 also includes a reset unit 134, the input end of the reset unit 134 is connected to the output end of the first delay unit 131, the output end of the reset unit 134 is connected to the reset end of the counter 120, and the reset unit 134 is used to delay a second set time after the first level of the first delay signal jumps to the second level, and reset the count value of the counter 120.
[0044] Specifically, the reset unit 134 refers to a circuit component for resetting the count value in the counter 120 to return it to an initial state for counting in the next cycle.
[0045] The second setting time refers to the time period that the reset unit 134 delays after the first level of the first delay signal changes to the second level, so as to ensure that the count value of the counter 120 can be accurately reset. The second setting time ensures that when the counter 120 is reset, all related signal states are stable, avoiding data inconsistency during reset.
[0046] In the embodiment of the present invention, after the first level of the first delay signal changes to the second level, the reset unit 134 delays the second set time to reset the counter 120 so as to reset the count value in the counter 120 and prepare for the next cycle counting.
[0047] Continue to see Figure 3 Optionally, based on the above embodiments, the reset unit 134 includes a second delay unit 135 and a second OR gate unit 136, the input end of the second delay unit 135 is connected to the output end of the first delay unit 131, the output end of the second delay unit 135 is connected to the first input end of the second OR gate unit 136, the second input end of the second OR gate unit 136 is connected to the counting window signal, and the output end of the second OR gate unit 136 is connected to the reset end of the counter 120. The second delay unit 135 is used to delay the first delay signal by a second set time to obtain a second delay signal. The second OR gate unit 136 is used to perform an OR operation on the second delay signal and the counting window signal, and output a reset signal. The counter 120 is used to reset the count value at the transition edge where the first level corresponding to the reset signal jumps to the second level.
[0048] Specifically, the second delay unit 135 refers to a circuit component for introducing a specific time delay between an input signal and an output signal. In an embodiment of the present invention, the second delay unit 135 outputs the first delayed signal after a second set time, thereby providing a delayed signal to the subsequent second OR gate unit 136. Exemplarily, the second delay unit 135 may include at least two cascaded inverters.
[0049] The second OR gate unit 136 refers to a basic logic gate that receives at least two input signals and generates an output according to a logic “OR” operation.
[0050] The second delay signal refers to the signal output after the first delay signal passes through the second delay unit 135, and the second delay signal lags behind the first delay signal by a second set time. In an embodiment of the present invention, the second delay unit 135 delays the first delay signal by a second set time to obtain a second delay signal, and the second delay signal is logically "ORed" with the counting window signal to obtain a reset signal. The reset signal refers to a control signal used to instruct the counter 120 to reset its state to an initial state. The rising edge of the reset signal is synchronized with the rising edge of the counting window signal, and the falling edge of the reset signal is synchronized with the falling edge of the second delay signal. At the transition edge where the reset signal changes from the first level to the second level, the counter 120 is reset to prepare for the counting of the next cycle.
[0051] The embodiment of the present invention delays the first delay signal by the second set time through the second delay unit 135, and then resets the counter 120, thereby ensuring the timing accuracy and signal stability of the reset operation. The present invention counts the events when the counting window signal of the current cycle is at the first level and then resets, which can ensure the accurate counting of the counter 120 in the next cycle, that is, it can realize the counting of discrete signals.
[0052] Continue to see Figure 3 Optionally, based on the above embodiments, the input module 110 includes an AND gate unit 111, a first input end of the AND gate unit 111 is connected to the oscillator output signal, a second input end of the AND gate unit 111 is connected to the counting window signal, and an output end of the AND gate unit 111 is connected to an input end of a counter 120, for outputting a clock signal corresponding to the oscillator output signal to the counter 120 when the oscillator output signal and the counting window signal are both at a first level.
[0053] Specifically, the AND gate unit 111 refers to a basic logic gate circuit, including at least two inputs and one output, and its output is at a high level only when all inputs are at a high level (logic 1).
[0054] Oscillator output signal refers to the periodic signal generated by the oscillator circuit, usually in the form of a square wave, sine wave, or triangle wave.
[0055] In the embodiment of the present invention, since the AND gate unit 111 performs a logical AND operation on the oscillator signal and the counting window signal, the oscillator clock signal is output only when the counting window signal is valid. This ensures that the counter 120 performs the counting operation at the appropriate time, effectively improving the reliability of the counter system.
[0056] Specifically, Figure 4 The signal waveform diagram of a counter system provided by an embodiment of the present invention. Figure 4As shown, when the counting window signal is at the first level, the counter 120 can receive the clock signal. At the first moment t0, the counting window signal jumps to the second level, and the counter 120 cannot receive the clock signal. The counting window signal is delayed by the first set time to obtain the first delayed signal. At the transition edge when the first delayed signal changes from the first level to the second level, that is, at the second moment t1, the latch unit 133 latches the value in the counter 120. The first delayed signal is delayed by the second set time to obtain the second delayed signal. At the transition edge when the second delayed signal changes from the first level to the second level, that is, at the third moment t3, the count value at the output end of the counter 120 is reset.
[0057] Figure 5 A schematic diagram of a structure of a counter provided by an embodiment of the present invention, based on the above embodiments, as Figure 5 As shown, optionally, the counter 120 includes at least two cascade-connected flip-flops 121 .
[0058] Specifically, the trigger 121 refers to a basic digital circuit element for storing and maintaining binary information. Exemplarily, the trigger 121 can be a D-type trigger, a T-type trigger, or a JK-type trigger.
[0059] In the embodiment of the present invention, four cascaded flip-flops 121 are used as an example for explanation. The four flip-flops 121 are cascaded together by connecting the output and the input, thereby forming a four-bit counter 120. The specific connection method is as follows: the clock signal terminal CLK of the first flip-flop 121 can receive the clock signal CLK_IN, and the first output terminal QB of each flip-flop 121 is not only connected to the clock signal terminal CLK of the next flip-flop 121, but also connected to its own trigger terminal D, so that the flip-flop 121 can provide feedback according to its own state. The reset terminal RST of each flip-flop 121 can receive the reset signal RESET. When the reset signal is valid, all flip-flops 121 will be reset to the initial state.
[0060] In the flip-flop 121, the first output terminal QB is the complement state of the second output terminal Q, that is, when the state of the second output terminal Q is 1, the state of the first output terminal QB is 0. When each pulse signal in the clock signal arrives, the first flip-flop 121 latches the current state according to the input signal and outputs it to the second output terminal Q, and at the same time, its first output terminal QB transmits the complement state of the second output terminal Q to the clock signal terminal CLK of the second flip-flop 121. When the second flip-flop 121 receives the output signal of the first output terminal QB of the first flip-flop 121, it will update its state when the next pulse signal arrives. This process is carried out in sequence to form a binary counter 120.
[0061] Continue to see Figure 5 Optionally, based on the above embodiments, the counter includes a first cascade unit 124 and a second cascade unit 125; the first cascade unit 124 includes at least two cascaded first triggers 122, the second cascade unit 125 includes at least two cascaded second triggers 123, the first-stage second trigger 123 of the second cascade unit 125 is cascaded with the last-stage first trigger 122 of the first cascade unit 124; the first trigger 122 is a D-type trigger with a true single-phase clock structure.
[0062] Specifically, the first cascade unit 124 refers to a part of the counter 120, including at least two cascade-connected first flip-flops 122. The second cascade unit 125 refers to another part of the counter 120, including at least two cascade-connected second flip-flops 123.
[0063] The first flip-flop 122 may be a true single-phase clock D-type flip-flop (TSPC_DFF). A true single-phase clock D-type flip-flop refers to a digital circuit element that uses a single-phase clock signal to control the latching and updating of data. Figure 6 A structural diagram of a D-type flip-flop with a true single-phase clock structure provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the left side of TSPC_DFF contains three MOS tube groups, each of which contains two PMOS tubes and one NMOS tube. The configuration of these MOS tubes can ensure that TSPC_DFF correctly latches the input data and controls the output state under the specific edge of the clock signal, that is, the 9 MOS tubes on the left complete the latching function. The middle part of TSPC_DFF contains a PMOS tube with a reset function, and its reset terminal RST receives the reset signal to complete the reset function. The right side of TSPC_DFF contains two MOS tube groups, each of which contains a PMOS tube and an NMOS tube to complete the signal output function.
[0064] The second flip-flop 123 may be a D flip-flop (D Flip-Flop, DFF).
[0065] Exemplarily, the first cascade unit 124 may include 4 cascaded TSPC_DFFs, each TSPC_DFF can divide the input signal of the clock signal terminal CLK thereof by two. Since the first output terminal QB output of each trigger is connected to the clock signal terminal CLK input of the next trigger, the first cascade unit 124 can divide the clock signal of the input counter 120 by 16. The second cascade unit 125 may include 14 cascaded DFFs, and the second cascade unit 125 further divides the clock signal after the 16-division. In an embodiment of the present invention, TSPC_DFF has a faster switching speed and lower power consumption, and is suitable for processing high-frequency signals. Therefore, TSPC_DFF is first used to divide the high-frequency signal by 16 to reduce the signal frequency and ensure the stability and reliability of the subsequent circuit. After the TSPC_DFF is divided, the next signal will be passed to the DFF, which is suitable for processing lower frequency signals and can provide better stability and data latching functions.
[0066] It should be noted that the embodiments of the present invention provide Figure 5 Only four triggers 121 are taken as an example for description, which does not constitute a limitation on the number of first triggers 122 and second triggers 123 in the embodiment of the present invention.
[0067] The embodiment of the present invention solves the power consumption and stability problems in high-frequency signal processing by cascading a first cascade unit 124 and a second cascade unit 125 including two different types of triggers to form a counter 120. In particular, by using TSPC_DFF in the first cascade unit 124 to divide the high-frequency signal by 16, the operating frequency of the subsequent circuit is effectively reduced, the power consumption is reduced, and the stability of the timer system is improved.
[0068] Figure 7 Flow chart of a counting method of a counter system provided by an embodiment of the present invention. Based on the above embodiments, Figure 7 As shown, optionally, the method includes:
[0069] S210 . When the received counting window signal is at a first level, the input module outputs a clock signal to the counter.
[0070] Specifically, the input module outputs the clock signal only when the counting window signal is at the first level, so as to ensure the validity of the counter counting.
[0071] S220: When the counting window signal is at the first level, the counter receives the clock signal and counts.
[0072] Specifically, the clock signal includes multiple pulse signals, and the counter receives a pulse signal and performs a count. The counter can accurately record the number of pulse signals in the time period when the counting window signal is at the first level, that is, the number of times the event occurs.
[0073] S230: When the first level of the counting window signal changes to the second level, the counter stops counting.
[0074] Specifically, at the transition edge where the first level of the counting window signal transitions to the second level, the counter stops counting, ensuring that the counter counts only under specific conditions, thereby avoiding interference from invalid data.
[0075] S240 , the latch module delays a first set time after the first level of the connected counting window signal jumps to the second level, and latches the count value of the output end of the counter.
[0076] Specifically, the latch module delays the first set time and then latches the count value in the counter. At this time, the state of the counter has stabilized, and the accuracy and reliability of the latched count value can be ensured.
[0077] Continue to participate Figure 7 Optionally, based on the above embodiments, after S240, the latch module delays the first set time after the first level of the connected counting window signal jumps to the second level, and latches the count value of the output end of the counter, it also includes:
[0078] S250: After a second set time has passed, the reset module resets the count value of the counter.
[0079] Specifically, the reset module resets the counter after the delay of the second set time, that is, the state of the counter is reset to the initial state, and the count value is set to 0, so as to prepare for the next cycle counter counting.
[0080] The embodiment of the present invention realizes the counting, latching and resetting functions of the counter through the coordinated work of the input module, the counter, the latch module and the reset module. The present invention enables the counter to count the clock signal within the time period when the counting window signal is at the first level, thereby effectively counting the discrete signal and ensuring the accuracy and reliability of the data.
[0081] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0082] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A counter system, characterized in that: include: Input module, counter, latch module; The input module is connected to the input end of the counter, and is used to output a clock signal to the counter when the input counting window signal is at a first level; The counter is used to count the clock signal; The latch module is connected to the output end of the counter, and is used to delay a first set time after the first level of the connected counting window signal jumps to a second level, and latch the count value output by the counter.
2. The counter system according to claim 1, characterized in that The latch module comprises a first delay unit, a first OR gate unit and a latch unit, wherein the output end of the first delay unit is connected to the first input end of the first OR gate unit, the second input end of the first OR gate unit is connected to the counting window signal, the output end of the first OR gate unit is connected to the trigger end of the latch unit, and the input end of the latch unit is connected to the output end of the counter; The first delay unit is used to delay the connected counting window signal by a first set time to obtain a first delayed signal; The first OR gate unit is used to output a trigger signal after performing an OR operation on the first delay signal and the counting window signal; The latch unit is used for latching the count value output by the counter at the transition edge where the first level corresponding to the trigger signal changes to the second level.
3. The counter system according to claim 2, characterized in that The first delay unit includes at least two cascaded inverters.
4. The counter system according to claim 2, characterized in that: The latch module also includes a reset unit, an input end of the reset unit is connected to the output end of the first delay unit, and the output end of the reset unit is connected to the reset end of the counter. The reset unit is used to delay a second set time after the first level of the first delay signal jumps to the second level, and reset the count value of the counter.
5. The counter system according to claim 4, characterized in that The reset unit comprises a second delay unit and a second OR gate unit, the input end of the second delay unit is connected to the output end of the first delay unit, the output end of the second delay unit is connected to the first input end of the second OR gate unit, the second input end of the second OR gate unit is connected to the counting window signal, and the output end of the second OR gate unit is connected to the reset end of the counter; The second delay unit is used to delay the first delay signal by a second set time to obtain a second delay signal; The second OR gate unit is used to perform an OR operation on the second delay signal and the counting window signal, and output the reset signal; The counter is used for resetting the count value at a transition edge at which the first level corresponding to the reset signal changes to the second level.
6. The counter system according to claim 1, characterized in that: The input module includes an AND gate unit, a first input end of the AND gate unit is connected to the oscillator output signal, a second input end of the AND gate unit is connected to the counting window signal, and an output end of the AND gate unit is connected to an input end of the counter, and is used for outputting the clock signal corresponding to the oscillator output signal to the counter when the oscillator output signal and the counting window signal are both at a first level.
7. The counter system according to claim 1, characterized in that: The counter includes at least two flip-flops connected in cascade.
8. The counter system according to claim 7, characterized in that The counter comprises a first cascade unit and a second cascade unit; The first cascade unit includes at least two cascaded first triggers, the second cascade unit includes at least two cascaded second triggers, and the first-stage second trigger of the second cascade unit is cascaded with the last-stage first trigger of the first cascade unit; The first trigger is a D-type trigger with a true single-phase clock structure.
9. A counting method of a counting system, characterized in that: The method comprises: The input module outputs a clock signal to the counter when the received counting window signal is at a first level; When the counting window signal is at a first level, the counter receives a clock signal to count; When the first level of the counting window signal jumps to the second level, the counter stops counting; The latch module delays a first set time after the first level of the connected counting window signal jumps to a second level, and latches the count value of the output end of the counter.
10. The counting method of the counting system according to claim 9, characterized in that: After the first level of the connected counting window signal jumps to the second level and the latch module latches the count value of the counter output end, the method further includes: after the second set time, the reset module resets the count value of the counter.