Analog-to-digital conversion circuit and image sensor

Abstract

The invention relates to an analog-to-digital conversion circuit and an image sensor, the analog-to-digital conversion circuit is connected to a buffer unit, the buffer unit comprises at least one buffer processing module and at least one buffer compensation module, and the buffer processing module comprises at least one first buffer circuit. The first buffer circuit is used for processing a first clock signal input to the first buffer circuit to obtain a second clock signal, and the rising time of the rising edge of the second clock signal is longer than the falling time of the falling edge of the second clock signal; the buffer compensation module comprises at least one second buffer circuit, the second buffer circuit is used for processing a second clock signal input to the second buffer circuit to obtain a third clock signal, and the rising time of the rising edge of the third clock signal is shorter than the falling time of the falling edge of the third clock signal. According to the invention, the second buffer circuit with the opposite effect can compensate the first buffer circuit with unbalanced pull-up and pull-down capabilities, so that the duty ratio of the clock signal meets the requirement.

Description

Technical Field

[0001] The present application relates to the field of buffer technology, and in particular to an analog-to-digital conversion circuit and an image sensor. Background Art

[0002] High-speed large-array image sensing systems currently have broad application prospects. Large-pixel large-array sensors are usually used in astronomy, in vivo imaging, x-rays, microscopes, and other fields. Astronomical scientists use large-array high-speed CMOS detectors to achieve astronomical observations; sports coaches use high-speed cameras to record the technical characteristics of athletes and improve training methods in a targeted manner; doctors use x-ray imaging to magnify images while maintaining high image quality to more accurately judge the patient's condition.

[0003] In large-array image sensors, signals, especially high-frequency clock signals, need to be transmitted over a long transmission line, which often encounters insufficient driving capability. Insufficient driving capability usually manifests itself in two situations: the first is insufficient output current, resulting in abnormal signal state, which often occurs when the subsequent circuit has requirements for input current; the other is insufficient output current, resulting in poor signal rise and fall edges, which often occurs when the input capacitance of the subsequent circuit is large. Usually, slew rate can be used as a parameter to measure the driving capability of a circuit. When the driving capability of a circuit is strong, the slew rate of the clock signal is large and the clock signal rises quickly; for circuits with weak driving capability, the slew rate of the clock signal is small and the clock signal rises slowly.

[0004] In the related art, in a large array image sensor, there is a buffer composed of several inverters or similar structures. Since the CMOS inverter has the advantages of high input resistance, low input current, low power consumption and high speed, it can maintain the stability of the circuit, reduce circuit loss, effectively reduce the overall power consumption, and quickly amplify and output, thereby increasing the speed of the circuit.

[0005] However, in the related art, due to the incomplete matching of the CMOS inverter, the NMOS transistor is turned on when pulling down, and the leakage current when pulling down is not strictly equal to the leakage current when the PMOS transistor is turned on when pulling up, which will lead to inconsistent charging and discharging speeds of the inverter for the load capacitor, that is, the output signal rise time of the inverter is not equal to the output signal fall time. Therefore, in the inverter chain of the related art, the superposition of several identical inverters may make the difference between the signal rise time and fall time more obvious, and ultimately make the output signal duty cycle not meet the design requirements. Summary of the invention

[0006] In view of this, the present application proposes an analog-to-digital conversion circuit and an image sensor, which can enable a second buffer circuit with opposite effects to compensate for a first buffer circuit with unbalanced pull-up and pull-down capabilities, so that the duty cycle of the compensated clock signal meets the design requirements. In addition, due to the simple structure of the buffer unit, the use and switching of the buffer circuit can be minimized, the use area and process complexity can be reduced, and the power consumption can be reduced.

[0007] According to one aspect of the present application, there is provided an analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit is connected to a buffer unit, wherein the buffer unit includes at least one buffer processing module and at least one buffer compensation module, wherein the buffer processing module is connected to the buffer compensation module, wherein the buffer processing module includes at least one first buffer circuit, wherein the first buffer circuit is used to process a first clock signal input to the first buffer circuit to obtain a second clock signal, wherein the rise time of a rising edge of the second clock signal is greater than the fall time of a falling edge of the second clock signal; and the buffer compensation module includes at least one second buffer circuit, wherein the second buffer circuit is used to process the second clock signal input to the second buffer circuit to obtain a third clock signal, wherein the rise time of a rising edge of the third clock signal is less than the fall time of a falling edge of the third clock signal.

[0008] According to another aspect of the present application, an image sensor is provided. The image sensor includes a buffer unit and the analog-to-digital conversion circuit.

[0009] By using a first buffer circuit and a second buffer circuit of different types and opposite functions to form a buffer unit, the present application can enable the second buffer circuit with opposite effects to compensate the first buffer circuit with unbalanced pull-up and pull-down capabilities, so that the duty cycle of the compensated clock signal meets the design requirements. In addition, due to the simple structure of the buffer unit, the use and switching of the buffer circuit can be minimized, the use area and process complexity can be reduced, and the power consumption can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram showing a buffer of the related art.

[0011] Figure 2 A schematic diagram showing a buffer cascade of the related art.

[0012] Figure 3 A schematic diagram showing clock signals with different driving capabilities in the related art.

[0013] Figure 4 A block diagram of a buffer unit according to an embodiment of the present application is shown.

[0014] Figure 5A schematic diagram showing a first embodiment of a buffer unit according to an embodiment of the present application.

[0015] Figure 6 A schematic diagram showing a second embodiment of a buffer unit according to an embodiment of the present application.

[0016] Figure 7 A schematic diagram showing a third embodiment of a buffer unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0018] In the related art, when the driving capability is insufficient, a buffer needs to be added. The buffer is generally a circuit of inverter or similar structure with several stages of gradually increasing device size, so that the circuit can achieve the optimal power consumption delay product when obtaining the required driving capability. The buffer can actually be two inverters connected in series, which are often used in the clock path to increase the clock driving capability so that the clock signal has good rising and falling edges. The buffer used to increase the clock driving capability itself is a buffer with a small input load and a strong output driving capability. Therefore, it is easy for the front-stage circuit to drive the buffer, and it is also easier for the buffer to drive the back-stage circuit.

[0019] Figure 1 FIG. 2 is a schematic diagram showing a buffer of the related art. Figure 1 As shown, the buffer in the related art may include at least two inverters, and the inverter includes a pull-up transistor T1 and a pull-down transistor T2. Among them, the gate of the pull-up transistor T1 is connected to the gate of the pull-down transistor T2, and they receive the inverted input signal Vin together. One of the source and drain of the pull-up transistor T1 is connected to one of the source and drain of the pull-down transistor T2, and is used to transmit the inverted output signal Vout. The other of the source and drain of the pull-up transistor T1 is connected to the power supply VDD, and the other of the source and drain of the pull-down transistor T2 is connected to the ground GND. The pull-up transistor T1 and the pull-down transistor T2 are of different types. The pull-up transistor T1 is a P-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor, PMOS) type transistor, and the pull-down transistor T2 is an N-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor, NMOS) type transistor.

[0020] When the inverting input signal Vin is at a high level, since the pull-down transistor T2 is NMOS, the pull-down transistor T2 is turned on, and the pull-up transistor T1 is PMOS, the pull-up transistor T1 is turned off, so the inverting output signal Vout presents a GND potential, that is, a low level. When the inverting input signal Vin is at a low level, since the pull-down transistor T2 is NMOS, the pull-down transistor T2 is turned off, and the pull-up transistor T1 is PMOS, the pull-up transistor T1 is turned on, so the inverting output signal Vout presents a VDD potential, that is, a high level. From the overall perspective of the inverter, regardless of whether the inverting input signal Vin is at a high level or a low level, the potential of the inverting output signal Vout is always opposite to the potential of the inverting input signal Vin.

[0021] Considering the electron mobility of NMOS transistors and PMOS transistors, it is necessary to adjust the gate width of the P tube to be larger than the gate width of the N tube, and keep the gate length L consistent, so as to ensure that the driving current is basically consistent. If the MOS tube of the inverter is completely matched, that is, the pull-up and pull-down capabilities are exactly the same, then the size of the PMOS device must be 3 to 4 times the size of the NMOS, which will result in a larger silicon area. On the one hand, some silicon area is wasted, which creates unfavorable conditions for device miniaturization; on the other hand, the capacitive impedance of the device is increased, which increases the time delay of the inverter. Therefore, under normal circumstances, the MOS tube of the inverter is not completely matched.

[0022] Figure 2 FIG. 4 is a schematic diagram showing a buffer cascade of the related art. Figure 2 As shown, in the related art, multiple buffers can be cascaded in series to form a buffer chain. The input Vi of the buffer chain is a square wave signal. After the square wave signal is buffered by several buffers, the rise time and the fall time are inconsistent, which will cause the final output signal Vo to be distorted, so that the duty cycle of the output signal Vo does not meet the design requirements.

[0023] The main function of the buffer is to improve the driving ability of the driving circuit. After adding the buffer, the driving ability of the driving circuit is enhanced and can drive more loads. The driving ability can be measured by the steepness of the rising edge and / or falling edge of the signal. The steepness of the rising edge and / or falling edge of the signal is high, the driving ability of the driving circuit is strong; the steepness of the rising edge and / or falling edge of the signal is high, the driving ability of the driving circuit is weak.

[0024] Figure 3 Schematic diagram showing clock signals under different driving capabilities of the related art. Figure 3 As shown, when the driving capability of the driving circuit is strong, the slew rate of the clock signal CLKa is large and the clock signal rises quickly; when the driving capability of the driving circuit is weak, the slew rate of the clock signal CLKa is small and the clock signal rises slowly.

[0025] like Figure 3 As shown in the figure, the output signal does not change according to the exponential law for a period of time after the jump, but shows a linear slope with a constant slope. This is the so-called "slewing" large signal characteristic of the operational amplifier. The slope of the linear part is the slew rate, also known as the conversion rate. The slew rate can be the fastest rate at which the output voltage of the closed-loop amplifier changes. The slew rate can be expressed by the formula: SR = I / C L , where slew rate, I is the charge and discharge current, C L is the load capacitance.

[0026] The transmission line is equivalent to a load. The load capacitance increases with the length of the transmission line, and the slew rate decreases. L The charge and discharge current is equal to I. Under the premise of a certain output voltage, I = V / R L , where R L is the equivalent impedance, and V is the output voltage. It can be seen that the load resistance increases with the length of the transmission line, the charge and discharge current decreases, and the slew rate decreases. Therefore, the slew rate decreases with the length of the transmission line, and the driving capability of the circuit also decreases with the length of the transmission line.

[0027] Combination Figure 1-Figure 3 It can be seen that the process of clock signal transmission on a large-size image sensor chip will cause signal waveform distortion due to insufficient driving capability. Inserting a buffer can solve the problem of insufficient driving capability, but as the number of buffers increases, the duty cycle change is introduced, causing signal distortion. Specifically, due to the incomplete matching of the CMOS inverter, the NMOS transistor is turned on when pulling down, and the leakage current when pulling down is not strictly equal to the leakage current when the PMOS transistor is turned on when pulling up, which will lead to inconsistent charging and discharging speeds of the inverter for the load capacitance, that is, the output signal rise time of the inverter is not equal to the fall time of the output signal. Therefore, in the inverter chain of the related art, the superposition of several identical inverters may make the difference between the signal rise time and fall time more obvious, and ultimately make the output signal duty cycle not meet the design requirements.

[0028] In view of this, the present application provides an analog-to-digital conversion circuit, which is connected to a buffer unit. The buffer unit includes at least one buffer processing module and at least one buffer compensation module, and the buffer processing module is connected to the buffer compensation module, wherein the buffer processing module includes at least one first buffer circuit, the first buffer circuit is used to process a first clock signal input to the first buffer circuit to obtain a second clock signal, and the rising time of the rising edge of the second clock signal is greater than the falling time of the falling edge of the second clock signal; the buffer compensation module includes at least one second buffer circuit, the second buffer circuit is used to process the second clock signal input to the second buffer circuit to obtain a third clock signal, and the rising time of the rising edge of the third clock signal is less than the falling time of the falling edge of the third clock signal.

[0029] Figure 4 FIG. 2 is a block diagram of a buffer unit according to an embodiment of the present application. Figure 4 As shown, the present application proposes a buffer unit, which includes at least one buffer processing module 100 and at least one buffer compensation module 200 , wherein the buffer processing module 100 is connected to the buffer compensation module 200 .

[0030] The buffer processing module 100 includes at least one first buffer circuit 101, which is used to process a first clock signal input to the first buffer circuit 101 to obtain a second clock signal, wherein the rising time of the rising edge of the second clock signal is greater than the falling time of the falling edge of the second clock signal.

[0031] The buffer compensation module 200 includes at least one second buffer circuit 201, which is used to process the second clock signal input to the second buffer circuit 201 to obtain a third clock signal, and the rising time of the rising edge of the third clock signal is shorter than the falling time of the falling edge of the third clock signal.

[0032] exist Figure 4 In the embodiment, the first clock signal input to the first buffer circuit 101 is CLKa, the second clock signal output by the buffer processing module 100 to the buffer compensation module 200 is CLKb, and the third clock signal output by the buffer compensation module 200 is CLKc. The first clock signal CLKa can be a first clock signal, such as a square wave. The rising time of the rising edge of the second clock signal CLKb is greater than the falling time of the falling edge of the third clock signal, and the rising time of the rising edge of the third clock signal CLKc is less than the falling time of the falling edge of the third clock signal.

[0033] In one embodiment, the buffer processing module 100 is connected to a clock source for receiving at least one first clock signal. Optionally, the first clock signal is a square wave. The clock source may be a clock source of an image sensor or a clock source of other application fields. It is understood that the present application does not limit the specific source of the clock source.

[0034] The first clock signal is a periodic signal having a plurality of clock cycles. Each clock cycle includes a clock pulse, and the clock pulse includes a rising edge and a falling edge. The clock pulse is at a high level in a corresponding part of the clock cycle, and the first clock signal is at a low level for the rest of the time in the clock cycle. The duty cycle of the first clock signal can be represented by the ratio of the clock pulses in a single clock cycle to the clock cycle. Exemplarily, the duty cycle of the first clock signal is 50%. It can be understood that the duty cycle of the first clock signal can be set according to actual needs, and the present application does not limit this.

[0035] In one embodiment, the buffer processing module 100 may be one or more. The buffer compensation module 200 may be one or more. In some embodiments, the number of one of the buffer processing modules 100 and the buffer compensation module 200 may be more than two, and the number of the other may be more than one. For example, when the number of the buffer processing modules 100 is two, the number of the buffer compensation modules 200 may be one or more; and when the number of the buffer compensation modules 200 is two, the number of the buffer processing modules 100 may be one or more.

[0036] In one embodiment, the first buffer circuit 101 is used to process the first clock signal input to the first buffer circuit 101 to obtain a second clock signal, and the rising time of the rising edge of the second clock signal is greater than the falling time of the falling edge of the second clock signal. Therefore, after the first clock signal is processed by the first buffer circuit 101, the steepness of the signal will change, thereby causing the duty cycle of the second clock signal after being processed by the first buffer circuit 101 to change compared with the duty cycle of the first clock signal before being input to the first buffer circuit 101.

[0037] The second buffer circuit 201 is used to process the second clock signal input to the second buffer circuit 201 to obtain a third clock signal, wherein the rising time of the rising edge of the third clock signal is less than the falling time of the falling edge of the third clock signal. Similar to the first buffer circuit 101, after the second clock signal is processed by the second buffer circuit 201, the steepness of the signal will change, thereby causing the duty cycle of the third clock signal processed by the second buffer circuit 201 to change compared to the duty cycle of the second clock signal before being input to the second buffer circuit 201. The difference is that the change trend of the third clock signal processed by the second buffer circuit 201 is opposite to the change trend of the second clock signal processed by the first buffer circuit 101.

[0038] Since the first buffer circuit 101 and the second buffer circuit 201 are of different types and have opposite functions or effects, the second buffer circuit 201 with opposite effects can compensate for the first buffer circuit 101 with unbalanced pull-up and pull-down capabilities, so that the duty cycle of the compensated output signal meets the design requirements. In addition, since the structure of the buffer unit is simple, the use and switching of the buffer circuit can be minimized, the use area and process complexity can be reduced, and the power consumption can be reduced.

[0039] In one embodiment, the analog-to-digital conversion circuit includes a plurality of analog-to-digital converters (ADCs), the output end of the first buffer circuit and the output end of the second buffer circuit can be connected to an analog-to-digital converter, and the analog-to-digital converter is electrically connected to a load to drive the load to work. It can be understood that the number of analog-to-digital converters can be set as needed, and this application does not limit this.

[0040] In one embodiment, the buffer processing module includes at least two first buffer circuits 101, and the buffer compensation module includes at least two second buffer circuits 201, wherein at least two of the first buffer circuits 101 are connected in series with each other, and at least two of the second buffer circuits 201 are connected in series with each other.

[0041] Figure 5 A schematic diagram of a first embodiment of a buffer unit according to an embodiment of the present application is shown. Figure 5As shown, the buffer unit includes a first buffer processing module 100a and a first buffer compensation module 200a. The first buffer compensation module 200a is connected to the first buffer processing module 100a. The first buffer processing module 100a is used to receive a first clock signal CLK0 from a clock source and buffer the first clock signal CLK0 into a second clock signal CLK1. The duty cycle of the second clock signal CLK1 is a preset first duty cycle critical value. The first buffer compensation module 200a is used to buffer the second clock signal CLK1 into an intermediate clock signal CLK2. The duty cycle of the intermediate clock signal CLK2 is the same as the duty cycle of the first clock signal CLK0.

[0042] The buffer unit also includes a second buffer compensation module 200b, which is connected to the first buffer compensation module 200a. The second buffer compensation module 200b is used to buffer the intermediate clock signal CLK2 into a third clock signal CLK3, and the duty cycle of the third clock signal CLK3 is a preset second duty cycle critical value, and the second duty cycle critical value is greater than the first duty cycle critical value.

[0043] In one embodiment, the second duty cycle threshold value is the highest duty cycle threshold value that meets the design requirements, and the first duty cycle threshold value is the lowest duty cycle threshold value that meets the design requirements. The first duty cycle threshold value and the second duty cycle threshold value can be flexibly determined according to specific design requirements, and this application does not limit this.

[0044] exist Figure 5 In the embodiment, the buffer unit structure includes two different types of buffers, buffer A makes the rising time of the rising edge of the clock signal input to the buffer greater than the falling time of the falling edge of the clock signal, and buffer B makes the falling time of the falling edge of the clock signal input to the buffer greater than the rising time of the rising edge. After the first clock signal CLK0 in the form of a square wave passes through a certain number of buffers Buffer A, the duty cycle of the signal input to the ADC2 circuit reaches the minimum critical value required by the design. Then, buffer Buffer B is used to compensate the signal that reaches the minimum critical value until the duty cycle of the signal input to the ADC6 circuit reaches the highest critical value required by the design. In this way, the clock signal that reaches the critical value can be compensated by alternately using buffers Buffer A and buffers Buffer B.

[0045] It should be noted that in Figure 5In the figure, the duty cycle of the intermediate clock signal CLK2 input to ADC4 is the same as the duty cycle of the first clock signal CLK0, that is, the intermediate clock signal CLK2 input to ADC4 has been compensated to the form of a square wave, but in order to make the signal duty cycle reach the highest critical value required by the design, it is necessary to continue to use buffer B for compensation.

[0046] exist Figure 5 In the design, a buffer processing module and two buffer compensation modules are used to make the clock signal duty cycle reach the minimum critical value and the maximum critical value required by the design, and the signal duty cycle changes in sequence, the buffer switches less frequently, occupies a smaller area, and the chip process is simpler, and the production and use costs are also lower. In other words, Figure 5 The solution can minimize the use and switching of buffer circuits, reduce the usage area and process complexity of the chip, and reduce the power consumption of the buffer unit in the entire image sensor.

[0047] Figure 6 A schematic diagram showing a second embodiment of the buffer unit of the present application is shown. Figure 6 As shown, the buffer unit includes at least two buffer processing modules 100 and at least one buffer compensation module 200, and the at least two buffer processing modules 100 and the at least one buffer compensation module 200 are cross-connected.

[0048] The buffer unit includes a second buffer processing module 100b and a third buffer compensation module 200c, the third buffer compensation module 200c is connected to the second buffer processing module 100b, the second buffer processing module 100b is used to receive a first clock signal CLK0 from a clock source and buffer the first clock signal CLK0 into a fourth clock signal CLK4, the duty cycle of the fourth clock signal CLK4 is a preset first duty cycle critical value; the third buffer compensation module is used to buffer the fourth clock signal CLK4 into a fifth clock signal CLK5, the duty cycle of the fifth clock signal CLK5 is the same as the duty cycle of the first clock signal CLK0.

[0049] The buffer unit further includes a third buffer processing module 100c, which is connected to the third buffer compensation module 200c. The third buffer processing module 100c is used to buffer the fifth clock signal CLK5 into a sixth clock signal CLK6, and the duty cycle of the sixth clock signal CLK6 is the same as the duty cycle of the fourth clock signal CLK4.

[0050] exist Figure 6In the embodiment, buffer B performs incomplete compensation for the signal that reaches the critical value, so that the signal duty cycle can quickly reach the minimum critical value required by the design.

[0051] Figure 7 FIG. 2 is a schematic diagram showing a third embodiment of a buffer unit according to an embodiment of the present application. Figure 7 As shown, the buffer processing module includes a first buffer circuit 101, the buffer compensation module includes a second buffer circuit 201, and a plurality of the first buffer circuits 101 and a plurality of the second buffer circuits 201 are alternately connected.

[0052] The buffer unit includes a plurality of fourth buffer processing modules 100d and a plurality of fourth buffer compensation modules 200d, wherein the fourth buffer compensation module 200d is connected to the fourth buffer processing module 100d, and the fourth buffer processing module 100d is used to receive a first clock signal CLK0 from a clock source and buffer the first clock signal CLK0 into a seventh clock signal CLK7, wherein the duty cycle of the seventh clock signal CLK7 is a preset first duty cycle critical value; the fourth buffer compensation module 200d is used to buffer the seventh clock signal CLK7 into an eighth clock signal CLK8, wherein the duty cycle of the eighth clock signal CLK8 is the same as the duty cycle of the first clock signal CLK0.

[0053] exist Figure 7 In the example, once buffer A changes the duty cycle of the signal, buffer B immediately compensates the changed buffer to the ideal state. In this way, the switching of the buffer circuit is faster.

[0054] In one embodiment, the buffer unit may be connected to a processor, and the processor may output a buffer control signal for controlling the number of buffers that need to be connected to the buffer unit, thereby adjusting the duty cycle of the second clock signal or the duty cycle of the third clock signal. It is understood that the present application does not limit the specific number of buffers in the buffer unit, and it can be selected according to actual needs.

[0055] Wherein, when the number of buffers connected to the first buffer circuit increases, the duty cycle of the second clock signal decreases, and in this case, the first duty cycle critical value is smaller. When the number of buffers connected to the second buffer circuit increases, the duty cycle of the third clock signal increases, and in this case, the second duty cycle critical value is larger.

[0056] In summary, the present application uses a first buffer circuit and a second buffer circuit of different types and opposite functions to form a buffer unit, so that the second buffer circuit with opposite effects can compensate the first buffer circuit with unbalanced pull-up and pull-down capabilities, so that the duty cycle of the compensated clock signal meets the design requirements. In addition, due to the simple structure of the buffer unit, the use and switching of the buffer circuit can be minimized, the use area and process complexity can be reduced, and the power consumption can be reduced.

[0057] In addition, the present application also provides a global buffer system, which includes the buffer unit, and the output ends of each first buffer circuit and the output ends of each second buffer circuit of the buffer unit are connected to different analog-to-digital converters. Since the buffer unit is composed of first buffer circuits and second buffer circuits of different types, the duty cycle of the compensated clock signal can meet the design requirements. In addition, since the structure of the buffer unit is simple, the use and switching of the buffer circuit can be minimized, the use area and process complexity can be reduced, and the power consumption can be reduced. In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0058] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0059] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. Although the present application has been described in examples with different focuses on the description of each embodiment, for the parts not described in detail in a certain embodiment, reference can be made to the relevant effective embodiments of other embodiments. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that: The analog-to-digital conversion circuit is connected to a buffer unit, which includes at least one buffer processing module and at least one buffer compensation module. The buffer processing module is connected to the buffer compensation module, wherein the buffer processing module includes at least one first buffer circuit, which is used to process a first clock signal input to the first buffer circuit to obtain a second clock signal, and the rise time of the rising edge of the second clock signal is greater than the fall time of the falling edge of the second clock signal; the buffer compensation module includes at least one second buffer circuit, which is used to process the second clock signal input to the second buffer circuit to obtain a third clock signal, and the rise time of the rising edge of the third clock signal is less than the fall time of the falling edge of the third clock signal.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The buffer processing module includes at least two first buffer circuits, wherein at least two first buffer circuits are connected in series with each other.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The buffer compensation module includes at least two second buffer circuits, wherein at least two second buffer circuits are connected in series with each other.

4. The analog-to-digital conversion circuit according to claim 3, characterized in that: The buffer unit includes a first buffer processing module, which is used to receive a first clock signal from a clock source and buffer the first clock signal into a second clock signal, wherein the duty cycle of the second clock signal is a preset first duty cycle critical value.

5. The analog-to-digital conversion circuit according to claim 4, characterized in that: The buffer unit also includes a first buffer compensation module, which is connected to the first buffer processing module and is used to buffer the second clock signal into an intermediate clock signal, and the duty cycle of the intermediate clock signal is the same as the duty cycle of the first clock signal.

6. The analog-to-digital conversion circuit according to claim 5, characterized in that: The buffer unit also includes a second buffer compensation module, which is connected to the first buffer compensation module. The second buffer compensation module is used to buffer the intermediate clock signal into a third clock signal, and the duty cycle of the third clock signal is a preset second duty cycle critical value, and the second duty cycle critical value is greater than the first duty cycle critical value.

7. The analog-to-digital conversion circuit according to claim 3, characterized in that: The buffer unit includes at least two buffer processing modules and at least one buffer compensation module, and the at least two buffer processing modules and the at least one buffer compensation module are cross-connected.

8. The analog-to-digital conversion circuit according to claim 7, characterized in that: The buffer unit includes a second buffer processing module, which is used for receiving a first clock signal from a clock source and buffering the first clock signal into a fourth clock signal, wherein the duty cycle of the fourth clock signal is a preset first duty cycle critical value.

9. The analog-to-digital conversion circuit according to claim 8, characterized in that: The buffer unit also includes a third buffer compensation module, which is connected to the second buffer processing module and is used to buffer the fourth clock signal into a fifth clock signal, and the duty cycle of the fifth clock signal is the same as the duty cycle of the first clock signal.

10. The analog-to-digital conversion circuit according to claim 9, characterized in that: The buffer unit also includes a third buffer processing module, which is connected to the third buffer compensation module and is used to buffer the fifth clock signal into a sixth clock signal, and the duty cycle of the sixth clock signal is the same as the duty cycle of the fourth clock signal.

11. The analog-to-digital conversion circuit according to claim 1, characterized in that: The buffer processing module includes a first buffer circuit, the buffer compensation module includes a second buffer circuit, and a plurality of the first buffer circuits and a plurality of the second buffer circuits are connected in an alternating manner.

12. The analog-to-digital conversion circuit according to claim 11, characterized in that: The buffer unit includes a plurality of fourth buffer processing modules. The fourth buffer processing modules are used to receive a first clock signal from a clock source and buffer the first clock signal into a seventh clock signal. The duty cycle of the seventh clock signal is a preset first duty cycle critical value.

13. The analog-to-digital conversion circuit according to claim 12, characterized in that: The buffer unit also includes multiple fourth buffer compensation modules, which are connected to the fourth buffer processing module. The fourth buffer compensation module is used to buffer the seventh clock signal into an eighth clock signal, and the duty cycle of the eighth clock signal is the same as the duty cycle of the first clock signal.

14. The analog-to-digital conversion circuit according to any one of claims 1 to 13, characterized in that: The analog-to-digital conversion circuit includes a plurality of analog-to-digital converters. The output end of the first buffer circuit and the output end of the second buffer circuit are both connected to one of the analog-to-digital converters. The analog-to-digital converter is electrically connected to a load to drive the load to work.

15. The analog-to-digital conversion circuit according to any one of claims 1 to 13, characterized in that: The buffer unit is connected to a processor, and the processor is used to output a buffer control signal, and the buffer control signal is used to control the number of buffers connected to the buffer unit to adjust the duty cycle of the second clock signal or the duty cycle of the third clock signal.

16. The analog-to-digital conversion circuit according to claim 15, characterized in that: When the number of buffers connected to the first buffer circuit increases, the duty cycle of the second clock signal decreases.

17. The analog-to-digital conversion circuit according to claim 15, characterized in that: When the number of buffers connected to the second buffer circuit increases, the duty cycle of the third clock signal increases.

18. An image sensor, characterized in that: The image sensor comprises a buffer unit and an analog-to-digital conversion circuit as claimed in any one of claims 1 to 17.

Images