Turbo Code Decoder, Decoding Method and Beidou Receiver Adopting a New Architecture

Abstract

The present invention relates to a Turbo code decoder, a decoding method, and a Beidou receiver adopting a new architecture. The decoder includes: a first interleaver that performs interleaving processing on the input systematic bit soft information and outputs the systematic bit soft information; a second interleaver that performs interleaving processing on the L12 information output by the first decoder and outputs the L12 information; a deinterleaver that performs deinterleaving processing on the L21 information output by the second decoder and outputs the L21 information; a second decoder that calculates the L21 information and the LLR information according to the systematic bit soft information, the L12 information, and the parity bit 2 soft information; a first decoder that calculates the L12 information according to the input parity bit 1 soft information, the systematic bit soft information, and the deinterleaved L21 information; and a decision module that makes a decision on the LLR information satisfying the stop iteration condition and outputs the Turbo code decoding result. The present invention adopts a new decoder architecture, shortening the operation duration and improving the decoding efficiency.

Description

Technical Field

[0001] The present invention relates to the technical fields of decoding and satellite navigation, and particularly to a Turbo code decoder, a decoding method, and a Beidou receiver adopting a new architecture. Background Art

[0002] Turbo code is a channel error correction coding scheme that can approach the Shannon limit. Many communication systems, such as voice coding and decoding, and 3G and 4G mobile communication systems supported by 3GPP, have adopted Turbo code as their channel coding scheme. In recent years, with the popularity of LDPC code and Polar code, 5G NR has adopted LDPC code and Polar code as its channel coding scheme. However, many communication systems, especially some satellite communication systems, such as the RDSS subsystem in the Beidou satellite navigation system BDS in China, still adopt the Turbo code coding scheme due to the good performance shown by the Turbo code scheme.

[0003] However, the decoder architecture of traditional Turbo code has a phenomenon of relatively high complexity. For example, after the last iteration process, to output the hard-decision systematic bits, after the internal operations of the second decoder are completed, a deinterleaving operation still needs to be performed, which is unnecessary and also prolongs the module operation time of the decoder. Summary of the Invention

[0004] In view of the above analysis, the present invention aims to disclose a Turbo code decoder, a decoding method, and a Beidou receiver adopting a new architecture, and improve the decoder architecture to solve the problem of the module operation time of traditional Turbo code and improve the decoding efficiency.

[0005] On the one hand, the present invention discloses a Turbo code decoder adopting a new architecture, which is used to decode the coding information without tail bits, and includes: a first decoder, a second decoder, a first interleaver, a second interleaver, a deinterleaver, and a decision module;

[0006] The first interleaver is used to perform interleaving processing on the input systematic bit soft information and output the interleaved systematic bit soft information;

[0007] The second interleaver is used to perform interleaving processing on the L12 information output by the first decoder and output the interleaved L12 information;

[0008] The deinterleaver is used to perform deinterleaving processing on the L21 information output by the second decoder and output the deinterleaved L21 information;

[0009] The second decoder is used to calculate the L21 information and the LLR information according to the interleaved systematic bit soft information, the L12 information, and the parity bit 2 soft information;

[0010] A first decoder, configured to calculate L12 information according to the input soft information of parity bit 1, soft information of systematic bits, and de-interleaved L21 information;

[0011] A decision module, configured to perform a decision on the LLR information that meets the stop iteration condition and output the Turbo code decoding result.

[0012] Another aspect of the present invention also discloses a decoding method based on a Turbo code decoder adopting a new architecture as described above, including the following steps:

[0013] Step S1, obtaining the soft information corresponding to systematic bits, parity bit 1, and parity bit 2; setting the decoding iteration times;

[0014] Step S2, performing an interleaving process on the soft information of systematic bits, and sending the output result of the interleaver to a second decoder;

[0015] Step S3, performing the operation of the second decoder; inputting the soft information of parity bit 2, the interleaved soft information of systematic bits, and the interleaved L12 information sent from the first decoder into the second decoder to calculate and output the external information L21 information sent to the de-interleaver; the initial value of the L21 information is an all-zero sequence;

[0016] Step S4, performing the operation of the first decoder; inputting the soft information of parity bit 1, the soft information of systematic bits, and the de-interleaved L21 information into the first decoder to calculate and output the external information L12 information sent to a second interleaver, and the LLR information; the LLR information corresponds to the systematic bits;

[0017] Step S5, jumping to Step S3, performing the operation of the sub-second decoder, and then performing the operation of the first decoder, and iteratively performing in this way until the preset maximum iteration times are reached;

[0018] Step S6, performing a hard decision on the LLR information output by the first decoder and outputting the Turbo code decoding result.

[0019] Another aspect of the present invention also discloses another Turbo code decoder adopting a new architecture, configured to decode encoded information including tail bits, including:

[0020] Including: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module, and a decision module; wherein, the first and second decoders are both tail bit sub-decoders;

[0021] A first decoder, configured to calculate first LLR information according to the input soft information of parity bit 1 including tail bits, L21 information, and first soft information of systematic bits;

[0022] A second decoder, configured to calculate second LLR information according to input parity bit 2 soft information including tail bits, L12 information, and second system bit soft information;

[0023] The second system bit soft information is the soft information obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the soft information of the tail bits;

[0024] An L12 calculation module, configured to perform extrinsic information calculation, interleaving, and zero-padding on the first LLR information and then output L12 information including tail bits;

[0025] An L21 calculation module, configured to perform extrinsic information calculation, deinterleaving, and zero-padding on the second LLR information and then output L21 information including tail bits;

[0026] A decision module, configured to make a decision on the first LLR information that meets the stop iteration condition and output the Turbo code decoding result.

[0027] Another aspect of the present invention also discloses a decoding method based on another Turbo code decoder adopting a new architecture as described above, including the following steps:

[0028] Step S1: Obtain the first system bit soft information with a length of K+T input by the system, the parity bit 1 soft information and the parity bit 2 soft information both with a length of K+T; initialize the L21 information and L12 information with a length of K+T; set the decoding iteration times;

[0029] Step S2: Interleave the first K data of the first system bit soft information, and then perform a concatenation process with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information;

[0030] Step S3: Execute the operation of the second decoder, input the parity bit 2 soft information, L12 information, and second system bit soft information into the second decoder to calculate the second LLR information; input the second LLR information into the L21 calculation module to perform extrinsic information calculation, deinterleaving, and zero-padding, and then output L21 information including tail bits;

[0031] Step S4: Execute the operation of the first decoder, input the parity bit 1 soft information, L21 information, and first system bit soft information into the first decoder to calculate the first LLR information; input the first LLR information into the L12 calculation module to perform extrinsic information calculation, interleaving, and zero-padding, and then output L12 information including tail bits;

[0032] Step S5: Jump to Step S3, execute the operation of the sub-second decoder, and then execute the operation of the first decoder, and iterate in this way until the preset maximum iteration times are reached;

[0033] Step S6: Perform hard decision on the first LLR information output by the first decoder to output the Turbo code decoding result.

[0034] On the other hand, the present invention also discloses a Beidou receiver. The Beidou receiver receives the signals of the RDSS subsystem in the Beidou satellite navigation system BDS. When performing Turbo code decoding, it uses a Turbo code decoder with a new architecture as described above to decode the coded information without tail bits; or uses another Turbo code decoder with a new architecture as described above to decode the coded information with tail bits.

[0035] One of the beneficial effects that the present invention can achieve is as follows:

[0036] The Turbo code decoder, decoding method, and Beidou receiver with a new architecture disclosed by the present invention adopt a new decoder architecture to decode the coded information without tail bits. By adjusting the processing order of the two sub-decoders, the first decoder and the second decoder, the redundant operation of still needing to execute a deinterleaver before the decision module is avoided, the execution time is reduced, and the processing efficiency is improved.

[0037] When using a new decoder architecture to decode the coded information with tail bits, by adjusting the processing order of the two sub-decoders, the first decoder and the second decoder, the redundant operation of still needing to execute a deinterleaver before the decision module is avoided, the execution time is reduced, and the processing efficiency is improved; at the same time, the tail bit information of the Turbo code is used for decoding, improving the performance of the decoder; it is applicable to reliable data transmission under relatively low signal-to-noise ratio (SNR) conditions and can gradually improve the decoding accuracy through iteration. Description of the Drawings

[0038] The drawings are only for the purpose of showing specific embodiments and are not considered as limitations of the present invention. Throughout the drawings, the same reference signs denote the same components;

[0039] Figure 1 It is a schematic diagram of the encoding scheme of the Turbo code in the embodiment of the present invention;

[0040] Figure 2 It is a schematic diagram of the encoder architecture of the commonly used Turbo code listed in the embodiment of the present invention;

[0041] Figure 3 It is a connection schematic diagram of a Turbo code decoder with a new architecture in the embodiment of the present invention;

[0042] Figure 4 It is a flowchart of the decoding method of a Turbo code decoder with a new architecture in the embodiment of the present invention;

[0043] Figure 5 A schematic diagram of coding of a Turbo code used in a CDMA2000 system in an embodiment of the present invention;

[0044] Figure 6 is a schematic diagram of a signal processing structure of a sub-encoder in an embodiment of the present invention;

[0045] Figure 7 A schematic diagram of the connection components of another Turbo code decoder using a new architecture in an embodiment of the present invention;

[0046] Figure 8 This is a flow chart of another decoding method of a Turbo code decoder using a new architecture in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0048] Embodiment 1

[0049] An embodiment of the present invention discloses a Turbo code decoder using a new architecture, which is used to decode coded information that does not contain tail bits.

[0050] like Figure 1 As shown in FIG. 1 , the coding scheme of the Turbo code corresponding to the decoder of this embodiment mainly includes two sub-encoders, an interleaver, and a rate matching module. The rate matching module mainly performs the puncturing function, which punctures some check bits or repeated system bits to meet the requirements of the transmission data rate. We usually use Figure 2 The upper sub-encoder is called sub-encoder 1, and the lower sub-encoder is called sub-encoder 2. The structures of the two sub-encoders are the same, and they also output systematic bits and check bits, so the structures of their corresponding sub-decoders are also the same. The difference from sub-encoder 1 is that the input bits of sub-encoder 2 are interleaved.

[0051] It should be pointed out that in the solution of the embodiment of the present invention, rate matching is not the focus, and therefore, the rate matching solution submodule is not involved.

[0052] like Figure 2 The following is a commonly used Turbo code encoder architecture; the sub-decoder 1 corresponds to Figure 1 Sub-encoder 1 and sub-decoder 2 in Figure 2 Subcoder 2 in; Interleaver scheme and Figure 1 The interleaver scheme in is consistent with that in; the deinterleaver corresponds to Figure 1 The interleaver in is the reverse process.

[0053] Figure 2 Among them,

[0054] The soft information of parity bit 1 refers to the soft information corresponding to the parity bit of sub - decoder 1, which may contain multiple juxtaposed parity bits;

[0055] The soft information of systematic bit refers to the bit with the same value as the input bit of the sub - encoder;

[0056] The soft information of parity bit 2 refers to the soft information corresponding to the parity bit of sub - decoder 2;

[0057] The soft information can generally be represented by the log - likelihood ratio (LLR);

[0058] L12 refers to the extrinsic information passed from sub - decoder 1 to sub - decoder 2. Similarly, L21 refers to the extrinsic information passed from sub - decoder 2 to sub - decoder 1.

[0059] Figure 2 Sub - decoder 2 in [] outputs two types of information, one is the extrinsic information, and the other is the LLR information corresponding to the systematic bit.

[0060] During the decoding process, according to the processing order of first sub - decoder 1 and then sub - decoder 2, based on the input extrinsic information (the initial value can be set to all 0), the soft information of the systematic bit corresponding to the systematic bit, and the soft information of the parity bit corresponding to the parity bit, after trellis inference and calculation, the extrinsic information to be transmitted and the soft information of the corresponding systematic bit are output. Then, after the processing of the interleaver and de - interleaver, the extrinsic information is iteratively transmitted between the two sub - decoders. After multiple iterations, the LLR information output by sub - decoder 2 is de - interleaved and then hard - decision is performed to obtain the output bits of the decoder.

[0061] After analyzing the decoder architecture of the traditional Turbo code, the following conclusions are obtained:

[0062] There are some unreasonable parts and a relatively high complexity in the decoder architecture of the traditional Turbo code. For example, after the last iteration process, to output the hard - decision systematic bit, after the internal operations of sub - decoder 2 are completed, a de - interleaving operation is still required, which is unnecessary and also prolongs the module operation time of the decoder.

[0063] To address the technical problems of the decoder architecture of the traditional Turbo code, a Turbo code decoder with a new architecture proposed in this embodiment, as Figure 3 shown, includes:

[0064] A first decoder, a second decoder, a first interleaver, a second interleaver, a de - interleaver, and a decision module;

[0065] A first interleaver for interleaving the input system bit soft information and outputting the interleaved system bit soft information;

[0066] A second interleaver for interleaving the L12 information output by the first decoder and outputting the interleaved L12 information;

[0067] A deinterleaver for deinterleaving the L21 information output by the second decoder and outputting the deinterleaved L21 information;

[0068] A second decoder for calculating the L21 information and the LLR information according to the interleaved system bit soft information, the L12 information, and the parity bit 2 soft information;

[0069] A first decoder for calculating the L12 information according to the input parity bit 1 soft information, the system bit soft information, and the deinterleaved L21 information;

[0070] The decision module is used to make a decision on the LLR information that meets the stop iteration condition and output the Turbo code decoding result.

[0071] Specifically, the lengths of the input information of the first and second decoders are both K, which is the same as the length of the encoded input data block; decoding algorithms including the log-map algorithm and the max-log-map algorithm are adopted in the first and second decoders, and the operation loops K times, and the LLR information output by the first decoder;

[0072] During the decoding process, first perform the decoding operation of the second decoder to obtain the L21 information; after deinterleaving the L21 information in the deinterleaver, input it to the first decoder for decoding operation to obtain the L12 information; perform the decoding operation of the second decoder again; iterate in this way until the maximum number of iterations is met; the decision module makes a decision on the LLR information output by the first decoder and outputs the Turbo code decoding result.

[0073] In the LLR output of the first decoder in this embodiment, it can be directly output as the output bit of the entire decoder through the decision module; there is no need for re-deinterleaving as in the traditional decoding architecture.

[0074] Therefore, in the decoder architecture of this embodiment, by adjusting the processing order of the first decoder and the second sub-decoder, the redundant operation of the deinterleaver before the decision module is avoided, the execution time is reduced, and the processing efficiency is improved.

[0075] Moreover, it can be additionally pointed out that external information such as L12 information is also calculated from the LLR. In fact, it can be considered that the decoder only outputs the LLR item. If external information is needed, the step of calculating external information from the LLR information is then executed.

[0076] Embodiment 2

[0077] This embodiment discloses a decoding method using the Turbo code decoder with a new architecture disclosed in Embodiment 1, as Figure 4 shown, including the following steps:

[0078] Step S1: Obtain the soft information corresponding to the systematic bits, parity bits 1 and 2; set the number of decoding iterations;

[0079] Step S2: Interleave the systematic bit soft information, and send the output result of the interleaver to the second decoder;

[0080] Step S3: Perform the operation of the second decoder; input the parity bit 2 soft information, the interleaved systematic bit soft information, and the interleaved L12 information sent from the first decoder into the second decoder to calculate and output the external information L21 information sent to the deinterleaver; the initial value of the L21 information is an all-zero sequence;

[0081] Step S4: Perform the operation of the first decoder; input the parity bit 1 soft information, the systematic bit soft information, and the deinterleaved L21 information into the first decoder to calculate and output the external information L12 information sent to the second interleaver, and the LLR information; the LLR information corresponds to the systematic bits;

[0082] Step S5: Jump to Step S3, perform the operation of the sub-second decoder, and then perform the operation of the first decoder, and iterate in this way until the preset maximum number of iterations is reached;

[0083] Step S6: Perform a hard decision on the LLR information output by the first decoder to output the Turbo code decoding result.

[0084] The specific technical details and beneficial effects in this embodiment are the same as those described in Embodiment 1. Please refer to them specifically and will not be elaborated here one by one.

[0085] Embodiment 3

[0086] An embodiment of the present invention discloses a Turbo code decoder with a new architecture for decoding encoded information including tail bits.

[0087] As Figure 5The encoding of Turbo codes adopted by the CDMA2000 system shown; for each input information bit, each sub-encoder of the encoder outputs three bits, X, Y, and Z, where X is the systematic bit, and both Y and Z are parity bits. The systematic bit is the bit with the same value as the input bit of the sub-encoder; however, the X bit sequence may contain tail bits in addition to the bit sequence input to the sub-encoder.

[0088] The signal processing structures of the two sub-encoders are the same. For details, please refer to Figure 6 .

[0089] As Figure 6 shown, for each input bit I of the sub-encoder, three bits X, Y, and Z are output. Assuming that the length of each information data block, i.e., the sequence of encoded input bits I, is K, then Figure 1 and Figure 2 the length of the interleaver in Figure 2 is also K. However, due to the encoding mechanism of the tail bits, the lengths of the three output sequences X, Y, and Z of the sub-encoder are all K + T. Among them, the length of the tail bit sequence corresponding to each output bit sequence is denoted as T (as Figure 2 where T = 3).

[0090] Additionally, before performing Turbo code encoding on each block of data, the initial values of the three registers in Figure 3 are set to 0.

[0091] Specifically, taking Figure 6 as an example, in the generation scheme of the tail bits, when the sequence of input bits I, i.e., the first K bits, is input, the switch branch is closed with the upper branch for encoding, and three output bit sequences X, Y, and Z with a length of K are generated respectively; then, the switch branch is switched to the lower branch and closed with the lower branch, and the sub-encoder continues to operate to generate three tail bit sequences with a length of T (here T = 3) respectively, and are appended to the X, Y, and Z sequences respectively. Finally, the lengths of the X, Y, and Z sequences are all K + T, i.e., all K + 3 bits. The role of the tail bits is to finally zero the trellis of the sub-encoder, which is beneficial for the receiver to correctly decode. Therefore, the tail bit sequence also carries non-negligible useful information.

[0092] For the decoding of the encoded information including the tail bits, a Turbo code decoder with a new architecture proposed in this embodiment, as Figure 7 shown, includes:

[0093] including: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module, and a decision module; among them, the first and second decoders are both tail bit sub-decoders;

[0094] A first decoder, configured to calculate first LLR information according to input check bit 1 soft information including tail bits, L21 information, and first system bit soft information;

[0095] A second decoder, configured to calculate second LLR information according to input check bit 2 soft information including tail bits, L12 information, and second system bit soft information;

[0096] The second system bit soft information is the soft information obtained by interleaving the information before the tail bits of the first system bit soft information and then splicing the tail bits;

[0097] An L12 calculation module, configured to perform extrinsic information calculation, interleaving, and zero-padding on the first LLR information and then output L12 information including tail bits;

[0098] An L21 calculation module, configured to perform extrinsic information calculation, de-interleaving, and zero-padding on the second LLR information and then output L21 information including tail bits;

[0099] A decision module, configured to make a decision on the first LLR information that meets the stop iteration condition and output the Turbo code decoding result.

[0100] Specifically, both the first and second decoders are tail bit sub-decoders; the length of the input information of the tail bit sub-decoder is K + T; K is the length of the encoded input data block, and T is the data length of the tail bits; decoding algorithms including the log-map algorithm and the max-log-map algorithm are adopted in the tail bit sub-decoder, and the decoding operation is looped K + T times to obtain the decoded output LLR information;

[0101] During the decoding process, first perform the decoding operation of the second decoder to obtain L21 information; input the L21 information into the first decoder for decoding operation to obtain L12 information; perform the decoding operation of the second decoder again; iterate in this way until the maximum number of iterations is met; the decision module makes a decision on the LLR information output by the first decoder and outputs the Turbo code decoding result.

[0102] Specifically, the input information of the first decoder in this embodiment is check bit 1 soft information including tail bits, L21 information, and first system bit soft information with a length of K + T;

[0103] Among them, the check bit 1 soft information and the first system bit soft information are the information for decoding input by the system; the L21 information is the extrinsic information with a length of K + T calculated by the L21 calculation module;

[0104] In this embodiment, the input information of the second bit sub-decoder includes the check bit 2 soft information with tail bits, which is K + T in length, the L12 information; and the second systematic bit soft information obtained by interleaving the information before the tail bits and then concatenating the tail bit soft information;

[0105] Among them, the check bit 2 soft information is the information for decoding transmitted by the system; the L12 information is the external information with a length of K + T calculated by the L12 calculation module;

[0106] The solution in this embodiment further includes: a first interleaver and a splicer for generating the second systematic bit soft information;

[0107] The first interleaver is a K-bit interleaver; it is used to interleave the first K bit soft information of the first systematic bit soft information and output the interleaved data to the splicer;

[0108] The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first systematic bit soft information together and output the second systematic bit soft information.

[0109] Specifically, the L12 calculation module includes a first external information calculation module, a second interleaver, and a first zero-padding module;

[0110] The first external information calculation module is used to access the first K data of the first LLR information with a length of K + T output by the first decoder, discard the last T data, and perform calculations using the first K data of the first LLR information to remove the influence of the prior information and the systematic bit soft information, so as to obtain pure external information with a length of K;

[0111] The calculation method of the external information is:

[0112] ;

[0113] Among them, LLR ext1 is the external information output by the first external information calculation module in the current calculation, LLR1 is the first LLR information output by the first decoder, LLR sys1 is the first systematic bit soft information input to the first decoder, and LLR a1 is the external information input to the first decoder;

[0114] The second interleaver is a K-bit interleaver, which is used to interleave the external data with a length of K output by the first external information calculation module;

[0115] The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver and output the L12 information with a length of K + T as the external information input to the second decoder.

[0116] Specifically, the L21 calculation module includes a second external information calculation module, a deinterleaver, and a second zero-padding module;

[0117] The second external information calculation module is configured to access the first K data of the second LLR information with a length of K + T output by the second decoder, discard the last T data, perform calculations using the first K data of the second LLR information, and remove the influence brought by the prior information and the system bit soft information, so as to obtain pure external information with a length of K;

[0118] The calculation method of the external information is as follows:

[0119] ;

[0120] where LLR ext2 is the external information output by the second external information calculation module in the current calculation, LLR2 is the second LLR information output by the second decoder, LLR sys2 is the second system bit soft information input to the second decoder, and LLR a2 is the external information input to the second decoder;

[0121] The deinterleaver is a K-bit deinterleaver, which is configured to deinterleave the external data with a length of K output by the second external information calculation module;

[0122] The second zero-padding module is configured to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K + T as the external information input to the first decoder.

[0123] The purpose of the calculation formula of the external information is to remove the influence brought by the prior information and the system bit soft information in the LLR information output by the first and second decoders, so as to obtain pure external information. This part of information will be transmitted to the next sub-decoder to improve the performance of the entire Turbo decoding process.

[0124] The input end of the decision module is connected to the output end of the first decoder, and it makes a decision on the first LLR information that meets the stop iteration condition and outputs the Turbo code decoding result;

[0125] The stop iteration condition is that the iteration reaches the preset maximum number of iterations.

[0126] In the decoding operation of the tail bit sub-decoder of the solution in this embodiment, the input data length is all K + T. Therefore, the operation loop in the tail bit sub-decoder is K + T times, rather than the K times loop of the traditional sub-decoder;

[0127] Referring to the max - log - map decoding algorithm, the tail - bit sub - decoder needs to perform the following operations:

[0128] 1) Initialize variables; the variables include branch metrics, forward state metrics, backward state metrics, and output LLR values, all of which are initialized to zero vectors;

[0129] 2) Perform backward iteration; perform bit - by - bit calculation on the input information from the back to the front for K + T times to obtain branch metrics gamma and backward state metrics beta;

[0130] Among them, the initial value of the backward state metrics utilizes the trellis 0 - state information brought by the tail bits;

[0131] 3) Perform forward iteration; perform bit - by - bit calculation on the input information from the front to the back to obtain branch metrics gamma and forward state metrics alpha;

[0132] Among them, the initial value of the forward state metrics utilizes the state information that the initial value of the encoder register is 0;

[0133] 4) Calculate the output LLR information;

[0134] Calculate the LLR information using the forward state metrics alpha and the backward state metrics beta.

[0135] In the operation, the calculation methods of branch metrics gamma, backward state metrics beta, forward state metrics alpha, and LLR information can all refer to existing calculation methods.

[0136] In summary, the tail - bit decoding device of the Turbo code disclosed in this embodiment decodes using the tail - bit information of the Turbo code, improving the performance of the decoder; it is applicable to reliable data transmission under lower signal - to - noise ratio (SNR) conditions, and can gradually improve the decoding accuracy through iteration; moreover, by adopting a new decoder architecture and adjusting the processing order of the two sub - decoders, the first decoder and the second decoder, it avoids the redundant operation of still needing to execute a de - interleaver before the decision module, reduces the execution time, and improves the processing efficiency.

[0137] Embodiment Four

[0138] Another embodiment of the present invention discloses a decoding method using the Turbo code decoder with a new architecture disclosed in Embodiment Three, as Figure 8 shown, including the following steps:

[0139] Step S1: Obtain the first system bit soft information of length K+T input by the system, the parity bit 1 soft information and the parity bit 2 soft information, both of length K+T; Initialize the L21 information and L12 information of length K+T; Set the number of decoding iterations.

[0140] Step S2: Interleave the first K data of the first system bit soft information, and then splice it with the last T tail bit soft information of the first system bit soft information to obtain the soft information of length K+T as the second system bit soft information.

[0141] Step S3: Perform the operation of the second decoder. Input the parity bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; Input the second LLR information into the L21 calculation module for external information calculation, deinterleaving and zero-padding, and then output the L21 information including tail bits.

[0142] Step S4: Perform the operation of the first decoder. Input the parity bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; Input the first LLR information into the L12 calculation module for external information calculation, interleaving and zero-padding, and then output the L12 information including tail bits.

[0143] Step S5: Jump to Step S3, perform the operation of the sub-second decoder, and then perform the operation of the first decoder. Iterate in this way until the preset maximum number of iterations is reached.

[0144] Step S6: Perform hard decision on the first LLR information output by the first decoder to output the Turbo code decoding result.

[0145] Specifically, the external information calculation methods in the L12 calculation module and the L21 calculation module are as follows:

[0146] ;

[0147] Among them, LLR ext1 , LLR ext2 are the external information calculated by the L12 and L21 calculation modules in the current calculation respectively. LLR1 and LLR2 are the first and second LLR information output by the first and second decoders respectively. LLR sys1 , LLR sys2 are the first and second system bit soft information input to the first and second decoders respectively. LLR a1 , LLR a2 are the external information input to the first and second decoders.

[0148] The specific technical details and beneficial effects in this embodiment are the same as those described in Embodiment 1. Please refer to the specific content and will not be elaborated here one by one.

[0149] Embodiment 5

[0150] Another embodiment of the present invention discloses a Beidou receiver. The Beidou receiver receives the signals of the RDSS subsystem in the Beidou satellite navigation system BDS. When performing Turbo code decoding, it uses the Turbo code decoder with a new architecture in Embodiment 1 to decode the encoded information without tail bits; or uses the Turbo code decoder with a new architecture in Embodiment 3 to decode the encoded information with tail bits. This improves the decoding performance and efficiency.

[0151] The specific technical details and beneficial effects in this embodiment are the same as those described in the foregoing embodiments. Please refer to the specific content and will not be elaborated here one by one.

[0152] The above is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A Turbo code decoder using a new architecture for decoding coded information including tail bits, characterized in that: include: The invention comprises: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision module; wherein the first decoder and the second decoder are both tail bit sub-decoders; the length of the input information of the tail bit sub-decoder is K+T; K is the length of the encoded input data block, and T is the data length of the tail bit; the operation cycles in the tail bit sub-decoder are all K+T times; A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bit obtained by interleaving the information before the tail bit of the first system bit soft information and then concatenating the tail bit; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; A decision module, used for deciding the first LLR information that meets the iteration stop condition and outputting the Turbo code decoding result; It also includes: a first interleaver and a splicer, which are used to generate second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

2. The Turbo code decoder using a new architecture according to claim 1, characterized in that: The L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The second interleaver is a K-bit interleaver, used to interleave the external data with a length of K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

3. The Turbo code decoder using a new architecture according to claim 1, characterized in that: The L21 calculation module includes a second external information calculation module, a deinterleaver and a second zero padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The deinterleaver is a K-bit deinterleaver, used to deinterleave the external data with a length of K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

4. The Turbo code decoder using a new architecture according to claim 2 or 3, characterized in that: The calculation method of the external information is: ； Among them, LLR ext1 , LLR ext2 are the external information calculated by the first and second external information calculation modules at the current time, LLR1 and LLR2 are the first and second LLR information output by the first and second decoders, respectively. sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

5. A decoding method based on a Turbo code decoder using a new architecture as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; Input the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then output the L21 information including the tail bits; Step S4, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; Input the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then output the L12 information including the tail bits; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the first LLR information output by the first decoder to output a Turbo code decoding result.

6. A Beidou receiver, characterized in that: The Beidou receiver receives the RDSS subsystem signal in the Beidou satellite navigation system BDS, and when performing Turbo code decoding, uses the Turbo code decoder with a new architecture as described in any one of claims 1-4 to decode the coded information including tail bits.

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