Semiconductor structure and forming method thereof
By etching the hard mask layer on the bottom surface of the sidewall of the gate structure of the semiconductor device, the thickness is consistent with the rest of the sidewall, the problem of difficulty in completely removing the hard mask layer is solved, the parasitic capacitance is reduced, and the device performance is improved.
Patent Information
- Application Number
- CN202311342088.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-17
- Publication Date
- 2025-04-18
AI Technical Summary
In existing semiconductor devices, it is difficult to completely remove the hard mask layer, resulting in an increase in parasitic capacitance between the gate and the source and drain, affecting device performance.
Before forming the epitaxial layer, the hard mask layer covered by the bottom surface of the sidewall of the gate structure is etched so that its thickness is not greater than the thickness of the rest of the sidewall, and a process window for removing the hard mask layer is added to achieve complete removal.
By completely removing the hard mask layer, the parasitic capacitance is reduced and the device's operating speed and performance is improved.
Smart Images
Figure CN119855181A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] As the size of semiconductor devices shrinks, it is often necessary to use an embedded epitaxial layer in the source and drain regions of a substrate to change the stress in the channel region of the semiconductor device, thereby increasing the mobility of carriers and improving the performance of the device.
[0003] Taking PMOS devices as an example, the embedded epitaxial layer usually adopts a germanium silicon epitaxial layer. The existing germanium silicon module process is to first grow a hard mask layer on the surface of the gate, which is used to protect the gate and define the horizontal distance from the germanium silicon trench to the gate. Then, photolithography and etching are used to form a germanium silicon trench in the area where the germanium silicon is grown, and then the germanium silicon epitaxial layer is deposited in the germanium silicon trench by epitaxy. Finally, the hard mask layer is cleaned and removed.
[0004] However, in practical applications, it is always difficult to completely remove the hard mask layer. Since the hard mask layer has a large dielectric constant, it will increase the parasitic capacitance of the gate and the source and drain, affecting the device performance. Summary of the invention
[0005] The object of the present invention is to provide a semiconductor structure and a method for forming the same, so as to solve the problem of large parasitic capacitance between a gate structure and a source and a drain.
[0006] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, comprising: providing a substrate and forming a gate structure on the surface of the substrate; forming a hard mask layer, wherein the hard mask layer covers the side wall and the top surface of the gate structure, and etching the hard mask layer covering the bottom surface of the side wall so that the thickness of the hard mask layer on the bottom surface of the side wall is not greater than the thickness of the hard mask layer on the surface of the remaining part of the side wall; performing an etching process on the substrate on both sides of the gate structure to form a groove, and growing an epitaxial layer in the groove; and removing the remaining hard mask layer.
[0007] Preferably, in the method for forming the semiconductor structure, the hard mask layer is etched using a dry etching process.
[0008] Preferably, in the method for forming the semiconductor structure, the etching gas used in the dry etching includes tetrafluoromethane or helium.
[0009] Preferably, in the method for forming the semiconductor structure, the substrate has an N-well region and a P-well region, and the gate structure is formed on the surface of the substrate including the N-well region and the P-well region.
[0010] Preferably, in the method for forming the semiconductor structure, the method for performing an etching process on the substrate on both sides of the gate structure to form a groove includes: forming a photoresist layer on the N-well region or the P-well region; exposing and developing the photoresist layer to form a patterned photoresist layer; and, using the patterned photoresist layer as a mask, performing an etching process on the exposed substrate of the N-well region or the P-well region to form the groove.
[0011] Preferably, in the method for forming the semiconductor structure, before forming the photoresist layer, the method further comprises: performing an oxygen plasma ashing process on the surface of the hard mask layer to form a protective layer on the surface of the hard mask layer.
[0012] Preferably, in the method for forming the semiconductor structure, after growing the epitaxial layer, the method further comprises: removing the protective layer covering the surface of the hard mask layer by using a hydrofluoric acid solution.
[0013] Preferably, in the method for forming the semiconductor structure, the hard mask layer is removed using a phosphoric acid solution.
[0014] Preferably, in the method for forming the semiconductor structure, the hard mask layer is a silicon nitride layer, and the method for forming the hard mask layer includes: using hexachlorodisilane and ammonia as reaction gases and depositing the hard mask layer by chemical vapor deposition.
[0015] The present invention also provides a semiconductor structure, which is prepared by using the above-mentioned semiconductor structure forming method.
[0016] In summary, the present invention provides a semiconductor structure and a method for forming the same, by etching the hard mask layer covering the bottom surface of the side wall of the gate structure before forming an epitaxial layer, so that the thickness of the hard mask layer on the bottom surface of the side wall is not greater than the thickness of the hard mask layer on the surface of the remaining portion of the side wall, thereby increasing the process window for removing the hard mask layer after forming the epitaxial layer, and completely removing the hard mask layer, thereby reducing parasitic capacitance and improving the device operating speed. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a schematic diagram of the position between the foot and the epitaxial layer in the prior art;
[0018] Figure 2 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;
[0019] Figure 3 is a structural schematic diagram corresponding to step S2 of forming a semiconductor structure in an embodiment of the present invention;
[0020] Figure 4-5 is a structural schematic diagram corresponding to step S3 of forming a semiconductor structure in an embodiment of the present invention;
[0021] Figure 6 to Figure 8 is a structural schematic diagram corresponding to step S4 of forming a semiconductor structure in an embodiment of the present invention;
[0022] Fig. 9 is a structural schematic diagram corresponding to step S5 of forming a semiconductor structure in an embodiment of the present invention;
[0023] Wherein, each figure is marked as:
[0024] 10-base;
[0025] 20-gate structure;
[0026] 30-groove;
[0027] 40-epitaxial layer;
[0028] 50-photoresist layer;
[0029] 210-hard mask layer;
[0030] 211-Foot. DETAILED DESCRIPTION
[0031] As mentioned in the background technology, when removing the hard mask layer, it is always difficult to completely remove the hard mask layer, which leads to an increase in the parasitic capacitance of the gate structure and the source and drain, affecting the device performance. Figure 1 When the hard mask layer 210 is formed on the surface of the gate structure 20, a footing 211 is always formed at the root of the gate structure 20. The reason for the formation of the footing 211 is that in the process of etching to form the gate structure 20, the etching gas usually includes a fluorine-containing gas, and the fluorine reacts with organic substances such as the photoresist and the photolithography reflective layer used in the previous photolithography step to generate an organic polymer, and the organic polymer is deposited along the etching direction of the gate structure 20 at the position where the bottom of the gate structure 20 contacts the substrate 10, and the hard mask layer 210 covers the surface of the gate structure 20 to naturally form a "footing 211" corresponding to the morphology of the gate structure 20. The foot 211 extends in a direction away from the gate structure 20 and gradually approaches the epitaxial layer 40 subsequently formed in the groove of the substrate 10 on both sides of the gate structure 20, so that the process window between the hard mask layer 210 and the epitaxial layer 40 is reduced and the operating space is insufficient. When removing the hard mask layer 210, it is difficult for the etching solution to enter the gap between the hard mask layer 210 and the epitaxial layer 40 and the hard mask layer 210 cannot be removed, thereby affecting the device performance.
[0032] In order to solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same, which will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.
[0033] In the description of this embodiment, it should be noted that the terms "upper", "lower", "inner", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0034] See also Figure 2 , an embodiment of the present invention provides a method for forming a semiconductor structure, comprising:
[0035] S1, providing a substrate, and forming a gate structure on a surface of the substrate;
[0036] S2, forming a hard mask layer, the hard mask layer covering the sidewall and the top surface of the gate structure, and etching the hard mask layer covering the bottom surface of the sidewall so that the thickness of the hard mask layer on the bottom surface of the sidewall is not greater than the thickness of the hard mask layer on the surface of the remaining portion of the sidewall;
[0037] S3, performing an etching process on the substrate at both sides of the gate structure to form a groove, and growing an epitaxial layer in the groove; and,
[0038] S4, removing the remaining hard mask layer.
[0039] In an embodiment of the present invention, the hard mask layer covering the bottom surface of the side wall is etched before forming the epitaxial layer so that the thickness of the hard mask layer on the bottom surface of the side wall is not greater than the thickness of the hard mask layer on the surface of the remaining portion of the side wall, thereby removing the hard mask layer in the form of the foot, increasing the process window for removing the hard mask layer after forming the epitaxial layer, and completely removing the hard mask layer, thereby reducing parasitic capacitance and improving the operating speed of the device.
[0040] The following combination Figure 3 to Figure 8 Steps S1 to S4 are described in further detail.
[0041] First, step S1 is performed to provide a substrate 10, and a gate structure 20 is formed on the surface of the substrate 10. The material of the substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or silicon on insulator (SOI) or germanium on insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide, and those skilled in the art may select the type of substrate 10 according to the semiconductor device formed on the substrate 10, and therefore, the type of substrate 10 should not limit the protection scope of the present invention.
[0042] Optionally, the step of forming a gate structure 20 on the surface of the substrate 10 includes: forming a gate material layer on the surface of the substrate 10; coating an anti-reflective layer and a photoresist on the surface of the gate material layer; patterning the photoresist and then etching the gate material layer to form a gate.
[0043] In this embodiment, the substrate 10 has an N-well region and a P-well region, and a gate structure 20 is formed on the surface of the substrate 10 including the N-well region and the P-well region. Further, a germanium silicon epitaxial layer is formed in the groove 30 of the substrate 10 in the N-well region, and a phosphorus silicon epitaxial layer is formed in the groove 30 of the substrate 10 in the P-well region. For the convenience of description, this embodiment takes the formation of a germanium silicon epitaxial layer in the groove 30 of the substrate 10 in the N-well region as an example to describe in detail the morphology modification process of the hard mask layer 210.
[0044] Next, execute step S2, see Figure 3 to Figure 5 , forming a hard mask layer 210, the hard mask layer 210 covers the sidewalls and the top surface of the gate structure 20, and etching the hard mask layer 210 covering the bottom surface of the sidewall so that the thickness of the hard mask layer 210 on the bottom surface of the sidewall is not greater than the thickness of the hard mask layer 210 on the rest of the surface of the sidewall.
[0045] The hard mask layer 210 is used to protect the gate structure 20 from damage and contamination during subsequent processes, and can also be used to define the horizontal distance between the trench 30 and the gate structure 20. In order to keep the hard mask layer 210 in a stable size and shape to provide better protection for the gate structure 20, the hard mask layer 210 is generally made of a material that is resistant to high temperatures, chemical corrosion, and has high mechanical strength. In a preferred embodiment, the hard mask layer 210 is a silicon nitride layer.
[0046] Specifically, the method for forming the hard mask layer 210 includes: using hexachlorodisilane and ammonia as reaction gases and depositing the hard mask layer 210 by chemical vapor deposition.
[0047] In step S2 , the etching method used for etching the hard mask layer 210 is a dry etching process, and the etching gas used for the dry etching includes tetrafluoromethane or helium.
[0048] Optionally, the dry etching process is a plasma dry etching process, and the bias voltage in the plasma dry etching process can cause the energetic particles of the etching gas to produce directional movement. In an optional embodiment, the bias voltage can be controlled to control the etching to occur only in a direction perpendicular to the surface of the substrate 10. This etching method will only thin the hard mask layer 210 covering the top surface of the gate structure 20 and the hard mask layer 20 covering the surface of the substrate 10 to a certain extent during the process of removing the foot 211, but will not etch the hard mask layer 210 covering the side wall surface, thereby protecting the hard mask layer 210 covering the side wall from etching.
[0049] In other embodiments, the hard mask layer 210 may be etched at an angle to further reduce the thickness of the hard mask layer 210 at the bottom surface of the sidewall.
[0050] The purpose of removing the foot portion 211 is to increase the process window for the subsequent removal of the hard mask layer 210. Therefore, any morphology of the hard mask layer 210 that meets this purpose falls within the protection scope of the embodiment of the present invention. Figure 4 , the hard mask layer 210 covering the bottom surface of the sidewall is etched to remove the foot 211, so that the thickness of the hard mask layer 210 on the bottom surface of the sidewall is equal to the thickness of the hard mask layer 210 on the surface of the remaining part of the sidewall, that is, the hard mask layer 210 covering the sidewall is perpendicular to the surface of the substrate 10; as another embodiment, see Figure 5 ,exist Figure 4 On the basis of this, the etching process is continued to be performed on the hard mask layer 210 covering the bottom surface of the side wall, and the thickness of the hard mask layer 210 on the bottom surface of the side wall is made smaller than the thickness of the hard mask layer 210 on the surface of the remaining part of the side wall, that is, a notch is formed in the hard mask layer 210 on the bottom surface of the side wall, and the process window for subsequent removal of the hard mask layer 210 is continued to increase.
[0051] However, it should be noted that in the above two embodiments, the hard mask layer 210 after etching still completely covers the sidewall of the gate structure 20 to protect the gate structure 20 from damage and contamination.
[0052] Next, execute step S3, see Figure 6 to Figure 8 , an etching process is performed on the substrate 10 at both sides of the gate structure 20 to form a trench 30 , and an epitaxial layer 40 is grown in the trench 30 .
[0053] Specifically, the method of performing an etching process on the surface of the substrate 10 at both sides of the gate structure 20 to form the trench 30 includes: Figure 6 , forming a photoresist layer 50 on the N-well region or the P-well region; exposing and developing the photoresist layer 50 to form a patterned photoresist layer 50; and Figure 7 , using the patterned photoresist layer 50 as a mask, an etching process is performed on the surface of the substrate 10 exposed in the N-well region or the P-well region to form a trench 30 .
[0054] Further, such as Figure 8 , an epitaxial layer 40 is grown in the trench 30 . Since the hard mask layer 210 in the form of the foot 211 is removed in the previous process, a gap exists between the hard mask layer 210 and the epitaxial layer 40 , which makes it easy for subsequent etching solution to enter and remove the remaining hard mask layer 210 .
[0055] Before forming the photoresist layer 50, it also includes: performing an oxygen plasma ashing process on the surface of the hard mask layer 210 to form an oxidation protection layer (not shown) on the surface of the hard mask layer 210 to avoid the subsequent photoresist poisoning phenomenon. The so-called "photoresist poisoning" means that if the photoresist layer 50 is directly coated on the surface of the hard mask layer 210, the nitrogen element contained in the hard mask layer 210 will react with the chemical substances in the photoresist layer 50 material, so that the quality of the photoresist layer 50 is reduced, and the photoresist's ability to control the photolithography size is reduced. The oxidation protection layer can effectively avoid the phenomenon of photoresist poisoning.
[0056] Finally, execute step S4, see Fig. 9 , and remove the remaining hard mask layer 210 .
[0057] Specifically, the oxidation protection layer covering the surface of the hard mask layer 210 is removed using a hydrofluoric acid solution, and the hard mask layer 210 is removed using a phosphoric acid solution.
[0058] An embodiment of the present invention also provides a semiconductor structure, which is prepared by the above-mentioned semiconductor structure forming method, including a gate structure and an epitaxial layer, and no hard mask layer remains between the gate structure and the epitaxial layer, which can ensure a smaller parasitic capacitance and a faster operating speed.
[0059] In summary, the present invention provides a semiconductor structure and a method for forming the same, including providing a substrate and forming a gate structure on the surface of the substrate; forming a hard mask layer, the hard mask layer covering the sidewall and top surface of the gate structure, etching the hard mask layer covering the bottom surface of the sidewall so that the thickness of the hard mask layer on the bottom surface of the sidewall is not greater than the thickness of the hard mask layer on the surface of the remaining portion of the sidewall; performing an etching process on the substrate on both sides of the gate structure to form a groove, and growing an epitaxial layer in the groove; and removing the remaining hard mask layer. The present invention etches the hard mask layer covering the bottom surface of the sidewall of the gate structure before forming the epitaxial layer so that the thickness of the hard mask layer on the bottom surface of the sidewall is not greater than the thickness of the hard mask layer on the surface of the remaining portion of the sidewall, thereby increasing the process window for removing the hard mask layer after forming the epitaxial layer, and achieving complete removal of the hard mask layer, thereby reducing parasitic capacitance and improving device operation speed.
[0060] In addition, it should be recognized that although the present invention application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, and forming a gate structure on a surface of the substrate; Forming a hard mask layer, the hard mask layer covering the sidewall and the top surface of the gate structure, and etching the hard mask layer covering the bottom surface of the sidewall so that the thickness of the hard mask layer on the bottom surface of the sidewall is not greater than the thickness of the hard mask layer on the surface of the remaining portion of the sidewall; Performing an etching process on the substrate at both sides of the gate structure to form a groove, and growing an epitaxial layer in the groove; and, The remaining hard mask layer is removed.
2. The method for forming a semiconductor structure according to claim 1, wherein: The hard mask layer is etched using a dry etching process.
3. The method for forming a semiconductor structure according to claim 2, wherein: The etching gas used in the dry etching includes tetrafluoromethane or helium.
4. The method for forming a semiconductor structure according to claim 1, wherein: The substrate has an N-well region and a P-well region, and the gate structure is formed on the surface of the substrate including the N-well region and the P-well region.
5. The method for forming a semiconductor structure according to claim 4, wherein: The method of performing an etching process on the substrate at both sides of the gate structure to form a groove comprises: forming a photoresist layer on the N-well region or the P-well region; exposing and developing the photoresist layer to form a patterned photoresist layer; and, Using the patterned photoresist layer as a mask, an etching process is performed on the exposed N-well region or the P-well region of the substrate to form the trench.
6. The method for forming a semiconductor structure according to claim 5, wherein: Before forming the photoresist layer, the method further includes: performing an oxygen plasma ashing process on the surface of the hard mask layer to form a protective layer on the surface of the hard mask layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: After growing the epitaxial layer, the method further includes: removing the protective layer covering the surface of the hard mask layer by using a hydrofluoric acid solution.
8. The method for forming a semiconductor structure according to claim 1, wherein: The hard mask layer is removed using a phosphoric acid solution.
9. The method for forming a semiconductor structure according to claim 1, wherein: The hard mask layer is a silicon nitride layer. The method for forming the hard mask layer includes: using hexachlorodisilane and ammonia as reaction gases and depositing the hard mask layer by a chemical vapor deposition method.
10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for forming a semiconductor structure according to any one of claims 1 to 9.