Transistor and manufacturing method thereof
By using Si2H6 and NH3 as reactants to grow the SiNx passivation layer and plating the AlN passivation layer on it, the problem of poor density and uniformity of the SiN passivation layer is solved, and the electrical performance and reliability of the transistor are significantly improved.
Patent Information
- Application Number
- CN202411734091.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-04-18
AI Technical Summary
In the prior art, the density and uniformity of the SiN passivation layer are poor, resulting in large leakage of transistors and poor electrical performance and reliability.
Si2H6 and NH3 are used as reactants to grow the SiNx passivation layer on the barrier layer, and the AlN passivation layer is plated on the SiNx passivation layer to improve the density and uniformity of the passivation layer.
By improving the density and uniformity of the SiNx passivation layer, the leakage of transistors is reduced, and the electrical performance and reliability of transistors are improved.
Smart Images
Figure CN119855182A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art
[0002] GaN-on-Si is widely used in semiconductors, such as transistors.
[0003] The related technology provides a silicon-based gallium nitride transistor, which mainly includes a channel layer, a barrier layer and a SiN passivation layer.
[0004] However, the SiN passivation layer has poor compactness and uniformity, resulting in large transistor leakage, which deteriorates the electrical performance and reliability of the transistor. Summary of the invention
[0005] The present disclosure provides a transistor and a method for manufacturing the same. The technical solution is as follows:
[0006] In one aspect, a method for manufacturing a transistor is provided, the method comprising:
[0007] manufacturing a channel layer;
[0008] forming a barrier layer on the channel layer;
[0009] Si2H6 and NH3 are used as reactants to form SiN on the barrier layer. x Passivation layer, x is greater than 0;
[0010] In the SiN x An AlN passivation layer is formed on the passivation layer.
[0011] Optionally, the use of Si2H6 and NH3 as reactants includes:
[0012] A mixed gas of Si2H6 and H2 or a mixed gas of Si2H6 and N2 with a flow rate of 20 to 10,000 sccm and NH3 with a flow rate of 5,000 to 50,000 sccm are used as reactants.
[0013] Optionally, in the mixed gas of Si2H6 and H2 or the mixed gas of Si2H6 and N2, the proportion of Si2H6 is 1 / 10000 to 1000 / 10000.
[0014] Optionally, a SiN x Passivation layer, including:
[0015] In an environment where the reaction chamber temperature is 800-1100° C. and the reaction chamber pressure is 50-400 mbar, the SiN with a thickness of 5-100 nm is grown. x Passivation layer.
[0016] Optionally, in the SiN x An AlN passivation layer is formed on the passivation layer, comprising:
[0017] The SiN x The transistor structure of the passivation layer is placed on a PVD carrier;
[0018] The temperature of the PVD carrier is controlled to be 400-700°C. Under the environment of N2 flow rate of 50-1000sccm, O2 flow rate of 500-5000sccm, Ar flow rate of 10-200sccm, and coating power of 2000-5000W, a 2-10nm AlN film is plated to obtain the AlN passivation layer, and the coating time is 10-100s.
[0019] Optionally, in the SiN x An AlN passivation layer is formed on the passivation layer, comprising:
[0020] The SiN x The transistor structure of the passivation layer is placed on the ALD carrier and introduced into the coating chamber;
[0021] Pre-treating the transistor structure with NH3 for 5 to 20 seconds;
[0022] The temperature of the coating chamber is controlled to be 200-400° C., the coating power is 100-400W, a 2-10nm AlN film is coated to obtain the AlN passivation layer, and the coating time is 10-100s.
[0023] Optionally, the method further comprises:
[0024] In making the SiN x Before the passivation layer is formed, a cap layer with a thickness of 0.5 to 5 nm is formed on the barrier layer in an environment where the reaction chamber temperature is 900 to 1200° C. and the reaction chamber pressure is 50 to 300 mbar.
[0025] In another aspect, a transistor is provided. The transistor is manufactured by the above method, and the transistor comprises:
[0026] A channel layer, a barrier layer, a SiN x passivation layer and AlN passivation layer, x is greater than 0.
[0027] Optionally, the SiN x The thickness of the passivation layer is 5 to 100 nm.
[0028] Optionally, the AlN passivation layer has a thickness of 2-10 nm.
[0029] Optionally, the transistor further includes a cap layer, wherein the cap layer is located between the barrier layer and the SiN x Between the passivation layers;
[0030] The thickness of the cap layer is 0.5-5 nm.
[0031] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:
[0032] The transistor includes a channel layer. The function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer. SiN is made on the barrier layer. x The passivation layer is made by using Si2H6 and NH3 as reactants. Compared with the related technology using SiH4 and NH3 as reactants, the SiN x The passivation layer has better density and uniformity, which can prevent Si from diffusing into the barrier layer. x An AlN passivation layer is made on the passivation layer. The AlN passivation layer can play a passivation role and also play an etching stop role. x The combination of the passivation layer and the AlN passivation layer solves the problem of poor density and uniformity of the SiN passivation layer in the related technology, which leads to large leakage of the transistor, and improves the electrical performance and reliability of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0034] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;
[0035] Figure 2 is a schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure;
[0036] Figure 3 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;
[0037] Figure 4 is a flow chart of another method for manufacturing a transistor provided by an embodiment of the present disclosure;
[0038] Figure 5 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0039] Figure 6is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0040] Figure 7 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0041] Figure 8 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0042] Fig. 9 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0043] Fig.10 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0044] Fig.11 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0045] Fig.12 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0046] Fig.13 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0047] Fig.14 is a schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure during the manufacturing process;
[0048] Fig.15 is a schematic diagram comparing transistor leakage provided by an embodiment of the present disclosure;
[0049] Fig.16 2 is a schematic diagram for comparing transistor leakage provided by an embodiment of the present disclosure.
[0050] Reference numerals
[0051] 101: channel layer; 102: barrier layer; 103: SiN x Passivation layer; 104: AlN passivation layer; 105: cap layer; 106: buffer layer; 107: substrate; 108: nucleation layer; 109: gate; 110: source; 111: drain; 112: first SiN passivation layer; 113: second SiN passivation layer; 114: SiO2 passivation layer; 1101: ohmic contact portion; 1102: first electrode portion; 1103: second electrode portion; 2000: ion implantation region; 1120: ohmic contact through hole; 1130: first through hole; 1140: second through hole. DETAILED DESCRIPTION
[0052] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0053] In the related art, SiH4 and NH3 are used as reactants to form a SiN passivation layer, and an Al2O3 etching stop layer is formed on the SiN passivation layer. However, there are problems such as poor density and uniformity, which leads to large leakage of transistors.
[0054] After research, it was found that the use of SiH4 and NH3 as reactants to grow the SiN passivation layer in the related art is too slow and time-consuming, which will cause a large amount of Si generated by the decomposition of SiH4 to diffuse into the barrier layer to produce over-doping, low density of the SiN passivation layer and low production efficiency. In addition, the related art uses Al2O3 as the etching cut-off layer after the SiN passivation layer, which has poor density and uniformity, resulting in large lateral and vertical leakage of the device. The disclosed embodiment solves the problem of poor density and uniformity of the passivation layer, which leads to large leakage of the transistor, by changing the SiN passivation layer growth process and replacing Al2O3, thereby improving the electrical performance and reliability of the transistor.
[0055] Figure 1 A schematic diagram of a transistor structure provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a channel layer 101, a barrier layer 102, a SiN x For the passivation layer 103 and the AlN passivation layer 104 , x is greater than 0.
[0056] Among them, SiN x The passivation layer 103 is manufactured using Si2H6 and NH3 as reactants.
[0057] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer, and a SiN x The passivation layer is made by using Si2H6 and NH3 as reactants. Compared with the related technology using SiH4 and NH3 as reactants, the SiN x The passivation layer has better density and uniformity, and can also speed up the reaction and prevent Si from diffusing into the barrier layer. x An AlN passivation layer is made on the passivation layer. The AlN passivation layer can play a passivation role and also play an etching stop role. x The combination of the passivation layer and the AlN passivation layer solves the problem of poor density and uniformity of the SiN passivation layer in the related technology, which leads to large leakage of the transistor, and improves the electrical performance and reliability of the transistor.
[0058] In the embodiment of the present disclosure, the channel layer 101 is a GaN channel layer.
[0059] The channel layer 101 has a thickness of 20-600 nm, for example, 300 nm.
[0060] In the embodiment of the present disclosure, the barrier layer 102 may be a single layer or a composite layer.
[0061] For example, the barrier layer 102 is an AlGaN layer or an InAlN layer.
[0062] The barrier layer 102 has a thickness of 5-30 nm, for example, 20 nm.
[0063] For another example, the barrier layer 102 is a stacked layer of two or three of an AlN layer, an AlGaN layer, and a GaN layer.
[0064] In the embodiment of the present disclosure, SiN x The thickness of the passivation layer 103 is 5-100 nm. The above thickness can ensure the passivation effect, density and uniformity.
[0065] For example, SiN x The thickness of the passivation layer 103 is 50 nm.
[0066] In the embodiment of the present disclosure, the thickness of the AlN passivation layer 104 is 2-10 nm. The above thickness can ensure the passivation effect and the etching cut-off effect.
[0067] For example, the thickness of the AlN passivation layer 104 is 5 nm.
[0068] Figure 2 A schematic diagram of the structure of another transistor provided by an embodiment of the present disclosure. Figure 2 , the transistor and Figure 1 Compared with the transistor shown in FIG. 1 , the difference is that the transistor further includes a cap layer 105, and the cap layer 105 is located between the barrier layer 102 and the SiN x between the passivation layers 103 .
[0069] In this implementation, the cap layer 105 is a GaN thin layer, and the barrier layer can be protected by providing the cap layer 105 .
[0070] In the embodiment of the present disclosure, the thickness of the cap layer 105 is 0.5-5 nm. The above thickness can ensure the protection effect of the barrier layer, and the low thickness will not cause the transistor size to be too large.
[0071] For example, the thickness of the cap layer 105 is 2 nm.
[0072] Optionally, the transistor further includes a buffer layer 106 , and the channel layer 101 is located in the buffer layer 106 .
[0073] The buffer layer 106 includes a super lattice structure composed of an AlN layer and an AlGaN layer.
[0074] In this implementation, by providing a buffer layer of a superlattice structure composed of an AlN layer and an AlGaN layer, the growth quality of the channel layer of the transistor is improved.
[0075] In other implementations, the buffer layer 106 may be a GaN buffer layer.
[0076] In the disclosed embodiment, the thickness of the buffer layer 106 is 100-5000 nm.
[0077] For example, the thickness of the buffer layer 106 is 1000 nm.
[0078] In the embodiment of the present disclosure, the number of periods of the superlattice structure in the buffer layer 106 is 40-60.
[0079] Exemplarily, the number of periods of the superlattice structure in the buffer layer 106 is 50.
[0080] Optionally, the buffer layer 106 may further include a carbon-doped GaN layer, and the carbon-doped GaN layer is located between the superlattice structure in the buffer layer 106 and the channel layer 101 .
[0081] In the embodiment of the present disclosure, the thickness of the carbon-doped GaN layer is 1200-1800 nm.
[0082] Exemplarily, the thickness of the carbon-doped GaN layer is 1500 nm.
[0083] Optionally, the transistor further includes a substrate 107 and a nucleation layer 108 , and the nucleation layer 108 is located between the substrate 107 and the buffer layer 106 .
[0084] Exemplarily, the substrate 107 is a Si substrate, a silicon carbide substrate, a sapphire substrate, a gallium oxide substrate or a gallium nitride substrate.
[0085] In the embodiment of the present disclosure, the nucleation layer 108 is an AlN nucleation layer, and the thickness of the AlN nucleation layer is 10-300 nm.
[0086] Exemplarily, the thickness of the AlN nucleation layer is 150 nm.
[0087] In other embodiments, the nucleation layer 108 is Al y Ga 1-y N nucleation layer, Al y Ga 1-y The thickness of the N nucleation layer is 10 to 50 nm, and y is greater than 0.
[0088] For example, Al y Ga1-y The thickness of the N nucleation layer is 30 nm.
[0089] Optionally, the transistor further includes a gate 109 , a source 110 and a drain 111 .
[0090] The transistor is a high electron mobility transistor (HEMT). Current can be transmitted between the drain and the source through a conductive channel formed by a two-dimensional electron gas. The gate is connected to the gallium nitride structure through a gate dielectric layer. By controlling the gate voltage, the conduction and cutoff of the transistor conductive channel can be controlled.
[0091] In the embodiment of the present disclosure, the gate 109 is located on the AlN passivation layer 104 .
[0092] In one example, the source 110 and the drain 111 pass through the cap layer 105 and the barrier layer 102 respectively, and are connected to the channel layer 101 .
[0093] In another example, the source 110 and the drain 111 respectively pass through the cap layer 105 and are connected to the barrier layer 102 .
[0094] Optionally, the transistor further includes a first SiN passivation layer 112 , a second SiN passivation layer 113 and a SiO 2 passivation layer 114 , and the first SiN passivation layer 112 , the second SiN passivation layer 113 and the SiO 2 passivation layer 114 sequentially cover the AlN passivation layer 104 .
[0095] In the embodiment of the present disclosure, the gate 109 , the source 110 and the drain 111 may include an ohmic contact portion 1101 , a first electrode portion 1102 and a second electrode portion 1103 , and the ohmic contact portion 1101 , the first electrode portion 1102 and the second electrode portion 1103 are connected in sequence.
[0096] Exemplarily, in the gate 109 , the ohmic contact portion 1101 contacts the surface of the AlN passivation layer 104 through the first SiN passivation layer 112 , the first electrode portion 1102 contacts the ohmic contact portion 1101 through the second SiN passivation layer 113 , and the second electrode portion 1103 contacts the first electrode portion 1102 through the SiO 2 passivation layer 114 .
[0097] Exemplarily, in the source 110 and the drain 111, the ohmic contact portion 1101 contacts the barrier layer 102 through the first SiN passivation layer 112 and the cap layer 105, the first electrode portion 1102 contacts the ohmic contact portion 1101 through the second SiN passivation layer 113, and the second electrode portion 1103 contacts the first electrode portion 1102 through the SiO2 passivation layer 114.
[0098] Figure 3is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure. Figure 3 The method steps include:
[0099] 301. Fabricate a channel layer.
[0100] 302. Fabricate a barrier layer on the channel layer.
[0101] 303. Si2H6 and NH3 are used as reactants to form SiN on the barrier layer. x Passivation layer, x is greater than 0.
[0102] 304. In the SiN x An AlN passivation layer is formed on the passivation layer.
[0103] In the embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer, and a SiN x The passivation layer is made by using Si2H6 and NH3 as reactants. Compared with the related technology using SiH4 and NH3 as reactants, the SiN x The passivation layer has better density and uniformity, which can prevent Si from diffusing into the barrier layer. x An AlN passivation layer is made on the passivation layer. The AlN passivation layer can play a passivation role and also play an etching stop role. x The combination of the passivation layer and the AlN passivation layer solves the problem of poor density and uniformity of the SiN passivation layer in the related technology, which leads to large leakage of the transistor, and improves the electrical performance and reliability of the transistor.
[0104] Figure 4 A flow chart of a method for manufacturing a transistor provided in an embodiment of the present disclosure, see Figure 4 , the method flow chart includes:
[0105] 401. Provide a substrate.
[0106] Exemplarily, the substrate is a Si substrate, a silicon carbide substrate, a sapphire substrate, a gallium oxide substrate or a gallium nitride substrate.
[0107] Optionally, the method may further include:
[0108] The substrate is placed in a Metal-organic Chemical Vapor Deposition (MOCVD) reaction chamber for nitride epitaxy, hydrogen is introduced as a carrier gas and the substrate temperature is raised to 1000°C to 1200°C, the stress of the reaction chamber is controlled at 50 to 800 mbar, the oxide on the substrate surface is decomposed at high temperature to obtain a clean surface, and the processing time is 60 to 600 seconds.
[0109] For example, a silicon substrate is placed in MOCVD, the substrate temperature is raised to 1050°C, the stress of the reaction chamber is controlled at 500 mbar, and the substrate is treated in a H2 atmosphere for 100 seconds to obtain a clean silicon surface.
[0110] 402. A nucleation layer, a buffer layer, a channel layer and a barrier layer are sequentially fabricated on the substrate.
[0111] In the embodiment of the present disclosure, the nucleation layer is an AlN nucleation layer, and the thickness of the AlN nucleation layer is 10 to 300 nm.
[0112] Exemplarily, the thickness of the AlN nucleation layer is 150 nm.
[0113] In other embodiments, the nucleation layer is Al y Ga 1-y N nucleation layer, Al y Ga 1-y The thickness of the N nucleation layer is 10 to 50 nm, and y is greater than 0.
[0114] For example, Al y Ga 1-y The thickness of the N nucleation layer is 30 nm.
[0115] In the embodiment of the present disclosure, the buffer layer includes a super lattice structure consisting of an AlN layer and an AlGaN layer.
[0116] In this implementation, by providing a buffer layer of a superlattice structure composed of an AlN layer and an AlGaN layer, the growth quality of the channel layer of the transistor is improved.
[0117] In other implementations, the buffer layer may be a GaN buffer layer.
[0118] In the disclosed embodiment, the thickness of the buffer layer is 100-5000 nm.
[0119] For example, the thickness of the buffer layer is 1000 nm.
[0120] In the disclosed embodiment, the number of periods of the superlattice structure in the buffer layer is 40-60.
[0121] Exemplarily, the number of periods of the superlattice structure in the buffer layer is 50.
[0122] Optionally, the buffer layer may further include a carbon-doped GaN layer, and the carbon-doped GaN layer is located between the superlattice structure and the channel layer in the buffer layer.
[0123] In the embodiment of the present disclosure, the thickness of the carbon-doped GaN layer is 1200-1800 nm.
[0124] Exemplarily, the thickness of the carbon-doped GaN layer is 1500 nm.
[0125] In the embodiment of the present disclosure, the channel layer is a GaN channel layer.
[0126] The thickness of the channel layer is 20-600 nm, for example, 300 nm.
[0127] In the embodiment of the present disclosure, the barrier layer can be a single layer or a composite layer.
[0128] For example, the barrier layer is an AlGaN layer or an InAlN layer.
[0129] The thickness of the barrier layer is 5-30 nm, for example, 20 nm.
[0130] For another example, the barrier layer is a stacked layer of two or three of an AlN layer, an AlGaN layer, and a GaN layer.
[0131] In the embodiment of the present disclosure, step 402 may include:
[0132] The first step is to adjust the temperature of the reaction chamber to 500-1100°C, control the stress of the reaction chamber to 50-200 mbar, introduce NH3 and TMAl, and grow the AlN nucleation layer or Al y Ga 1-y N nucleation layer.
[0133] For example, the temperature of the reaction chamber is raised to 1000°C, the stress of the reaction chamber is controlled at 100 mbar, and the AlN nucleation layer or Al y Ga 1-y N nucleation layer.
[0134] In the second step, the temperature of the reaction chamber is adjusted to 900-1200°C and the pressure of the reaction chamber is 50-200 mbar, and NH3, TMGa and TMAl are introduced to grow a superlattice buffer layer composed of AlN layer and AlGaN layer.
[0135] For example, the temperature of the reaction chamber is adjusted to 1100° C., the pressure of the reaction chamber is adjusted to 100 mbar, and a superlattice buffer layer consisting of an AlN layer and an AlGaN layer is grown.
[0136] The third step is to adjust the reaction chamber temperature to 1000-1200°C and the reaction chamber pressure to 100-400 mbar, introduce NH3 and TMGa, and grow a GaN channel layer.
[0137] For example, the temperature of the reaction chamber is adjusted to 1050° C. and the pressure of the reaction chamber is adjusted to 200 mbar to grow a GaN channel layer.
[0138] The fourth step is to adjust the reaction chamber temperature to 900-1150° C. and the reaction chamber pressure to 50-200 mbar to grow an AlGaN or InAlN barrier layer.
[0139] For example, the temperature of the reaction chamber is adjusted to 1050° C. and the pressure of the reaction chamber is 100 mbar to grow an AlGaN or InAlN barrier layer.
[0140] 403. A cap layer is fabricated on the surface of the barrier layer.
[0141] In the embodiment of the present disclosure, the cap layer is a GaN layer.
[0142] In this implementation, the cap layer mainly protects the barrier layer from the influence of moisture, oxygen, etc. in the environment.
[0143] In the disclosed embodiment, the thickness of the cap layer is 0.5-5 nm.
[0144] Exemplarily, the thickness of the cap layer is 2 nm.
[0145] In the embodiment of the present disclosure, step 403 may include:
[0146] The temperature of the reaction chamber is adjusted to 900-1200° C. and the pressure of the reaction chamber is adjusted to 50-300 mbar to grow a GaN cap layer.
[0147] For example, the temperature of the reaction chamber is adjusted to 1050° C. and the pressure of the reaction chamber is adjusted to 200 mbar to grow a GaN cap layer.
[0148] 404. Si2H6 and NH3 are used as reactants to form SiN on the cap layer. x Passivation layer.
[0149] Among them, SiN x The passivation layer uses Si2H6 and NH3 as reactants. Compared with the related technology using SiH4 and NH3 as reactants, the SiN x The passivation layer has better density and uniformity, which can prevent Si from diffusing into the barrier layer.
[0150] In the embodiment of the present disclosure, a mixed gas of Si2H6 and H2 or a mixed gas of Si2H6 and N2 with a flow rate of 20 to 10,000 sccm and NH3 with a flow rate of 5,000 to 50,000 sccm are used as reactants.
[0151] For example, a mixed gas of Si2H6 and H2 or a mixed gas of Si2H6 and N2 with a flow rate of 5000 sccm and NH3 with a flow rate of 10000 sccm are used as reactants.
[0152] In this implementation, Si2H6 and NH3 with the above flow rates are used as reactants, so that SiN x The density and uniformity of the passivation layer are better. Among them, the mixed gas of Si2H6 and H2 or the mixed gas of Si2H6 and N2 with a flow rate of 20 to 10000sccm can cover the mixed gas of high concentration and low concentration Si2H6, ensure the effective gas volume of Si2H6, and obtain high-speed SiN x Passivation layer. Using NH3 with a flow rate of 10000sccm to ensure the full reaction of Si2H6 and NH3 to generate high-quality SiN x Membrane layer.
[0153] In the disclosed embodiment, in the mixed gas of Si2H6 and H2 or the mixed gas of Si2H6 and N2, the proportion of Si2H6 is 1 / 10000 to 1000 / 10000. Moreover, the proportion of Si2H6 in the mixed gas is negatively correlated with the flow rate of the mixed gas, that is, the greater the flow rate of the mixed gas, the smaller the proportion of Si2H6 in the mixed gas.
[0154] For example, the ratio of Si2H6 is 500 / 10000.
[0155] In the embodiment of the present disclosure, step 404 may include:
[0156] In an environment where the reaction chamber temperature is 800-1100° C. and the reaction chamber pressure is 50-400 mbar, the SiN with a thickness of 5-100 nm is grown. x Passivation layer.
[0157] For example, in an environment where the reaction chamber temperature is 1000° C. and the reaction chamber pressure is 200 mbar, the SiN with a thickness of 50 nm is grown. x Passivation layer.
[0158] In this implementation, the above environment is used to grow SiN x The passivation layer makes the SiN x The film quality of the passivation layer is better. In addition, SiN with a thickness of 5 to 100 nm is used. x The passivation layer can play a good role as passivation and gate dielectric; if SiN x The passivation layer thickness is less than 5nm, and the passivation effect is poor. x The passivation layer thickness is greater than 100nm and the gate dielectric is too thick, which affects the threshold voltage.
[0159] 405. In the SiN x An AlN passivation layer is formed on the passivation layer.
[0160] In one example, step 405 may include:
[0161] The SiN x The transistor structure of the passivation layer is placed in a physical vapor deposition (PVD) carrier;
[0162] The temperature of the PVD carrier is controlled to be 400-700°C. Under the environment of N2 flow rate of 50-1000sccm, O2 flow rate of 500-5000sccm, Ar flow rate of 10-200sccm, and coating power of 2000-5000W, a 2-10nm AlN film is plated to obtain the AlN passivation layer, and the coating time is 10-100s.
[0163] For example, the temperature of the PVD carrier is controlled to be 500° C., and a 5 nm AlN film is deposited under an environment of a N2 flow rate of 500 sccm, an O2 flow rate of 1000 sccm, an Ar flow rate of 100 sccm, and a coating power of 3000 W to obtain the AlN passivation layer, and the coating time is 60 s.
[0164] In this implementation, the above conditions are used to grow an AlN passivation layer on a PVD carrier to ensure the growth process window, and a high-quality AlN film layer can be obtained; a 2-10nm AlN film can play a passivation and etching cutoff role. If it is too thin, there will be problems of poor local passivation, and if it is too thick, there will be problems of stress between film layers.
[0165] In another example, step 405 may include:
[0166] The SiN x The transistor structure of the passivation layer is placed on an atomic layer deposition (ALD) carrier and introduced into the coating chamber;
[0167] Pre-treating the transistor structure with NH3 for 5 to 20 seconds;
[0168] The temperature of the coating chamber is controlled to be 200-400° C., the coating power is 100-400W, a 2-10nm AlN film is coated to obtain the AlN passivation layer, and the coating time is 10-100s.
[0169] For example, the transistor structure is pretreated with NH3 for 10 seconds; the temperature of the coating chamber is controlled to be 300°C, the coating power is 300W, a 5nm AlN film is coated to obtain the AlN passivation layer, and the coating time is 60 seconds.
[0170] In this implementation, the above conditions are used to grow an AlN passivation layer on an ALD carrier to ensure the growth process window, and a high-quality AlN film layer can be obtained; a 2-10nm AlN film can play a passivation and etching cutoff role. If it is too thin, there will be problems of poor local passivation, and if it is too thick, there will be problems of stress between film layers.
[0171] In the embodiments of the present disclosure, the PVD or ALD process is used for film coating, which can effectively improve the density and uniformity of the AlN film layer and better achieve the etching cutoff effect.
[0172] 406. Fabricate an electrode structure and a passivation layer structure.
[0173] The electrode structure includes a gate, a source and a drain. The passivation layer structure includes a first SiN passivation layer, a second SiN passivation layer and a SiO2 passivation layer, and the first SiN passivation layer, the second SiN passivation layer and the SiO2 passivation layer sequentially cover the AlN passivation layer.
[0174] In the embodiment of the present disclosure, the gate, the source and the drain may include an ohmic contact portion, a first electrode portion and a second electrode portion, and the ohmic contact portion, the first electrode portion and the second electrode portion are connected in sequence.
[0175] Exemplarily, in the gate, the ohmic contact portion contacts the surface of the AlN passivation layer through the first SiN passivation layer, the first electrode portion contacts the ohmic contact portion through the second SiN passivation layer, and the second electrode portion contacts the first electrode portion through the SiO2 passivation layer.
[0176] Exemplarily, in the source and drain, the ohmic contact portion contacts the barrier layer through the first SiN passivation layer and the cap layer, the first electrode portion contacts the ohmic contact portion through the second SiN passivation layer, and the second electrode portion contacts the first electrode portion through the SiO2 passivation layer.
[0177] In the embodiment of the present disclosure, step 406 may include:
[0178] In the first step, after the epitaxial wafer is manufactured in steps 401 to 405, the epitaxial wafer is cleaned and a first SiN passivation layer of 10 to 50 nm is deposited on the epitaxial wafer using a low pressure chemical vapor deposition (LPCVD) device.
[0179] Figure 5 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Figure 5 As shown, the first SiN passivation layer 112 covers the epitaxial layer. In the embodiment of the present disclosure, the first SiN passivation layer 112 can cover the entire epitaxial layer, including the surface and the side, when the deposition is completed.
[0180] In the second step, ohmic contact holes are etched in the first SiN passivation layer by dry etching, wherein the bottoms of the ohmic contact holes corresponding to the source and drain are located in the barrier layer and are 1 to 5 nm away from the surface of the barrier layer, and the bottom of the ohmic contact hole corresponding to the gate is located in the AlN passivation layer.
[0181] Figure 6 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Figure 6 As shown, three ohmic contact holes 1120 are opened on the first SiN passivation layer 112 , wherein the bottoms of the two ohmic contact holes 1120 corresponding to the source and the drain are located at the barrier layer 102 , and the bottom of the ohmic contact hole 1120 corresponding to the gate is located at the AlN passivation layer 104 .
[0182] In the third step, ohmic contacts are respectively made in the three ohmic contact through holes.
[0183] The thickness of the ohmic contact portion is 300 to 600 nm.
[0184] Figure 7 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Figure 7 As shown, ohmic contact portions 1101 are respectively made in three ohmic contact through holes 1120 .
[0185] In the fourth step, ion implantation equipment is used to perform ion implantation on the epitaxial layer and the first SiN passivation layer to form an isolation region.
[0186] Figure 8 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Figure 8 As shown, an ion implantation region 2000 is formed in the epitaxial layer and the first SiN passivation layer 112 .
[0187] The fifth step is to deposit a second SiN passivation layer.
[0188] Fig. 9 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Fig. 9 As shown, the second SiN passivation layer 113 covers the first SiN passivation layer 112 .
[0189] Step 6: Use dry etching to etch three first through holes in the second SiN passivation layer.
[0190] The three first through holes are in contact with the three ohmic contact portions respectively.
[0191] Fig.10 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Fig.10As shown, three first through holes 1130 are opened on the second SiN passivation layer 113 .
[0192] In the seventh step, first electrode portions are respectively formed in the three first through holes.
[0193] Fig.11 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Fig.11 As shown, the first electrode portions 1102 are respectively made in the three first through holes 1130 .
[0194] Step 8: Deposit a SiO2 passivation layer.
[0195] Fig.12 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Fig.12 As shown, the SiO 2 passivation layer 114 covers the second SiN passivation layer 113 .
[0196] In the ninth step, three second through holes are etched in the SiO2 passivation layer by dry etching.
[0197] The three second through holes are in contact with the three first electrode portions respectively.
[0198] Fig.13 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Fig.13 As shown, three second through holes 1140 are opened on the SiO 2 passivation layer 114 .
[0199] In the tenth step, second electrode portions are respectively formed in the three second through holes.
[0200] Fig.14 is a schematic diagram of the structure of the transistor provided in the embodiment of the present disclosure during the manufacturing process, such as Fig.14 As shown, the second electrode portions 1103 are respectively made in the three second through holes 1140 .
[0201] Optionally, after the electrode structure is manufactured, the method may further include: manufacturing a protective layer.
[0202] The method provided in the embodiment of the present disclosure and the method provided in the related technology are used to respectively prepare SiN x Passivation layer, comparison of SiN made by two methods x The roughness of the passivation layer is shown in Table 1 below:
[0203] Table 1
[0204] Technology Roughness(nm) Related technologies 0.375 Embodiments of the present disclosure 0.142
[0205] It can be seen from Table 1 that the SiN xThe passivation layer has lower roughness, better density and uniformity.
[0206] The method provided in the embodiment of the present disclosure and the method provided in the related technology are used to respectively prepare SiN x Passivation layer, comparing the Idss leakage and Igss leakage of the transistor obtained by the two methods, as shown in Fig.15 and Fig.16 shown. Fig.15 and Fig.16 The horizontal axis is the current, in amperes; Fig.15 The vertical axis is the Idss leakage current, in amperes; Fig.16 The vertical axis is the Igss leakage current, in amperes.
[0207] exist Fig.15 and Fig.16 In the figure, the line corresponding to the right arrow is the transistor corresponding to the method provided by the embodiment of the present disclosure, and the line corresponding to the left arrow is the transistor corresponding to the method provided by the related art.
[0208] based on Fig.15 and Fig.16 As shown, the transistor manufactured by the method provided by the embodiment of the present disclosure has smaller leakage.
[0209] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A method for manufacturing a transistor, characterized in that: The method comprises: manufacturing a channel layer; forming a barrier layer on the channel layer; Si2H6 and NH3 are used as reactants to form SiN on the barrier layer. x Passivation layer, x is greater than 0; In the SiN x An AlN passivation layer is formed on the passivation layer.
2. The method according to claim 1, characterized in that The method of using Si2H6 and NH3 as reactants comprises: A mixed gas of Si2H6 and H2 or a mixed gas of Si2H6 and N2 with a flow rate of 20 to 10,000 sccm and NH3 with a flow rate of 5,000 to 50,000 sccm are used as reactants.
3. The method according to claim 2, characterized in that In the mixed gas of Si2H6 and H2 or the mixed gas of Si2H6 and N2, the proportion of Si2H6 is 1 / 10000 to 1000 / 10000.
4. The method according to claim 2, characterized in that: SiN is formed on the barrier layer. x Passivation layer, including: In an environment where the reaction chamber temperature is 800-1100° C. and the reaction chamber pressure is 50-400 mbar, the SiN with a thickness of 5-100 nm is grown. x Passivation layer.
5. The method according to any one of claims 1 to 4, characterized in that: In the SiN x An AlN passivation layer is formed on the passivation layer, comprising: The SiN x The transistor structure of the passivation layer is placed on a PVD carrier; The temperature of the PVD carrier is controlled to be 400-700°C. Under the environment of N2 flow rate of 50-1000sccm, O2 flow rate of 500-5000sccm, Ar flow rate of 10-200sccm, and coating power of 2000-5000W, a 2-10nm AlN film is plated to obtain the AlN passivation layer, and the coating time is 10-100s.
6. The method according to any one of claims 1 to 4, characterized in that: In the SiN x An AlN passivation layer is formed on the passivation layer, comprising: The SiN x The transistor structure of the passivation layer is placed on the ALD carrier and introduced into the coating chamber; Pre-treating the transistor structure with NH3 for 5 to 20 seconds; The temperature of the coating chamber is controlled to be 200-400° C., the coating power is 100-400W, a 2-10nm AlN film is coated to obtain the AlN passivation layer, and the coating time is 10-100s.
7. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: In making the SiN x Before the passivation layer is formed, a cap layer with a thickness of 0.5 to 5 nm is formed on the barrier layer in an environment where the reaction chamber temperature is 900 to 1200° C. and the reaction chamber pressure is 50 to 300 mbar.
8. A transistor, characterized in that: The transistor is manufactured by the method according to any one of claims 1 to 7, and the transistor comprises: A channel layer (101), a barrier layer (102), a SiN x The passivation layer (103) and the AlN passivation layer (104), x is greater than 0.
9. The transistor according to claim 8, characterized in that The SiN x The thickness of the passivation layer (103) is 5-100 nm.
10. The transistor according to claim 8, characterized in that The thickness of the AlN passivation layer (104) is 2-10 nm.