A planar-gate silicon carbide VDMOS for surge voltage resistance and its manufacturing method

Abstract

The present invention provides a planar-gate silicon carbide VDMOS for resisting surge voltage and a preparation method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer on the drift layer, etching, and ion implanting to form a protection region, a current sharing region, a second P-type well region, a Schottky region, a first P-type well region, and a protrusion; reforming the blocking layer, etching, and ion implanting to form an N-type source region; reforming the blocking layer, etching, and depositing to form an insulating dielectric layer; reforming the blocking layer, etching, and depositing metal to form a gate metal layer; reforming the blocking layer, etching, and depositing metal to form a source metal layer, and removing the blocking layer to complete the preparation, achieving the improvement of device reliability, reduction of device conduction loss, and improvement of the ability to resist surge voltage.

Description

Technical Field

[0001] The present invention relates to a planar-gate silicon carbide VDMOS for surge voltage resistance and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the performance requirements for devices vary in different fields, but generally, higher breakdown voltage capabilities, lower on-resistances, faster switching speeds, higher reliability (including gate reliability, drain voltage surge reliability, short-circuit reliability, etc.), and lower body diode conduction losses are required.

[0003] In fields such as aerospace, high reliability becomes the key restricting application. In fields such as aerospace and electric vehicles, large surge voltages are likely to occur. In application scenarios with high reliability requirements, improving the surge resistance of devices while ensuring low on-resistance of the devices is the key to special applications. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a planar-gate silicon carbide VDMOS for surge voltage resistance and a preparation method thereof. By optimizing the design of the protection area, current sharing area, and parasitic JBS body diode design of the device, the reliability of the device is improved, the conduction loss of the device is reduced, and the surge voltage resistance ability is enhanced.

[0005] In the first aspect, the present invention provides a preparation method of a planar-gate silicon carbide VDMOS for surge voltage resistance, including the following steps:

[0006] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0007] Step 2: Form a blocking layer on the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a protection area;

[0008] Step 3: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a current sharing area;

[0009] Step 4: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a second P-type well region;

[0010] Step 5: Remove the original blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a Schottky region;

[0011] Step 6: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through-hole, perform ion implantation to form a first P-type well region and a protrusion;

[0012] Step 7: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through-hole, perform ion implantation to form an N-type source region;

[0013] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through-hole, deposit to form an insulating dielectric layer;

[0014] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through-hole, deposit metal to form a gate metal layer;

[0015] Step 10: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form a through-hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0016] In a second aspect, the present invention provides a planar-gate silicon carbide VDMOS for resisting surge voltage, and the silicon carbide VDMOS is prepared by using the preparation method of a planar-gate silicon carbide VDMOS for resisting surge voltage described in the first aspect.

[0017] The advantages of the present invention are as follows:

[0018] 1. The present invention designs a protection area. When a large surge voltage is applied in the area of the protection area, a breakdown space charge region is formed between the drift layer and the protection area, thereby avoiding the impact of the drain surge voltage on the gate structure of the device;

[0019] 2. The present invention designs a current-sharing area, which is horizontally distributed on the left and right sides above the protection area, does not affect the surge voltage resistance ability of the protection area, and redistributes the current in the JFET area when the device is turned on to the left and right sides of the P-type protection area, thereby reducing the on-resistance of the device;

[0020] 3. On the basis of constructing a JBS body diode inside the device, a second P-type well region is constructed. The bottom of the second P-type well region is in direct contact with the current-sharing area, and a low-resistance path from the parasitic pn junction body diode of the device to the drain of the device is constructed, which can reduce the conduction loss of the device under high-current conditions. Description of the Drawings

[0021] The present invention will be further described below with reference to the drawings in conjunction with the embodiments.

[0022] Figure 1 It is a schematic diagram of a planar-gate silicon carbide VDMOS for resisting surge voltage of the present invention.

[0023] Figure 2 It is a process cross-section of a planar-gate silicon carbide VDMOS for resisting surge voltage of the present inventionFigure 1 。

[0024] Figure 3 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 2 。

[0025] Figure 4 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 3 。

[0026] Figure 5 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 4 。

[0027] Figure 6 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 5 。

[0028] Figure 7 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 6 。

[0029] Figure 8 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 7 。

[0030] Figure 9 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 8 。

[0031] Figure 10 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 9 。

[0032] Figure 11 Process cross-section of a planar-gate silicon carbide VDMOS with surge voltage resistance according to the present invention Figure 10 。 Detailed implementation manners

[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0036] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also have other orientations (such as rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0037] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0038] As Figures 1 to 11 shown, the embodiment of the present application provides a method for preparing a planar-gate silicon carbide VDMOS for surge voltage resistance, including the following steps:

[0039] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8; epitaxially grow on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0040] Step 2: Form a blocking layer 9 on the drift layer 2, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a protection region 21;

[0041] Step 3: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a current sharing region 22;

[0042] Step 4: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a second P-type well region 41;

[0043] Step 5: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a Schottky region 4;

[0044] Step 6: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form a first P-type well region 3 and a protrusion 23;

[0045] Step 7: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and perform ion implantation to form an N-type source region 31;

[0046] Step 8: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and deposit to form an insulating dielectric layer 5;

[0047] Step 9: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, and deposit metal to form a gate metal layer 6;

[0048] Step 10: Remove the original blocking layer, reform the blocking layer 9, etch the blocking layer 9 to form a through hole, deposit metal to form a source metal layer 7, and remove the blocking layer 9 to complete the preparation.

[0049] In this embodiment, preferably, the sum of the width of the current sharing region 22 and the width of the protection region 21 is equal to the width of the drift layer 2, and the width of the protection region 21 is equal to the width of the protrusion 23.

[0050] In this embodiment, preferably, the upper side of the protection region 21 and the lower side of the current sharing region 22 are located in the same plane.

[0051] Preferably, in this embodiment, the thickness of the protection region 21 is 300 nm; the thickness of the current sharing region 22 is 300 nm.

[0052] Preferably, in this embodiment, the silicon carbide substrate 1, the drift layer 2, the current sharing region 22, and the Schottky region 4 are all N-type, and the protection region 21 is P-type.

[0053] Preferably, in this embodiment, the doping concentration of the protection region 21 is greater than that of the drift layer 2; the doping concentration of the protection region 21 is greater than that of the current sharing region 22.

[0054] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0055] A silicon carbide substrate 1;

[0056] A drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a protection region 21, a current sharing region 22, and a protrusion 23 are provided in the drift layer 2; the protection region 21 is located below the current sharing region 22 and directly below the protrusion 23, and the current sharing region 22 is not directly below the protrusion 23;

[0057] A first P-type well region 3, the lower side of the first P-type well region 3 is connected to the upper side of the drift layer 2, and the inner side of the first P-type well region 3 is connected to the outer side of the protrusion 23; an N-type source region 31 is provided on the first P-type well region 3;

[0058] A Schottky region 4, the lower side of the Schottky region 4 is connected to the upper side of the drift layer 2, and the inner side of the Schottky region 4 is connected to the outer side of the first P-type well region 3; a second P-type well region 41 is provided in the Schottky region 4, and the lower part of the second P-type well region 41 passes through the drift layer 2 and is connected to the upper side of the current sharing region 22;

[0059] An insulating dielectric layer 5, the lower side of the insulating dielectric layer 5 is respectively connected to the upper side of the protrusion 23, the first P-type well region 3, and the N-type source region 31;

[0060] A gate metal layer 6, the gate metal layer 6 is connected to the insulating dielectric layer 5;

[0061] A source metal layer 7, the lower side of the source metal layer 7 is respectively connected to the upper side of the N-type source region 31, the upper side of the first P-type well region 3, the upper side of the second P-type well region 41, and the upper side of the Schottky region 4;

[0062] And a drain metal layer 8, the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1.

[0063] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e16 cm -3 , the doping concentration of the P-type protection region 21 is 5-12e17 cm -3 , the doping concentration of the N-type current sharing region 22 is 1-5e17 cm -3 , the doping concentration of the first P-type well region 3 is 1-5e17 cm -3 , the doping concentration of the N-type source region 31 is 2-8e18 cm -3 , the material of the insulating dielectric layer 5 can be silicon dioxide; the doping concentration of the first P-type well region 3 is less than that of the second P-type well region 41;

[0064] The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse breakdown voltage and the on-resistance of the device; the P-type protection region 21 is to construct a P-type buffer region directly under the gate of the device, thereby suppressing the impact of the large drain voltage on the gate structure; the doping concentration of the first P-type well region 3 is mainly considered in two aspects. One is to protect the gate and source structures of the device, and a relatively high doping concentration needs to be ensured. The other is to ensure that the charge of the gate is small, so that when the device is driven by the gate charge, a lower concentration needs to be ensured. Therefore, a compromise is made between the two, and this doping concentration is selected; the doping concentration of the N-type current sharing region 22 is mainly to reduce the on-resistance of the device without affecting the protection effect of the P-type protection region 21 of the device on the device structure; the N-type source region 31 is to reduce the ohmic contact resistance of the source of the device without damaging the device lattice due to too high a concentration during ion implantation and affecting the device stability;

[0065] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 30 - 100 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device. The thickness of the N-type source region 31 is 200 nm, the thickness of the first P-type well region 3 is 500 nm, the thickness of the N-type Schottky region 4 is 500 nm, the thickness of the N-type current-sharing region 22 is 300 nm, the thickness of the P-type protection region 21 is 300 nm. The top of the P-type protection region 21 is flush with the bottom of the N-type current-sharing region 22. The thickness of the insulating dielectric layer 5 is 50 nm, and the thickness of the source metal layer 7 is 200 nm. In this embodiment, a P-type protection region 21 is designed. When the drain of the device withstands a large surge voltage, a breakdown space charge region is formed in the N-type drift layer 2 and the P-type protection region 21, thereby avoiding the impact of the drain surge voltage on the gate structure of the device. An N-type current-sharing region 22 is designed in the device structure. The N-type current-sharing region 22 is horizontally distributed on both sides of the P-type protection region 21 and vertically distributed above the P-type protection region 21, so as not to affect the surge voltage resistance ability of the P-type protection region 21, and at the same time redistribute the current in the JFET region when the device is conducting to both sides of the P-type protection region 21, thereby reducing the on-resistance of the device.

[0066] On the basis of constructing a JBS body diode inside the device, a second P-type well region 41 is constructed on both sides of the device. The bottom of the second P-type well region 41 is in direct contact with the N-type current-sharing region 22, constructing a low-resistance path from the parasitic pn junction body diode of the device to the drain of the device, which can reduce the conduction loss under large current conditions of the device.

[0067] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a protection zone; Step 3, removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a current equalizing area; Step 4, removing the barrier layer of step 3, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a second P-type well region; Step 5, removing the barrier layer of step 4, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a Schottky region; Step 6, removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a first P-type well region and a protruding portion; Step 7, removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 8, removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating dielectric layer; Step 9, removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10, removing the barrier layer of step 9, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal to form a source metal layer, removing the barrier layer, and completing the preparation; The lower side of the drift layer is connected to the upper side of the silicon carbide substrate; a protection zone, a flow balancing zone and a protrusion are provided in the drift layer; the protection zone is located below the flow balancing zone and directly below the protrusion, and the flow balancing zone is not located directly below the protrusion; The lower side of the first P-type well region is connected to the upper side of the drift layer, and the inner side of the first P-type well region is connected to the outer side of the protrusion; an N-type source region is provided on the first P-type well region; The lower side of the Schottky region is connected to the upper side of the drift layer, and the inner side of the Schottky region is connected to the outer side of the first P-type well region; a second P-type well region is provided in the Schottky region, and the lower part of the second P-type well region passes through the drift layer and is connected to the upper side of the current balancing region; The lower side of the insulating dielectric layer is respectively connected to the upper side of the protrusion, the first P-type well region and the N-type source region; The gate metal layer is connected to the insulating dielectric layer; The lower side surface of the source metal layer is respectively connected to the upper side surface of the N-type source region, the upper side surface of the first P-type well region, the upper side surface of the second P-type well region and the upper side surface of the Schottky region.

2. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The sum of the width of the current balancing area and the width of the protection area is equal to the width of the drift layer, and the width of the protection area is equal to the width of the protrusion.

3. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The upper side surface of the protection zone and the lower side surface of the flow equalization zone are located in the same plane.

4. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The thickness of the protection zone is 300 nm; the thickness of the flow equalization zone is 300 nm.

5. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The silicon carbide substrate, drift layer, current balancing region and Schottky region are all N-type, and the protection region is P-type.

6. The method for preparing a planar gate silicon carbide VDMOS with surge voltage resistance according to claim 1, characterized in that: The doping concentration of the protection zone is greater than the doping concentration of the drift layer; the doping concentration of the protection zone is greater than the doping concentration of the current balancing zone.

7. A planar gate silicon carbide VDMOS with surge voltage resistance, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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