A left and right shielded trench-gate silicon carbide VDMOS and its manufacturing method

Abstract

The present invention provides a left-right shielded trench-gate silicon carbide VDMOS and a manufacturing method thereof. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a blocking layer above the drift layer, etching, and ion implanting to form a P-type source region, a low-resistance region, a P-type well region, and an N-type source region; reforming the blocking layer, etching to form a first groove, depositing to form an insulating dielectric layer; reforming the blocking layer, etching, and depositing metal to form a first gate metal layer and a second gate metal layer; reforming the blocking layer, etching, and depositing metal to form a first source metal layer; reforming the blocking layer, etching the blocking layer to form a via hole, etching the low-resistance region, the P-type source region, and the N-type source region, depositing metal to form a second source metal layer, and removing the blocking layer to complete the manufacturing. Through the design improvement of the shielded gate structure, the on-resistance of the device is reduced.

Description

Technical Field

[0001] The present invention relates to a left - right shielded trench - gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. For silicon carbide power VDMOS, the requirements for device performance vary in different fields. Generally speaking, the comprehensive requirements include higher breakdown voltage capability, lower on - resistance, faster switching speed, higher reliability (including gate reliability, drain - voltage - surge reliability, short - circuit reliability, etc.), and lower body - diode conduction loss.

[0003] For silicon carbide VDMOS devices in the range of 650 - 900V, there is an urgent need to provide a technical solution for silicon carbide VDMOS devices in the range of 650 - 900V to reduce their on - resistance and improve the switching speed. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a left - right shielded trench - gate silicon carbide VDMOS and a preparation method thereof. By improving the design of the shield - gate structure, the on - resistance of the device is reduced and the process difficulty is simplified.

[0005] In the first aspect, the present invention provides a preparation method of a left - right shielded trench - gate silicon carbide VDMOS, including the following steps:

[0006] Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially grow on the upper side of the silicon carbide substrate to form a drift layer;

[0007] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through - hole, and perform ion implantation to form a P - type source region;

[0008] Step 3: Remove the original blocking layer, re - form the blocking layer, etch the blocking layer to form a through - hole, and perform ion implantation to form a low - resistance region;

[0009] Step 4: Remove the original blocking layer, re - form the blocking layer, etch the blocking layer to form a through - hole, and perform ion implantation to form a P - type well region;

[0010] Step 5: Remove the original blocking layer, re - form the blocking layer, etch the blocking layer to form a through - hole, and perform ion implantation to form an N - type source region;

[0011] Step 6: Remove the original blocking layer, re - form the blocking layer, etch the blocking layer to form a through - hole, and etch the drift layer to form a first groove, and deposit to form an insulating dielectric layer;

[0012] Step 7: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form vias, etch the insulating dielectric layer to form a first trench and a second trench, deposit metal to form a first gate metal layer and a second gate metal layer;

[0013] Step 8: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form vias, etch the insulating dielectric layer to form a third trench, deposit metal to form a first source metal layer;

[0014] Step 9: Remove the original barrier layer, reform the barrier layer, etch the barrier layer to form vias, etch the low-resistance region, P-type source region and N-type source region, deposit metal to form a second source metal layer, remove the barrier layer, and complete the preparation.

[0015] In a second aspect, the present invention provides a left and right shielded trench gate silicon carbide VDMOS, which is prepared by using the preparation method of a left and right shielded trench gate silicon carbide VDMOS described in the first aspect.

[0016] The advantages of the present invention are as follows:

[0017] First, the present invention designs a first gate metal layer, a first source metal layer and a second gate metal layer, all of which are wrapped by an insulating dielectric layer. The depth of the first source metal layer is 1.5-3 times that of the first gate metal layer, so as to ensure that the first source metal layer distributed between the first gate metal layer and the second gate metal layer can assist in depleting the impurities in the epitaxial layer, thereby reducing the equivalent concentration of the epitaxial region near the left and right sides of the first source metal layer, avoiding the problem of large electric field breakdown caused by high doping concentration in the epitaxial region, and realizing the improvement of the doping concentration in the epitaxial region and the reduction of the on-resistance of the device;

[0018] Second, the first gate metal layer and the second gate metal layer of the present invention form a gate control structure - P-type source region - N-type low-resistance region structure. Through the expansion of the space charge region of the P-type source region, the device's low-doped P-type well region and N-type low-resistance region are protected when the drain bears a large voltage, improving the breakdown voltage resistance between the drain and the source of the device;

[0019] Third, due to the adoption of the gate control structure - P-type source region - N-type low-resistance region structure, the doping concentration of the P-type well region can be effectively reduced. Therefore, when the device gate controls the switching of the device, due to the reduction of the inversion layer concentration, the driving charge can be reduced, and the switching speed of the device can be improved;

[0020] Fourth, the first source metal layer and the second source metal layer of the present invention are distributed in the middle and top of the device and can be directly in contact with the source electrode, avoiding the problem of complex structure of the shielded gate source potential lead-out structure caused by the traditional up and down shielded gate structure, and reducing the complexity of the preparation process. Description of the Drawings

[0021] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0022] Figure 1 It is a schematic diagram of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention.

[0023] Figure 2 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 1 。

[0024] Figure 3 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 2 。

[0025] Figure 4 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 3 。

[0026] Figure 5 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 4 。

[0027] Figure 6 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 5 。

[0028] Figure 7 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 6 。

[0029] Figure 8 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 7 。

[0030] Figure 9 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 8 。

[0031] Figure 10 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 9 。

[0032] Figure 11 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 10 。

[0033] Figure 12 It is a process cross - section of a left - and - right - shielded trench - gate silicon carbide VDMOS of the present invention Figure 10 One.

[0034] Figure 13 Process cross-section of a left and right shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 II.

[0035] Figure 14 Process cross-section of a left and right shielded trench-gate silicon carbide VDMOS according to the present invention Figure 10 III. Specific embodiments

[0036] To facilitate understanding of the present application, the present application will be described more fully hereinafter with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application may be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application.

[0038] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0039] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature described in the figure with other elements or features. It should be understood that, in addition to the orientations described in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Therefore, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also include other orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0040] As used herein, the singular forms of "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0041] As Figures 1 to 14 shown, an embodiment of the present application provides a method for preparing a left - right shielded trench - gate silicon carbide VDMOS, including the following steps:

[0042] Step 1: Deposit metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 112; epitaxially grow on the upper side of the silicon carbide substrate 101 to form a drift layer 102;

[0043] Step 2: Form a blocking layer 113 above the drift layer 102, etch the blocking layer 113 to form a through - hole, and perform ion implantation to form a P - type source region 104;

[0044] Step 3: Remove the original blocking layer, reform the blocking layer 113, etch the blocking layer 113 to form a through - hole, and perform ion implantation to form a low - resistance region 103;

[0045] Step 4: Remove the original blocking layer, reform the blocking layer 113, etch the blocking layer 113 to form a through - hole, and perform ion implantation to form a P - type well region 105;

[0046] Step 5: Remove the original blocking layer, reform the blocking layer 113, etch the blocking layer 113 to form a through - hole, and perform ion implantation to form an N - type source region 106;

[0047] Step 6: Remove the original barrier layer, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, etch the drift layer 102 to form a first groove 1021, deposit to form an insulating dielectric layer 107;

[0048] Step 7: Remove the original barrier layer, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, etch the insulating dielectric layer 107 to form a first trench 1071 and a second trench 1072, deposit metal to form a first gate metal layer 108 and a second gate metal layer 109;

[0049] Step 8: Remove the original barrier layer, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, etch the insulating dielectric layer 107 to form a third trench 1073, deposit metal to form a first source metal layer 110;

[0050] Step 9: Remove the original barrier layer, reform the barrier layer 113, etch the barrier layer 113 to form a through hole, etch the low-resistance region 103, the P-type source region 104, and the N-type source region 106, deposit metal to form a second source metal layer 111, remove the barrier layer 113, and complete the preparation.

[0051] In this embodiment, preferably, the lower side surface of the insulating dielectric layer 107 is lower than the lower side surface of the P-type source region 105.

[0052] In this embodiment, preferably, the lower side surfaces of the first gate metal layer 108, the second gate metal layer 109, and the P-type well region 105 are located in the same plane.

[0053] In this embodiment, preferably, the depth of the third trench 1073 is greater than the depth of the first trench 1071.

[0054] In this embodiment, preferably, the thickness of the insulating dielectric layer 107 on the left side of the first gate metal layer 108 is less than the insulating dielectric layer 107 on the right side of the first gate metal layer 108.

[0055] In this embodiment, preferably, the thickness of the insulating dielectric layer 107 on the left side of the second gate metal layer 109 is greater than the insulating dielectric layer 107 on the right side of the second gate metal layer 109.

[0056] In this embodiment, preferably, the doping concentration of the P-type source region 104 is greater than the doping concentration of the low-resistance region 103, and the doping concentration of the low-resistance region 103 is greater than the doping concentration of the drift layer 102.

[0057] In this embodiment, preferably, the doping concentration of the P-type source region 104 is greater than the doping concentration of the P-type well region 105, and the doping concentration of the P-type source region 104 is greater than the doping concentration of the N-type source region 106.

[0058] As Figure 1 shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0059] A silicon carbide substrate 101;

[0060] A drift layer 102, the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a first groove 1021 and a second groove 1022 are provided on the drift layer 102;

[0061] A low-resistance region 103, the lower side of the low-resistance region 103 is connected to the upper side of the drift layer 102;

[0062] A P-type source region 104, the lower part of the P-type source region 104 is disposed in the second groove 1022, and the outer side of the P-type source region 104 is connected to the inner side of the low-resistance region 103;

[0063] A P-type well region 105, the lower side of the P-type well region 105 is connected to the upper side of the drift layer 102, and the outer side of the P-type well region 105 is connected to the inner side of the P-type source region 104;

[0064] An N-type source region 106, the lower side of the N-type source region 106 is connected to the upper side of the P-type well region 105, and the outer side of the N-type source region 106 is connected to the inner side of the P-type source region 104;

[0065] An insulating dielectric layer 107, the lower part of the insulating dielectric layer 107 is disposed in the first groove 1021, and the outer side of the insulating dielectric layer 107 is connected to the inner side of the P-type well region 105 and the inner side of the N-type source region 106; first trenches 1071, second trenches 1072 and third trenches 1073 are provided on the insulating dielectric layer 107;

[0066] A first gate metal layer 108, the first gate metal layer 108 is disposed in the first trench 1071;

[0067] A second gate metal layer 109, the second gate metal layer 109 is disposed in the second trench 1072;

[0068] A first source metal layer 110, the first source metal layer 110 is disposed in the third trench 1073;

[0069] A second source metal layer 111, the second source metal layer 111 is respectively connected to the low-resistance region 103, the P-type source region 104 and the N-type source region 106;

[0070] And a drain metal layer 112, the drain metal layer 112 is connected to the lower side of the silicon carbide substrate 101.

[0071] In another embodiment of the present invention, the silicon carbide substrate 101, the drift layer 102, and the low-resistance region 103 are all N-type; the doping concentration of the silicon carbide substrate 101 is 2-8e18 cm -3 , the doping concentration of the drift layer 102 is 5-9e17 cm -3 , the doping concentration of the low-resistance region 103 is 6-10e17 cm -3 , the doping concentration of the P-type well region 105 is 1-5e16 cm -3 , the doping concentration of the P-type source region 104 is 1-5e19 cm -3 , the material of the insulating dielectric layer 107 can be silicon dioxide, and the doping concentration of the N-type source region 106 is 2-8e18 cm -3 ; wherein, the doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 112 and reduce the overall on-resistance of the device; the doping concentration of the drift layer 102 is a trade-off between the reverse breakdown voltage and the on-resistance of the device. Due to the design of the left and right shield trench gate structure, the N-type drift layer 102 can increase the doping concentration on the basis of ensuring the breakdown voltage and reduce the on-resistance of the device; the doping concentration of the P-type well region 105 is to achieve the breakdown voltage of the pn junction structure of the device when the drain of the device bears a high voltage. Reducing the doping concentration can reduce the gate switching charge and reduce the drive loss; the concentration of the P-type source region 104 is to form a space charge region diffusing into the N-type drift layer 102 with the N-type drift layer 102 to achieve the protection of the P-type well 105 and the gate of the device when the drain bears a large voltage. At the same time, the P-type source region 104 also needs to achieve an ohmic contact with the second source metal layer 111, so as to complete the supplement of the device current capacity and improve the device current capacity when the freewheeling of the parasitic Schottky substrate diode of the device is insufficient; the doping concentration of the N-type low-resistance region 103 is to form a Schottky contact with the second source metal layer 111, reduce the on-voltage drop of the body diode of the device and ensure the reverse breakdown voltage;

[0072] The thickness of the N-type silicon carbide substrate 101 of the device is 500 nm, which is for forming a low-resistance ohmic contact with the drain metal layer 112 to reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 30 - 60 μm, which is adjusted within the above range according to different requirements for the breakdown voltage characteristics of the device, and the breakdown voltage range of the device is 650 - 900 V; the thickness of the second source metal layer 111 is 200 nm and the width is 3 μm; the thickness of the first source metal layer 110 is 1.5 - 3 times the thickness of the first gate metal layer 108, the thickness of the first source metal layer 110 is 900 - 1800 nm, and the width is 800 nm; the thickness of the P-type source region 104 is 600 nm and the width is 2 μm; the thickness of the N-type source region 106 is 100 nm and the width is 500 nm; the thickness of the P-type well region 105 is 300 nm and the width is 500 nm; the thickness of the N-type low-resistance region 103 is 400 nm and the width is 500 nm; the thicknesses of the first gate metal layer 108 and the second gate metal layer are both 600 nm, and the thickness of the insulating dielectric layer 107 directly below the first gate metal layer 108 is 150 nm; the width of the insulating dielectric layer 107 on one side of the first gate metal layer 108 and the second gate metal layer 109 and close to the P-type well region 105 is 50 nm, the width of the insulating dielectric layer 107 on the side away from the P-type well region 105 is 100 nm, the thickness of the insulating dielectric layer 107 directly below the first source metal layer 110 is 100 nm, and the widths of the first gate metal layer 108 and the second gate metal layer 109 are 300 - 500 nm;

[0073] Among them, the tops of the N-type low-resistance region 103, the P-type source region 104, and the N-type source region 106 are flush and are in direct contact with the second source metal layer 111, and the lower sides of the N-type low-resistance region 103, the P-type well region 105, the lower side of the first gate metal layer 108, and the lower side of the second gate metal layer 109 are flush.

[0074] In this embodiment, the first gate metal layer 108, the first source metal layer 110, and the second gate metal layer 109 are designed and are all wrapped by the insulating dielectric layer 107. Among them, the depth of the first source metal layer 110 is 1.5 - 3 times the depth of the first gate metal layer 108, so as to ensure that the first source metal layer 110 distributed between the first gate metal layer 108 and the second gate metal layer 109 can assist in depleting the impurities in the epitaxial layer, thereby reducing the equivalent concentration of the epitaxial regions on the left and right sides close to the first source metal layer 110, avoiding the problem of large electric field breakdown caused by high doping concentration in the epitaxial regions, achieving an increase in the doping concentration of the epitaxial regions, and reducing the on-resistance of the device;

[0075] In this embodiment, the first gate metal layer 108 and the second gate metal layer 109 form a gate-controlled structure - P-type source region - N-type low-resistance region structure. Through the extension of the space charge region of the P-type source region 104, when the drain bears a large voltage, the low-doped P-type well region 105 and the N-type low-resistance region 103 of the device are protected, improving the drain-source breakdown voltage capability of the device; due to the adoption of the gate-controlled structure - P-type source region - N-type low-resistance region structure, the doping concentration of the P-type well region 105 can be effectively reduced. Thus, when the device gate controls the switching of the device, since the inversion layer concentration is reduced, the driving charge can be reduced, improving the switching speed of the device; the first source metal layer 110 and the second source metal layer 111 are distributed in the middle and at the top of the device and can be directly in contact with the source electrode, avoiding the problem of the complex structure of the shielding gate source potential lead-out structure caused by the traditional up-and-down shielding gate structure, and reducing the complexity of the manufacturing process.

[0076] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.

Claims

1. A method for preparing left and right shielded trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a low resistance area; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to form a first groove, and deposit to form an insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a first trench and a second trench, depositing metal to form a first gate metal layer and a second gate metal layer; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a third trench, depositing metal, and forming a first source metal layer; Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the low resistance area, P-type source area and N-type source area, deposit metal to form a second source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the insulating dielectric layer is lower than the lower side surface of the P-type source region.

3. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the first gate metal layer, the lower side surface of the second gate metal layer and the lower side surface of the P-type well region are located in the same plane.

4. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The depth of the third trench is greater than the depth of the first trench.

5. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating dielectric layer on the left side of the first gate metal layer is smaller than that of the insulating dielectric layer on the right side of the first gate metal layer.

6. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the insulating dielectric layer on the left side of the second gate metal layer is greater than that of the insulating dielectric layer on the right side of the second gate metal layer.

7. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the low resistance region, and the doping concentration of the low resistance region is greater than the doping concentration of the drift layer.

8. The method for preparing a left-right shielded trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type source region is greater than the doping concentration of the N-type source region.

9. A left and right shielded trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 8.

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