Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; an active pattern extending in a first direction on the substrate; a plurality of channel layers on the active pattern and spaced apart from each other in a vertical direction; a gate structure crossing the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction orthogonal to the first direction; and a source / drain pattern on a region of the active pattern on both sides of the gate structure and having a semiconductor liner connected to each of side surfaces of the plurality of channel layers and a semiconductor fill layer on the semiconductor liner. The semiconductor liner layer includes silicon germanium (SiGe) doped with a first conductivity type impurity. The semiconductor filling layer includes an epitaxial layer having a germanium (Ge) concentration higher than a germanium (Ge) concentration of the semiconductor liner layer, and the epitaxial layer is doped with Ga.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0139862 filed on October 18, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0003] As demands for achieving high performance, high speed, and / or multi-functions of semiconductor devices increase, the integration degree of semiconductor devices has been increasing.

[0004] Recently, in order to overcome limitations in operating characteristics due to reductions in the size of planar metal oxide semiconductor field effect transistors (FETs) (MOSFETs), semiconductor devices having three-dimensional channels have been developed. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a semiconductor device having improved electrical characteristics and reliability.

[0006] Example embodiments of the inventive concepts provide a method of manufacturing a semiconductor device having improved electrical characteristics and reliability.

[0007] An example embodiment of the inventive concept provides a semiconductor device, including: a substrate; an active pattern extending in a first direction on the substrate; a plurality of channel layers, on the active pattern, the plurality of channel layers are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure intersecting the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction, the second direction being orthogonal to the first direction; and a source / drain pattern, on a region of the active pattern on both sides of the gate structure, the source / drain pattern having a semiconductor liner connected to each of the side surfaces of the plurality of channel layers and a semiconductor filling layer on the semiconductor liner. The semiconductor liner may include silicon germanium (SiGe) doped with a first conductive type impurity. The semiconductor filling layer may include an epitaxial layer, the epitaxial layer having a Ge concentration greater than a germanium (Ge) concentration of the semiconductor liner, and the epitaxial layer is doped with Ga.

[0008] An example embodiment of the inventive concept also provides a semiconductor device, including: a substrate; an active pattern extending in a first direction on the substrate; a plurality of channel layers, on the active pattern, the plurality of channel layers are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a gate structure intersecting the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction, the second direction being orthogonal to the first direction; a source / drain pattern, on a region of the active pattern on both sides of the gate structure, the source / drain pattern having a semiconductor liner connected to each of the side surfaces of the plurality of channel layers and a semiconductor contact layer conformally on the semiconductor liner, the source / drain pattern defining a trench, and the semiconductor contact layer covering the semiconductor liner in the trench; a metal-semiconductor compound layer filling the trench, the metal-semiconductor compound layer contacting the semiconductor contact layer. The semiconductor liner may include a first epitaxial layer doped with a first impurity of a second conductivity type. The semiconductor contact layer may include a second epitaxial layer doped with a second impurity of a second conductivity type.

[0009] Example embodiments of the inventive concept also provide a semiconductor device, comprising: a substrate having a first region and a second region; a first active pattern and a second active pattern, extending in a first direction in the first region and the second region of the substrate, respectively; a plurality of first channel layers, on the first active pattern, the plurality of first channel layers are spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a plurality of second channel layers, on the second active pattern, the plurality of second channel layers are spaced apart from each other in the vertical direction; a first gate structure, intersecting the first active pattern, the first gate structure surrounding the plurality of first channel layers and extending in a second direction, the second direction being orthogonal to the first direction; a second gate structure, intersecting the second active pattern, the second gate structure surrounding the plurality of second channel layers and extending in the second direction; a first source / drain pattern, on regions of the first active pattern on both sides of the first gate structure, the first The source / drain pattern has a first semiconductor liner connected to each of the side surfaces of the plurality of first channel layers and a semiconductor filling layer on the first semiconductor liner; a second source / drain pattern, on the region on both sides of the second active pattern of the second gate structure, the second source / drain pattern has a second semiconductor liner connected to each of the side surfaces of the plurality of second channel layers and a semiconductor contact layer conformally on the second semiconductor liner; a second source / drain pattern, defining a groove, and the semiconductor contact layer covers the second semiconductor liner in the groove; a first metal-semiconductor compound layer, covering the first semiconductor liner and the semiconductor filling layer; a second metal-semiconductor compound layer, filling the groove, the second metal-semiconductor compound layer contacts the semiconductor contact layer; and a first contact structure and a second contact structure, respectively on the first metal-semiconductor compound layer and the second metal-semiconductor compound layer. The first semiconductor liner includes silicon germanium (SiGe) doped with a first conductive type impurity, the semiconductor filling layer includes an epitaxial layer, the epitaxial layer has a Ge concentration greater than a germanium (Ge) concentration of the semiconductor liner, and the epitaxial layer is doped with Ga. The second semiconductor liner layer includes a first epitaxial layer doped with a second conductivity type first impurity, and the semiconductor contact layer includes a second epitaxial layer doped with a second conductivity type second impurity.

[0010] An example embodiment of the inventive concept provides a method for manufacturing a semiconductor device, the method comprising: preparing a fin structure on a substrate, the fin structure comprising a first semiconductor pattern and a second semiconductor pattern formed of different materials and alternately stacked, and a dummy gate structure intersecting the fin structure; forming a first groove for a first source / drain pattern by removing a portion of the fin structure on both sides of the dummy gate structure, and two side surfaces of the fin structure are exposed in the first groove; forming a gap between the second semiconductor patterns by removing a portion of the first semiconductor pattern below the dummy gate structure from the exposed two side surfaces; in each of the first grooves, forming a first semiconductor liner from a bottom surface of the first groove along a side surface of the second semiconductor pattern, the first semiconductor liner comprising silicon germanium (SiGe) doped with a first conductive type impurity; conformally forming a first barrier layer on the first semiconductor liner ; forming a first sacrificial filling layer including SiGe on the first barrier layer, the first sacrificial filling layer filling the first groove; forming a first semiconductor cap layer on the first sacrificial filling layer; forming an interlayer insulating layer on the substrate, the interlayer insulating layer covering the first semiconductor cap layer; removing the dummy gate structure, and forming an active gate structure in the space from which the dummy gate structure is removed and in the gap; forming a first contact hole in the interlayer insulating layer, the first contact hole extending to the first semiconductor cap layer; removing the first semiconductor cap layer and the first sacrificial filling layer from the first contact hole; providing a high concentration of first conductive type impurities to the first barrier layer; forming a semiconductor filling layer including germanium, the semiconductor filling layer filling the space from which the first sacrificial filling layer is removed; forming a first metal-semiconductor compound layer by silicideing the upper portion of the semiconductor filling layer; and forming a first contact structure connected to the first metal-semiconductor compound layer in the first contact hole.

[0011] An example embodiment of the inventive concept also provides a method for manufacturing a semiconductor device, the method comprising: preparing a fin structure on a substrate, the fin structure comprising a first semiconductor pattern and a second semiconductor pattern formed of different materials and alternately stacked, and a dummy gate structure intersecting the fin structure; forming a second groove for a second source / drain pattern by removing a portion of the fin structure on both sides of the dummy gate structure, and two side surfaces of the fin structure are exposed in the second groove; forming a gap between the second semiconductor patterns by removing a portion of the first semiconductor pattern below the dummy gate structure from the exposed two side surfaces; in each of the second grooves, forming a second semiconductor liner including silicon (Si) from a bottom surface of the second groove along a side surface of the second semiconductor pattern; conformally forming a second barrier layer on the second semiconductor liner; forming a second barrier layer including silicon on the second barrier layer A second sacrificial filling layer of germanium (SiGe), the second sacrificial filling layer filling the second groove; forming a second semiconductor cap layer on the second sacrificial filling layer; forming an interlayer insulating layer on the substrate, the interlayer insulating layer covering the second semiconductor cap layer; removing the dummy gate structure, and forming an active gate structure in the space from which the dummy gate structure is removed and in the gap; forming a second contact hole in the interlayer insulating layer, the second contact hole extending to the second semiconductor cap layer; removing the second semiconductor cap layer and the second sacrificial filling layer from the second contact hole; applying second conductive type impurities to the second barrier layer; forming a semiconductor contact layer on the second barrier layer so that the groove from which the second sacrificial filling layer is removed is retained; forming a second metal-semiconductor compound layer filling the groove by silicideing a portion of the semiconductor film; and forming a second contact structure connected to the second metal-semiconductor compound layer in the second contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a plan view showing a semiconductor device according to some example embodiments of the inventive concept;

[0014] Figure 2 yes Figure 1 A cross-sectional view of a semiconductor device taken along line II';

[0015] Figure 3A and Figure 3B yes Figure 1 sectional views of the semiconductor device taken along line II1-II1' and line II2-II2', respectively;

[0016] Figure 4 It is shown Figure 2a graph of a P-type impurity concentration distribution in a first source / drain pattern;

[0017] Figure 5A and Figure 5B is a graph showing an impurity concentration distribution of a first source / drain pattern applicable to various example embodiments of the inventive concept;

[0018] Figure 6 is a plan view showing a semiconductor device according to some example embodiments of the inventive concept;

[0019] Figure 7 yes Figure 6 A cross-sectional view of a semiconductor device taken along line II';

[0020] Fig. 8A and Figure 8B yes Figure 6 sectional views of the semiconductor device taken along lines II1-II1' and II2-II2', respectively;

[0021] Fig. 9 It is shown Figure 7 a graph of N-type impurity concentration distribution in a second source / drain pattern;

[0022] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a cross-sectional view illustrating a process of forming a fin structure and a dummy gate structure of a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept;

[0023] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E and Fig.11F is a cross-sectional view illustrating a process of forming a preliminary source / drain pattern of a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts; and

[0024] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E and Fig.12F are cross-sectional views illustrating a process of forming an active source / drain pattern and a contact structure of a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0025] Hereinafter, various exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0026] When the terms "about" or "substantially" are used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with geometric shapes, it is intended that the precision of the geometric shape is not required, but rather the tolerance of the shape is within the disclosed range. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween (such as, increments of 0.1%).

[0027] In addition, for example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C (such as, for example, ABC, AB, BC, and AC).

[0028] Figure 1 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept. Figure 2 yes Figure 1 1 is a cross-sectional view of a semiconductor device taken along line II'. Figure 3A and Figure 3B They are Figure 1 sectional views of the semiconductor device taken along line II1-II1' and line II2-II2'.

[0029] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B , a semiconductor device 100A according to some example embodiments may include a substrate 101, an active pattern 105 protruding on the substrate 101 and extending in a first direction (e.g., an X direction), a plurality of channel layers 131, 132, 133, and 134 disposed on the active pattern 105, and a gate structure 160 intersecting the active pattern 105 and extending in a second direction (e.g., a Y direction). The plurality of channel layers 131, 132, 133, and 134 may be disposed on the active pattern 105 to be spaced apart from each other in a direction (e.g., a Z direction) perpendicular to an upper surface of the substrate 101.

[0030] The semiconductor device 100A may further include: a first source / drain pattern 140 (also referred to as a "first active source / drain") disposed on both sides of the gate structure 160 to contact both side surfaces of the plurality of channel layers 131, 132, 133, and 134, a first metal-semiconductor compound layer 180A disposed on the first source / drain pattern 140, and a first contact structure 190A connected to the first source / drain pattern 140 through the first metal-semiconductor compound layer 180A. The semiconductor device according to some example embodiments may be a P-type metal oxide semiconductor field effect transistor (MOSFET).

[0031] In some example embodiments, as described above, the active pattern 105 may have a fin type structure extending and protruding in the first direction (eg, X direction). For example, the substrate 101 may be a semiconductor substrate (eg, a silicon substrate or a germanium substrate, or a silicon on insulator (SOI) substrate). Figure 3A and Figure 3B , the isolation layer 110 may define the active pattern 105. The isolation layer 110 may be disposed on the substrate 101 to cover the side surface of the active pattern 105 of the substrate 101. The isolation layer 110 may be formed such that an upper region of the active pattern 105 is exposed. In some example embodiments, the isolation layer 110 may have a curved upper surface having a higher height as the distance from the active pattern 105 decreases. For example, the isolation layer 110 may include an oxide film, a nitride film, or a combination thereof.

[0032] In some example embodiments, the isolation layer 110 may be formed using a shallow trench isolation (STI) process. In some other example embodiments, the isolation layer 110 may further include a region extending deeper below the upper surface of the substrate 101. The region extending deeper may also be referred to as a deep trench isolation (DTI).

[0033] and Figure 1 Refer to Figure 2 and Figure 3B As described above, the upper surface of the active pattern 105 may protrude from the upper surface of the isolation layer 110. The channel structure 130 according to some example embodiments is exemplified as including four channel layers 131, 132, 133, and 134, which are disposed on the upper surface of the active pattern 105 to be spaced apart from each other in a direction (e.g., Z direction) perpendicular to the upper surface of the substrate 101. However, the inventive concept is not limited thereto, and the channel structure 130 may be implemented with a different number (e.g., three) of channel layers.

[0034] like Figure 2As shown in the figure, the gate structure 160 may include a gate electrode 165 extending in a second direction (e.g., the Y direction) and surrounding a plurality of channel layers 131, 132, 133, and 134, a gate insulating layer 162 disposed between the gate electrode 165 and the plurality of channel layers 131, 132, 133, and 134, a spacer 164 disposed on a side surface of the gate insulating layer 162, and a gate covering layer 166 disposed on the gate electrode 165.

[0035] like Figure 2 As shown in FIG. 1 , the gate insulating layer 162 may be disposed between the active pattern 105 and the gate electrode 165 and between the plurality of channel layers 131, 132, 133, and 134 and the gate electrode 165. The gate insulating layer 162 may be formed to surround the plurality of channel layers 131, 132, 133, and 134 in the second direction (e.g., the Y direction), and may extend from the upper surface of the active pattern 105 to the upper surface of the isolation layer 110 (see FIG. 1 ). Figure 3B For example, the gate insulating layer 162 may include oxide, nitride, or a high-κ material. The high-κ material may refer to a material having a higher 2 ) dielectric material with a high dielectric constant. High κ materials may include, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ) at least one of ).

[0036] The gate electrode 165 may be disposed on the upper portion of the active pattern 105 to fill the space between the plurality of channel layers 131, 132, 133, and 134, and extend to the upper portion of the uppermost fourth channel layer 134. The gate electrode 165 may be spaced apart from the plurality of channel layers 131, 132, 133, and 134 by the gate insulating layer 162. The gate electrode 165 may include a conductive material (e.g., a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or a metal material (e.g., aluminum (Al), tungsten (W), or molybdenum (Mo)), or a semiconductor material (e.g., doped polysilicon)). In some example embodiments, the gate electrode 165 may include two or more multilayers.

[0037] The gate spacer 164 may be disposed on both side surfaces of the gate electrode 165. The gate spacer 164 may insulate the source / drain region 140A and the gate electrode 165 from each other. In some example embodiments, the gate spacer 164 may have a multilayer structure. For example, the gate spacer 164 may include oxide, nitride, and oxynitride, and may particularly include a low-κ film.

[0038] Reference Figure 1 and Figure 2 , the channel structure 130 and the active pattern 105 located on both sides of the gate structure 160 may be partially removed to form a groove for the first source / drain pattern 140. Side surfaces of the plurality of channel layers 131, 132, 133, and 134 may be exposed through the groove, and the first source / drain pattern 140 may contact both side surfaces of each of the plurality of channel layers 131, 132, 133, and 134 in the first direction (X direction).

[0039] Reference Figure 2 , the width of each of the first to fourth channel layers 131, 132, 133, and 134 in the first direction (e.g., X direction) may be the same as or similar to (e.g., slightly narrower than) the width of the active pattern 105. The width of each of the first to fourth channel layers 131, 132, 133, and 134 in the first direction (e.g., X direction) may be the same as or similar to the width of the gate structure 160. In some example embodiments, the widths of the first to fourth channel layers 131, 132, 133, and 134 may be slightly different from each other.

[0040] The first to fourth channel layers 131, 132, 133, and 134 may include a semiconductor material capable of providing a channel region. For example, the first to fourth channel layers 131, 132, 133, and 134 may be semiconductor patterns (such as silicon (Si), silicon germanium (SiGe), or germanium (Ge)). In some example embodiments, the first to fourth channel layers 131, 132, 133, and 134 may be formed of the same material as that of the substrate 101 (e.g., silicon). In some example embodiments, regions of the first to fourth channel layers 131, 132, 133, and 134 adjacent to the first source / drain pattern 140 may include an impurity region.

[0041] The first source / drain pattern 140 according to some example embodiments may be a source / drain pattern for a P-type MOSFET.

[0042] Reference Figure 2 and Figure 3A , the first source / drain pattern 140 may be disposed in the groove and may include a semiconductor liner 141 (also referred to as a “first semiconductor liner”) connected to side surfaces of the first to fourth channel layers 131 , 132 , 133 , and 134 , and a semiconductor filling layer 145 disposed on the semiconductor liner 141 .

[0043] The semiconductor liner 141 may be disposed on one region of the active pattern 105 along each of the side surfaces of the plurality of channel layers 131, 132, 133, and 134. The semiconductor liner 141 may be disposed in a groove in a first direction (e.g., X direction), and a groove extending in a second direction (e.g., Y direction) may be provided therein. The groove may be a deep groove extending to a depth at which the groove at least partially overlaps the lowermost first channel layer 131.

[0044] The semiconductor filling layer 145 may be formed by filling the trench to cover the semiconductor liner 141. The semiconductor filling layer 145 may at least partially overlap the lowermost first channel layer 131 in a direction parallel to the upper surface of the substrate 101. In some example embodiments, the bottom of the semiconductor filling layer 145 may be located at a height lower than that of the lowermost first channel layer 131, the height being taken, for example, from the upper surface of the substrate 101.

[0045] The semiconductor liner 141 and the semiconductor filling layer 145 may have different compositions. The semiconductor liner 141 may include silicon germanium (SiGe) doped with P-type (or first conductivity type) impurities. For example, the P-type impurities may be at least one of boron (B), gallium (Ga), and indium (In). In some example embodiments, the semiconductor liner 141 may be SiGe doped with B. In some example embodiments, the semiconductor liner 141 may include a first epitaxial layer and a second epitaxial layer, the first epitaxial layer including germanium (Ge) having a first concentration, and the second epitaxial layer including germanium (Ge) having a second concentration higher than the first concentration. For example, the first concentration may be 5at% to 20at%, and the second concentration may be 20at% to 60at%.

[0046] The semiconductor filling layer 145 may include an epitaxial layer having a composition capable of applying compressive stress. For example, the epitaxial layer included in the semiconductor filling layer 145 may include a germanium concentration higher than the germanium (Ge) concentration of the semiconductor liner 141. For example, the Ge concentration of the semiconductor filling layer 145 may be 70at% or more. In some example embodiments, the Ge concentration of the semiconductor filling layer 145 may be 80at% or more. For example, the epitaxial layer included in the semiconductor filling layer 145 may be Ge, SiGe, or GeSn. Figure 3A , the first source / drain pattern 140 (specifically, the semiconductor filling layer 145 ) may have a pentagonal cross-section.

[0047] As described above, the semiconductor filling layer 145 according to some example embodiments may be formed in a "deep trench", and thus compressive stress may be effectively applied to the first to fourth channel layers 131, 132, 133, and 134 in a horizontal direction. The semiconductor filling layer 145 may include an epitaxial layer including germanium (Ge) as its main component, and thus gallium (Ga) may be used as a P-type impurity suitable therefor. Even when the semiconductor filling layer 145 has a significantly high germanium concentration (e.g., 70 at % or more), sufficient conductivity may be ensured by such impurity doping.

[0048] The interlayer insulating layer 115 may be disposed on the isolation layer 110 to cover the first source / drain pattern 140 and the gate structure 160 (see Figure 3A ). For example, the interlayer insulating layer 115 may include at least one of oxide, nitride, and oxynitride, and may include a low-κ material.

[0049] Reference Figure 2 and Figure 3A, the semiconductor device 100A according to some example embodiments may further include a first contact structure 190A passing through the interlayer insulating layer 115 and a first metal-semiconductor compound layer 180A between the first source / drain pattern 140 and the first contact structure 190A. The first metal-semiconductor compound layer 180A may reduce the contact resistance between the first source / drain pattern 140 and the first contact structure 190A. In some example embodiments, the first metal-semiconductor compound layer 180A may be disposed to cover the upper surface of the first source / drain pattern 140 (i.e., the semiconductor liner 141 and the semiconductor filling layer 145).

[0050] In some example embodiments, the first metal-semiconductor compound layer 180A may be formed mainly by silicideing a portion of the semiconductor filling layer 145. For example, the first metal-semiconductor compound layer 180A may include TiGe:Ga, TiSiGe:Ga, or TiGeSn:Ga.

[0051] An electrical signal may be applied to the first source / drain pattern 140 through the first contact structure 190A. The first contact structure 190A may be disposed on the first source / drain pattern 140. In some example embodiments, the first contact structure 190A may have a lower portion having a width narrower than a width of an upper portion thereof. For example, the first contact structure 190A or the first metal-semiconductor compound layer 180A may overlap at least a portion of the uppermost fourth channel layer 134 in a horizontal direction. For example, the first contact structure 190A may include a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)). The first contact structure 190A may also include a barrier material film (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) surrounding the metal material.

[0052] The first source / drain pattern 140 according to some example embodiments may provide a deep trench for forming the semiconductor filling layer 145. In some example embodiments, as described above, the deep trench may be defined by the first sacrificial filling layer 143 disposed on the semiconductor liner 141. Fig. 12A and Fig. 12B ), an ex-situ doping process may be performed. The doping process may be performed using plasma doping (PLAD) or ion implantation. The P-type impurities supplied in the doping process may have a unique concentration distribution in the boundary region between the semiconductor liner 141 and the semiconductor filling layer 145.

[0053] Figure 4 It is shown Figure 2 FIG. 1 is a graph showing a P-type impurity concentration distribution in the first source / drain pattern 140 . Figure 4 The graph schematically shows Figure 2Distribution of the P-type impurity concentration along a1 - a2 in the first source / drain pattern 140 .

[0054] Reference Figure 4 , the semiconductor liner 141 may include silicon germanium (SiGe:B) doped with boron (B), and the semiconductor filling layer 145 may include germanium (Ge:Ga) doped with gallium (Ga). As described above, an example is shown in which the surface of the semiconductor liner 141 is doped with a high concentration of indium (In) (additional P-type impurities) before the semiconductor filling layer 145 is formed. In a subsequent annealing process (such as millisecond annealing (MSA) or nanosecond annealing (NSA)), the P-type impurities may diffuse into other adjacent layers 141 or 145. Specifically, indium (In) doped with a high concentration may diffuse into the adjacent semiconductor liner 141 and the semiconductor filling layer 145. However, the concentration of the added indium (In) may have a concentration peak in the boundary region ML1 between the semiconductor liner 141 and the semiconductor filling layer 145.

[0055] Even when other P-type impurities (Ga and B) are injected into the semiconductor liner 141 before the semiconductor filling layer 145 is formed, the other P-type impurities (Ga and B) may have a concentration peak in the boundary region ML1 between the semiconductor liner 141 and the semiconductor filling layer 145 .

[0056] Reference Figure 5A and Figure 5B In a similar manner to that described above, the semiconductor liner 141 may include silicon germanium doped with boron (B) (SiGe:B), and the semiconductor filling layer 145 may include germanium doped with gallium (Ga) (Ge:Ga).

[0057] Figure 5A The graph of shows an example in which the surface of the semiconductor liner 141 is doped with a high concentration of gallium (Ga(D)) (additional P-type impurities) before the semiconductor filling layer 145 is formed. That is, the additional P-type impurity (Ga(D)) may be the same as the P-type impurity (Ga(145)) of the semiconductor filling layer 145. In the impurity analysis of the final structure, the concentration distribution of gallium (Ga) (indicated by a solid line) may also have a concentration peak in the boundary region ML1 between the semiconductor liner 141 and the semiconductor filling layer 145.

[0058] Figure 5BThe graph of shows an example in which the surface of the semiconductor liner 141 is doped with a high concentration of gallium (B(D)) (additional P-type impurities) before the semiconductor filling layer 145 is formed. That is, the additional P-type impurities (B(D)) may be the same as the P-type impurities (B(141)) of the semiconductor liner 141. In the impurity analysis of the final structure, the concentration distribution of boron (B) (indicated by a solid line) may also have a concentration peak in the boundary region ML1 between the semiconductor liner 141 and the semiconductor filling layer 145.

[0059] Thus, in some example embodiments, the first sacrificial filling layer 143 (see Fig. 12A and Fig. 12B ) Perform a P-type impurity doping process from the surface of the deep trench from which it is removed as an ex-situ doping process. By performing this doping process, a specific P-type impurity can have a unique concentration distribution in the boundary region between the semiconductor liner 141 and the semiconductor filling layer 145.

[0060] Figure 6 are plan views illustrating semiconductor devices according to some example embodiments of the inventive concept. Figure 7 yes Figure 6 1 is a cross-sectional view of a semiconductor device taken along line II'. Fig. 8A and Figure 8B They are Figure 6 sectional views of the semiconductor device taken along lines II1-II1' and II2-II2'.

[0061] Reference Figure 6 , Figure 7 , Fig. 8A and Figure 8B , except that the second source / drain pattern 150 (also referred to as a “second active source / drain pattern”) includes an N-type epitaxial layer, the semiconductor device 100B has a structure different from that of the first source / drain pattern 140 according to the above-described example embodiments, and the second metal-semiconductor compound layer is located in the deep trench, the semiconductor device 100B according to some example embodiments may be understood as being similar to Figures 1 to 3B Unless otherwise specified, reference may be made to the semiconductor device 100A shown in FIG. Figures 1 to 3B The components according to the example embodiments can be understood by referring to the description of the same or similar components of the semiconductor device 100A shown in FIG. The semiconductor device 100A according to the above example embodiments may be implemented as a P-type MOSFET, and the following description of the components according to the example embodiments may be understood by referring to the description of the same or similar components of the semiconductor device 100A shown in FIG. Figures 6 to 9 The described semiconductor device 100B according to example embodiments may be understood as being implemented as an N-type MOSFET.

[0062] The semiconductor device 100B (N-type MOSFET according to some example embodiments) may be formed in different regions of the same substrate together with the semiconductor device 100A (P-type MOSFET according to the above example embodiments). FIG. 10A to FIG. 10D , FIG. 11A to FIG. 11F and FIG. 12A to FIG. 12F The described manufacturing process forms two semiconductor devices 100A and 100B simultaneously on the same substrate 101 .

[0063] and Figure 6 Refer to Figure 7 and Fig. 8A , the second source / drain pattern 150 according to some example embodiments may be a source / drain pattern for an N-type MOSFET.

[0064] The second source / drain pattern 150 in the source / drain region 150A may include a semiconductor liner 151 (also referred to as a “second semiconductor liner”) disposed in the groove and connected to side surfaces of the first to fourth channel layers 131 , 132 , 133 , and 134 , and a semiconductor contact layer 155 disposed on the semiconductor liner 151 .

[0065] The semiconductor liner 151 may be disposed on one region of the active pattern 105 along each of the side surfaces of the plurality of channel layers 131, 132, 133, and 134. The semiconductor liner 151 may be disposed in a groove in a first direction (e.g., X direction), and a first trench extending in a second direction (e.g., Y direction) may be provided therein. The semiconductor contact layer 155 may be conformally disposed on the semiconductor liner 151, and a second trench extending in a second direction (e.g., Y direction) may be provided therein in a manner similar to the first trench. The second trench may be a deep trench extending to a depth at which the second trench at least partially overlaps the lowermost first channel layer 131. In this way, the second source / drain pattern 150 may have a second trench space surrounded by the semiconductor contact layer 155.

[0066] The semiconductor liner 151 may include a first epitaxial layer doped with a second conductive type (N-type) first impurity. In some example embodiments, the semiconductor liner 151 may include a first silicon epitaxial layer (as a first epitaxial layer) that is intentionally undoped or doped with a first concentration of a first impurity, and a second silicon epitaxial layer (as a second epitaxial layer) doped with a second concentration of the first impurity that is higher than the first concentration. For example, the first silicon epitaxial layer may be Si, and the second silicon epitaxial layer may be silicon doped with phosphorus (P) (Si:P). The semiconductor contact layer 155 may include a second epitaxial layer doped with an N-type second impurity. In some example embodiments, the semiconductor contact layer 155 may be silicon doped with As and P (Si:As,P). For example, at least one of the N-type first impurity and the N-type second impurity may include at least one of P, As, Sb, and Bi.

[0067] The second metal-semiconductor compound layer 180B according to some example embodiments may be formed to fill a deep second trench space in the semiconductor contact layer 155. Therefore, the second metal-semiconductor compound layer 180B may overlap at least a portion of the lowermost first channel layer 131 among the plurality of channel structures 130 in a direction parallel to the upper surface of the substrate.

[0068] The second metal-semiconductor compound layer 180B may be formed mainly by silicideing a portion of the semiconductor contact layer 155. The second metal-semiconductor compound layer 180B according to some example embodiments may include a material capable of applying tensile stress. For example, the second metal-semiconductor compound layer 180B may include TiSi:As,P. As described above, the second metal-semiconductor compound layer 180B according to some example embodiments may be formed in the “deep second trench”, and thus tensile stress may be effectively applied to the first to fourth channel layers 131, 132, 133, and 134 in the horizontal direction. The second metal-semiconductor compound layer 180B may be formed in the “deep second trench”, and thus may have a large contact area with the semiconductor contact layer 155, and may structurally greatly reduce contact resistance.

[0069] The second source / drain pattern 150 according to some example embodiments may provide a deep first trench for forming the semiconductor contact layer 155. In some example embodiments, as described above, the first trench may be defined by the second sacrificial filling layer 153 disposed on the semiconductor liner 151. Fig.12D ), an ex-situ doping process may be performed. The N-type impurities supplied in the doping process may have a unique concentration profile in a boundary region between the semiconductor liner layer 151 and the semiconductor contact layer 155 .

[0070] Fig. 9 It is shown Figure 7FIG. 1 is a graph showing a concentration distribution of N-type impurities in the second source / drain pattern 150. FIG. Fig. 9 The graph schematically shows Figure 7 The N-type impurity concentration distribution along b1 - b2 in the second source / drain pattern 150 .

[0071] Reference Fig. 9 , the semiconductor liner 151 may include silicon (SiP) doped with phosphorus (P), and the semiconductor contact layer 155 may include silicon (SiP) doped with phosphorus (P). As described above, an example is shown in which the surface of the semiconductor liner 151 is doped with high concentration of arsenic (As) (additional N-type impurities) before the semiconductor contact layer 155 is formed. In the subsequent annealing process, the N-type impurities may diffuse into other adjacent layers 151 or 155. Specifically, the high-concentration doped arsenic (As) may diffuse into the adjacent semiconductor liner 151 and the semiconductor contact layer 155. However, the concentration of the added arsenic (As) may have a concentration peak in the boundary region ML2 between the semiconductor liner 151 and the semiconductor contact layer 155.

[0072] Figure 1 and Figure 2 The semiconductor device 100A (P-type MOSFET) shown in FIG. Figure 6 and Figure 7 The semiconductor devices 100B (N-type MOSFET) shown in the figure can each be formed using a unique manufacturing process. Mainly, a preliminary source / drain pattern including a sacrificial filling layer for a deep trench structure can be formed after forming a groove, and a contact hole can be formed after forming an active gate structure 160. Subsequently, an epitaxial structure for compressive stress (e.g., a P-type source / drain pattern 140) or a metal-semiconductor compound structure for tensile stress (e.g., an N-type source / drain pattern 150) can be formed in each deep trench space obtained by removing the sacrificial filling layer.

[0073] According to some example embodiments, the first source / drain pattern 140 and the second source / drain pattern 150 may be formed in different regions of the same substrate. FIG. 10A to FIG. 10D , FIG. 11A to FIG. 11F as well as FIG. 12A to FIG. 12F The manufacturing process described in the accompanying drawings simultaneously forms two semiconductor devices 100A and 100B on the same substrate 101.

[0074] FIG. 10A to FIG. 10D 1 is a cross-sectional view showing a process of forming a fin structure and a dummy gate structure of a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept. The process of forming the fin structure FS and the dummy gate structure 170 may be performed together in a first region A for a P-type MOSFET and a second region B for an N-type MOSFET of a substrate 101.

[0075] First, refer to Fig. 10A , a semiconductor stack ST in which the first semiconductor layers 120L and the second semiconductor layers 130L are alternately stacked may be formed on the substrate 101. The semiconductor stack ST may be formed on the first region A and the second region B of the substrate 101.

[0076] The first semiconductor layer 120L may be removed in a subsequent process and used as a sacrificial layer, and the second semiconductor layer 130L may be used as a channel layer. The first semiconductor layer 120L and the second semiconductor layer 130L may include a semiconductor material such as silicon (Si) or silicon germanium (SiGe). In some example embodiments, the first semiconductor layer 120L and the second semiconductor layer 130L may include different semiconductor materials. The first semiconductor layer 120L may be formed of a material having a high etching selectivity relative to the second semiconductor layer 130L. The second semiconductor layer 130L may include impurities, but the inventive concept is not limited thereto.

[0077] In some example embodiments, the first semiconductor layer 120L may include silicon germanium (SiGe), and the second semiconductor layer 130L may include silicon (Si). The first semiconductor layer 120L and the second semiconductor layer 130L may be grown on the substrate 101 using an epitaxial growth process. Each of the first semiconductor layer 120L and the second semiconductor layer 130L may have a thickness ranging from about 1 nm to 100 nm.

[0078] Reference Fig. 10B , an active structure may be formed by removing a portion of the semiconductor stack ST and the substrate 101 using a first mask pattern M1 extending in a first direction (eg, X direction).

[0079] The active structure may include a portion of the active pattern 105 and a fin structure FS. The active pattern 105 may protrude from the upper surface of the substrate 101 by removing a portion of the substrate 101, and the fin structure FS may include a first semiconductor pattern 120 and a second semiconductor pattern 130 alternately stacked on the active pattern 105. The active pattern 105 and the fin structure FS may have a linear shape extending in a direction such as a first direction (e.g., an X direction). The isolation layer 110 may be formed in a region where a portion of the substrate 101 is removed by filling an insulating material and then performing an etch-back process so that a portion of the active pattern 105 protrudes. That is, the etch-back process may be performed so that the upper surface of the isolation layer 110 is lower than the upper surface of the active pattern 105.

[0080] Reference Fig. 10C , a dummy gate structure 170 extending in the second direction (eg, the Y direction) may be formed to intersect a portion of the active structure.

[0081] The dummy gate structure 170 may be formed in a subsequent process. Figure 2 131, 132, 133, and 134 shown in the figure, and a sacrificial structure in the region where the gate insulating layer 162 and the gate electrode 165 are provided. The dummy gate structure 170 may have a linear shape intersecting the active structure and extending in the second direction (e.g., the Y direction), and may be spaced apart from each other in the first direction (e.g., the X direction). A first sacrificial gate layer 172 and a second sacrificial gate layer 175 may be formed, and then the stack may be patterned using a second mask pattern M2, thereby forming a dummy gate structure 170 extending in the second direction (e.g., the Y direction), the first sacrificial gate layer 172 and the second sacrificial gate layer 175 being sequentially stacked on the substrate 101 (specifically, the isolation layer 110) on which the active structure is formed. In some example embodiments, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The second mask pattern M2 may include silicon oxide and / or silicon nitride.

[0082] Reference Fig. 10D , the gate spacers 164 may be formed on both side surfaces of the dummy gate structure 170 and both side surfaces of the active structure, respectively.

[0083] A spacer material layer may be conformally formed on the dummy gate structure 170 and the active structure, and then anisotropic etching may be applied to form a gate spacer 164 on both side surfaces of the dummy gate structure 170. Portions of the gate spacer 164 may be disposed on both side surfaces of the active structure (i.e., on both side surfaces of the active pattern 105 and the fin structure FS). The two side surfaces on which the gate spacer 164 is formed may be side surfaces of the dummy gate structure 170 that are opposite to each other in a first direction (e.g., X direction). The gate spacer 164 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0084] FIG. 11A to FIG. 11F are cross-sectional views illustrating a process of forming a preliminary source / drain pattern of a method of fabricating a semiconductor device according to some example embodiments of the inventive concepts. FIG. 11A to FIG. 11F Show Fig. 10D A cross-sectional view of the semiconductor structure taken along line II'.

[0085] Subsequent processes of forming the first preliminary source / drain pattern 140 ′ and the second preliminary source / drain pattern 150 ′ may be sequentially performed in the first region A for the P-type MOSFET and the second region B for the N-type MOSFET of the substrate 101 .

[0086] Reference Fig.11A, a first photomask PR1 may be formed in the second region B, and then portions of the fin structure FS located on both sides of the dummy gate structure 170 may be removed from the first region A to form a first groove RC1.

[0087] Here, the sacrificial layer 120 may correspond to Fig.11A The first semiconductor pattern 120 shown in FIG. 1 and the channel layers 131, 132, 133 and 134 may correspond to Fig.11A The second semiconductor pattern 130 is shown in FIG.

[0088] The exposed sacrificial layer 120 and the channel layers 131, 132, 133, and 134 may be removed using the second mask pattern M2 and the gate spacer 164 as a mask. Such a process may be used to determine the length of the channel layers 131, 132, 133, and 134 in a first direction (e.g., X direction). The sacrificial layer 120 and the channel layers 131, 132, 133, and 134 may be partially and additionally removed from the side surface below the dummy gate structure 170, and each of the sacrificial layer 120 and the channel layers 131, 132, 133, and 134 may have a width in the first direction (e.g., X direction) that is smaller than the width of the lower portion of the structure including the dummy gate structure 170 and the gate spacer 164.

[0089] Reference Fig. 11B , in the first region A, a first semiconductor liner 141 and a first barrier layer 142 may be sequentially formed in the first groove RC1 located on both sides of the dummy gate structure 170 .

[0090] The first semiconductor liner 141 may be formed on the region of the active pattern 105 along each of the side surfaces of the plurality of channel layers 131, 132, 133, and 134. In some example embodiments, the first semiconductor liner 141 may be SiGe doped with a P-type impurity (e.g., B). In some example embodiments, the first semiconductor liner 141 may include a first epitaxial layer including germanium (Ge) having a first concentration and a second epitaxial layer including germanium (Ge) having a second concentration higher than the first concentration. For example, the first concentration may be 5 at% to 20 at%, and the second concentration may be 20 at% to 60 at%.

[0091] The first barrier layer 142 may be formed on the first semiconductor liner 141. The first barrier layer 142 may include a material having selectivity with respect to the first sacrificial filling layer 143 to be formed in a subsequent process. For example, the first barrier layer 142 may include silicon.

[0092] Reference Fig. 11CIn the first region A, a first sacrificial filling layer 143 and a first semiconductor capping layer 144 may be formed on the first barrier layer 142 in the first groove RC1 , thereby forming a desired first preliminary source / drain pattern 140 ′.

[0093] The first sacrificial filling layer 143 may include silicon germanium. For example, the germanium concentration of the first sacrificial filling layer 143 may be 5at% to 70at%. The first sacrificial filling layer 143 may define a deep trench space. Subsequently, a first semiconductor capping layer 144 may be formed to cover an upper surface of the first sacrificial filling layer 143. In some example embodiments, the first semiconductor capping layer 144 may include an epitaxial layer (e.g., SiGe:B) that is the same as or similar to the first semiconductor liner 141. Thus, the first preliminary source / drain pattern 140' may be formed in the first recess RC1.

[0094] Reference Fig.11D , the first photomask PR1 may be removed from the second region B of the substrate 101, and a second photomask PR2 may be formed covering the first region A of the substrate 101. Subsequently, a second groove RC2 may be formed in the second region B of the substrate 101, and then a second preliminary source / drain pattern 150' may be formed.

[0095] With FIG. 11A to FIG. 11C In a manner similar to the process shown in , a second preliminary source / drain pattern 150' may be provided by sequentially forming a second semiconductor liner 151, a second barrier layer 152, a second sacrificial filling layer 153, and a second semiconductor cap layer 154 in the second groove RC2. The second semiconductor liner 151 may include a first epitaxial layer doped with a first impurity of a second conductivity type (N-type). The second semiconductor liner 151 may be formed in the second groove RC2 in a first direction (e.g., X direction). Specifically, the second semiconductor liner 151 may be formed to have a first trench extending in a second direction (e.g., Y direction) therein. In some example embodiments, the second semiconductor liner 151 may include a first silicon epitaxial layer and a second silicon epitaxial layer, the first silicon epitaxial layer being intentionally undoped or doped with a first concentration of a first impurity, and the second silicon epitaxial layer being doped with a second concentration of a first impurity higher than the first concentration. For example, the first silicon epitaxial layer may be Si, and the second silicon epitaxial layer may be silicon doped with phosphorus (P) (Si:P).

[0096] Subsequently, a second barrier layer 152, a second sacrificial filling layer 153, and a second semiconductor cap layer 154 may be sequentially formed on the second semiconductor liner 151. The second barrier layer 152 may include a material that is selective to the second sacrificial filling layer 153. For example, the second barrier layer 152 may include silicon, and the second sacrificial filling layer 153 may include silicon germanium. For example, similar to the germanium concentration of the first sacrificial filling layer 143, the germanium concentration of the second sacrificial filling layer 153 may be 5at% to 70at%. The second semiconductor cap layer 154 may be formed to cover the second sacrificial filling layer 153. In some example embodiments, the second semiconductor cap layer 154 may include an epitaxial layer (e.g., Si:P) that is the same as or similar to the second semiconductor liner 151.

[0097] Reference Fig.11E , the interlayer insulating layer 115 may be formed, and the sacrificial layer 120 and the dummy gate structure 170 may be removed to form the gap region G1 and the gate space G2.

[0098] First, an interlayer insulating layer 115 may be formed by forming an insulating film covering the dummy gate structure 170 and the first and second preliminary source / drain patterns 140' and 150' and performing a planarization process. The sacrificial layer 120 and the dummy gate structure 170 may be selectively removed relative to the gate spacer 164, the interlayer insulating layer 115, and the channel layers 131, 132, 133, and 134. First, the gate space G2 may be formed by removing the dummy gate structure 170 together with the second mask pattern M2, and then the sacrificial layer 120 exposed by the gate space G2 may be removed to form the gap region G1. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel layer includes silicon (Si), the sacrificial layer 120 may be selectively removed by performing a wet etching process using peracetic acid as an etchant. During such a removal process, the first preliminary source / drain pattern 140 ′ and the second preliminary source / drain pattern 150 ′ may be protected by the interlayer insulating layer 115 .

[0099] Reference Fig.11F , a gate structure 160 may be formed in the gap region G1 and the gate space G2.

[0100] The gate insulating layer 162 may be formed to conformally cover the inner surfaces of the gap region G1 and the gate space G2. The gate electrode 165 may be formed to fill the gap region G1 and the gate space G2, and then the gate electrode 165 is removed from the upper portion of the gate space G2 to a desired (and / or optionally, predetermined) depth. The gate capping layer 166 may be formed in the region where the gate electrode 165 is removed from the gate space G2. Such a process may be used to form a gate structure 160 including a gate insulating layer 162, a gate electrode 165, a gate spacer 164, and a gate capping layer 166.

[0101] FIG. 12A to FIG. 12F 2 is a cross-sectional view illustrating a process of forming first and second active source / drain patterns and first and second contact structures of a method of fabricating a semiconductor device according to some example embodiments of the inventive concept.

[0102] Subsequent processes of forming the first and second active source / drain patterns 140 and 150 may be sequentially performed in the first region A for the P-type MOSFET and the second region B for the N-type MOSFET of the substrate 101 .

[0103] Reference Fig. 12A , first and second contact holes CH1 and CH2 connected to the first and second preliminary source / drain patterns 140' and 150', respectively, may be formed to pass through the interlayer insulating layer 115 in the first and second regions, respectively, and the first insulating barrier layer 211 may be conformally formed to cover the first and second regions A and B. For example, the first insulating barrier layer 211 may include silicon nitride or aluminum nitride.

[0104] Reference Fig. 12B A third photomask PR3 may be formed on the first insulating barrier layer 211 in the second region B, and the first preliminary source / drain pattern 140' may be selectively exposed in the first region A. Subsequently, the first semiconductor capping layer 144 and the first sacrificial filling layer 143 may be sequentially removed to form a first trench DT1.

[0105] During the process of removing the first sacrificial filling layer 143, the first semiconductor liner 141 may be protected by the first barrier layer 142. Even after this process, the first barrier layer 142 may remain. An additional non-in-situ doping process may be applied to the remaining first barrier layer 142. The doping process may be performed using plasma doping or ion implantation. The additional P-type impurities may be, for example, at least one of boron (B), gallium (Ga), and indium (In). In some example embodiments, no additional doping process may be applied. For example, when the remaining first barrier layer 142 has a significantly small thickness (e.g., 1 nm or less), the P-type impurities may diffuse from the first semiconductor liner 141 or the semiconductor filling layer 145 in a subsequent process, so that an additional doping process may not be required.

[0106] Reference Fig. 12C The first source / drain pattern 140 may be formed by forming a semiconductor filling layer 145 on the first semiconductor liner 141 in the first region A. Subsequently, a second insulating barrier layer 212 may be formed on the first region A and the second region B after removing the third photomask PR3 from the second region B.

[0107] The semiconductor filling layer 145 may include an epitaxial layer having a composition capable of applying compressive stress. For example, the epitaxial layer included in the semiconductor filling layer 145 may have a germanium (Ge) concentration higher than the germanium (Ge) concentration of the first semiconductor liner 141. For example, the Ge concentration of the semiconductor filling layer 145 may be 70at% or more. For example, the epitaxial layer included in the semiconductor filling layer 145 may be Ge, SiGe, or GeSn. As described above, the semiconductor filling layer 145 may be formed in a "deep trench", so that compressive stress can be effectively applied to the first to fourth channel layers 131, 132, 133, and 134 in the horizontal direction. In some example embodiments, the semiconductor filling layer 145 may be formed to cover the upper end of the first semiconductor liner 141 while filling the trench in the first semiconductor liner 141.

[0108] Before forming the second insulating barrier layer 212, the remaining first insulating barrier layer 211 may be removed. Before or after removing the third photomask PR3, an additional annealing process may be applied to diffuse the P-type impurities doped into the remaining first barrier layer 142. The additionally diffused P-type impurities may have a unique concentration profile in the boundary region ML1 between the first semiconductor liner layer 141 and the semiconductor filling layer 145 (see FIG. Figure 4 ).

[0109] Reference Fig.12D , a fourth photomask PR4 may be formed on the second insulating barrier layer 212 in the first region A, and the second preliminary source / drain pattern 150' may be selectively exposed in the second region B. Subsequently, the second semiconductor cap layer 154 and the second sacrificial filling layer 153 may be removed. Such a process may be performed in the same manner as in reference Fig. 12B The described process is performed in a similar manner.

[0110] Reference Fig.12E , the second source / drain pattern 150 may be formed by forming a semiconductor contact layer 155 ′ on the second semiconductor liner 151 in the second region B. Subsequently, the fourth photomask PR4 may be removed from the second region B.

[0111] The semiconductor contact layer 155' may be conformally disposed on the second semiconductor liner 151, and may be formed to have a second trench DT2 therein extending in a second direction (e.g., Y direction) in a manner similar to the first trench. For example, the second source / drain pattern 150 may include a semiconductor contact layer 155' covering the second semiconductor liner 151. The second source / drain pattern 150 may define a second trench. The semiconductor contact layer 155' may cover the second semiconductor liner 151 within the second trench. Before forming the semiconductor contact layer 155', the remaining second barrier layer may be doped with N-type impurities. An additional annealing process may be used to diffuse the N-type impurities. For example, the N-type impurities may be at least one of P, As, Sb, and Bi. The additionally diffused N-type impurities may have a unique concentration profile in the boundary region ML2 between the second semiconductor liner 151 and the semiconductor contact layer 155 (see Fig. 9 ).

[0112] In some example embodiments, no additional doping process may be applied. For example, when the remaining second barrier layer 152 has a significantly small thickness (e.g., 1 nm or less), N-type impurities may diffuse from the second semiconductor liner 151 or the semiconductor contact layer 155' in a subsequent process, so that an additional doping process may not be required.

[0113] Reference Fig.12F After removing the remaining second barrier layer 152, the upper regions of the semiconductor filling layer 145 and the semiconductor contact layer 155 may be silicided to form a first metal-semiconductor compound layer 180A and a second metal-semiconductor compound layer 180B, respectively, and then a first contact structure 190A and a second contact structure 190B, respectively.

[0114] First, in the first region A, the upper region of the semiconductor filling layer 145 may be silicided to form a first metal-semiconductor compound layer 180A. For example, the first metal-semiconductor compound layer 180A may include TiGe:Ga, TiSiGe:Ga, or TiGeSn:Ga. In the second region B, a portion of the semiconductor contact layer 155 may be silicided to form a second metal-semiconductor compound layer 180B. The second metal-semiconductor compound layer 180B according to some example embodiments may include a material capable of applying tensile stress. For example, the second metal-semiconductor compound layer 180B may include TiSi:As,P. Specifically, the second metal-semiconductor compound layer 180B may be formed in the “deep second trench”, and thus tensile stress may be effectively applied to the first to fourth channel layers 131, 132, 133, and 134 in the horizontal direction in the second region B. The second metal-semiconductor compound layer 180B may be formed in the “deep second trench”, and thus may have a large contact area with the semiconductor contact layer 155, and may greatly reduce contact resistance. The processes of forming the first metal-semiconductor compound layer 180A and the second metal-semiconductor compound layer 180B may be performed simultaneously. Subsequently, the first contact structure 190A and the second contact structure 190B respectively connected to the first metal-semiconductor compound layer 180A and the second metal-semiconductor compound layer 180B may be formed.

[0115] According to the above-described example embodiments, the first source / drain pattern (e.g., P-MOSFET) may have a deep trench doped with Ga, and may include a semiconductor filling layer containing Ge at a high concentration (e.g., 70 at% or more). The semiconductor filling layer may effectively apply sufficient compressive stress to the first channel layer. The second source / drain pattern (e.g., N-MOSFET) may include a metal-semiconductor compound layer (e.g., TiSiAsP) that provides tensile stress to the deep trench. The metal-semiconductor compound layer may not only reduce contact resistance by a sufficient contact area, but also apply sufficient tensile stress to all second channel layers.

[0116] In some example embodiments, after the process of forming the deep trench (the process of removing the SiGe layer), a process of additionally applying impurities to the remaining etching stopper layer (e.g., Si) may be performed. The source / drain pattern may have an impurity concentration peak in a boundary region between the semiconductor liner layer and the semiconductor filling layer (semiconductor contact layer).

[0117] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: substrate; an active pattern extending in a first direction on the substrate; a plurality of channel layers, on the active pattern, the plurality of channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; A gate structure intersecting the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction, the second direction being orthogonal to the first direction; as well as a source / drain pattern having a semiconductor liner connected to each of the plurality of side surfaces of the plurality of channel layers and a semiconductor filling layer on the semiconductor liner on a region of the active pattern on both sides of the gate structure, The semiconductor liner includes silicon germanium SiGe doped with first conductive type impurities, and the semiconductor filling layer includes an epitaxial layer having a Ge concentration greater than a Ge concentration of the semiconductor liner, and the epitaxial layer is doped with Ga.

2. The semiconductor device according to claim 1, wherein The Ge concentration of the semiconductor filling layer is 70 at % or more.

3. The semiconductor device according to claim 2, wherein: The semiconductor filling layer includes Ge, SiGe or GeSn.

4. The semiconductor device according to claim 1, wherein The semiconductor filling layer overlaps at least a portion of a lowermost channel layer among the plurality of channel layers in a direction parallel to an upper surface of the substrate.

5. The semiconductor device according to claim 1, wherein The semiconductor liner includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer includes germanium with a first concentration, and the second epitaxial layer includes germanium with a second concentration greater than the first concentration.

6. The semiconductor device according to claim 5, wherein: The first concentration of the first epitaxial layer is 5 at % to 20 at %, and The second concentration of the second epitaxial layer is 20 at % to 60 at %.

7. The semiconductor device according to claim 1, further comprising: a metal-semiconductor compound layer covering the semiconductor liner layer and the semiconductor filling layer; as well as Contact structure, on the metal-semiconductor compound layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The first conductive type impurity includes at least one of B, Ga, and In.

9. The semiconductor device according to claim 8, wherein: The concentration distribution of the first conductive type impurity from the semiconductor liner layer to the semiconductor filling layer has a peak in a boundary region between the semiconductor liner layer and the semiconductor filling layer.

10. A semiconductor device comprising: substrate; an active pattern extending in a first direction on the substrate; a plurality of channel layers, on the active pattern, the plurality of channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; A gate structure intersecting the active pattern, the gate structure surrounding the plurality of channel layers and extending in a second direction, the second direction being orthogonal to the first direction; a source / drain pattern having a semiconductor liner connected to each of a plurality of side surfaces of the plurality of channel layers and a semiconductor contact layer conformally on the semiconductor liner, on a region of the active pattern on both sides of the gate structure, wherein the source / drain pattern defines a trench and the semiconductor contact layer covers the semiconductor liner within the trench; and A metal-semiconductor compound layer fills the trench, the metal-semiconductor compound layer contacts the semiconductor contact layer, The semiconductor liner layer includes a first epitaxial layer doped with first impurities of a second conductivity type, and the semiconductor contact layer includes a second epitaxial layer doped with second impurities of the second conductivity type.

11. The semiconductor device according to claim 10, wherein The metal-semiconductor compound layer overlaps at least a portion of a lowermost channel layer among the plurality of channel layers in a direction parallel to an upper surface of the substrate.

12. The semiconductor device according to claim 10, wherein: The semiconductor liner includes a first silicon epitaxial layer as a first epitaxial layer intentionally undoped or doped with a first impurity at a first concentration, and a second silicon epitaxial layer as a second epitaxial layer doped with the first impurity at a second concentration, and the second concentration is greater than the first concentration.

13. The semiconductor device according to claim 10, wherein: At least one of the first impurity and the second impurity includes at least one of P, As, Sb, and Bi.

14. The semiconductor device according to claim 10, wherein: The first impurity of the semiconductor liner includes P, and The second impurity of the semiconductor contact layer includes As and P.

15. The semiconductor device according to any one of claims 10 to 14, wherein: A concentration distribution of at least one of the first impurity and the second impurity from the semiconductor liner layer to the semiconductor contact layer has a peak in a boundary region between the semiconductor liner layer and the semiconductor contact layer.

16. A semiconductor device comprising: a substrate having a first region and a second region; A first active pattern and a second active pattern extending in a first direction in a first region and a second region of the substrate, respectively; a plurality of first channel layers on the first active pattern, the plurality of first channel layers being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; a plurality of second channel layers, on the second active pattern, the plurality of second channel layers being spaced apart from each other in the vertical direction; A first gate structure intersecting the first active pattern, the first gate structure surrounding the plurality of first channel layers and extending in a second direction, the second direction being orthogonal to the first direction; a second gate structure intersecting the second active pattern, the second gate structure surrounding the plurality of second channel layers and extending in a second direction; a first source / drain pattern having a first semiconductor liner connected to each of a plurality of side surfaces of the plurality of first channel layers and a semiconductor filling layer on the first semiconductor liner on a region of the first active pattern on both sides of the first gate structure; a second source / drain pattern on a region of the second active pattern on both sides of the second gate structure, the second source / drain pattern having a second semiconductor liner connected to each of a plurality of side surfaces of the plurality of second channel layers and a semiconductor contact layer conformally on the second semiconductor liner, wherein the second source / drain pattern defines a trench, and the semiconductor contact layer covers the second semiconductor liner within the trench; a first metal-semiconductor compound layer covering the first semiconductor liner and the semiconductor filling layer; a second metal-semiconductor compound layer filling the trench, the second metal-semiconductor compound layer being in contact with the semiconductor contact layer; and The first contact structure and the second contact structure are respectively disposed on the first metal-semiconductor compound layer and the second metal-semiconductor compound layer, The first semiconductor liner includes silicon germanium SiGe doped with first conductive type impurities, and the semiconductor filling layer includes an epitaxial layer, the epitaxial layer has a Ge concentration greater than the Ge concentration of the first semiconductor liner, and the epitaxial layer is doped with Ga, and The second semiconductor liner layer includes a first epitaxial layer doped with first impurities of a second conductivity type, and the semiconductor contact layer includes a second epitaxial layer doped with second impurities of the second conductivity type.

17. The semiconductor device according to claim 16, wherein: The semiconductor filling layer includes Ge, SiGe or GeSn, and The Ge concentration of the semiconductor filling layer is 70 at % or more.

18. The semiconductor device according to claim 16, wherein: The semiconductor filling layer overlaps at least a portion of the lowest first channel layer among the plurality of first channel layers in a direction parallel to the upper surface of the substrate, and The second metal-semiconductor compound layer overlaps at least a portion of a lowermost second channel layer among the plurality of second channel layers in a direction parallel to the upper surface of the substrate.

19. The semiconductor device according to claim 16, wherein: The concentration distribution of the first conductive type impurity from the first semiconductor liner layer to the semiconductor filling layer has a peak in a boundary region between the first semiconductor liner layer and the semiconductor filling layer.

20. The semiconductor device according to any one of claims 16 to 19, wherein: The first semiconductor liner includes a third epitaxial layer and a fourth epitaxial layer, the third epitaxial layer includes germanium with a first concentration, the fourth epitaxial layer includes germanium with a second concentration, the second concentration is greater than the first concentration, The first concentration of the third epitaxial layer is 5 at % to 20 at %, and The second concentration of the fourth epitaxial layer is 20 at % to 60 at %.

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