Semiconductor device with increased operating voltage characteristics

Abstract

The invention relates to a semiconductor device having increased operating voltage characteristics. A semiconductor device, such as a gate-all-around field effect transistor (GAAFET), may provide advantages in terms of higher operating voltages. The semiconductor device includes: a substrate having a p-type well, an n-type well, and a depletion region; an insulating layer disposed on the p-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the p-type well, the n-type well, and / or the depletion region; and the grid electrode surrounds the channel and is formed between the first epitaxial layer and the second epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor manufacturing techniques. More particularly, the present disclosure relates to semiconductor device structures that can be used to provide a more diverse operating voltage range for implementation of gate all around field effect transistor (GAAFET) devices and other similar devices. Background Art

[0002] For example, the semiconductor device structures described herein may be used in various implementations of laterally diffused metal oxide semiconductors (LDMOS) used in a variety of different high power applications, such as power amplifiers, radio frequency (RF) amplifiers, and power transistors for radio and wireless communication systems. As the demand for high power applications increases, research and development efforts continue to advance semiconductor technology to meet foundry manufacturing capabilities and capacities and enhance the functionality of various electronic devices and circuits. Summary of the invention

[0003] In one aspect, the present disclosure relates to a semiconductor device, comprising: a substrate comprising a p-type well, an n-type well, and a depletion region, the depletion region being disposed between the p-type well and the n-type well; an insulating layer disposed on the p-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the n-type well and on the depletion region; and a gate surrounding a channel and formed between the first epitaxial layer and the second epitaxial layer.

[0004] In another aspect, the present disclosure relates to a semiconductor device, comprising: a substrate comprising a p-type well, an n-type well and a depletion region, wherein the depletion region is disposed between the p-type well and the n-type well; an insulating layer disposed on the n-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the depletion region; and a gate surrounding a channel and formed between the first epitaxial layer and the second epitaxial layer.

[0005] In another aspect, the present disclosure relates to a semiconductor device, comprising: a substrate comprising a p-type well, an n-type well and a depletion region, wherein the depletion region is disposed between the p-type well and the n-type well; a first insulating layer disposed on the p-type well; a first epitaxial layer disposed on the first insulating layer; a second insulating layer disposed on the p-type well; a second epitaxial layer disposed on the second insulating layer; a third epitaxial layer disposed on the depletion region; a first gate surrounding a channel and formed between the first epitaxial layer and the second epitaxial layer; and a second gate surrounding the channel and formed between the second epitaxial layer and the third epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1Shown are cross-sections illustrating example components of a semiconductor device according to some aspects of the present disclosure.

[0007] Figure 2 Demonstrating some aspects of the present disclosure Figure 1 A top view of an example semiconductor device.

[0008] Figure 3 Shown is a cross-section illustrating example components of another semiconductor device according to some aspects of the present disclosure.

[0009] Figure 4 Shown are cross-sections illustrating example components of further semiconductor devices according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0010] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that other aspects may be practiced without some of the details. Different examples are described herein, and although various features are attributed to the examples, it should be understood that features described with respect to one example may also be combined with other examples. However, for the same reason, a single feature or several features of any described example should not be considered essential to each example, because other examples may omit such features.

[0011] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0012] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0013] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include an intervening element that is present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which an intervening element may be present.

[0014] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used only for explanation purposes and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0015] In addition, unless otherwise indicated, all numbers used herein to indicate quantities, dimensions, etc., are to be understood as being modified by the term "approximately" in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "includes" and "have" as well as other forms (e.g., "includes / included", "has / have and had") should be considered non-exclusive. Moreover, unless otherwise specifically stated, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0016] Although some features and aspects have been described with respect to examples, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although for ease of description, the various methods and processes described herein may be described with respect to specific structural and / or functional components, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture but may be implemented with any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, this functionality may be distributed throughout various other system components according to several embodiments.

[0017] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, the various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise indicates. In addition, the procedures described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized into alternative structural architectures and / or incorporated into other described systems. Therefore, although various examples are described as having or not having some features for ease of description and to illustrate aspects of those embodiments, the various components and / or features described herein with respect to a particular example may be replaced, added, and / or subtracted from other described embodiments unless the context otherwise indicates. Therefore, although several examples are described above, it should be understood that the present disclosure is intended to cover all modifications and equivalents within the scope of the appended claims.

[0018] refer to Figure 1 , showing a cross-section of example components of a semiconductor device 100 according to some aspects of the present disclosure. The semiconductor device 100 may be implemented as various types of semiconductor devices, such as various different types and combinations of transistor structures. For example, the semiconductor device 100 may be a non-planar (three-dimensional) GAAFET device, such as a gate-all-around LDMOS device. Figure 1 , the semiconductor device 100 includes a plurality of channels 192, and the gate 162 may be formed around the channel 192. The channel 192 may be implemented using a silicon nanosheet, for example, in some examples, the width of the silicon nanosheet is between 10 nanometers and 50 nanometers and its thickness is 5 nanometers. However, the channel 192 may be implemented using any suitable type and / or structure of nanosheet, wherein the term nanosheet generally refers to a conductive channel structure. The channel 192 may also be implemented using silicon nanowires and other possible implementations of the channel 192. In some examples, the channel 192 may include three vertically stacked channels, however, any suitable number of channels (e.g., one channel, two channels, five channels, seven channels, etc.) may be used. Various types of spacer layers (e.g., silicon nitride and / or silicon dioxide layers) may be disposed on and / or around the channel 192.

[0019] like Figure 1The semiconductor device 100 shown in FIG. 1 also includes a substrate 110, a p-type well 122, an n-type well 124, and a depletion region 126 disposed between the p-type well 122 and the n-type well 124. The substrate 110 may include a silicon material (e.g., crystalline silicon) and / or other suitable materials or material combinations. The depletion region 126 may be defined by the substrate 110. The substrate 110 may be implemented using various manufacturing techniques, such as using a silicon-on-insulator (SOI) structure, a bulk semiconductor structure, an alloy semiconductor, a compound semiconductor, germanium, and / or various other suitable materials and combinations thereof. The substrate 110 generally provides a base for forming components of the semiconductor device 100 thereon. It should be understood that the semiconductor device 100 may be implemented in various different types of circuits, resulting in various types of integrated circuit (IC) chips. The semiconductor device 100 is also shown to include a deep n-type well (DNW) 128 formed within the substrate 110 that may provide noise suppression within the substrate 110. The deep n-well 128 may be formed by doping the substrate 110 with any suitable n-type dopant, such as arsenic, phosphorus, and / or other similar n-type dopants.

[0020] The p-type well 122 is generally a region of the substrate 110 that is doped with a p-type dopant, such as boron and / or other similar p-type dopants. The n-type well 124 is generally a region of the substrate 110 that is doped with an n-type dopant, such as arsenic, phosphorus, and / or other similar n-type dopants. The p-type well 122 and the n-type well 124 may also be formed at least partially separate from the substrate 110, such as at least partially formed within various types of oxide layers and / or other insulating / dielectric layers within the semiconductor device 100. The depletion region 126 is generally an insulating region of the substrate 110 where mobile charge carriers have been diffused and / or forced away by an electric field. The ionized donor and / or acceptor impurities that remain in the depletion region 126 cause a depletion of charge carriers within the depletion region 126, thereby limiting the amount of current that can flow through the depletion region 126. In some examples, the depletion region 126 may be lightly doped with a p-type dopant to help maintain a higher operating voltage.

[0021] like Figure 1The semiconductor device 100 shown in FIG. 1 also includes an isolation structure 132, an isolation structure 134, and an isolation structure 136. The isolation structure 132, the isolation structure 134, and the isolation structure 136 may be, for example, a shallow trench isolation (STI) structure, as well as other possible types of isolation structures (e.g., a dielectric material layer, etc.). The isolation structure 132, the isolation structure 134, and the isolation structure 136 may be formed by etching a trench in the semiconductor device 100. For example, after etching a trench between the epitaxial layer 174 and the epitaxial layer 176, the isolation structure 134 may be formed by depositing a dielectric material at least partially within the trench. The isolation structure 132 and the isolation structure 136 may be formed in a similar manner. The dielectric material used to form the isolation structure 132, the isolation structure 134, and the isolation structure 136 may be, for example, silicon oxide, silicon nitride, and / or other suitable materials and combinations of materials. The isolation structure 132, the isolation structure 134, and the isolation structure 136 may prevent current leakage between different components of the semiconductor device 100.

[0022] like Figure 1 The semiconductor device 100 shown in FIG. 1 also includes various epitaxial layers, including epitaxial layer 172, epitaxial layer 174, and epitaxial layer 176. Figure 1 The semiconductor device 100 shown in includes an insulating layer 182 disposed on the p-type well 122. The insulating layer 182 may include any suitable material, such as silicon nitride, aluminum oxide, silicon dioxide and / or other suitable insulating materials and combinations thereof. The epitaxial layer 172, the epitaxial layer 174 and the epitaxial layer 176 may be formed using various types of epitaxial processes and various suitable epitaxial materials. For example, the epitaxial layer 172, the epitaxial layer 174 and the epitaxial layer 176 may be formed using silicon, gallium arsenide and / or other suitable epitaxial materials and combinations thereof. In the semiconductor device 100, the epitaxial layer 172, the epitaxial layer 174 and the epitaxial layer 176 may be highly doped using a suitable n-type dopant (such as arsenic, phosphorus and / or other similar n-type dopant). Obviously, as Figure 1 , epitaxial layer 172 may be disposed on insulating layer 182, epitaxial layer 174 may be disposed on p-type well 122, n-type well 124, and / or depletion region 126, and epitaxial layer 176 may be disposed on n-type well 124. Epitaxial layer 172 may be ultimately used to form a source terminal of a transistor (e.g., after forming a silicide layer and interconnects on epitaxial layer 172), and epitaxial layer 176 may be ultimately used to form a drain terminal of a transistor (e.g., after forming a silicide layer and interconnects on epitaxial layer 176).

[0023] like Figure 11. The semiconductor device 100 shown in FIG. 1 also includes a layer of polysilicon material formed on an oxide defined region edge (PODE). Specifically, the semiconductor device 100 is shown to include PODE layer 152, PODE layer 154, PODE layer 156, and PODE layer 158. PODE layer 152, PODE layer 154, PODE layer 156, and PODE layer 158 may generally be "dummy" polysilicon segments (e.g., "dummy" refers to dummy segments that are connected to ground or a power supply and are not intended to actively work) formed on the edges of different silicon oxide defined regions (e.g., active regions) of the semiconductor device 100 to prevent the semiconductor device 100 from being degraded due to transistor facets near the oxide defined region edges. As shown, PODE layer 152 may be formed adjacent to epitaxial layer 172 on the opposite side of epitaxial layer 172 relative to gate 162. PODE layer 154 may be formed adjacent to epitaxial layer 174 on the opposite side of epitaxial layer 174 relative to gate 162. The PODE layer 156 and the PODE layer 158 may be formed adjacent to the epitaxial layer 176 on opposite sides of the epitaxial layer 176 , respectively.

[0024] The gate 162 may surround the channel 192 and be formed between the epitaxial layer 172 and the epitaxial layer 174 so that the channel 192 is surrounded by the gate 162 on all sides. The gate 162 may be formed using a polysilicon material (e.g., to provide a high-k gate) and / or another suitable material or material combination (e.g., a metal gate). The voltage applied at the gate 162 may generally control the operation and conductivity of the semiconductor device 100. Various types of spacers may be at least partially formed around the gate 162 to electrically isolate the gate 162 and prevent charge leakage. The spacers may include a material with a high dielectric constant (e.g., silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof). In addition, a gate oxide layer may be formed between the gate 162 and the channel 192 using materials such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof. A silicide layer may be formed on the gate 162 (e.g., using a trench silicide process), and an interconnect may be landed on the gate 162 to form a gate terminal of the transistor. It should be understood that the gate 162 can be formed in various ways to surround the channel 192. For example, the gate 162 can completely surround the channel 192, or the gate 162 can partially surround the channel 192 (e.g., there can be a gap between the channel 192 and the gate 162, the gate 162 can completely surround some channels 192 and partially surround some channels 192, etc.).

[0025] like Figure 1The structure of the semiconductor device 100 shown in FIG. 1 may provide various advantages in providing a higher operating voltage. In some previous device designs including GAAFET devices and other similar types of devices, the operating range may be limited to about 0.75V to 0.9V. This operating voltage limitation may make the use of these devices in power applications challenging. In these designs, relative to Figure 1 , an intermediate epitaxial layer (e.g., an epitaxial layer similar to epitaxial layer 174) is typically formed on an insulating layer similar to insulating layer 182. That is, the intermediate epitaxial layer is typically disposed on an insulating layer, which is disposed on a p-type well (e.g., similar to p-type well 122) of a substrate. In addition, the previous design also does not include a depletion region (e.g., similar to depletion region 126) between the n-type well and the p-type well. Due to this structure, when a higher operating voltage is applied, the current flowing through the device does not face sufficient resistance, and therefore various components of these devices may be damaged and / or the device may become inoperable.

[0026] However, when a higher operating voltage is applied, such as Figure 1 The structure of the semiconductor device 100 shown in FIG. 1 can provide increased resistance to current flowing through the semiconductor device 100, thereby making the semiconductor device 100 more suitable for power applications. For example, when the semiconductor device 100 is used, the operating range can be increased to about 1.8V to 3.0V. By removing the isolation of the epitaxial layer 174 (e.g., by not including an insulating layer similar to the insulating layer 182), the depletion region 126 and the n-type well 124 below the epitaxial layer 174 form a drift region that can limit the flow of current through the semiconductor device 100. However, in some examples, the depletion region 126 can be partially or completely replaced by the n-type well 124, because removing the isolation of the epitaxial layer 174 can still limit the flow of current within the semiconductor device 100. The epitaxial layer 174 can still be used together with the n-type well 124 as a "floating" layer that provides a drift region within the semiconductor device 100 due to the n-type doping of the epitaxial layer 174 and the non-isolated positioning of the epitaxial layer 174 on the n-type well 124. For example, if the epitaxial layer 174 is lightly doped, then the depletion region 126 may not be needed to form a drift region within the semiconductor device 100 , and the epitaxial layer 174 may be formed only on the n-type well 124 .

[0027] exist Figure 1, various widths of different components of semiconductor device 100 are shown. Gate 162 may have a width W1 between 3 nanometers and 100 nanometers. Epitaxial layer 174 may have a width W2 between 40 nanometers and 100 nanometers. Depletion region 126 may have a width W3 between 5 nanometers and 300 nanometers, or may be 0 nanometer in embodiments where depletion region 126 is not included in semiconductor device 100. Shallow trench isolation 134 may have a width W4 between 40 nanometers and 300 nanometers. Figure 1 , shallow trench isolation 134 may be formed between PODE layer 154 and PODE layer 156, and thus between epitaxial layer 174 and epitaxial layer 176, and within n-type well 124. The specific dimensions of these components may provide advantages in facilitating proper operation of semiconductor device 100 under higher operating voltage conditions.

[0028] Reference Figure 2 , showing a top view of an example semiconductor device 100 according to some aspects of the present disclosure. Specifically, from Figure 2 In the top view shown in FIG. 1 , the channel 192 can be seen relative to the gate 162 and the PODE layers 152, 154, 156, and 158. In addition, the position of the shallow trench isolation 134 can be seen from Figure 2 As described, to form shallow trench isolation 134, an associated trench may be etched through channel 192 and into n-type well 124. This particular location of shallow trench isolation 134 and the size of shallow trench isolation 134 as previously described may provide advantages in facilitating proper operation of semiconductor device 100 under higher operating voltage conditions due to the electrical characteristics exhibited by semiconductor device 100.

[0029] refer to Figure 3 , shows a cross-section of an example component of another example semiconductor device 200 according to some aspects of the present disclosure. As shown, the structure of the semiconductor device 200 is similar to that of Figure 1 2 , however, the semiconductor device 200 provides a split gate structure including both the gate 262 and the gate 264. Like the semiconductor device 100, the semiconductor device 200 may be implemented as various types of semiconductor devices, such as various different types and combinations of transistor structures. For example, the semiconductor device 200 may be a non-planar (three-dimensional) GAAFET device, such as a gate-all-around LDMOS device.

[0030] like Figure 32 shows that the semiconductor device 200 includes a plurality of channels 292, and both the gate 262 and the gate 264 can be formed around the channel 292. The channel 292 can be implemented using a silicon nanosheet, for example, in some examples, the width of the silicon nanosheet is between 10 nanometers and 50 nanometers and its thickness is 5 nanometers. The channel 292 can also be implemented using silicon nanowires and other possible implementations of the channel 292. In some examples, the channel 292 can include three vertically stacked channels, however, any suitable number of channels (e.g., one channel, two channels, five channels, seven channels, etc.) can be used. Various types of spacer layers (e.g., silicon nitride and / or silicon dioxide layers) can be disposed on and / or around the channel 292. The channel 292 can be implemented using any suitable type and / or configuration of nanosheets, where the term nanosheet generally refers to a conductive channel structure.

[0031] like Figure 3 The semiconductor device 200 shown in FIG. 2 also includes a substrate 210, a p-type well 222, an n-type well 224, and a depletion region 226 disposed between the p-type well 222 and the n-type well 224. The depletion region 226 may be defined by the substrate 210. The substrate 210 may be formed of a silicon material (e.g., crystalline silicon) and / or other suitable materials or material combinations. The substrate 210 may be implemented using various manufacturing techniques, such as using an SOI structure, a bulk semiconductor structure, an alloy semiconductor, a compound semiconductor, germanium, and / or various other suitable materials and combinations thereof. The substrate 210 generally provides a base for forming components of the semiconductor device 200 thereon. It should be appreciated that the semiconductor device 200 may be implemented in various different types of circuits, resulting in various types of IC chips.

[0032] The p-type well 222 is generally a region of the substrate 210 that is doped with a p-type dopant, such as boron and / or other similar p-type dopants. The n-type well 224 is generally a region of the substrate 210 that is doped with an n-type dopant, such as arsenic, phosphorus, and / or other similar n-type dopants. The p-type well 222 and the n-type well 224 may also be formed at least partially separate from the substrate 210, such as at least partially formed within various types of oxide layers and / or other insulating / dielectric layers within the semiconductor device 200. The depletion region 226 is generally an insulating region of the substrate 210 where mobile charge carriers have been diffused and / or forced away by an electric field. The ionized donor and / or acceptor impurities that remain in the depletion region 226 cause the charge carriers within the depletion region 226 to be depleted, thereby limiting the amount of current that can flow through the depletion region 226.

[0033] like Figure 3The semiconductor device 200 shown in FIG. 2 also includes an isolation structure 232, an isolation structure 234, and an isolation structure 236. The isolation structure 232, the isolation structure 234, and the isolation structure 236 may be, for example, a shallow trench isolation (STI) structure, as well as other possible types of isolation structures (e.g., a dielectric material layer, etc.). The isolation structure 232, the isolation structure 234, and the isolation structure 236 may be formed by etching a trench in the semiconductor device 200. For example, after etching a trench between the epitaxial layer 276 and the epitaxial layer 278, the isolation structure 234 may be formed by depositing a dielectric material at least partially within the trench. The isolation structure 232 and the isolation structure 236 may be formed in a similar manner. The dielectric material used to form the isolation structure 232, the isolation structure 234, and the isolation structure 236 may be, for example, silicon oxide, silicon nitride, and / or other suitable materials and combinations of materials. The isolation structure 232, the isolation structure 234, and the isolation structure 236 may be used to prevent current leakage between different components of the semiconductor device 200.

[0034] like Figure 3 The semiconductor device 200 shown in FIG. 2 also includes various epitaxial layers, including epitaxial layer 272, epitaxial layer 274, epitaxial layer 276, and epitaxial layer 278. Figure 3 The semiconductor device 200 shown in FIG. 2 also includes an insulating layer 282 and an insulating layer 284, both disposed on the p-type well 222. The insulating layer 282 and the insulating layer 284 may be formed using any suitable material, such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable insulating materials and combinations thereof. The epitaxial layer 272, the epitaxial layer 274, the epitaxial layer 276, and the epitaxial layer 278 may be formed using various types of epitaxial processes and various suitable epitaxial materials. For example, the epitaxial layer 272, the epitaxial layer 274, the epitaxial layer 276, and the epitaxial layer 278 may be formed using silicon, gallium arsenide, and / or other suitable epitaxial materials and combinations thereof.

[0035] In semiconductor device 200, epitaxial layer 272, epitaxial layer 274, epitaxial layer 276, and epitaxial layer 278 may be heavily doped using a suitable n-type dopant (eg, arsenic, phosphorus, and / or other similar n-type dopants). Figure 32 , epitaxial layer 272 may be disposed on insulating layer 282 and epitaxial layer 274 may be disposed on insulating layer 284. In contrast, epitaxial layer 276 may be disposed on p-type well 222, n-type well 224, and / or depletion region 226, and epitaxial layer 278 may be disposed on n-type well 224. By removing the isolation of epitaxial layer 276, a drift region that limits current flow within semiconductor device 200 may be formed, similar to the drift region of semiconductor device 100. Epitaxial layer 272 may be ultimately used to form a source terminal of a transistor (e.g., after forming a silicide layer and interconnects on epitaxial layer 272), while epitaxial layer 278 may be ultimately used to form a drain terminal of a transistor (e.g., after forming a silicide layer and interconnects on epitaxial layer 278).

[0036] like Figure 3 2 also includes a layer of polysilicon material formed on an oxide defined region edge (PODE). Specifically, semiconductor device 200 is shown to include PODE layer 252, PODE layer 254, PODE layer 256, and PODE layer 258. PODE layer 252, PODE layer 254, PODE layer 256, and PODE layer 258 may generally be "dummy" polysilicon segments formed on the edges of different silicon oxide defined regions (e.g., active regions) of semiconductor device 200 to prevent semiconductor device 200 from degrading due to transistor facets near the oxide defined region edges. As shown, PODE layer 252 may be formed adjacent to epitaxial layer 272 on an opposite side of epitaxial layer 272 relative to gate 262. PODE layer 254 may be formed adjacent to epitaxial layer 276 on an opposite side of epitaxial layer 276 relative to gate 264. The PODE layer 256 and the PODE layer 258 may be formed adjacent to the epitaxial layer 278 on opposite sides of the epitaxial layer 278 , respectively.

[0037] The gate 262 may surround the channel 292 and be formed between the epitaxial layer 272 and the epitaxial layer 274, so that the channel 292 is surrounded by the gate 262 on all sides. The gate 264 may surround the channel 292 and be formed between the epitaxial layer 274 and the epitaxial layer 276, so that the channel 292 is surrounded by the gate 264 on all sides. The gate 262 and the gate 264 may be formed using polysilicon material and / or another suitable material or material combination. The voltage applied at the gate 262 and / or the gate 264 may generally control the operation and conductivity of the semiconductor device 200. Various types of spacers may be at least partially formed around the gate 262 and / or the gate 264 to electrically isolate the gate 262 and / or the gate 264 to prevent charge leakage. The spacer may be formed using a material having a high dielectric constant, such as silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof. In addition, a gate oxide layer may be formed between the gate 262 and / or the gate 264 and the channel 292 using materials such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof (e.g., using thermal oxidation). It should be appreciated that the gate 262 may be formed around the channel 292 in various ways. For example, the gate 262 may completely surround the channel 292, or the gate 262 may partially surround the channel 292 (e.g., there may be a gap between the channel 292 and the gate 262, the gate 262 may completely surround some of the channels 292 and partially surround some of the channels 292, etc.). The gate 264 may also be formed around the channel 292 in various ways.

[0038] The use of gate 262 and gate 264 may provide advantages with respect to the operation of semiconductor device 200 in some applications relative to semiconductor device 100. Semiconductor device 200 may provide similar advantages as semiconductor device 100, including an increase in the operating range to about 1.8V to 3.0V. In addition, it should be understood that the width and other dimensional characteristics described with respect to semiconductor device 100 also apply to semiconductor device 200. For example, the width of shallow trench isolation 234 may be between 40 nanometers and 300 nanometers, and the width of depletion region 226 may be between 5 nanometers and 300 nm (or 0 nanometers in embodiments in which depletion region 226 is not included in semiconductor device 200). Also, the width of epitaxial layer 276 may be between 40 nanometers and 100 nanometers, the width of gate 262 may be between 3 nanometers and 100 nanometers, and the width of gate 264 may also be between 3 nanometers and 100 nanometers.

[0039] refer to Figure 4 , showing a cross-section of an example component of another example semiconductor device 300 according to some aspects of the present disclosure. As shown, the structure of the semiconductor device 300 is also similar to that of Figure 1, however, semiconductor device 300 provides a device implementation with opposite polarity relative to semiconductor device 100. Like semiconductor device 100, semiconductor device 300 can be implemented as various types of semiconductor devices, such as various different types and combinations of transistor structures. For example, as detailed, semiconductor device 300 can be a full-surround gate PLDMOS device.

[0040] like Figure 4 , the semiconductor device 300 includes a plurality of channels 392, and the gate 362 may be formed around the channel 392. The channel 392 may be implemented as a silicon nanosheet, and in some examples, the width of the silicon nanosheet is between 10 nanometers and 50 nanometers and its thickness is 5 nanometers. The channel 392 may also be implemented using silicon nanowires and other possible implementations of the channel 392. In some examples, the channel 392 may include three vertically stacked channels, however, any suitable number of channels (e.g., one channel, two channels, five channels, seven channels, etc.) may be used. Various types of spacer layers (e.g., silicon nitride and / or silicon dioxide layers) may be disposed on and / or around the channel 392. The channel 392 may be implemented using any suitable type and / or configuration of nanosheets, where the term nanosheet generally refers to a conductive channel structure.

[0041] like Figure 4 The semiconductor device 300 shown in FIG. 3 also includes a substrate 310, an n-type well 322, a p-type well 324, and a depletion region 326 disposed between the n-type well 322 and the p-type well 324. The depletion region 326 may be defined by the substrate 310. The substrate 310 may be formed of a silicon material and / or other suitable materials or material combinations. The substrate 310 may be implemented using various manufacturing techniques, such as using an SOI structure, a bulk semiconductor structure, an alloy semiconductor, a compound semiconductor, germanium, and / or various other suitable materials and combinations thereof. The substrate 310 generally provides a base for forming components of the semiconductor device 300 thereon. It should be understood that the semiconductor device 300 may be implemented in various different types of circuits, resulting in various types of IC chips.

[0042] The n-well 322 is generally a region of the substrate 310 that is doped with an n-type dopant, such as arsenic, phosphorus, and / or other similar n-type dopants. The p-well 324 is generally a region of the substrate 310 that is doped with a p-type dopant, such as boron and / or other similar p-type dopants. The n-well 322 and the p-well 324 may also be formed at least partially separate from the substrate 310, such as at least partially formed within various types of oxide layers and / or other insulating / dielectric layers within the semiconductor device 300. The depletion region 326 is generally an insulating region of the substrate 310 where mobile charge carriers have been diffused and / or forced away by an electric field. The ionized donor and / or acceptor impurities that remain in the depletion region 326 cause the charge carriers within the depletion region 326 to be depleted, thereby limiting the amount of current that can flow through the depletion region 326.

[0043] like Figure 4 334 and 336. The isolation structures 332, 334 and 336 may be, for example, shallow trench isolation (STI) structures, as well as other possible types of isolation structures (e.g., dielectric material layers, etc.). The isolation structures 332, 334 and 336 may be formed by etching trenches in the semiconductor device 300. For example, after etching trenches between the epitaxial layer 374 and the epitaxial layer 376, the isolation structure 334 may be formed by depositing a dielectric material at least partially within the trenches. The isolation structures 332 and 336 may be formed in a similar manner. The dielectric material used to form the isolation structures 332, 334 and 336 may be, for example, silicon oxide, silicon nitride and / or other suitable materials and combinations of materials. The isolation structures 332, 334 and 336 may be used to prevent current leakage between different components of the semiconductor device 300.

[0044] like Figure 4 The semiconductor device 300 shown in FIG. 1 also includes various epitaxial layers, including epitaxial layer 372, epitaxial layer 374, and epitaxial layer 376. Figure 4 The semiconductor device 300 shown in FIG. 1 includes an insulating layer 382 disposed on the n-type well 322. The insulating layer 382 may be formed using any suitable material, such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable insulating materials and combinations thereof. The epitaxial layer 372, the epitaxial layer 374, and the epitaxial layer 376 may be formed using various types of epitaxial processes and various suitable epitaxial materials. For example, the epitaxial layer 372, the epitaxial layer 374, and the epitaxial layer 376 may be formed using silicon, gallium arsenide, and / or other suitable epitaxial materials and combinations thereof.

[0045] In semiconductor device 300, epitaxial layer 372, epitaxial layer 374, and epitaxial layer 376 may be heavily doped using a suitable p-type dopant (eg, boron and / or other similar p-type dopants). Figure 4 , epitaxial layer 372 may be disposed on insulating layer 382, ​​and epitaxial layer 374 may be disposed on n-type well 322, p-type well 324, and / or depletion region 326. By removing the isolation of epitaxial layer 374, a drift region that limits the flow of current within semiconductor device 300 may be formed, similar to the drift region of semiconductor device 100. Also, epitaxial layer 376 may be disposed on p-type well 324. Epitaxial layer 372 may be ultimately used to form a source terminal of a transistor (e.g., after forming a silicide layer and interconnects on epitaxial layer 372), and epitaxial layer 376 may be ultimately used to form a drain terminal of a transistor (e.g., after forming a silicide layer and interconnects on epitaxial layer 376).

[0046] like Figure 4 3. The semiconductor device 300 shown in FIG. 3 also includes a layer of polysilicon material formed on an oxide defined region edge (PODE). Specifically, the semiconductor device 300 is shown to include a PODE layer 352, a PODE layer 354, a PODE layer 356, and a PODE layer 358. The PODE layer 352, the PODE layer 354, the PODE layer 356, and the PODE layer 358 may generally be "dummy" polysilicon segments formed on the edges of different silicon oxide defined regions (e.g., active regions) of the semiconductor device 300 to prevent the semiconductor device 300 from being degraded due to transistor facets near the oxide defined region edges. As shown, the PODE layer 352 may be formed adjacent to the epitaxial layer 372 on an opposite side of the epitaxial layer 372 relative to the gate 362. The PODE layer 354 may be formed adjacent to the epitaxial layer 374 on an opposite side of the epitaxial layer 374 relative to the gate 362. PODE layer 356 and PODE layer 358 may be formed adjacent to epitaxial layer 376 on opposite sides of epitaxial layer 376 , respectively.

[0047] The gate 362 may surround the channel 392 and be formed between the epitaxial layer 372 and the epitaxial layer 374 so that the channel 392 is surrounded by the gate 362 on all sides. The gate 362 may be formed using polysilicon material and / or another suitable material or material combination. The voltage applied at the gate 362 may generally control the operation and conductivity of the semiconductor device 300. Various types of spacers may be at least partially formed around the gate 362 to electrically isolate the gate 362 and prevent charge leakage. The spacers may be formed using materials with high dielectric constants (e.g., silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof). In addition, a gate oxide layer may be formed between the gate 362 and the channel 392 using materials such as silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof. A silicide layer may be formed on the gate 362 (e.g., using a trench silicide process), and an interconnect may be landed on the gate 362 to form a gate terminal of the transistor. It should be understood that the gate 362 may be formed around the channel 392 in various ways. For example, gate 362 may completely surround channel 392, or gate 362 may partially surround channel 392 (eg, there may be a gap between channel 392 and gate 362, gate 362 may completely surround some channels 392 and partially surround some channels 392, etc.).

[0048] Semiconductor device 300 may provide similar advantages as semiconductor device 100, including an increase in the operating range to about 1.8V to 3.0V. In addition, it should be understood that the width and other dimensional characteristics described with respect to semiconductor device 100 also apply to semiconductor device 300. For example, the width of shallow trench isolation 334 may be between 40 nanometers and 300 nanometers, and the width of depletion region 326 may be between 5 nanometers and 300 nm (or 0 nanometers in embodiments where depletion region 326 is not included in semiconductor device 300). Also, the width of epitaxial layer 374 may be between 40 nanometers and 100 nanometers, and the width of gate 362 may be between 3 nanometers and 100 nanometers.

Claims

1. A semiconductor device comprising: A substrate comprising a p-type well, an n-type well and a depletion region, wherein the depletion region is disposed between the p-type well and the n-type well; an insulating layer disposed on the p-type well; a first epitaxial layer disposed on the insulating layer; A second epitaxial layer disposed on the n-type well and the depletion region; and A gate surrounds the channel and is formed between the first epitaxial layer and the second epitaxial layer. 2 . The semiconductor device of claim 1 , wherein the second epitaxial layer comprises an n-type dopant. 3 . The semiconductor device of claim 1 , comprising a third epitaxial layer disposed on the n-type well, wherein the second epitaxial layer is disposed between the first epitaxial layer and the third epitaxial layer. The semiconductor device according to claim 3 , wherein the third epitaxial layer includes an n-type dopant.

5. The semiconductor device according to claim 3, wherein: The n-type well includes an isolation structure disposed between the second epitaxial layer and the third epitaxial layer; and The isolation structure disposed between the second epitaxial layer and the third epitaxial layer has a width between 40 nanometers and 300 nanometers. The semiconductor device of claim 1 , wherein a width of the depletion region is between 5 nanometers and 300 nanometers. 7 . The semiconductor device of claim 1 , wherein a width of the second epitaxial layer is between 40 nanometers and 100 nanometers. The semiconductor device according to claim 1 , wherein a width of the gate is between 3 nanometers and 100 nanometers. 9 . The semiconductor device of claim 1 , wherein the gate comprises a polysilicon gate and the channel comprises a silicon nanosheet.

10. A semiconductor device comprising: A substrate comprising a p-type well, an n-type well and a depletion region, wherein the depletion region is disposed between the p-type well and the n-type well; an insulating layer disposed on the n-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the depletion region; and A gate surrounds the channel and is formed between the first epitaxial layer and the second epitaxial layer. The semiconductor device of claim 10 , wherein the second epitaxial layer comprises a p-type dopant. 12 . The semiconductor device of claim 10 , comprising a third epitaxial layer doped with a p-type dopant and disposed on the p-type well, wherein the second epitaxial layer is disposed between the first epitaxial layer and the third epitaxial layer.

13. The semiconductor device according to claim 12, wherein: The p-type well includes an isolation structure disposed between the second epitaxial layer and the third epitaxial layer; and The isolation structure disposed between the second epitaxial layer and the third epitaxial layer has a width between 40 nanometers and 300 nanometers.

14. The semiconductor device according to claim 10, wherein: The width of the depletion region is between 5 nanometers and 300 nanometers; The width of the second epitaxial layer is between 40 nanometers and 100 nanometers; and The gate has a width between 3 nanometers and 100 nanometers. 15 . The semiconductor device of claim 10 , wherein the gate comprises a polysilicon gate and the channel comprises a silicon nanosheet.

16. A semiconductor device comprising: A substrate comprising a p-type well, an n-type well and a depletion region, wherein the depletion region is disposed between the p-type well and the n-type well; a first insulating layer disposed on the p-type well; a first epitaxial layer disposed on the first insulating layer; a second insulating layer disposed on the p-type well; a second epitaxial layer disposed on the second insulating layer; a third epitaxial layer disposed on the depletion region; a first gate surrounding the channel and formed between the first epitaxial layer and the second epitaxial layer; and A second gate surrounds the channel and is formed between the second epitaxial layer and the third epitaxial layer. The semiconductor device of claim 16 , wherein the third epitaxial layer comprises an n-type dopant. 18 . The semiconductor device of claim 16 , comprising a fourth epitaxial layer doped with an n-type dopant and disposed on the n-type well, wherein the third epitaxial layer is disposed between the second epitaxial layer and the fourth epitaxial layer.

19. The semiconductor device according to claim 18, wherein: The n-type well includes an isolation structure disposed between the third epitaxial layer and the fourth epitaxial layer; and The isolation structure disposed between the third epitaxial layer and the fourth epitaxial layer has a width between 40 nanometers and 300 nanometers.

20. The semiconductor device according to claim 16, wherein: The width of the depletion region is between 5 nanometers and 300 nanometers; The width of the third epitaxial layer is between 40 nanometers and 100 nanometers; The width of the first gate is between 3 nanometers and 100 nanometers; and The width of the second gate is between 3 nanometers and 100 nanometers.

Images