A power semiconductor device

Abstract

The application provides a power semiconductor device, in particular to a low-voltage lateral power semiconductor device. By introducing a trench gate structure in the power semiconductor device, the structure can extend the channel width and also play a role of auxiliary depletion drift region to reduce the on-state loss of the device. With the gradual reduction of the size of the power device and the gradual improvement of the performance of the device, the development of small-size devices in the low-voltage field is most obviously limited. Based on this background, the application adopts a design scheme of combination of the trench gate and the planar gate, provides different low-conduction-loss and low-switching-loss power semiconductor structures including voltage level expansion, trench stress technology and shield gate (Shield Gate Trench) structure under the premise of ensuring that the size of the device is not increased, so that the performance of the low-voltage power semiconductor device is further improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of power semiconductor, in particular to low voltage power semiconductor devices. BACKGROUND

[0002] With the integrated circuit technology gradually entering the post-moore era, the size of power semiconductor devices is gradually reduced, and the short channel effect, quantum tunneling effect and parasitic effect begin to restrict the further reduction of device size, so the development of small size device performance is more and more important. Laterally double-diffused metal oxide semiconductor (LDMOS) devices are widely used in power integrated circuit field due to their advantages such as easy integration, high input impedance and low conduction loss. However, under the background of post-moore era, the performance development of low voltage LDMOS devices is also limited due to the size reduction.

[0003] In order to further optimize the static and dynamic characteristics of the device on the basis of the traditional LDMOS device without involving the small size problem such as short channel effect, the present application proposes a LDMOS structure combined with trench gate (TG-LDMOS). Due to the reduction of device size, channel resistance gradually becomes the main part affecting the static loss of the device. Considering the limitation of BCD manufacturing process, without changing the original device size and the process of drift region and channel, TG-LDMOS uses trench structure to fold the original planar channel in the width direction, while retaining the original channel width, it introduces an additional width of channel by using the trench sidewall, which is equivalent to connecting multiple channel resistances in parallel to reduce the channel resistance; on the other hand, the trench gate in the drift region also has the function of field plate, which can assist the depletion of the drift region to optimize the breakdown voltage (BV) and specific on-resistance (Ron, sp) of the device. on，sp In addition, the trench stress technology is also used to grow a stress oxide layer inside the trench gate, which transmits stress to the channel region and drift region on the trench sidewall through thermal expansion, introduces tensile stress in the current direction, and further reduces the channel resistance and drift region resistance.

[0004] However, due to the introduction of additional trench gate electrode, it will cause the increase of total gate charge of the device, which will affect the switching loss of the device, therefore, in order to solve this problem, the present application also designs the structure of field oxide layer, trench gate protection area, shielding gate electrode, etc. to reduce the influence of additional introduced gate charge. In order to avoid the small size effect, without changing the size of the device, the static and dynamic characteristics of the device are optimized, and thus the embodiment of the present application appears. SUMMARY

[0005] To achieve the above-mentioned purposes of the application, the technical solutions of the application are as follows:

[0006] A power semiconductor device comprises a first-conductivity-type substrate 101, a first-conductivity-type buried layer 102 arranged on the first-conductivity-type substrate 101, a first-conductivity-type body region 103 and a second-conductivity-type drift region 104 arranged above the first-conductivity-type buried layer 102; a first-conductivity-type contact region 105 and a second-conductivity-type source region 106 are arranged above the first-conductivity-type body region 103, wherein the first-conductivity-type contact region 105 is located on the left side of the second-conductivity-type source region 106; a second-conductivity-type drain region 107 is arranged above the right side of the second-conductivity-type drift region 104; a planar gate oxide layer 108 is arranged above the first-conductivity-type body region 103 and part of the second-conductivity-type drift region 104; and a planar gate electrode 109 is arranged above the planar gate oxide layer 108.

[0007] The second power semiconductor device provided by the application is configured as follows: an A-A' cross section is a cross section pointing from the first-conductivity-type contact region 105 to the second-conductivity-type drain region 107 and passing through the planar gate electrode 109; a B-B' cross section is a cross section pointing from the first-conductivity-type contact region 105 to the second-conductivity-type drain region 107 and passing through the trench gate electrode 110; and a C-C' longitudinal section is a cross section of an area in which the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0008] Along the B-B' cross section, the first-conductivity-type substrate 101 is arranged, the first-conductivity-type buried layer 102 is arranged on the first-conductivity-type substrate 101, the first-conductivity-type body region 103 and the second-conductivity-type drift region 104 are arranged above the first-conductivity-type buried layer 102; the first-conductivity-type contact region 105, the second-conductivity-type source region 106, a second-conductivity-type source region extension 114 and a trench region are arranged above the first-conductivity-type body region 103; wherein the first-conductivity-type contact region 105 is located on the left side of the second-conductivity-type source region 106, the second-conductivity-type source region extension 114 is located below the second-conductivity-type source region 106, the trench region is located on the right side of the second-conductivity-type source region 106 and the second-conductivity-type source region extension 114, and part of the trench structure is located in the second-conductivity-type drift region 104; and the bottom depth of the trench region is equal to or less than the depth of the second-conductivity-type source region extension 114.

[0009] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate electrode 110 is arranged between the second-conductivity-type source region 106, the second-conductivity-type source region extension 114, the first-conductivity-type body region 103 and the second-conductivity-type drift region 104, respectively, and the trench gate oxide layer 111 is arranged therebetween.

[0010] A second-conductivity-type drift region 104 is arranged above the first-conductivity-type body region 103;

[0011] Along a C-C' longitudinal section, a planar gate oxide layer 108 is arranged above the first-conductivity-type body region 103 and part of the second-conductivity-type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in actual process manufacturing, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0012] As a preferred mode, along a B-B' cross section, a field oxide layer 112 is arranged on the side of the trench gate electrode 110 close to the drain region inside the trench region, and the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level.

[0013] As a preferred mode, along a B-B' cross section, a first-conductivity-type protection region 119 is arranged inside the second-conductivity-type drift region 104, the first-conductivity-type protection region 119 is arranged on the right side of the trench region and in contact with the trench gate oxide layer 111, and the depth of the first-conductivity-type protection region 119 is greater than or equal to the trench depth.

[0014] The third power semiconductor device provided by the application is a device structure containing a trench stress technology, and is provided with: an A-A' cross section that points from the first-conductivity-type contact region 105 to the second-conductivity-type drain region 107 and passes through the planar gate electrode 109; a B-B' cross section that points from the first-conductivity-type contact region 105 to the second-conductivity-type drain region 107 and passes through the trench gate electrode 110; and a C-C' longitudinal section that is a section of the alternately arranged region of the planar gate electrode 109 and the trench gate electrode 110.

[0015] Along a B-B' cross section, a first-conductivity-type substrate 101 is included, a first-conductivity-type buried layer 102 is arranged on the first-conductivity-type substrate 101, a first-conductivity-type body region 103 and a second-conductivity-type drift region 104 are arranged above the first-conductivity-type buried layer 102; a first-conductivity-type contact region 105, a second-conductivity-type source region 106, a second-conductivity-type source region extension 114 and a trench region are arranged inside and above the first-conductivity-type body region 103; the first-conductivity-type contact region 105 is located on the left side of the second-conductivity-type source region 106, the second-conductivity-type source region extension 114 is located below the second-conductivity-type source region 106, the trench region is located on the right side of the second-conductivity-type source region 106 and the second-conductivity-type source region extension 114, and part of the trench structure is located in the second-conductivity-type drift region 104; the bottom depth of the trench region is equal to or less than the depth of the second-conductivity-type source region extension 114.

[0016] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with the trench gate oxide layer 111, the trench gate electrode 110, the stress oxide layer 113 and the field oxide layer 112 from left to right, wherein the stress oxide layer 113 is provided around the trench gate electrode 110; the trench gate electrode 110 is provided with the trench gate oxide layer 111 between the second conductive type source region 106, the second conductive type source region extension 114, the first conductive type body region 103 and the second conductive type drift region 104, respectively;

[0017] The second conductive type drain region 107 is provided at the upper right inside of the second conductive type drift region 104;

[0018] Along the C-C' longitudinal section, the planar gate oxide layer 108 is provided above the first conductive type body region 103 and part of the second conductive type drift region 104, and the planar gate electrode 109 is provided directly above the planar gate oxide layer 108; the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in the actual process, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0019] As a preferred mode, along the B-B' cross section, the trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with the trench gate oxide layer 111, the trench gate electrode 110, the stress oxide layer 113 and the field oxide layer 112 from left to right; wherein the stress oxide layer 113 is surrounded by the trench gate electrode 110 on three sides, and is in contact with the field oxide layer 112 on the side close to the drain; wherein the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the voltage level of the device.

[0020] The fourth power semiconductor device provided by the application is a large current device structure with expanded voltage level, and is provided with: an A-A' cross section pointing from the first conductive type contact region 105 to the drain electrode metal 115 and passing through the planar gate electrode 109; a B-B' cross section pointing from the first conductive type contact region 105 to the drain electrode metal 115 and passing through the trench gate electrode 110; and a C-C' longitudinal section being a cross section of the alternating arrangement region of the planar gate electrode 109 and the trench gate electrode 110;

[0021] Along the B-B' cross section, the first conductive type substrate 101 is included, the first conductive type substrate 101 is provided with the first conductive type buried layer 102, the first conductive type buried layer 102 is provided with the first conductive type body region 103 and the second conductive type drift region 104 above the first conductive type buried layer 102; the first conductive type body region 103 is provided with the first conductive type contact region 105, the second conductive type source region 106, the second conductive type source region extension 114 and the trench region inside and above the first conductive type body region 103; the first conductive type contact region 105 is located on the left side of the second conductive type source region 106; the second conductive type source region extension 114 is located below the second conductive type source region 106; the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension 114;

[0022] The trench region is provided with the trench gate oxide layer 111 and the trench gate electrode 110 from bottom to top, and the trench gate electrode 110 is provided with the trench gate oxide layer 111 between the second conductive type source region 106, the second conductive type source region extension 114, the first conductive type body region 103 and the second conductive type drift region 104 respectively;

[0023] The second conductive type drain region 107 and the drain electrode metal 115 are provided inside and above the right side of the second conductive type drift region 104; wherein the bottom depth of the drain electrode metal 115 is greater than or equal to the bottom of the trench region, and the second conductive type drain region 107 is provided in a ring shape on the left side and below the drain electrode metal 115;

[0024] Along the C-C' longitudinal section, the planar gate oxide layer 108 is provided above the first conductive type body region 103 and part of the second conductive type drift region 104, and the planar gate electrode 109 is provided above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in the actual process, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0025] The fifth power semiconductor device provided by the application is a channel punch-through structure, and the A-A' cross section is a cross section from the second conductive type source region 106 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the B-B' cross section is a cross section from the second conductive type source region 106 to the second conductive type drain region 107 and passing through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the alternating arrangement region of the planar gate electrode 109 and the trench gate electrode 110;

[0026] Along the B-B' cross section, the first conductive type substrate 101 is included, the first conductive type buried layer 102 is arranged on the first conductive type substrate 101, the first conductive type body region 103 and the second conductive type drift region 104 are arranged above the first conductive type buried layer 102; the first conductive type body buried layer 120 is arranged inside the first conductive type body region 103, the first conductive type contact region 105, the second conductive type source region 106, the second conductive type source region extension region 114, the source region electrode metal 116 and the trench region are arranged above the first conductive type body buried layer 120; wherein the source region electrode metal 116 is located in the middle of the second conductive type source region 106 and the depth exceeds the second conductive type source region 106; the first conductive type contact region 105 is located below the source region electrode metal 116 and left of the second conductive type source region extension region 114; the second conductive type source region extension region 114 is located below the second conductive type source region 106 and in contact with the source region electrode metal 116, the trench region is located right of the second conductive type source region 106 and the second conductive type source region extension region 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114; the first conductive type body buried layer 120 is arranged below the trench region and in the first conductive type body region 103;

[0027] The trench region is provided with the trench gate oxide layer 111 and the trench gate electrode 110 from bottom to top, and the trench gate electrode 110 is provided with the trench gate oxide layer 111 between the second conductive type source region 106, the second conductive type source region extension region 114, the first conductive type body region 103 and the second conductive type drift region 104 respectively;

[0028] The second conductive type drain region 107 is arranged inside the second conductive type drift region 104 right above;

[0029] Along the C-C' longitudinal section, the planar gate oxide layer 108 is arranged above the first conductive type body region 103 and part of the second conductive type drift region 104, and the planar gate electrode 109 is arranged above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in actual process manufacturing, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0030] The sixth power semiconductor device provided by the application is a low gate-drain parasitic capacitance design, and the following is set: A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; B-B' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110 and the shielding gate electrode 118; C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0031] Along the B-B' cross section, the first conductive type substrate 101 is included, the first conductive type buried layer 102 is arranged on the first conductive type substrate 101, the first conductive type body region 103 and the second conductive type drift region 104 are arranged above the first conductive type buried layer 102; the first conductive type contact region 105, the second conductive type source region 106, the second conductive type source region extension region 114 and the trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located on the left side of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension region 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0032] The trench region is provided with the trench gate oxide layer 111, the trench gate electrode 110, the dielectric isolation layer 117, the shielding gate electrode 118 and the field oxide layer 112 from left to right; wherein the trench gate oxide layer 111 is arranged between the trench gate electrode 110 and the second conductive type source region 106, the second conductive type source region extension region 114, the first conductive type body region 103 and the second conductive type drift region 104 respectively, the dielectric isolation layer 117 is arranged between the trench gate electrode 110 and the shielding gate electrode 118; the field oxide layer 112 is arranged between the shielding gate electrode 118 and the second conductive type drift region 104, wherein the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level;

[0033] The second conductive type drain region 107 is arranged in the right upper part of the second conductive type drift region 104;

[0034] Along the C-C' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductive type body region 103 and part of the second conductive type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in actual process manufacturing, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0035] The principles and benefits of the present application are as follows: based on the traditional LDMOS structure, as the size of the LDMOS device gradually decreases, the channel resistance gradually increases in the device on-resistance, therefore, in order to optimize the device while avoiding the negative effects such as small size effect caused by too small size, the present application provides a series of power semiconductor devices to optimize the static and dynamic characteristics of LDMOS. Based on advanced power semiconductor process, an alternating arrangement mode of trench gate and planar gate is adopted, an additional width of channel is introduced through the trench sidewall, the source region extension area formed by the oblique implantation of the trench sidewall is used to utilize the channel at the bottom of the trench, and then the channel width is maximized to reduce the channel resistance. At the same time, combined with the trench stress technology, the oxide layer grown inside the trench gate is used to transmit stress to the channel region and the drift region, to improve the carrier mobility and reduce the on-resistance. On the other hand, by deforming the trench gate electrode structure, introducing field oxide layer and shield gate electrode structure design, the influence of the additional gate charge caused by the trench gate electrode is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A power semiconductor device structure is provided for the embodiment 1 of the present application.

[0037] Fig. 2(a) is a three-dimensional perspective view of a power semiconductor device provided by the embodiment 2 of the present application.

[0038] Fig. 2(b) is a layout structure of a power semiconductor device provided by the embodiment 2 of the present application. The A-A' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the B-B' cross section is set as the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110; and the C-C' longitudinal section is set as the cross section of the alternating arrangement region of the planar gate electrode 109 and the trench gate electrode 110.

[0039] Fig. 2(c) is the B-B' cross section corresponding to the power semiconductor device structure provided by the embodiment 2 of the present application.

[0040] Fig. 2(d) is the C-C' longitudinal section corresponding to the power semiconductor device structure provided by the embodiment 2 of the present application.

[0041] Figure 3(a) is a layout structure of a power semiconductor device according to an embodiment of the present application. The A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0042] Figure 3(b) is a B-B' cross section of a power semiconductor device structure according to the embodiment of the present application.

[0043] Figure 4(a) is a layout structure of a power semiconductor device according to an embodiment of the present application. The A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0044] Figure 4(b) is a B-B' cross section of a power semiconductor device structure according to the embodiment of the present application.

[0045] Figure 5(a) is a layout structure of a power semiconductor device according to an embodiment of the present application. The A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0046] Figure 5(b) is a B-B' cross section of a power semiconductor device structure according to the embodiment of the present application.

[0047] Figure 5(c) is a C-C' longitudinal section of a power semiconductor device structure according to the embodiment of the present application.

[0048] Figure 6(a) is a layout structure of a power semiconductor device according to an embodiment 6 of the present application. The A-A' cross section is a cross section from the first conductivity type contact region 105 to the second conductivity type drain region 107 and through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductivity type contact region 105 to the second conductivity type drain region 107 and through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0049] Figure 6(b) is a B-B' cross section of a power semiconductor device structure according to the embodiment 6 of the present application.

[0050] Figure 7(a) is a layout structure of a power semiconductor device according to an embodiment 7 of the present application. The A-A' cross section is a cross section from the first conductivity type contact region 105 to the drain electrode metal 115 and through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductivity type contact region 105 to the drain electrode metal 115 and through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0051] Figure 7(b) is an A-A' cross section of a power semiconductor device structure according to the embodiment 7 of the present application.

[0052] Figure 7(c) is a B-B' cross section of a power semiconductor device structure according to the embodiment 7 of the present application.

[0053] Figure 7(d) is a C-C' longitudinal section of a power semiconductor device structure according to the embodiment 7 of the present application.

[0054] Figure 8(a) is a layout structure of a power semiconductor device according to an embodiment 8 of the present application. The A-A' cross section is a cross section from the second conductivity type source region 106 to the second conductivity type drain region 107 and through the planar gate electrode 109; the B-B' cross section is a cross section from the second conductivity type source region 106 to the second conductivity type drain region 107 and through the trench gate electrode 110; and the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0055] Figure 8(b) is a B-B' cross section of a power semiconductor device structure according to the embodiment 8 of the present application.

[0056] Figure 8(c) is a C-C' longitudinal section of a power semiconductor device structure according to the embodiment 8 of the present application.

[0057] Figure 9(a) is a layout structure of a power semiconductor device according to an embodiment of the present application. The A-A' cross section is a cross section from the first conductivity type contact region 105 to the second conductivity type drain region 107 and through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductivity type contact region 105 to the second conductivity type drain region 107 and through the trench gate electrode 110 and the shield gate electrode 118; the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately.

[0058] Figure 9(b) is a B-B' cross section of a power semiconductor device structure according to an embodiment of the present application.

[0059] Figure 9(c) is a C-C' longitudinal section of a power semiconductor device structure according to an embodiment of the present application.

[0060] In the figure, 101 is a first conductivity type substrate, 102 is a first conductivity type buried layer, 103 is a first conductivity type body region, 104 is a second conductivity type drift region, 105 is a first conductivity type contact region, 106 is a second conductivity type source region, 107 is a second conductivity type drain region, 108 is a planar gate oxide layer, 109 is a planar gate electrode, 110 is a trench gate electrode, 111 is a trench gate oxide layer, 112 is a field oxide layer, 113 is a stress oxide layer, 114 is a second conductivity type source region extension, 115 is a drain electrode metal, 116 is a source electrode metal, 117 is a dielectric isolation layer, 118 is a shield gate electrode, 119 is a first conductivity type guard region, and 120 is a first conductivity type body buried layer. DETAILED DESCRIPTION

[0061] In order to make the description of the present application more clear, the following describes the embodiments of the present application through specific examples, and the advantages and application modes of the present application can be understood by those skilled in the art from the disclosure of the present specification. The details in the present specification can also be modified or changed in different views and applications without departing from the principles of the present application.

[0062] In the following embodiments:

[0063] The planar gate electrode can be polysilicon, or other suitable materials such as metal.

[0064] The trench gate electrode can be polysilicon, or other suitable materials such as metal.

[0065] The shield gate electrode can be polysilicon, or other suitable materials such as metal.

[0066] The potential of the shield gate electrode can be consistent with the source, or can be provided through a bias circuit.

[0067] The gate oxide layer can be silicon dioxide or a high dielectric constant material.

[0068] The dielectric isolation layer between the channel gate electrode and the shield gate electrode can be silicon dioxide or other insulating material.

[0069] The first conductivity type is P-type doping, and the second conductivity type is N-type doping; or the first conductivity type is N-type doping, and the second conductivity type is P-type doping. All described herein are explained with the first conductivity type being P-type doping and the second conductivity type being N-type doping.

[0070] Embodiment 1

[0071] As shown in FIG. 1(a), FIG. 1(b), FIG. 1(c) and FIG. 1(d), the A-A' cross section of this embodiment is consistent with that of Embodiment 1, and this embodiment is a TG-LDMOS device combined with a trench gate. Figure 1 As shown in FIG. 1(a), FIG. 1(b), FIG. 1(c) and FIG. 1(d), the A-A' cross section of this embodiment is consistent with that of Embodiment 1, and this embodiment is a TG-LDMOS device combined with a trench gate.

[0072] This embodiment is a low-voltage small-size device structure, and the biggest difference from the high-voltage structure is that the length of the second conductivity type drift region 104 is less than or equal to its depth; therefore, it is necessary to design the first conductivity type body region 103 and the first conductivity type buried layer 102 with appropriate doping concentration, and according to the charge balance principle, the two regions are used to perform two-dimensional depletion on the second conductivity type drift region 104, so that the second conductivity type drift region 104 can fully withstand voltage and ensure current control capability.

[0073] Embodiment 2

[0074] As shown in FIG. 2(a), FIG. 2(b), FIG. 2(c) and FIG. 2(d), the A-A' cross section of this embodiment is consistent with that of Embodiment 1, and this embodiment is a TG-LDMOS device combined with a trench gate.

[0075] Setting: A-A' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the planar gate electrode 109; B-B' cross section is the cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and through the trench gate electrode 110; C-C' longitudinal section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately;

[0076] As shown in Fig. 2(c), along the B-B' cross section, it comprises the first conductive type substrate 101, the first conductive type buried layer 102 is arranged on the first conductive type substrate 101, the first conductive type body region 103 and the second conductive type drift region 104 are arranged above the first conductive type buried layer 102; the first conductive type contact region 105, the second conductive type source region 106, the second conductive type source region extension region 114 and the trench region are arranged above the first conductive type body region 103; wherein the first conductive type contact region 105 is located on the left side of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension region 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0077] The trench region is provided with the trench gate oxide layer 111 and the trench gate electrode 110 from bottom to top, and the trench gate electrode 110 is respectively provided with the trench gate oxide layer 111 between the second conductive type source region 106, the second conductive type source region extension region 114, the first conductive type body region 103 and the second conductive type drift region 104;

[0078] The second conductive type drain region 107 is arranged in the upper right part of the second conductive type drift region 104;

[0079] As shown in Fig. 2(d), along the C-C' longitudinal section, the planar gate oxide layer 108 is arranged above the first conductive type body region 103 and part of the second conductive type drift region 104, and the planar gate electrode 109 is arranged above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in the actual process, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0080] The structure of embodiment 2 is designed by the trench and the second conductive type source region extension 114 structure, which transfers the planar channel in the area where the trench is originally located to the bottom of the trench, ensures the original channel width, and introduces additional channel width through the trench sidewall, which is equivalent to connecting multiple channel resistances in parallel to reduce the channel resistance. The additional introduced channel width is equal to twice the trench depth, so the size of the channel resistance decreases with the increase of the depth of the trench gate electrode; and in the width direction, the smaller the trench width, the larger the ratio of the trench gate and the planar gate, and the more obvious the reduction of the channel resistance. On the other hand, the trench gate electrode 110 in the second conductive type drift region 104 also serves as an additional field plate, which can assist in the depletion of the second conductive type drift region 104. And the more the number of trench regions introduced, the more obvious the field plate effect, and the better the trade-off optimization effect of the BV and R SP of the device. In the actual manufacturing process, the trench gate electrode 110 and the planar gate electrode 109 are prepared by the same process.

[0081] Embodiment 3

[0082] As shown in FIG. 3(a) and FIG. 3(b), the A-A' cross section and the C-C' longitudinal section of this embodiment are consistent with embodiment 2. Embodiment 3 is an optimization scheme of the structure of embodiment 2, the main difference is that in the trench area, the trench gate electrode 110 is provided with a field oxide layer 112 near the drain side, and the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the voltage level of the device, as shown in FIG. 3(b). Due to the additional introduction of the trench gate electrode, the total gate charge of the device increases, and the gate-drain parasitic capacitance increases, which will increase the switching loss of the device. Therefore, in order to reduce the influence of the gate-drain parasitic capacitance, the field oxide layer 112 is provided in this embodiment, which increases the insulation area between the trench gate electrode 110 and the second conductive type drain 107, reduces the dielectric constant of the medium layer between the gate and the drain, thereby reducing the gate-drain parasitic capacitance and improving the dynamic characteristics of the device.

[0083] Embodiment 4

[0084] As shown in FIG. 4(a) and FIG. 4(b), the A-A' cross section and the C-C' longitudinal section of this embodiment are consistent with those of embodiment 2. Embodiment 4 is another optimization scheme for the structure of embodiment 2, which can also be further optimized on the basis of embodiment 3. The main difference is that a first-conductivity-type protection region 119 is arranged inside the second-conductivity-type drift region 104, as shown in FIG. 4(b). The first-conductivity-type protection region 119 is arranged to the right of the trench region and in contact with the trench gate oxide layer 111, and the depth of the first-conductivity-type protection region 119 is greater than or equal to the trench depth. The design principle is to use the depletion layer formed between the first-conductivity-type protection region 119 and the second-conductivity-type drift region 104 as an isolation layer for the gate, thereby reducing the gate-drain parasitic capacitance and improving the dynamic characteristics of the device. On the other hand, the first-conductivity-type protection region 119 can protect the trench gate oxide layer 111 and assist in depleting the second-conductivity-type drift region 104, thereby ensuring the voltage withstand capability of the device while reducing the on-resistance and optimizing the static characteristics of the device.

[0085] Embodiment 5

[0086] As shown in FIG. 5(a), FIG. 5(b) and FIG. 5(c), the A-A' cross section of this embodiment is consistent with that of embodiment 2, and embodiment 5 is a structure provided by combining the trench stress technology on the basis of the structure of embodiment 2.

[0087] Setting: the A-A' cross section is a cross section pointing from the first-conductivity-type contact region 105 to the second-conductivity-type drain region 107 and passing through the planar gate electrode 109; the B-B' cross section is a cross section pointing from the first-conductivity-type contact region 105 to the second-conductivity-type drain region 107 and passing through the trench gate electrode 110; the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately;

[0088] As shown in FIG. 5(b), along the B-B' cross section, it includes a first-conductivity-type substrate 101, a first-conductivity-type buried layer 102 arranged on the first-conductivity-type substrate 101, a first-conductivity-type body region 103 and a second-conductivity-type drift region 104 arranged above the first-conductivity-type buried layer 102; a first-conductivity-type contact region 105, a second-conductivity-type source region 106, a second-conductivity-type source region extension 114 and a trench region are arranged inside and above the first-conductivity-type body region 103; wherein the first-conductivity-type contact region 105 is located to the left of the second-conductivity-type source region 106, the second-conductivity-type source region extension 114 is located below the second-conductivity-type source region 106, the trench region is located to the right of the second-conductivity-type source region 106 and the second-conductivity-type source region extension 114, and part of the trench structure is located in the second-conductivity-type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second-conductivity-type source region extension 114;

[0089] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with the trench gate oxide layer 111, the trench gate electrode 110, the stress oxide layer 113 and the trench gate electrode 110 from left to right, wherein the stress oxide layer 113 is provided around the trench gate electrode 110; the trench gate electrode 110 is provided with the trench gate oxide layer 111 between the second conductive type source region 106, the second conductive type source region extension 114, the first conductive type body region 103 and the second conductive type drift region 104, respectively;

[0090] The second conductive type drain region 107 is provided inside the second conductive type drift region 104 at the upper right;

[0091] As shown in Fig. 5(c), along the C-C' longitudinal section, the planar gate oxide layer 108 is provided above the first conductive type body region 103 and part of the second conductive type drift region 104, and the planar gate electrode 109 is provided directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in actual process manufacturing, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0092] In the actual process of manufacturing the trench gate electrode 110, the stress oxide layer 113 is grown inside the trench gate electrode 110, the stress is transmitted to the channel region and the drift region around the trench through thermal expansion, tensile stress is introduced in the current direction, thereby improving the mobility of the carriers and reducing the channel resistance and the drift region resistance.

[0093] Embodiment 6

[0094] As shown in Fig. 6(a) and Fig. 6(b), the A-A' cross section and the C-C' longitudinal section of this embodiment are consistent with those of Embodiment 2. Embodiment 6 is an optimization scheme for the structure of Embodiment 5. The difference between Embodiment 6 and Embodiment 5 is that the trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110 and a stress oxide layer 113 from bottom to top, and is provided with the trench gate oxide layer 111, the trench gate electrode 110, the stress oxide layer 113 and the field oxide layer 112 from left to right, wherein the stress oxide layer 113 is surrounded by the trench gate electrode 110 on three sides, contacts the field oxide layer 112 on the side close to the drain, and the thickness of the field oxide layer 112 is greater than that of the trench gate oxide layer 111 and increases with the increase of the voltage level of the device. By removing the trench gate electrode 110 on the side close to the drain in the structure of the trench gate electrode 110 of Embodiment 5 and providing the field oxide layer 112, the gate-drain overlap area is reduced, the dielectric constant of the dielectric layer between the gate and the drain is reduced to reduce the parasitic capacitance, and the effect of optimizing the dynamic characteristics is achieved.

[0095] Embodiment 7

[0096] As shown in FIG. 7(a), Figure 7(b) , 7(c) and 7(d), this embodiment is a voltage level-extended large-current TG-LDMOS structure.

[0097] Setting: A-A' cross section is the cross section from the first-conductivity-type contact region 105 to the drain electrode metal 115 and through the planar gate electrode 109; B-B' cross section is the cross section from the first-conductivity-type contact region 105 to the drain electrode metal 115 and through the trench gate electrode 110; C-C' longitudinal section is the cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately;

[0098] As shown in FIG. 7(c), along the B-B' cross section, it comprises a first-conductivity-type substrate 101, a first-conductivity-type buried layer 102 is arranged on the first-conductivity-type substrate 101, a first-conductivity-type body region 103 and a second-conductivity-type drift region 104 are arranged above the first-conductivity-type buried layer 102; a first-conductivity-type contact region 105, a second-conductivity-type source region 106, a second-conductivity-type source region extension 114 and a trench region are arranged inside and above the first-conductivity-type body region 103; wherein the first-conductivity-type contact region 105 is located left to the second-conductivity-type source region 106, the second-conductivity-type source region extension 114 is located below the second-conductivity-type source region 106, the trench region is located right to the second-conductivity-type source region 106 and the second-conductivity-type source region extension 114, and part of the trench structure is located in the second-conductivity-type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second-conductivity-type source region extension 114;

[0099] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate electrode 110 is respectively provided with a trench gate oxide layer 111 between the second-conductivity-type source region 106, the second-conductivity-type source region extension 114, the first-conductivity-type body region 103 and the second-conductivity-type drift region 104;

[0100] A second-conductivity-type drain region 107 and a drain electrode metal 115 are arranged inside and above right of the second-conductivity-type drift region 104; wherein the bottom depth of the drain electrode metal 115 is greater than or equal to the bottom of the trench region, and the second-conductivity-type drain region 107 is arranged around left and below the drain electrode metal 115;

[0101] As shown in Fig. 7(d), along the C-C' longitudinal section, a planar gate oxide layer 108 is arranged above the first conductive type body region 103 and part of the second conductive type drift region 104, and a planar gate electrode 109 is arranged directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in actual process manufacturing, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0102] This embodiment is a voltage level expansion structure of the structure of Embodiment 2, and the voltage resistance part of the device is divided into a depletion region between the first conductive type body region 103 and the second conductive type drift region 104 in the lateral direction, and a depletion region between the first conductive type buried layer 102 and the second conductive type drift region 104 in the longitudinal direction. By increasing the length of the drift region, the body region and the trench region in the longitudinal direction, the voltage resistance capability of the device is increased, and at the same time the width-length ratio of the channel region is also increased, which can further reduce the channel resistance. At the same time, the drain electrode metal 115 is made into the device body in the form of a groove, and the second conductive type drain region 107 is longitudinally extended, which can shorten the current path of the lower half of the trench region channel current, thereby reducing the on-resistance.

[0103] Embodiment 8

[0104] As shown in Fig. 8(a), Fig. 8(b) and Fig. 8(c), wherein the A-A' cross section and the C-C' longitudinal section are consistent with Embodiment 2.

[0105] Embodiment 8 is a small size structure design to prevent channel punch-through.

[0106] Setting: the A-A' cross section is a cross section from the second conductive type source region 106 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the B-B' cross section is a cross section from the second conductive type source region 106 to the second conductive type drain region 107 and passing through the trench gate electrode 110; the C-C' longitudinal section is a cross section of the alternating arrangement region of the planar gate electrode 109 and the trench gate electrode 110;

[0107] As shown in Fig. 8(b), along the B-B' cross section, a first-conductivity-type substrate 101 is included, the first-conductivity-type substrate 101 is provided with a first-conductivity-type buried layer 102, a first-conductivity-type body region 103 and a second-conductivity-type drift region 104 are provided above the first-conductivity-type buried layer 102; the first-conductivity-type body region 103 is internally provided with a first-conductivity-type body buried layer 120, and the first-conductivity-type body region 103 is provided with a first-conductivity-type contact region 105, a second-conductivity-type source region 106, a second-conductivity-type source region extension region 114, a source region electrode metal 116 and a trench region above the first-conductivity-type contact region 105; wherein the source region electrode metal 116 is located in the middle of the second-conductivity-type source region 106 and has a depth exceeding the second-conductivity-type source region 106; the first-conductivity-type contact region 105 is located below the source region electrode metal 116 and left of the second-conductivity-type source region extension region 114; the second-conductivity-type source region extension region 114 is located below the second-conductivity-type source region 106 and in contact with the source region electrode metal 116, the trench region is located right of the second-conductivity-type source region 106 and the second-conductivity-type source region extension region 114, and part of the trench structure is located in the second-conductivity-type drift region 104; wherein the bottom of the trench region has a depth equal to or less than the depth of the second-conductivity-type source region extension region 114; the first-conductivity-type body buried layer 120 is provided below the trench region and in the first-conductivity-type body region 103;

[0108] The trench region is provided with a trench gate oxide layer 111 and a trench gate electrode 110 from bottom to top, and the trench gate electrode 110 is respectively provided with the trench gate oxide layer 111 between the second-conductivity-type source region 106, the second-conductivity-type source region extension region 114, the first-conductivity-type body region 103 and the second-conductivity-type drift region 104;

[0109] The second-conductivity-type drift region 104 is internally provided with the second-conductivity-type drain region 107 at the upper right;

[0110] As shown in Fig. 8(c), along the C-C' longitudinal cross section, a planar gate oxide layer 108 is provided above the first-conductivity-type body region 103 and part of the second-conductivity-type drift region 104, and a planar gate electrode 109 is provided above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged in an alternating manner in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in actual process manufacturing, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0111] The embodiment designs the source region electrode metal 116 in the device body, and sets the first conductive type contact region 105 below the source region electrode metal 116. The design can reduce the area of the first conductive type contact region 105, thereby reducing the overall size of the device. Considering the doping mode of the first conductive type body region 103 in actual process manufacturing, the channel at the bottom of the trench is prone to punch-through, and additional attention is required for reliability; therefore, setting the first conductive type body buried layer 120 can control the threshold of the bottom channel to prevent punch-through phenomenon.

[0112] Embodiment 9

[0113] As shown in FIG. 9(a), FIG. 9(b) and FIG. 9(c), the A-A' cross section and the C-C' longitudinal section are consistent with Embodiment 2.

[0114] Setting: the A-A' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the planar gate electrode 109; the B-B' cross section is a cross section from the first conductive type contact region 105 to the second conductive type drain region 107 and passing through the trench gate electrode 110 and the shielding gate electrode 118; the C-C' longitudinal section is a cross section of the region where the planar gate electrode 109 and the trench gate electrode 110 are alternately arranged;

[0115] As shown in FIG. 9(b), along the B-B' cross section, it includes the first conductive type substrate 101, the first conductive type buried layer 102 is set on the first conductive type substrate 101, the first conductive type body region 103 and the second conductive type drift region 104 are set above the first conductive type buried layer 102; the first conductive type contact region 105, the second conductive type source region 106, the second conductive type source region extension region 114 and the trench region are set inside and above the first conductive type body region 103; wherein the first conductive type contact region 105 is located on the left side of the second conductive type source region 106, the second conductive type source region extension region 114 is located below the second conductive type source region 106, the trench region is located on the right side of the second conductive type source region 106 and the second conductive type source region extension region 114, and part of the trench structure is located in the second conductive type drift region 104; wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region 114;

[0116] The trench region is provided with a trench gate oxide layer 111, a trench gate electrode 110, a dielectric isolation layer 117, a shielding gate electrode 118, and a field oxide layer 112 from left to right; wherein the trench gate electrode 110 is provided with the trench gate oxide layer 111 between the second-conductivity-type source region 106, the second-conductivity-type source region extension 114, the first-conductivity-type body region 103, and the second-conductivity-type drift region 104; the dielectric isolation layer 117 is provided between the trench gate electrode 110 and the shielding gate electrode 118; the field oxide layer 112 is provided between the shielding gate electrode 118 and the second-conductivity-type drift region 104, wherein the thickness of the field oxide layer 112 is greater than the thickness of the trench gate oxide layer 111 and increases with the increase of the device voltage level.

[0117] The second-conductivity-type drain region 107 is provided in the upper right part of the second-conductivity-type drift region 104.

[0118] As shown in Fig. 9(c), along the C-C' longitudinal section, the planar gate oxide layer 108 is provided above the first-conductivity-type body region 103 and part of the second-conductivity-type drift region 104, and the planar gate electrode 109 is provided directly above the planar gate oxide layer 108; wherein the planar gate electrode 109 and the trench gate electrode 110 are arranged alternately in the width direction, and the planar gate electrode 109 and the trench gate electrode 110 are connected in the actual process, and the trench gate oxide layer 111 and the planar gate oxide layer 108 are connected.

[0119] This embodiment is a structure design for optimizing the dynamic characteristics of the device, and the shielding gate electrode 118 is introduced to the right side of the trench gate electrode 110 to reduce the overlapping area of the gate and the drain, thereby reducing the gate-drain parasitic capacitance. The potential of the shielding gate electrode 118 can be connected to the source potential or to the external bias circuit. The shielding gate electrode 118 is located in the second-conductivity-type drift region 104 and can function as a field plate to assist in depleting the drift region, thereby optimizing the static characteristics of the device. The field oxide layer 112 can prevent the gate oxide layer from being broken down due to the excessive field strength caused by the proximity of the trench region to the drain.

[0120] In addition to the above-mentioned embodiments, all the structures provided herein can be combined with each other, and the parameters can be adjusted according to the actual process conditions and application requirements to achieve the optimal characteristics of the device.

[0121] The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A power semiconductor device, characterized by: Assume that: the A-A' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the trench gate electrode (110); the CC' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; The invention relates to a first conductive type substrate (101) along a BB' cross section, wherein a first conductive type buried layer (102) is provided on the first conductive type substrate (101), a first conductive type body region (103) and a second conductive type drift region (104) are provided above the first conductive type buried layer (102); a first conductive type contact region (105), a second conductive type source region (106), a second conductive type source region extension region (114) and a second conductive type contact region (105) are provided above the first conductive type body region (103) A trench region; wherein the first conductive type contact region (105) is located to the left of the second conductive type source region (106), the second conductive type source region extension region (114) is located below the second conductive type source region (106), the trench region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and a portion of the trench structure is located in the second conductive type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with a trench gate oxide layer (111) and a trench gate electrode (110) from bottom to top, and the trench gate oxide layer (111) is provided between the trench gate electrode (110) and the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103), and the second conductive type drift region (104). A second conductive type drain region (107) is provided in the upper right portion of the second conductive type drift region (104); Along the CC' longitudinal section, a planar gate oxide layer (108) is provided above the first conductive type body region (103) and above a portion of the second conductive type drift region (104), and a planar gate electrode (109) is provided directly above the planar gate oxide layer (108); the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately along the CC' longitudinal section, and the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

2. The power semiconductor device of claim 1, characterized in that: Along the BB' cross section, inside the trench region, a field oxide layer (112) is provided on the side of the trench gate electrode (110) close to the drain region. The field oxide layer (112) has a thickness greater than that of the trench gate oxide layer (111) and increases with the increase of the device voltage level.

3. The power semiconductor device of claim 1, wherein: Along the B-B' cross section, a first conductive type protection region (119) is arranged inside the second conductive type drift region (104), the first conductive type protection region (119) is arranged right to the trench region and contacts the trench gate oxide layer (111), and the depth of the first conductive type protection region (119) is greater than or equal to the trench depth.

4. A power semiconductor device, characterized by: Setting: the A-A' cross section is a cross section pointing from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the planar gate electrode (109); the B-B' cross section is a cross section pointing from the first conductive type contact region (105) to the second conductive type drain region (107) and passing through the trench gate electrode (110); and the C-C' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately; Along the B-B' cross section, the first conductive type substrate (101) is arranged, the first conductive type buried layer (102) is arranged on the first conductive type substrate (101), the first conductive type body region (103) and the second conductive type drift region (104) are arranged above the first conductive type buried layer (102); the first conductive type contact region (105), the second conductive type source region (106), the second conductive type source region extension region (114) and the trench region are arranged inside and above the first conductive type body region (103); the first conductive type contact region (105) is located left to the second conductive type source region (106), the second conductive type source region extension region (114) is located below the second conductive type source region (106), the trench region is located right to the second conductive type source region (106) and the second conductive type source region extension region (114), and part of the trench structure is located in the second conductive type drift region (104); the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with the trench gate oxide layer (111), the trench gate electrode (110) and the stress oxide layer (113) from bottom to top, and is provided with the trench gate oxide layer (111), the trench gate electrode (110), the stress oxide layer (113) and the trench gate electrode 110 from left to right, wherein the stress oxide layer (113) is at least partially surrounded by the trench gate electrode (110); the trench gate electrode (110) is provided with the trench gate oxide layer (111) between the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103) and the second conductive type drift region (104) respectively; The second conductive type drain region (107) is arranged inside and right above the second conductive type drift region (104); Along the CC' longitudinal section, a planar gate oxide layer (108) is provided above the first conductive type body region (103) and above a portion of the second conductive type drift region (104), and a planar gate electrode (109) is provided directly above the planar gate oxide layer (108); the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately along the CC' longitudinal section, and the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

5. The power semiconductor device of claim 4, wherein: Along the B-B' cross section, the trench region is provided with a trench gate oxide layer (111), a trench gate electrode (110) and a stress oxide layer (113) from bottom to top, and is provided with a trench gate oxide layer (111), a trench gate electrode (110), a stress oxide layer (113) and a field oxide layer (112) from left to right, wherein the left side and the bottom side of the stress oxide layer (113) are surrounded by the trench gate electrode (110), and the side near the drain is in contact with the field oxide layer (112), wherein the thickness of the field oxide layer (112) is greater than the thickness of the trench gate oxide layer (111) and increases with the increase of the device voltage level.

6. A power semiconductor device, characterized by: Assume that: the A-A' cross section is a cross section from the first conductive type contact region (105) to the drain region electrode metal (115) and passing through the planar gate electrode (109); the BB' cross section is a cross section from the first conductive type contact region (105) to the drain region electrode metal (115) and passing through the trench gate electrode (110); the CC' longitudinal cross section is a cross section of the region where the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged; Along the BB' cross section, it comprises a first conductive type substrate (101), a first conductive type buried layer (102) is arranged on the first conductive type substrate (101), and a first conductive type body region (103) and a second conductive type drift region (104) are arranged above the first conductive type buried layer (102); a first conductive type contact region (105), a second conductive type source region (106), a second conductive type source region extension region (114) and a trench region are arranged above the first conductive type body region (103); the first conductive type contact region (105) is located to the left of the second conductive type source region (106); the second conductive type source region extension region (114) is located below the second conductive type source region (106); the trench region is located to the right of the second conductive type source region (106) and the second conductive type source region extension region (114), and part of the trench structure is located in the second conductive type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second conductive type source region extension region (114); The trench region is provided with a trench gate oxide layer (111) and a trench gate electrode (110) from bottom to top, and the trench gate oxide layer (111) is provided between the trench gate electrode (110) and the second conductive type source region (106), the second conductive type source region extension region (114), the first conductive type body region (103), and the second conductive type drift region (104). The second-conductivity-type drift region (104) is internally provided with a second-conductivity-type drain region (107) and a drain region electrode metal (115) at the upper right; wherein the bottom depth of the drain region electrode metal (115) is greater than or equal to the bottom of the trench region, and the second-conductivity-type drain region (107) is annularly arranged at the left and below of the drain region electrode metal (115); Along the C-C' longitudinal section, a planar gate oxide layer (108) is arranged above the first-conductivity-type body region (103) and part of the second-conductivity-type drift region (104), and a planar gate electrode (109) is arranged directly above the planar gate oxide layer (108); wherein the planar gate electrode (109) and the trench gate electrode (110) are alternately arranged along the C-C' longitudinal section, and the planar gate electrode (109) and the trench gate electrode (110) are connected, the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

7. A power semiconductor device, characterized by: It is set that: the A-A' cross section is a section from the second-conductivity-type source region (106) to the second-conductivity-type drain region (107) and passing through the planar gate electrode (109); the B-B' cross section is a section from the second-conductivity-type source region (106) to the second-conductivity-type drain region (107) and passing through the trench gate electrode (110); and the C-C' longitudinal section is a section of the alternately arranged region of the planar gate electrode (109) and the trench gate electrode (110); Along the B-B' cross section, the first-conductivity-type substrate (101) is included, the first-conductivity-type buried layer (102) is arranged on the first-conductivity-type substrate (101), the first-conductivity-type body region (103) and the second-conductivity-type drift region (104) are arranged above the first-conductivity-type buried layer (102); the first-conductivity-type body buried layer (120) is arranged inside the first-conductivity-type body region (103), and the first-conductivity-type contact region (105), the second-conductivity-type source region (106), the second-conductivity-type source region extension region (114), the source region electrode metal (116) and the trench region are arranged above the first-conductivity-type body buried layer (120); wherein the source region electrode metal (116) is located at the center of the second-conductivity-type source region (106) and has a depth exceeding the second-conductivity-type source region (106); the first-conductivity-type contact region (105) is located below the source region electrode metal (116) and at the left of the second-conductivity-type source region extension region (114); the second-conductivity-type source region extension region (114) is located below the second-conductivity-type source region (106) and in contact with the source region electrode metal (116), the trench region is located at the right of the second-conductivity-type source region (106) and the second-conductivity-type source region extension region (114), and part of the trench structure is located in the second-conductivity-type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second-conductivity-type source region extension region (114); the first-conductivity-type body buried layer (120) is arranged below the trench region and in the first-conductivity-type body region (103). The trench region is provided with a trench gate oxide layer (111) and a trench gate electrode (110) from bottom to top, and the trench gate electrode (110) is provided with the trench gate oxide layer (111) between the second-conductivity-type source region (106), the second-conductivity-type source region extension (114), the first-conductivity-type body region (103) and the second-conductivity-type drift region (104) respectively; A second-conductivity-type drain region (107) is provided at the right upper part of the second-conductivity-type drift region (104); Along the C-C' longitudinal section, a planar gate oxide layer (108) is provided above the first-conductivity-type body region (103) and part of the second-conductivity-type drift region (104), and a planar gate electrode (109) is provided directly above the planar gate oxide layer (108); wherein the planar gate electrode (109) and the trench gate electrode (110) are arranged alternately along the C-C' longitudinal section, and the planar gate electrode (109) and the trench gate electrode (110) are connected, and the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

8. A power semiconductor device, characterized by: It is set that: the A-A' cross section is a section from the first-conductivity-type contact region (105) to the second-conductivity-type drain region (107) and passing through the planar gate electrode (109); the B-B' cross section is a section from the first-conductivity-type contact region (105) to the second-conductivity-type drain region (107) and passing through the trench gate electrode (110) and the shielding gate electrode (118); and the C-C' longitudinal section is a section of the alternately arranged region of the planar gate electrode (109) and the trench gate electrode (110); Along the B-B' cross section, the first-conductivity-type substrate (101) is included, the first-conductivity-type buried layer (102) is provided on the first-conductivity-type substrate (101), the first-conductivity-type body region (103) and the second-conductivity-type drift region (104) are provided above the first-conductivity-type buried layer (102); the first-conductivity-type contact region (105), the second-conductivity-type source region (106), the second-conductivity-type source region extension (114) and the trench region are provided inside and above the first-conductivity-type body region (103); wherein the first-conductivity-type contact region (105) is located at the left of the second-conductivity-type source region (106), the second-conductivity-type source region extension (114) is located below the second-conductivity-type source region (106), the trench region is located at the right of the second-conductivity-type source region (106) and the second-conductivity-type source region extension (114), and part of the trench structure is located in the second-conductivity-type drift region (104); wherein the bottom depth of the trench region is equal to or less than the depth of the second-conductivity-type source region extension (114). The trench region is provided with a trench gate oxide layer (111), a trench gate electrode (110), a dielectric isolation layer (117), a shielding gate electrode (118), and a field oxide layer (112) from left to right; wherein the trench gate electrode (110) is provided with the trench gate oxide layer (111) between the second conductive type source region (106), the second conductive type source region extension (114), the first conductive type body region (103), and the second conductive type drift region (104), respectively, the dielectric isolation layer (117) is provided between the trench gate electrode (110) and the shielding gate electrode (118), the field oxide layer (112) is provided between the shielding gate electrode (118) and the second conductive type drift region (104), wherein the thickness of the field oxide layer (112) is greater than the thickness of the trench gate oxide layer (111) and increases with the increase of the device voltage level; A second conductive type drain region (107) is provided at the upper right inside of the second conductive type drift region (104); Along the C-C' longitudinal section, a planar gate oxide layer (108) is provided above the first conductive type body region (103) and part of the second conductive type drift region (104), and a planar gate electrode (109) is provided directly above the planar gate oxide layer (108); wherein the planar gate electrode (109) and the trench gate electrode (110) are arranged in an alternating manner along the C-C' longitudinal section, and the planar gate electrode (109) and the trench gate electrode (110) are connected, the trench gate oxide layer (111) and the planar gate oxide layer (108) are connected.

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