Semiconductor device, preparation method and chip

Abstract

The invention provides a semiconductor device, a preparation method and a chip, and relates to the technical field of semiconductors. The semiconductor device comprises a substrate structure; a gate oxide dielectric stack; the gate-oxide dielectric laminated layer is formed on the first side of the substrate structure and comprises at least two gate-oxide dielectric layers, and at least one gate-oxide dielectric layer is a gate-oxide dielectric layer made of a high-K material so as to increase the dielectric constant of the gate-oxide dielectric laminated layer; a gate electrode; the grid electrode is arranged on the side, away from the substrate structure, of the gate-oxide dielectric lamination layer. According to the technical scheme, the dielectric constant of the gate oxide dielectric layer is improved, so that the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and a chip. Background Art

[0002] SiC is a compound semiconductor. Compared with Si materials, it has the advantages of high thermal conductivity, high breakdown field strength, and high electron saturation velocity. It is suitable as a manufacturing material for high-power, high-voltage, high-operating temperature, and high-operating frequency power semiconductor devices. Silicon carbide metal-oxide-semiconductor field-effect transistor (SiC Metal-Oxide-Semicon-ductor Field-Effect Transistor, SiC MOSFET) has the advantages of low on-resistance, fast switching speed, and high breakdown voltage. It has been widely used in high-voltage and high-current places such as power grids, new energy vehicles, and aerospace.

[0003] At present, most SiC MOSFET devices use in-situ oxidation of the SiC surface to form a thinner SiO2 as the dielectric layer of its gate. However, the SiO2 gate oxide dielectric layer is subject to a high withstand voltage during the short circuit of the device. When the electric field strength on the gate oxide dielectric layer reaches a certain level, electrons will continue to flow from the semiconductor to the gate oxide dielectric layer, generating electron tunneling current, which will eventually lead to the degradation of the electrical characteristics of the device, or even device failure. Summary of the invention

[0004] The present application provides a semiconductor device, a preparation method and a chip, which are used to provide a technical solution for improving device performance by increasing the dielectric constant of a gate oxide dielectric layer.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] Substrate structure;

[0007] A gate oxide dielectric stack; the gate oxide dielectric stack is formed on the first side of the substrate structure, and includes at least two gate oxide dielectric layers, wherein at least one gate oxide dielectric layer is a gate oxide dielectric layer using a high-K material to increase the dielectric constant of the gate oxide dielectric stack;

[0008] The gate is arranged on a side of the gate oxide dielectric stack away from the substrate structure.

[0009] In an optional implementation, the dielectric constant of the gate oxide dielectric layer made of high-K material is greater than or equal to 14.

[0010] In an optional embodiment, the gate oxide dielectric layer using a high-K material includes one of an ytterbium oxide layer, a hafnium oxide layer, and a zirconium oxide layer.

[0011] In an optional implementation, the gate oxide dielectric stack includes a first gate oxide dielectric layer, and the first gate oxide dielectric layer is a dielectric layer made of a high-K material.

[0012] In an optional implementation, the gate oxide dielectric stack further includes a second gate oxide dielectric layer, and the second gate oxide dielectric layer is disposed between the substrate structure and the first gate oxide dielectric layer.

[0013] In an optional embodiment, the thickness of the first gate oxide dielectric layer is greater than the thickness of the second gate oxide dielectric layer.

[0014] In an optional implementation, the thickness of the first gate oxide dielectric layer ranges from 250 Å to 550 Å.

[0015] In an optional implementation, the thickness of the second gate oxide dielectric layer ranges from 50 Å to 150 Å.

[0016] In an optional implementation, the semiconductor device is a silicon carbide metal oxide semiconductor field effect transistor.

[0017] In a possible implementation, the second gate oxide dielectric layer is a SiO2 layer.

[0018] In a possible implementation, the substrate structure includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate.

[0019] In an optional implementation, the second gate oxide dielectric layer is obtained by in-situ oxidation of the SiC epitaxial layer.

[0020] In an optional embodiment, the semiconductor device further includes a source;

[0021] The source electrode is disposed on the first side of the substrate structure and covers the outer side of the gate electrode.

[0022] In an optional implementation, the semiconductor device further includes a drain.

[0023] The drain is disposed on the second side of the substrate structure.

[0024] In a second aspect, the present application also provides a method for preparing a semiconductor device, the method comprising: forming a substrate structure;

[0025] Forming a gate oxide dielectric stack; the gate oxide dielectric stack is formed on the first side of the substrate structure, and includes at least two gate oxide dielectric layers, wherein at least one gate oxide dielectric layer is a gate oxide dielectric layer using a high-K material to increase the dielectric constant of the gate oxide dielectric stack;

[0026] A gate is formed; the gate is arranged on a side of the gate oxide dielectric stack away from the substrate structure.

[0027] In an optional embodiment, forming a gate oxide dielectric stack includes:

[0028] A first gate oxide dielectric layer is formed on the substrate structure; the first gate oxide dielectric layer is a dielectric layer made of high-K material.

[0029] In an optional embodiment, before forming the first gate oxide dielectric layer on the substrate structure, forming the gate oxide dielectric stack further includes:

[0030] A second gate oxide dielectric layer is formed on the substrate structure; the second gate oxide dielectric layer is arranged between the substrate structure and the first gate oxide dielectric layer.

[0031] In an optional embodiment, the semiconductor device is a silicon carbide metal oxide semiconductor field effect transistor; the substrate structure includes a SiC substrate, and a SiC epitaxial layer formed on the SiC substrate;

[0032] Forming a second gate oxide dielectric layer on the substrate structure includes:

[0033] The epitaxial layer is in-situ oxidized to form a second gate oxide dielectric layer.

[0034] In an optional embodiment, the atmosphere of the in-situ oxidation is an O2 atmosphere, and / or the oxidation temperature range of the in-situ oxidation is 1150°C to 1300°C, and / or the oxidation time range of the in-situ oxidation is 20min to 120min.

[0035] In an optional embodiment, after in-situ oxidation of the SiC epitaxial layer, the method further comprises:

[0036] A first annealing process is performed on the second gate oxide dielectric layer.

[0037] In an optional embodiment, the first annealing treatment is performed in a NO atmosphere, and / or the temperature range of the first annealing treatment is 500-700° C., and / or the time range of the first annealing treatment is 30s-300s.

[0038] In an optional implementation, forming a first gate oxide dielectric layer on the substrate structure includes:

[0039] A first gate oxide dielectric layer is formed on the second gate oxide dielectric layer.

[0040] In an optional embodiment, forming a first gate oxide dielectric layer on the second gate oxide dielectric layer includes:

[0041] An atomic layer deposition process is used to form a first gate oxide dielectric layer on the second gate oxide dielectric layer.

[0042] In an optional embodiment, the first gate oxide dielectric layer is an ytterbium oxide layer, the metal precursor of the atomic layer deposition process is an ytterbium precursor Yb(Cp)3 material; and / or, the oxygen gas source of the atomic layer deposition process is H2O or O3; and / or, the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

[0043] In an optional embodiment, the first gate oxide dielectric layer is a hafnium oxide layer, the metal precursor of the atomic layer deposition process is a clam precursor TEMAH material; and / or, the oxygen gas source of the atomic layer deposition process is H2O or O3; and / or, the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

[0044] In an optional embodiment, the first gate oxide dielectric layer is a zirconium oxide layer, and the metal precursor of the atomic layer deposition process is a zirconium precursor TDMAZ material; and / or, the oxygen gas source of the atomic layer deposition process is H2O or O3, and / or, the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

[0045] In an optional embodiment, after forming the first gate oxide dielectric layer on the second gate oxide dielectric layer, the method further comprises:

[0046] A second annealing process is performed on the first gate oxide dielectric layer.

[0047] In an optional embodiment, the second annealing treatment is performed in a N2 atmosphere, and / or the temperature range of the second annealing treatment is 500°C to 700°C, and / or the range of the second annealing treatment is 30s to 300s.

[0048] In a third aspect, an embodiment of the present application further provides a chip, comprising the semiconductor device of any one of the first aspects.

[0049] In the technical solution provided in the present application, the gate oxide dielectric stack in the semiconductor device includes at least one gate oxide dielectric layer made of high-K material. It should be understood that the gate oxide dielectric layer made of high-K material can increase the dielectric constant of the gate oxide dielectric layer. Based on this, the gate tunneling leakage current can be reduced and the gate capacitance can be increased, thereby reducing the device power consumption and enhancing the device performance.

[0050] Furthermore, the gate oxide dielectric layer in the present application is a stacked structure, and at least one layer of the gate oxide dielectric layer is a gate oxide dielectric layer made of high-K material. Therefore, compared with the single-layer structure in the related art, while maintaining the physical thickness of the gate oxide dielectric layer, it can effectively prevent the electron tunneling current caused by the gate oxide layer being too thin, improve the voltage resistance of the gate oxide dielectric layer and the short-circuit reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0052] Figure 1 A structural diagram of a semiconductor device provided in an embodiment of the present application;

[0053] Figure 2 A schematic structural diagram of a substrate structure provided in an embodiment of the present application;

[0054] Figure 3 A schematic diagram of a substrate structure after doping treatment provided in an embodiment of the present application

[0055] Figure 4 A schematic diagram of a structure after a second gate oxide dielectric layer is formed on a substrate structure provided in an embodiment of the present application;

[0056] Figure 5 A schematic diagram of a structure after a first gate oxide dielectric layer is formed on a second gate oxide dielectric layer provided in an embodiment of the present application;

[0057] Figure 6 A schematic diagram of a structure after a gate is formed in a first gate oxide dielectric layer provided in an embodiment of the present application.

[0058] 10: substrate structure; 101: SiC substrate; 102: SiC epitaxial layer; 103, second conductivity type well region; 104, second conductivity type heavily doped region; 105, first conductivity type heavily doped region;

[0059] 20: gate oxide dielectric stack; 201: first gate oxide dielectric layer; 202: second gate oxide dielectric layer;

[0060] 30: gate;

[0061] 40: source;

[0062] 50: Drain.

[0063] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0064] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present application belongs. The terms used herein in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. It is understood that the terms "first", "second", etc. used in the present application can be used to describe various information or data in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first information from another information. For example, without departing from the scope of the present application, the first action information can be referred to as the second action information, and similarly, the second action information can be referred to as the first action information. Both the first action information and the second action information are action information, but they are not the same action information.

[0066] SiC is a compound semiconductor. Compared with Si materials, it has the advantages of high thermal conductivity, high breakdown field strength, and high electron saturation velocity. It is suitable as a manufacturing material for high-power, high-voltage, high-operating temperature, and high-operating frequency power semiconductor devices. Silicon carbide metal-oxide-semiconductor field-effect transistor (SiC Metal-Oxide-Semicon-ductor Field-Effect Transistor, SiC MOSFET) has the advantages of low on-resistance, fast switching speed, and high breakdown voltage. It has been widely used in high-voltage and high-current places such as power grids, new energy vehicles, and aerospace.

[0067] At present, most SiC MOSFET devices use in-situ oxidation of the SiC surface to form a thinner SiO2 as the dielectric layer of its gate. However, the SiO2 gate oxide dielectric layer is subject to a high withstand voltage during the short circuit of the device. When the electric field strength on the gate oxide dielectric layer reaches a certain level, electrons will continue to flow from the semiconductor to the gate oxide dielectric layer, generating electron tunneling current, which will eventually lead to the degradation of the electrical characteristics of the device, or even device failure.

[0068] Based on this, the technical concept of the present application is: using a combination of relatively higher K dielectric materials and SiO2 to replace the single SiO2 material, which can effectively prevent the electron tunneling current caused by the gate oxide layer being too thin while maintaining the physical thickness of the gate oxide layer, improve the voltage resistance of the gate oxide layer and the short-circuit reliability of the SiC MOSFET device.

[0069] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0070] In a first aspect, an embodiment of the present application provides a semiconductor device, which may be a SiC MOSFET or other semiconductor device having a gate oxide dielectric layer and a gate, and the embodiment of the present application does not make any specific limitation on this.

[0071] The semiconductor device can be applied to chips with high voltage and high current requirements in power grids, new energy vehicles, aerospace, etc., and can also be applied to chips in other fields. The embodiments of the present application do not make any special limitations on this.

[0072] Please refer to Figure 1 , the semiconductor device may include:

[0073] Substrate structure 10: The substrate structure 10 can provide a stable support structure for the semiconductor device, which is used to carry subsequent process steps such as thin film deposition, photolithography, and etching, thereby ensuring the stability and integrity of the entire device. In some examples, the substrate structure 10 can be a doped semiconductor structure doped with ions. The ions doped with the substrate structure 10 can include one conductivity type or two conductivity types. It should be understood that when the doped ions are of two conductivity types, the two conductivity types of doped ions are partitioned and arranged in different areas of the substrate structure 10.

[0074] The material of the above-mentioned substrate structure can be silicon material, but is not limited to silicon, and can also be any other material suitable for power devices, such as silicon carbide, gallium nitride, diamond, etc. The embodiment of the present application does not make specific limitations on this.

[0075] The gate oxide dielectric stack 20 is formed on the first side of the substrate structure and includes at least two gate oxide dielectric layers, wherein at least one gate oxide dielectric layer is a gate oxide dielectric layer made of a high-K material to increase the dielectric constant of the gate oxide dielectric stack 20 .

[0076] Among them, the gate oxide dielectric layer refers to the insulating layer located between the gate and the semiconductor substrate structure, which is used to prevent the gate current from flowing directly into the substrate structure, while allowing the gate voltage to effectively control the conduction and shutdown of the channel, thereby controlling the current between the source and the drain. Therefore, the thickness and material properties of the gate oxide dielectric layer directly affect the performance of the semiconductor device, including threshold voltage, leakage current, switching speed and power consumption.

[0077] In the embodiment of the present application, the gate oxide dielectric stack 20 includes at least two gate oxide dielectric layers, and one of the gate oxide dielectric layers is a gate oxide dielectric layer made of a high-K material. It should be understood that the gate oxide dielectric layer made of a high-K material can increase the dielectric constant of the gate oxide dielectric layer, based on which the gate tunneling leakage current can be reduced and the gate capacitance can be increased, thereby reducing the device power consumption and enhancing the device performance.

[0078] Furthermore, the gate oxide dielectric layer in the present application is a stacked structure, and at least one layer of the gate oxide dielectric layer is a gate oxide dielectric layer made of high-K material. Therefore, compared with the single-layer structure in the prior art, while maintaining the physical thickness of the gate oxide dielectric layer, it is possible to effectively prevent the electron tunneling current caused by the gate oxide layer being too thin, improve the voltage resistance of the gate oxide dielectric layer, and the short-circuit reliability of the semiconductor device.

[0079] In some examples, the dielectric constant of the gate oxide dielectric layer made of high-K material is greater than or equal to 14 to ensure the voltage resistance of the gate oxide dielectric layer and the performance of the device.

[0080] and a gate 30 , which is disposed on a side of the gate oxide dielectric stack away from the substrate structure.

[0081] In semiconductor devices, the gate is used to control the flow of current between the source and drain. For example, in a metal oxide semiconductor field effect transistor, the gate adjusts the conductivity of the semiconductor channel by applying a voltage.

[0082] Optionally, the gate oxide dielectric stack may include a gate oxide dielectric layer made of high-K material, or may include two or three gate oxide dielectric layers made of high-K material. The embodiment of the present application does not make any special limitation on this and may be set according to actual needs.

[0083] For example, the gate oxide dielectric stack includes a gate oxide dielectric layer made of a high-K material, and the gate oxide dielectric layer made of a high-K material is an ytterbium oxide layer.

[0084] For another example, the gate oxide dielectric stack includes two gate oxide dielectric layers made of high-K material, and the two gate oxide dielectric layers made of high-K material are an ytterbium oxide layer and a hafnium oxide layer stacked from bottom to top.

[0085] As a specific example, see Figure 1 The gate oxide dielectric stack 20 includes a first gate oxide dielectric layer 201 , which is a dielectric layer made of a high-K material.

[0086] Compared with the gate oxide dielectric layer of SiO2 in the related art, the first gate oxide dielectric layer can increase the dielectric constant of the gate oxide dielectric stack 20, thereby reducing the gate tunneling leakage current and increasing the gate capacitance, thereby reducing the device power consumption and enhancing the device performance.

[0087] In a possible implementation manner, the gate oxide dielectric stack further includes a second gate oxide dielectric layer, and the second gate oxide dielectric layer is disposed between the substrate structure and the first gate oxide dielectric layer.

[0088] The second gate oxide dielectric layer may be made of a high-K material or a non-high-K material, and this embodiment of the present application does not impose any special limitation on this.

[0089] As an example, when the second gate oxide dielectric layer is a gate oxide dielectric layer made of high-K material, the thickness of the entire gate oxide dielectric stack can be further increased. Compared with the single-layer structure in the related art, while maintaining the physical thickness of the gate oxide dielectric layer, it can effectively prevent the electron tunneling current caused by the gate oxide layer being too thin, improve the voltage resistance of the gate oxide dielectric layer and the short-circuit reliability of the semiconductor device.

[0090] As another example, the second gate oxide dielectric layer may be made of non-high-K material. For example, in a SiC MOSFET device, the second gate oxide dielectric layer may be a SiO2 layer.

[0091] In a SiC MOSFET device, the substrate structure may include a SiC substrate and a SiC epitaxial layer formed on the SiC substrate. The SiC substrate is a highly doped region, and N-type or P-type impurities may be selectively doped, with a doping concentration of 1E 17 ~1E 21 cm -3 ; The SiC epitaxial layer is a low-doped drift region, which can be doped with N-type or P-type impurities, with a doping concentration of 1E 13 ~1E 16 cm -3 , the epitaxial layer thickness range is 10±5um.

[0092] The second gate oxide dielectric layer is obtained by in-situ oxidation of the SiC epitaxial layer.

[0093] Reference Figure 1 The gate oxide dielectric stack 20 comprises a first gate oxide dielectric layer 201 and a second gate oxide dielectric layer 202. The first gate oxide dielectric layer 201 is made of high-K material, and the second gate oxide dielectric layer is a SiO2 layer, which is obtained by in-situ oxidation of a SiC epitaxial layer.

[0094] Based on this, when forming the gate oxide dielectric stack, the second gate oxide dielectric layer is first obtained by an in-situ oxidation process. It should be understood that since the second gate oxide dielectric layer is obtained by in-situ oxidation of the SiC epitaxial layer, the interface defect density can be reduced. Then, the first gate oxide dielectric layer is formed on the second gate oxide dielectric layer. Compared with the related art in which SiO2 formed by in-situ oxidation of SiC is directly used as the gate oxide dielectric layer, the gate oxide dielectric stack not only reduces the device's dependence on the quality of SiO2, but also increases the gate oxide dielectric constant and improves the device performance.

[0095] Furthermore, the gate oxide dielectric stack can effectively prevent electron tunneling current caused by too thin a gate oxide layer while maintaining the physical thickness of the gate oxide dielectric layer, thereby improving the voltage resistance of the gate oxide layer and the short-circuit reliability of the SiC MOSFET device.

[0096] In some examples, the thickness of the first gate oxide dielectric layer is greater than the thickness of the second gate oxide dielectric layer.

[0097] In an embodiment of the present application, a thinner second gate oxide dielectric layer can be first formed by in-situ oxidation, and then a thicker first gate oxide dielectric layer can be formed by atomic layer deposition. This can reduce the device's dependence on the quality and thickness of the second gate oxide dielectric layer, and is beneficial to reducing the process difficulty of gate oxide processing.

[0098] It should be understood that the first gate oxide dielectric layer and the second gate oxide dielectric layer may have any suitable thickness, and the embodiment of the present application does not impose any particular limitation on this.

[0099] Optionally, the thickness of the first gate oxide dielectric layer is in the range of 250A to 550A; and / or the thickness of the second gate oxide dielectric layer is in the range of 50A to 150A.

[0100] Within the above thickness range, not only the interface defect density can be reduced, but also the dependence of the device on the quality of SiO2 is reduced, the gate oxide dielectric constant is increased, and the device performance is improved.

[0101] For example, the thickness of the first gate oxide dielectric layer is 250 Å; and / or the thickness of the second gate oxide dielectric layer is 50 Å.

[0102] For another example, the thickness of the first gate oxide dielectric layer is 330 Å; and / or the thickness of the second gate oxide dielectric layer is 80 Å.

[0103] For another example, the thickness of the first gate oxide dielectric layer is 450 Å; and / or the thickness of the second gate oxide dielectric layer is 120 Å.

[0104] For another example, the thickness of the first gate oxide dielectric layer is 550 Å; and / or the thickness of the second gate oxide dielectric layer is 150 Å.

[0105] In some examples, the first gate oxide dielectric layer may be one of a hafnium oxide layer, a ytterbium oxide layer, and a zirconium oxide layer.

[0106] Among them, hafnium oxide is one of the most commonly used high-K materials, with good thermal stability and a high dielectric constant of about 20 to 25.

[0107] Ytterbium oxide has a high dielectric constant and good thermal stability, and can maintain its physical and chemical properties in high temperature environments. Its dielectric constant is about 14 to 18.

[0108] Zirconia has a relatively high dielectric constant, making it a candidate for high-K material. Its dielectric constant is about 20 to 25.

[0109] It should be understood that the first gate oxide dielectric layer in the embodiment of the present application may be selected from one of an ytterbium oxide layer, a hafnium oxide layer and a zirconium oxide layer, or may be selected from dielectric layers of other high-K materials, without any special limitation.

[0110] For example, the first gate oxide dielectric layer is an ytterbium oxide layer.

[0111] For another example, the first gate oxide dielectric layer is a hafnium oxide layer.

[0112] Reference Figure 1 The semiconductor device of the embodiment of the present application further includes a source 40 and a drain 50 ; the source 40 is disposed on the first side of the substrate structure 10 and covers the outer side of the gate 30 ; the drain 50 is disposed on the second side of the substrate structure 10 .

[0113] The source is the terminal where current enters the transistor. In an n-type MOSFET, electrons flow from the source into the channel; in a p-type MOSFET, holes flow from the source into the channel.

[0114] The drain is the terminal from which current leaves the transistor. In an n-type MOSFET, electrons flow from the channel to the drain; in a p-type MOSFET, holes flow from the channel to the drain.

[0115] The overall structure of the semiconductor structure provided in the embodiment of the present application is described above, and the substrate structure is described below.

[0116] Reference Figure 1 The substrate structure includes a first conductive type doped region 101 and a first conductive type drift region 102 ; the first conductive type drift region 102 is arranged on a side of the first conductive type doped region 101 facing the gate oxide dielectric stack 20 .

[0117] The first conductive type doping region 101 is formed in the SiC substrate, and the first conductive type drift region 102 is formed in the SiC epitaxial layer.

[0118] In an optional implementation, the substrate structure further includes a second conductivity type well region 103 , a first conductivity type heavily doped region 105 , and a second conductivity type heavily doped region 104 .

[0119] Reference Figure 1 The substrate structure includes a first conductive type doped region 101 and a first conductive type drift region 102; a first conductive type heavily doped region 105 and a second conductive type heavily doped region 104 are adjacently arranged and connected to the source 40, and a second conductive type well region 103 is arranged between the first conductive type heavily doped region 105 and the second conductive type heavily doped region 104 and the first conductive type drift region 102.

[0120] Among them, the conductive ions in the first conductive type are N-type ions, and the conductive ions in the second conductive type are P-type ions; or, the conductive ions in the first conductive type are P-type ions, and the conductive ions in the second conductive type are N-type ions.

[0121] The above content describes the substrate structure in detail.

[0122] In a second aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising the following steps:

[0123] Reference Figure 2 , forming a substrate structure 10. The substrate structure may include a SiC substrate 101 and a SiC epitaxial layer 102. The SiC substrate 101 is a highly doped region, which may be doped with N-type or P-type ions, with a doping concentration of 1E 17 ~1E 21 cm -3 The SiC epitaxial layer 102 is a low-doped drift region, which can be doped with N-type or P-type ions, with a doping concentration of 1E 13 ~1E 16 cm -3 , the thickness of the epitaxial layer is selected to be 10±5um.

[0124] Afterwards, refer to Figure 3 , doping treatment is performed on different regions of the SiC epitaxial layer 102 to obtain a second conductivity type well region 103, a first conductivity type heavily doped region 105, and a second conductivity type heavily doped region 104. The first conductivity type heavily doped region 105 and the second conductivity type heavily doped region 104 are disposed adjacent to each other and connected to the source 40, and the second conductivity type well region 103 is disposed between the first conductivity type heavily doped region 105 and the second conductivity type heavily doped region 104 and the first conductivity type drift region 102.

[0125] Among them, the conductive ions in the first conductive type are N-type ions, and the conductive ions in the second conductive type are P-type ions; or, the conductive ions in the first conductive type are P-type ions, and the conductive ions in the second conductive type are N-type ions.

[0126] Specifically, doping different areas of the SiC epitaxial layer 102 may include: depositing a film layer such as SiO2 or polysilicon or Si3N4, and using a photolithography process to form a graphic window of a specific shape and position, and then dry etching the deposited film layer to form a Hard Mask barrier layer. Among them, the etching process can be selected to be RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma). Subsequently, SiC is implanted using a high-energy and high-temperature implanter, wherein the second conductive type well region can be implanted using aluminum ions or boron ions, and the doping concentration is 1E 15 ~1E 19 cm -3 The second conductive type heavily doped region can be implanted with aluminum ions or boron ions, with a doping concentration of >1E 19 cm -3 The first conductive type heavily doped region 105 can be implanted with phosphorus ions, nitrogen ions or arsenic ions, and the doping concentration is >1E 18 cm -3 After the implantation is completed, the barrier layer is removed by wet etching. Finally, a carbon film is deposited on the surface of the SiC epitaxial layer and annealed in a high-temperature inert atmosphere to activate the implanted ions. The annealing temperature is selected at 1600℃~1800℃ and the time is 20min~60min. After removing the carbon film, a carbon film is formed. Figure 3 The structure shown.

[0127] A gate oxide dielectric stack is formed; the gate oxide dielectric stack is formed on the first side of the substrate structure and includes at least two gate oxide dielectric layers, wherein at least one gate oxide dielectric layer is a gate oxide dielectric layer made of a high-K material.

[0128] Optional, see Figure 4 and Figure 5 , forming a gate oxide dielectric stack may include:

[0129] forming a second gate oxide dielectric layer 202 on the substrate structure 10;

[0130] A first gate oxide dielectric layer 201 is formed on the second gate oxide dielectric layer 202 ; the first gate oxide dielectric layer is a dielectric layer made of a high-K material.

[0131] In an optional example, when the semiconductor device is a silicon carbide metal oxide semiconductor field effect transistor; forming a second gate oxide dielectric layer on the substrate structure includes:

[0132] The epitaxial layer is in-situ oxidized to form a second gate oxide dielectric layer.

[0133] It should be understood that since the second gate oxide dielectric layer is obtained by in-situ oxidation of the SiC epitaxial layer, the interface defect density can be reduced. Then, the first gate oxide dielectric layer is formed on the second gate oxide dielectric layer. Compared with the related art in which SiO2 formed by in-situ oxidation of SiC is directly used as the gate oxide dielectric layer, the gate oxide dielectric stack not only reduces the device's dependence on the quality of SiO2, but also increases the gate oxide dielectric constant and improves the device performance.

[0134] The atmosphere of the in-situ oxidation is an O2 atmosphere, and / or the oxidation temperature range of the in-situ oxidation is 1150°C to 1300°C, and / or the oxidation time range of the in-situ oxidation is 20min to 120min.

[0135] After in-situ oxidation of the SiC epitaxial layer, the method further comprises:

[0136] The second gate oxide dielectric layer is subjected to a first annealing treatment; wherein the first annealing treatment is performed in a NO atmosphere; and / or the temperature range of the first annealing treatment is 500 to 700° C., and / or the time range of the first annealing treatment is 30s to 300s.

[0137] Specifically, in-situ oxidation of SiC to form a SiO2 film layer is carried out in a pure O2 atmosphere, and the thickness is controlled at 50A to 150A, wherein the oxidation temperature needs to be 1150°C to 1300°C, and the time needs to be 20min to 120min; after oxidation, NO annealing is required, which is carried out in a NO atmosphere for 20min to 120min to reduce the SiO2 interface state density.

[0138] Optionally, the process of forming the first gate oxide dielectric layer is an atomic layer deposition process, and the first gate oxide dielectric layer is one of an ytterbium oxide layer, a hafnium oxide layer and a zirconium oxide layer.

[0139] In one example, the first gate oxide dielectric layer is an ytterbium oxide layer, the metal precursor of the atomic layer deposition process is Yb(CP)3 (tri(cyclopentadienyl)ytterbium) material, and / or the oxygen gas source of the atomic layer deposition process is H2O or O3, and / or the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

[0140] Using Yb(CP)3 as a precursor, combined with H2O or O3 as an oxidant, atomic layer deposition can be performed in the temperature range of 200°C to 400°C to effectively deposit a high-quality ytterbium oxide layer. The ytterbium oxide layer can be used as a gate dielectric layer in semiconductor devices, providing good electrical properties and thermal stability.

[0141] In another example, the first gate oxide dielectric layer is a hafnium oxide layer, the metal precursor of the atomic layer deposition process is a clam precursor TEMAH material; the oxygen gas source of the atomic layer deposition process is H2O or O3, and the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

[0142] Among them, TEMAH is a commonly used metal organic precursor with the chemical formula Hf(N(C2H5)(CH3))4. It is composed of one hafnium (Hf) atom and four ethylmethylamino ligands. It is suitable for depositing hafnium oxide films. It has good volatility and thermal stability, and can provide high-purity and uniform hafnium oxide films in the atomic layer deposition process. The growth temperature range of 200°C to 450°C is suitable for the atomic layer deposition process of hafnium oxide. Within this temperature range, a hafnium oxide layer with good quality can be obtained. By optimizing the above process parameters, a high-quality hafnium oxide layer can be deposited as a gate dielectric layer in a semiconductor device to ensure the performance of the entire device.

[0143] In another example, the first gate oxide dielectric layer is a zirconium oxide layer, the metal precursor of the atomic layer deposition process is a zirconium precursor TDMAZ material; the oxygen gas source of the atomic layer deposition process is H2O or O3, and the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

[0144] Among them, TDMAZ is a commonly used metal organic precursor with the chemical formula Zr(N(CH3)2)4, which is composed of a zirconium (Zr) atom and four dimethylamino ligands. It is suitable for depositing zirconium oxide thin films, has good volatility and thermal stability, and can provide high-purity and uniform zirconium oxide layers in the atomic layer deposition process. The growth temperature range of 200℃ to 450℃ is suitable for the atomic layer deposition process of zirconium oxide, which can achieve good film quality and appropriate growth rate. By optimizing the above process parameters, a high-quality zirconium oxide layer can be deposited as a gate dielectric layer in a semiconductor device to ensure the electrical performance of the semiconductor device.

[0145] After forming the first gate oxide dielectric layer on the second gate oxide dielectric layer, the method further includes:

[0146] The first gate oxide dielectric layer is subjected to a second annealing treatment, wherein the second annealing treatment is performed in a N2 atmosphere, and / or the temperature range of the second annealing treatment is 500° C. to 700° C., and / or the range of the second annealing treatment is 30s to 300s.

[0147] As a specific example, a Yb2O3 film layer is deposited on a SiO2 film layer through an atomic layer deposition process, and the film layer thickness is controlled at 250A to 550A, wherein the metal precursor is Yb(CP)3 material, the oxygen gas source is H2O or O3, and the growth temperature is selected at 200°C to 400°C. Then, the film layer is rapidly annealed in a N2 atmosphere, the annealing temperature is selected at 500 to 700°C, and the time needs to be 30s to 300s to improve the quality of the Yb2O3 film layer.

[0148] In the embodiment of the present application, the gate oxide dielectric stack 20 includes at least two gate oxide dielectric layers, and one of the gate oxide dielectric layers is a gate oxide dielectric layer made of a high-K material. It should be understood that the gate oxide dielectric layer made of a high-K material can increase the dielectric constant of the gate oxide dielectric layer, based on which the gate tunneling leakage current can be reduced and the gate capacitance can be increased, thereby reducing the device power consumption and enhancing the device performance.

[0149] Furthermore, the gate oxide dielectric layer in the present application is a stacked structure, and at least one layer of the gate oxide dielectric layer is a gate oxide dielectric layer made of high-K material. Therefore, compared with the single-layer structure in the prior art, while maintaining the physical thickness of the gate oxide dielectric layer, it is possible to effectively prevent the electron tunneling current caused by the gate oxide layer being too thin, improve the voltage resistance of the gate oxide dielectric layer, and the short-circuit reliability of the semiconductor device.

[0150] Reference Figure 6 , forming a gate; the gate 30 is arranged on a side of the gate oxide dielectric stack 20 away from the substrate structure 10.

[0151] Specifically, chemical vapor deposition may be used to deposit an in-situ doped polysilicon film layer on the surface with a thickness of 4000A to 8000A, and photolithography and dry etching processes may be used to etch away excess dielectrics other than polysilicon and gate oxide.

[0152] Then, refer to Figure 1 , an interlayer dielectric BPSG film layer is deposited on the first side surface of the substrate structure by chemical vapor deposition, and a source contact hole is formed by photolithography and etching; a source ohmic contact metal is deposited on the front side, and a silicide contact is formed by rapid annealing, and the deposited metal is thickened to form a source 40 of the device; accordingly, a drain ohmic contact metal is deposited on the second side of the substrate structure, and an ohmic contact is formed by laser annealing, and the deposited metal is thickened to form a drain 50 of the device.

[0153] In a third aspect, an embodiment of the present application further provides a chip, which includes the semiconductor device described in any one of the first aspects.

[0154] In actual applications, the chip is used in power grids, new energy vehicles, smart home appliances, rail transit, and aerospace.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: Substrate structure (10); A gate oxide dielectric stack (20); the gate oxide dielectric stack (20) is formed on the first side of the substrate structure (10), and comprises at least two gate oxide dielectric layers; wherein at least one gate oxide dielectric layer is a gate oxide dielectric layer made of a high-K material, so as to increase the dielectric constant of the gate oxide dielectric stack (20); and a gate (30); the gate (30) is arranged on a side of the gate oxide dielectric stack (20) away from the substrate structure (10).

2. The semiconductor device according to claim 1, wherein: The dielectric constant of the gate oxide dielectric layer made of high-K material is greater than or equal to 14.

3. The semiconductor device according to claim 1, wherein: The gate oxide dielectric layer made of high-K material includes one of an ytterbium oxide layer, a hafnium oxide layer and a zirconium oxide layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The gate oxide dielectric stack (20) comprises a first gate oxide dielectric layer (201), wherein the first gate oxide dielectric layer (201) is a gate oxide dielectric layer made of a high-K material.

5. The semiconductor device according to claim 4, characterized in that The gate oxide dielectric stack (20) further comprises a second gate oxide dielectric layer (202), wherein the second gate oxide dielectric layer (202) is arranged between the substrate structure (10) and the first gate oxide dielectric layer (201).

6. The semiconductor device according to claim 5, characterized in that The thickness of the first gate oxide dielectric layer (201) is greater than the thickness of the second gate oxide dielectric layer (202).

7. The semiconductor device according to claim 6, characterized in that The thickness of the first gate oxide dielectric layer (201) ranges from 250A to 550A.

8. The semiconductor device according to claim 6, characterized in that The thickness of the second gate oxide dielectric layer (202) ranges from 50 Å to 150 Å.

9. The semiconductor device according to claim 5, characterized in that The semiconductor device is a silicon carbide metal oxide semiconductor field effect transistor.

10. The semiconductor device according to claim 9, characterized in that The second gate oxide dielectric layer (202) is a SiO2 layer.

11. The semiconductor device according to claim 10, characterized in that The substrate structure includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate.

12. The semiconductor device according to claim 11, characterized in that The second gate oxide dielectric layer (202) is obtained by in-situ oxidation of the SiC epitaxial layer.

13. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device also includes a source (40); The source electrode (40) is arranged on the first side of the substrate structure (10) and covers the outer side of the gate electrode (30).

14. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor device also includes a drain (40); The drain (50) is arranged on the second side of the substrate structure (10).

15. A method for preparing a semiconductor device, characterized in that: The method comprises: forming a substrate structure; forming a gate oxide dielectric stack; the gate oxide dielectric stack is formed on the first side of the substrate structure and comprises at least two gate oxide dielectric layers, wherein at least one gate oxide dielectric layer is a gate oxide dielectric layer made of a high-K material to increase the dielectric constant of the gate oxide dielectric stack (20); A gate is formed; the gate is arranged on a side of the gate oxide dielectric stack away from the substrate structure.

16. The method according to claim 15, characterized in that The forming of the gate oxide dielectric stack comprises: A first gate oxide dielectric layer is formed on the substrate structure; the first gate oxide dielectric layer is a dielectric layer made of high-K material.

17. The method according to claim 16, characterized in that Before forming the first gate oxide dielectric layer on the substrate structure, the forming of the gate oxide dielectric stack further includes: A second gate oxide dielectric layer is formed on the substrate structure; the second gate oxide dielectric layer is arranged between the substrate structure and the first gate oxide dielectric layer.

18. The method according to claim 17, characterized in that The semiconductor device is a silicon carbide metal oxide semiconductor field effect transistor, and the substrate structure includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate; The forming of a second gate oxide dielectric layer on the substrate structure comprises: The epitaxial layer is in-situ oxidized to form the second gate oxide dielectric layer.

19. The method according to claim 18, characterized in that The atmosphere of the in-situ oxidation is an O2 atmosphere, and / or the oxidation temperature range of the in-situ oxidation is 1150°C to 1300°C, and / or the oxidation time range of the in-situ oxidation is 20min to 120min.

20. The method according to claim 18, characterized in that After the in-situ oxidation of the SiC epitaxial layer, the method further comprises: Performing a first annealing treatment on the second gate oxide dielectric layer.

21. The method according to claim 20, characterized in that The first annealing treatment is performed in a NO atmosphere, and / or the temperature range of the first annealing treatment is 500-700° C., and / or the time range of the first annealing treatment is 30s-300s.

22. The method according to claim 17, characterized in that Forming a first gate oxide dielectric layer on the substrate structure includes: The first gate oxide dielectric layer is formed on the second gate oxide dielectric layer.

23. The method according to claim 22, characterized in that Forming the first gate oxide dielectric layer on the second gate oxide dielectric layer comprises: The first gate oxide dielectric layer is formed on the second gate oxide dielectric layer by an atomic layer deposition process.

24. The method according to claim 23, characterized in that The first gate oxide dielectric layer is an ytterbium oxide layer, and the metal precursor of the atomic layer deposition process is an ytterbium precursor Yb(Cp)3 material; And / or, the oxygen gas source of the atomic layer deposition process is H2O or O3; And / or, the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

25. The method according to claim 23, characterized in that The first gate oxide dielectric layer is a hafnium oxide layer, and the metal precursor of the atomic layer deposition process is a clam precursor TEMAH material; And / or, the oxygen gas source of the atomic layer deposition process is H2O or O3; And / or, the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

26. The method according to claim 23, characterized in that The first gate oxide dielectric layer is a zirconium oxide layer, and the metal precursor of the atomic layer deposition process is a zirconium precursor TDMAZ material; And / or, the oxygen gas source of the atomic layer deposition process is H2O or O3; And / or, the growth temperature range of the atomic layer deposition process is 200°C to 450°C.

27. The method according to claim 22, characterized in that After forming the first gate oxide dielectric layer on the second gate oxide dielectric layer, the method further includes: Performing a second annealing treatment on the first gate oxide dielectric layer.

28. The method according to claim 27, characterized in that The second annealing treatment is performed in a N2 atmosphere, and / or the temperature range of the second annealing treatment is 500°C to 700°C, and / or the range of the second annealing treatment is 30s to 300s.

29. A chip, characterized in that: A semiconductor device comprising any one of claims 1 to 14.

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