Silicon carbide power device cell, preparation method thereof and semiconductor device

Abstract

The embodiment of the invention discloses a silicon carbide power device cell, a preparation method thereof and a semiconductor device, and belongs to the technical field of semiconductors. The silicon carbide power device cell comprises a substrate; a gate structure disposed in the substrate; the source electrode structure is arranged in the substrate and surrounds at least part of the side surface of the gate electrode structure; the source electrode structure comprises a first source electrode structure and a second source electrode structure, and the first source electrode structure is connected with the second source electrode structure through the source electrode layer; part of the second source structure covers the bottom of the gate structure, and part of the second source structure serves as an electric field shielding structure. According to the invention, the channel area of the device during forward conduction can be increased, and forward conduction resistance is reduced, so that the performance of the device is improved, and the output characteristic of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide power device cell and a preparation method thereof, and a semiconductor device. Background Art

[0002] Silicon carbide has excellent properties such as wide band gap, high thermal conductivity, high breakdown field strength, and high electron saturation velocity. It is widely used in various power devices, but at present, obtaining higher performance silicon carbide power devices is still the current requirement.

[0003] Trench gate SiC power devices have higher channel mobility, and the device unit cell size can be further reduced, and the current density can be further increased, so trench gate SiC power devices have higher output characteristics. However, due to the high breakdown field strength and high dielectric constant of SiC materials, the gate oxide layer of SiC power devices is more prone to breakdown, leading to device failure. Therefore, it is key to ensure the gate oxide reliability of trench gate SiC power devices and further reduce the forward on-resistance. Summary of the invention

[0004] In view of the above problems, the present application provides a silicon carbide power device cell and a preparation method thereof, and a semiconductor device, which can increase the channel area of ​​the device when it is forward-conducting, reduce the forward conduction resistance, thereby improving the device performance and improving the output characteristics of the device.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A first aspect of an embodiment of the present application provides a silicon carbide power device cell, comprising:

[0007] substrate;

[0008] A gate structure, wherein the gate structure is disposed in the substrate;

[0009] A source structure, the source structure is disposed in the substrate and surrounds at least a portion of a side surface of the gate structure;

[0010] The source structure comprises a first source structure and a second source structure, wherein the first source structure is connected to the second source structure via a source electrode layer;

[0011] Part of the second source structure covers the bottom of the gate structure, and part of the second source structure serves as an electric field shielding structure.

[0012] In a possible implementation, along the thickness direction of the substrate, the first source structure includes a first source layer of a first conductivity type and a first source active layer of a second conductivity type;

[0013] The first source active layer of the second conductivity type is arranged on the substrate, and the first source layer of the first conductivity type is arranged on the first source active layer of the second conductivity type;

[0014] At least one of the first source active layer of the second conductivity type and the first source layer of the first conductivity type is connected to the second source structure through the source electrode layer.

[0015] In a possible implementation, along the thickness direction of the substrate, the second source structure includes a second source layer of the first conductivity type and a second source active layer of the second conductivity type;

[0016] The second conductive type second source active layer is disposed on the substrate, and the first conductive type second source layer is disposed on the second conductive type second source active layer;

[0017] At least one of the second source layer of the first conductivity type and the second source active layer of the second conductivity type is connected to the first source structure through the source electrode layer;

[0018] The second source active layer of the second conductivity type serves as an electric field shielding structure.

[0019] In a possible implementation manner, the second source layer of the first conductivity type covers the bottom and a portion of the side of the gate structure.

[0020] In a possible implementation manner, the second source active layer of the second conductivity type at least covers the bottom and a portion of the side of the second source layer of the first conductivity type.

[0021] In a possible implementation manner, the second source active layer of the second conductivity type also covers a portion of the side of the gate structure and is not connected to the first source structure.

[0022] In a possible implementation, the silicon carbide power device cell further includes an ohmic contact layer, and the conductivity type of the ohmic contact layer is the second conductivity type;

[0023] The first source structure and the second source structure are electrically connected to the source electrode layer through the ohmic contact layer, respectively.

[0024] In a possible implementation, the ohmic contact layer includes a first ohmic contact layer;

[0025] The first source active layer of the second conductivity type is connected to the source electrode layer through the first ohmic contact layer.

[0026] In a possible implementation manner, the first ohmic contact layer is doped into the first source active layer of the second conductivity type.

[0027] In a possible implementation manner, the first ohmic contact layer is doped into a first source layer of the first conductivity type.

[0028] In a possible implementation, the ohmic contact layer includes a second ohmic contact layer;

[0029] The second source active layer of the second conductivity type is connected to the source electrode layer through the second ohmic contact layer.

[0030] In a possible implementation manner, an orthographic projection of the first ohmic contact layer on the substrate surrounds an outer periphery of an orthographic projection of the second ohmic contact layer on the substrate.

[0031] In a possible implementation manner, an orthographic projection of the gate structure on the substrate surrounds an outer periphery of an orthographic projection of the second ohmic contact layer on the substrate.

[0032] In a possible implementation manner, the second ohmic contact layer is doped into a second source active layer of the second conductivity type.

[0033] In a possible implementation manner, the second ohmic contact layer is doped into a second source layer of the first conductivity type.

[0034] In a possible implementation manner, the first source structure surrounds the top of the gate structure.

[0035] In a possible implementation manner, on a plane parallel to where the substrate is located, the gate structure is a ring structure.

[0036] In a possible implementation manner, on a plane parallel to the substrate, the first ohmic contact layer is a ring structure and surrounds the gate structure.

[0037] In a possible implementation manner, on a plane parallel to where the substrate is located, the gate structure is a strip structure.

[0038] In a possible implementation, the first ohmic contact layer and the second ohmic contact layer each include a plurality of ohmic contact portions;

[0039] The plurality of ohmic contact portions are arranged at intervals along an extension direction of the gate structure.

[0040] In a possible implementation manner, the gate structure includes at least two sub-gate structures, and the at least two sub-gate structures are isolated from each other.

[0041] In a possible implementation manner, the source electrode layer includes an extension portion, and the extension portion is located in the gate structure and separates the gate structure into at least two sub-gate structures;

[0042] The extension portion is electrically insulated from each of the sub-gate structures.

[0043] In a possible implementation manner, the number of the sub-gate structures is two; and the two sub-gate structures are symmetrically distributed on two sides of the extension portion.

[0044] In a possible implementation manner, an end portion of the extension portion facing the bottom surface of the substrate extends into the second source structure;

[0045] Alternatively, an end portion of the extension portion facing the bottom surface of the substrate extends to a top surface of the second source structure.

[0046] In a possible implementation, the silicon carbide power device cell further includes an ohmic contact layer, and the conductivity type of the ohmic contact layer is the second conductivity type;

[0047] The ohmic contact layer contacts the bottom surface of the extension portion facing the substrate and protrudes from the extension portion.

[0048] In a possible implementation manner, an insulating layer is further included, and the insulating layer is located between the source electrode layer and the gate structure, and between the extension portion and the sub-gate structure.

[0049] In a possible implementation manner, the gate structure includes a gate and a gate dielectric layer, and the gate dielectric layer covers a bottom surface and side surfaces of the gate.

[0050] In a possible implementation manner, the base includes a substrate and an epitaxial layer, and the epitaxial layer is disposed on the substrate.

[0051] A second aspect of an embodiment of the present application provides a method for preparing a silicon carbide power device cell, comprising:

[0052] providing a substrate;

[0053] Forming a source structure disposed in the substrate; wherein the source structure comprises a first source structure and a second source structure disposed at intervals;

[0054] forming a gate structure, wherein the gate structure is disposed in the substrate; the first source structure at least partially surrounds at least a portion of the side surface of the gate structure; the second source structure at least covers the bottom of the gate structure, and a portion of the second source structure serves as an electric field shielding structure;

[0055] A source electrode layer is formed, wherein the source electrode layer connects the first source structure and the second source structure.

[0056] In a possible implementation, the step of providing a substrate includes:

[0057] providing a substrate;

[0058] An epitaxial layer is formed, wherein the epitaxial layer is disposed on the substrate.

[0059] In a possible implementation, the step of forming a source structure includes:

[0060] forming a first source structure material layer, wherein the first source structure material layer is disposed on the epitaxial layer;

[0061] The first source structure material layer and the substrate are removed to form a gate trench; the depth direction of the gate trench is perpendicular to the substrate, and the bottom of the gate trench extends into the epitaxial layer; wherein the first source structure material layer that remains constitutes a first source structure;

[0062] A second source structure is formed, wherein the second source structure at least covers a portion of the bottom of the gate trench.

[0063] In a possible implementation, the step of forming the second source structure includes:

[0064] Using an ion doping process, at least the epitaxial layer exposed at the bottom of the gate trench is doped to form a second source active layer of a second conductivity type;

[0065] The second source active layer of the second conductivity type is doped continuously by using the ion doping process to form a second source layer of the first conductivity type in the second source active layer of the second conductivity type.

[0066] In a possible implementation manner, the step of forming the gate structure further includes:

[0067] forming a second photoresist layer having a second mask opening, wherein the second mask opening exposes a portion of the gate structure;

[0068] The second photoresist layer is used as a mask to remove the gate structure exposed in the second mask opening to form an etching hole in the gate structure, wherein the etching hole separates the gate structure into at least two sub-gate structures.

[0069] In a possible implementation, after the step of forming the gate structure and before the step of forming the source electrode layer, the method

[0070] An ohmic contact layer is formed, wherein the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer; the first ohmic contact layer is disposed on the first source structure, and the second ohmic contact layer is disposed on the second source structure.

[0071] A third aspect of an embodiment of the present application provides a semiconductor device, comprising the silicon carbide power device cell described in the first aspect.

[0072] The embodiment of the present application provides a silicon carbide power device cell and a preparation method thereof, and a semiconductor device, wherein the source structure includes a first source structure and a second source structure, wherein the first source structure is connected to the second source structure through a source electrode layer; a portion of the second source structure serves as an electric field shielding structure. In this way, when a portion of the second source structure serves as an electric field shielding structure, it can effectively shield the gate oxide electric field when the device is in a reverse blocking state; at the same time, a channel extending upward from the bottom of the trench is added to the sidewall of the trench, which can further increase the channel length, thereby increasing the channel area of ​​the silicon carbide power device when it is forward-conducted as much as possible and reducing the forward conduction resistance of the device. Compared with the related art, the present application can ensure the gate oxide reliability when the silicon carbide power device is in a reverse blocking state, while further increasing the channel length of the trench sidewall, thereby minimizing the channel resistance when it is forward-conducted, reducing the forward conduction resistance of the silicon carbide power device, and improving the output characteristics of the silicon carbide power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 A schematic diagram of the structure of a first silicon carbide power device cell provided in an embodiment of the present application;

[0074] Figure 2 A top view of a second silicon carbide power device cell provided in an embodiment of the present application;

[0075] Figure 3 A cross-sectional view of a second silicon carbide power device cell provided in an embodiment of the present application;

[0076] Figure 4 A top view of a third silicon carbide power device cell provided in an embodiment of the present application;

[0077] Figure 5 for Figure 4 Section view along AA direction;

[0078] Figure 6 for Figure 4 The cross-section along the BB direction;

[0079] Figure 7 A process flow chart of a method for preparing a first silicon carbide power device cell provided in an embodiment of the present application;

[0080] Figure 8 A schematic diagram of forming a first source structure material layer in the first method for preparing a silicon carbide power device cell provided in an embodiment of the present application;

[0081] Fig. 9 A schematic diagram of forming a gate trench in the first method for preparing a silicon carbide power device cell provided in an embodiment of the present application;

[0082] Fig.10 A schematic diagram of forming a gate structure in the first method for preparing a silicon carbide power device cell provided in an embodiment of the present application;

[0083] Fig.11 A schematic diagram of forming a sub-gate structure in the first method for preparing a silicon carbide power device cell provided in an embodiment of the present application;

[0084] Fig.12 A schematic diagram of forming an insulating layer in the first method for preparing a silicon carbide power device cell provided in an embodiment of the present application;

[0085] Fig.13 A schematic diagram of forming an ohmic contact layer and a source electrode layer in a method for preparing a first silicon carbide power device cell provided in an embodiment of the present application.

[0086] Description of reference numerals:

[0087] 100: base; 110: substrate; 120: epitaxial layer; 130: first photoresist layer; 131: first mask opening;

[0088] 200-gate structure; 210-gate; 220-gate dielectric layer; 230-sub-gate structure; 240-etched hole;

[0089] 300-source structure; 310-first source structure; 311-first source layer of first conductivity type; 312-first source active layer of second conductivity type; 320-second source structure; 321-second source layer of first conductivity type; 322-second source active layer of second conductivity type;

[0090] 500-insulation layer;

[0091] 600 - ohmic contact layer; 610 - first ohmic contact layer; 620 - second ohmic contact layer;

[0092] 800 - source electrode layer; 810 - extension portion. DETAILED DESCRIPTION

[0093] At present, trench silicon carbide power devices have higher channel mobility than planar silicon carbide power devices, and the unit cell size can be smaller, which can further improve the channel density. Therefore, trench silicon carbide power devices have lower forward on-resistance, lower switching loss, and higher output characteristics. However, the reliability of the gate dielectric layer of trench silicon carbide power devices is poor. When the device is in the reverse blocking state, the electric field will be mainly concentrated at the bottom of the trench, making the gate dielectric layer at the bottom of the trench gate easy to break down, thereby affecting the reliability of the trench silicon carbide power device.

[0094] In the related art, in order to protect the gate dielectric layer and improve the reliability of the trench silicon carbide power device, high-energy ion implantation is usually performed in the epitaxial layer to form a gate oxide protection zone, which is located on one side of the trench and extends to the bottom of the trench to wrap the entire bottom of the trench. In this way, although the gate dielectric layer can be effectively protected, the channel on one side of the trench is sacrificed, which reduces the channel density during forward conduction to a certain extent, thereby increasing the channel resistance during forward conduction and reducing the performance of the trench silicon carbide power device.

[0095] In view of the above technical problems, the embodiment of the present application provides a silicon carbide power device cell and a preparation method thereof, and a semiconductor device, wherein the source structure includes a first source structure and a second source structure, and the first source structure is connected to the second source structure through a source electrode layer; a part of the structure of the second source structure serves as an electric field shielding structure. In this way, when a part of the structure of the second source structure serves as an electric field shielding structure, it can effectively shield the gate oxide electric field when the device is in a reverse blocking state; at the same time, a channel extending upward from the bottom of the trench is added to the side wall of the trench, which can further increase the channel length, and can increase the channel area of ​​the silicon carbide power device when it is forward-conducted as much as possible, thereby reducing the forward conduction resistance of the device. Compared with the related art, the present application can ensure the gate oxide reliability when the silicon carbide power device is in a reverse blocking state, while further increasing the channel length of the trench sidewall, thereby minimizing the channel resistance when forward-conducted, reducing the forward conduction resistance of the silicon carbide power device, and improving the output characteristics of the silicon carbide power device.

[0096] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below in conjunction with the drawings in the embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0097] Reference Figures 1 to 6 As shown, an embodiment of the present application provides a silicon carbide power device cell. In this embodiment, a trench-type silicon carbide power device cell is mainly used as an example for explanation.

[0098] Reference Figure 1 As shown, the silicon carbide power device cell includes a substrate 100 .

[0099] The base 100 includes a substrate 110. The substrate 110 is a supporting component of the silicon carbide power device cell, and is used to support other components arranged thereon. The substrate 110 may be made of a semiconductor material. For example, the material of the substrate 110 may include silicon carbide.

[0100] An epitaxial layer 120 is disposed on the front side of the substrate 110 , and a drain electrode layer is disposed on the back side of the substrate 110 . The front side of the substrate 110 refers to the upper surface of the substrate 110 , and the back side of the substrate 110 refers to the lower surface of the substrate 110 .

[0101] It should be noted that, in this embodiment, the doping concentration of the epitaxial layer 120 is not limited, and can be prepared according to actual needs. In addition, there is no limitation on the conductivity type of the epitaxial layer 120. Exemplarily, the conductivity type of the epitaxial layer 120 can be the first conductivity type N type, or the conductivity type of the epitaxial layer 120 can be the first conductivity type P type.

[0102] In this embodiment, the conductivity type of the epitaxial layer 120 is mainly described by taking the first conductivity type N type as an example.

[0103] Continue to refer to Figure 1 As shown, the silicon carbide power device cell includes a gate structure 200, and the gate structure 200 is disposed in the substrate 110, so that the gate structure 200 forms a trench gate. Compared with a planar gate semiconductor device, a trench gate semiconductor device can have a smaller cell structure size and a higher channel mobility, so the trench gate silicon carbide power device greatly reduces the resistance of the silicon carbide power device when it is forward-conducted, and improves the performance of the silicon carbide power device cell.

[0104] Reference Figure 1As shown, the gate structure 200 includes a gate 210 and a gate dielectric layer 220, and the gate dielectric layer 220 covers the bottom and side surfaces of the gate 210. In a specific preparation process, an epitaxial layer 120 of the first conductivity type can be first grown on a substrate 110 of the first conductivity type, and then the epitaxial layer 120 can be patterned to form a gate trench in the epitaxial layer 120, and then a gate dielectric layer 220 is formed on the inner wall of the gate trench by thermal oxidation or deposition process, and then a gate 210 is formed, and the gate 210 fills the area surrounded by the gate dielectric layer 220; in this way, the gate dielectric layer 220 covers the bottom and side surfaces of the gate 210. Among them, the material of the gate dielectric layer 220 includes silicon oxide. The material of the gate 210 includes but is not limited to polysilicon.

[0105] For example, a deposition process can be used to first grow a gate dielectric layer 220 on the sidewalls of the gate trench, wherein the gate dielectric layer 220 also covers the top surface of the exposed epitaxial layer 120, and then doped polysilicon is deposited in the gate trench to fill the gate trench to form a gate, and the polysilicon and the gate dielectric layer are etched back to retain the gate dielectric layer and the gate in the gate trench, thereby forming a gate structure 200.

[0106] Continue to refer to Figure 1 As shown, in the embodiment of the present application, the silicon carbide power device cell includes a source structure 300 and a source electrode layer 800. The source structure 300 is disposed in the substrate 100 and surrounds at least part of the side surface of the gate structure 200. The source electrode layer 800 is disposed on the source structure 300 and connected to the source structure 300.

[0107] In order to increase the channel area of ​​the silicon carbide power device during forward conduction and reduce the forward conduction resistance of the silicon carbide power device, in the embodiment of the present application, referring to Figure 1 As shown, the source structure 300 may include a first source structure 310 and a second source structure 320 , and the first source structure 310 is connected to the second source structure 320 through a source electrode layer 800 .

[0108] In the embodiment of the present application, there is no specific limitation on the locations of the first source structure 310 and the second source structure 320, which can be set according to actual needs. Figure 1 As shown, the first source structure may surround the top of the gate structure 200 , and the second source structure 320 may cover at least a portion of the bottom of the gate structure 200 .

[0109] In this way, the present application adds a channel extending upward from the bottom of the trench to the sidewall of the trench, which can further increase the channel length, thereby increasing the channel area of ​​the silicon carbide power device when it is forward-conducted as much as possible and reducing the forward on-resistance of the device. Compared with the related art, the present application can ensure the gate oxide reliability of the silicon carbide power device when it is in the reverse blocking state, while further increasing the channel path of the trench sidewall, thereby reducing the channel resistance during forward conduction to the greatest extent, reducing the forward on-resistance of the silicon carbide power device, and improving the output characteristics of the silicon carbide power device.

[0110] In the embodiment of the present application, the partial structure located at the bottom of the second source structure 320 can be used as an electric field shielding structure. In this way, when the cell structure of the silicon carbide power device is in a reverse bias state, the electric field can be prevented from converging at the bottom of the gate dielectric layer 220, thereby improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure caused by breakdown of the gate dielectric layer, thereby ensuring the performance and reliability of the gate structure, and further ensuring the performance and reliability of the semiconductor device.

[0111] In one possible implementation, referring to Figure 1 As shown, along the thickness direction of the substrate 100, the first source structure 310 includes a first source layer 311 of a first conductivity type and a first source active layer 312 of a second conductivity type. The first source active layer 312 of the second conductivity type is disposed on the substrate 100, and the first source layer 311 of the first conductivity type is disposed on the first source active layer 312 of the second conductivity type; the first source active layer 312 of the second conductivity type is connected to the second source structure 320 through the source electrode layer 800.

[0112] The first conductivity type may be N-type, and the second conductivity type may be P-type; or the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0113] In the embodiment of the present application, the first source active layer 312 of the second conductivity type is P-type and the first source layer 311 of the first conductivity type is N-type.

[0114] When a forward voltage is applied to the gate structure 200, the first source active layer 312 of the second conductivity type surrounds a portion of the gate structure 200 to form an inversion region, that is, a channel region, so that the conductivity type of the channel region is the same as the conductivity type of the first source layer 311 of the first conductivity type, thereby putting the silicon carbide power device in an on state.

[0115] In this embodiment, at least one of the first source active layer 312 of the second conductivity type and the first source layer 311 of the first conductivity type is connected to the second source structure 320 through the source electrode layer 800. That is, one of the first source active layer 312 of the second conductivity type and the first source layer 311 of the first conductivity type is connected to the second source structure 320 through the source electrode layer 800, or the first source active layer 312 of the second conductivity type and the first source layer 311 of the first conductivity type are simultaneously connected to the second source structure 320 through the source electrode layer 800 (please refer to Figure 6 ), thus, a channel is also formed between the second source structure 320 covering at least a portion of the bottom of the gate structure 200 and the gate structure 200, so that the channel area of ​​the silicon carbide power device during forward conduction can be increased as much as possible, thereby reducing the forward conduction resistance of the device.

[0116] In one possible implementation, see Figure 1 , Figure 3 , Figure 5 and Figure 6 , along the thickness direction of the substrate, the second source structure 320 includes a second source layer 321 of the first conductivity type and a second source active layer 322 of the second conductivity type; wherein the second source active layer 322 of the second conductivity type is disposed on the substrate 100, and the second source layer 321 of the first conductivity type is disposed on the second source active layer 322 of the second conductivity type. The first source active layer 312 of the second conductivity type is connected to the second source active layer 322 of the second conductivity type through the source electrode layer 800.

[0117] In the embodiment of the present application, the second source active layer 322 of the second conductivity type is P-type and the second source layer 321 of the first conductivity type is N-type.

[0118] When a forward voltage is applied to the gate structure 200, the second conductive type second source active layer 322 surrounds a portion of the gate structure 200 to form an inversion zone, i.e., a channel zone, so that the conductive type of the channel zone is the same as the conductive type of the first conductive type second source layer 321, thereby putting the silicon carbide power device in an on state.

[0119] In this embodiment, at least one of the second source layer 321 of the first conductivity type and the second source active layer 322 of the second conductivity type is connected to the first source structure 310 through the source electrode layer 800. In this way, when the source electrode layer 800 applies a voltage to the first source structure 310, a voltage is also applied to the second source structure 320 simultaneously, so that a channel is also formed between the second source structure 320 and the gate structure 200. In this way, channels are formed between the first source structure 310 and the second source structure 320 and the gate structure 200, thereby increasing the channel area of ​​the silicon carbide power device when it is forward-conducted as much as possible and reducing the forward conduction resistance of the device.

[0120] It should be noted that the second conductive type second source active layer 322 in the present embodiment serves as an electric field shielding structure. Thus, when the cell structure of the silicon carbide power device is in a reverse bias state, the electric field can be prevented from converging at the bottom of the gate dielectric layer 220, thereby improving the reliability of the gate dielectric layer and avoiding the problem of gate structure failure caused by breakdown of the gate dielectric layer, thereby ensuring the performance and reliability of the gate structure, and further ensuring the performance and reliability of the semiconductor device.

[0121] In a possible implementation, the second source layer 321 of the first conductivity type covers the bottom and part of the side of the gate structure 200. The second source layer 321 of the first conductivity type is not connected to the first source structure 310, so that the normal operation of the transistor formed by the gate structure 200 and the source structure 300 can be ensured.

[0122] In a possible implementation, the second conductive type second source active layer 322 covers the bottom and part of the side of the first conductive type second source layer 321. In this way, the second conductive type second source active layer 322 is half-wrapped in the first conductive type second source layer 321, which can reduce the difficulty of preparing the second conductive type second source active layer 322.

[0123] It should be noted that the second conductive type second source active layer 322 is not only half-wrapped in the first conductive type second source layer 321, but may also have other structures. Exemplarily, the second conductive type second source active layer 322 covers part of the side of the gate structure 200, that is, the second conductive type second source active layer 322 not only covers the first conductive type second source layer 321, but also extends toward the first source structure and covers part of the side of the gate structure 200. In this way, the second conductive type second source active layer 322 is in direct contact, so that the contact area between the gate structure 200 and the second conductive type second source active layer 322 is increased, thereby enhancing the control ability of the gate structure 200 over the channel region. When a voltage is provided to the gate structure 200, the contact area between the second conductive type second source active layer 322 and the gate structure 200 can be inverted more quickly, thereby improving the response speed of the transistor.

[0124] When the second conductive type second source active layer 322 covers part of the side of the gate structure 200, the second conductive type second source active layer 322 is not connected to the first source structure 310. In this way, the design that the first conductive type second source layer 321 is not connected to the first source structure 310 can ensure that the substrate 100 has a source structure and a drain structure, thus ensuring that the transistor works normally.

[0125] In one possible implementation, referring to Figure 1 As shown, the silicon carbide power device cell may further include an ohmic contact layer 600, the conductivity type of the ohmic contact layer 600 being the second conductivity type; the doping concentration of the second conductivity type of the ohmic contact layer 600 is greater than the doping concentration of the second conductivity type in the first source active layer 312 of the second conductivity type.

[0126] The first source structure 310 and the second source structure 320 are electrically connected to the source electrode layer 800 through the ohmic contact layer 600. Since the doping concentration of the second conductivity type of the ohmic contact layer 600 is greater than the doping concentration of the second conductivity type in the first source active layer 312 of the second conductivity type, the second conductivity type ohmic contact layer 600 provides a low resistance path, so that the contact resistance between the source electrode layer 800 and the first source structure 310, and between the source electrode layer 800 and the second source structure 320 is reduced, thereby improving the performance of the device.

[0127] In order to facilitate a detailed description of the connection between the ohmic contact layer 600 and the first source structure 310 or the second source structure 320 , the ohmic contact layer 600 may be divided.

[0128] For example, the ohmic contact layer 600 may include a first ohmic contact layer 610 . The second conductive type first source active layer 312 is connected to the source electrode layer 800 through the first ohmic contact layer 610 .

[0129] In this embodiment, the first ohmic contact layer 610 is doped into the first source active layer 312 of the second conductivity type. Figure 1 .

[0130] Alternatively, in this embodiment, the first ohmic contact layer 610 is doped in the first source layer 311 of the first conductivity type. Figure 3 .

[0131] Alternatively, in this embodiment, the first ohmic contact layer 610 is doped into the first source layer 31 of the first conductivity type and the first source active layer 312 of the second conductivity type at the same time. Figure 6 .

[0132] In the embodiment of the present application, the location of the ohmic contact layer 600 is flexibly designed, for example, by doping in the first source active layer 312 of the second conductivity type or in the first source layer 311 of the first conductivity type, to adapt to different device structures and performance requirements.

[0133] In the embodiment of the present application, the ohmic contact layer 600 further includes a second ohmic contact layer 620 ; the second source active layer 322 of the second conductivity type is connected to the source electrode layer 800 via the second ohmic contact layer 620 .

[0134] The orthographic projection of the first ohmic contact layer 610 on the substrate 100 surrounds the periphery of the orthographic projection of the second ohmic contact layer 620 on the substrate 100. This helps to distribute the current more evenly, prevents the current from being over-concentrated in certain areas and causing overheating or damage to the device, thereby improving the reliability and stability of the device.

[0135] In other embodiments, please refer to Figure 2 As shown, the orthographic projection of the gate structure 200 on the substrate 100 surrounds the periphery of the orthographic projection of the second ohmic contact layer 620 on the substrate 100. This layout enables the gate structure 200 to more effectively control the electric field distribution of the second conductive type second source active layer 322 and its surroundings, thereby improving the control capability of the gate structure 200 over the channel region, and helping to improve the switching speed and response characteristics of the device.

[0136] In a possible implementation, the second ohmic contact layer 620 is doped in the second source active layer 322 of the second conductivity type. Alternatively, the second ohmic contact layer 620 is doped in the second source layer 321 of the first conductivity type. In this way, by flexibly designing the location of the second ohmic contact layer 620, for example, the second ohmic contact layer 620 is doped in the second source active layer 322 of the second conductivity type, or the second source layer 321 of the first conductivity type, different device structures and performance requirements can be met.

[0137] In a possible implementation, the first source structure 310 may be disposed near the top of the gate structure 200. Since the first source structure 310 is usually prepared by a doping process, the position near the top of the gate structure 200 may be easier to achieve the required process conditions, thereby reducing the difficulty and complexity of the doping process. In addition, it is also easier to control the depth and concentration of doping, thereby improving the accuracy and uniformity of doping, helping to ensure that the first source structure 310 has the required electrical properties, thereby improving the performance and reliability of the entire device.

[0138] In the embodiment of the present application, the shape of the gate structure 200 can be selected in a variety of ways. Figure 2 As shown, on a plane parallel to the substrate 100 , the gate structure 200 is a ring-shaped structure.

[0139] Accordingly, on a plane parallel to the substrate 100, the first ohmic contact layer 610 is a ring structure and surrounds the gate structure 200. The ring-shaped gate structure 200 can more effectively control the electric field distribution around it, which helps to reduce electric field concentration and leakage current, thereby improving the breakdown voltage and reliability of the device.

[0140] Please refer to Figure 4 As shown, in another possible implementation, the gate structure 200 is a strip structure on a plane parallel to the substrate 100. Accordingly, the first ohmic contact layer 610 and the second ohmic contact layer 620 each include a plurality of ohmic contact portions; the plurality of ohmic contact portions are arranged at intervals along the extension direction of the gate structure 200. Such an arrangement can reduce the area of ​​the first ohmic contact layer 610 and the second ohmic contact layer 620, reduce parasitic capacitance, optimize current distribution, improve the switching speed and reliability of the device, and reduce manufacturing costs and improve the flexibility of the device.

[0141] Continue to refer to Figure 1As shown, in an embodiment of the present application, the gate structure 200 may include at least two sub-gate structures 230, and the at least two sub-gate structures 230 are isolated from each other to ensure that the at least two sub-gate structures 230 are independent of each other. This helps to avoid the problem of mutual interference in the current flow direction between the at least two sub-gate structures 230, thereby ensuring that the current can flow along two symmetrical channel sections, further ensuring an increase in the channel area during forward conduction, minimizing the channel resistance during forward conduction, and ensuring the reliability of the silicon carbide power device cell.

[0142] It should be noted that, in this embodiment, there is no limitation on the isolation method between the at least two sub-gate structures 230. Exemplarily, an isolation member with insulating properties may be provided between the at least two sub-gate structures 230, or an isolation hole may be provided on the gate structure 200, and the at least two sub-gate structures 230 are isolated by the isolation hole. This is not limited in this embodiment.

[0143] In the embodiment of the present application, there is no limitation on the number of sub-gate structures 230. For example, the number of sub-gate structures 230 may be two, three or more. At least two sub-gate structures 230 may be arranged along the circumference of the gate structure 200. For example, when the number of sub-gate structures 230 includes two, the two sub-gates may be arranged symmetrically along the circumference of the gate structure 200; when the number of sub-gate structures 230 includes three or more, three or more sub-gates may be arranged at intervals along the circumference of the gate structure 200.

[0144] In one possible implementation, referring to Figure 1 As shown, the source electrode layer 800 may include an extension portion 810 , which is located in the gate structure 200 and separates the gate structure 200 into at least two sub-gate structures 230 ; the extension portion 810 is electrically insulated from each sub-gate structure 230 .

[0145] In the embodiment of the present application, the shape, size, position, etc. of the extension portion 810 are not limited. For example, the extension portion 810 may be a columnar structure, and the extension portion 810 separates the gate structure 200 into two sub-gate structures 230 symmetrically distributed on both sides of the extension portion 810 .

[0146] When a forward voltage is applied to the gate structure 200, the first source active layer 312 of the second conductivity type and the second source active layer 322 of the second conductivity type respectively surround the partial regions of the two sub-gate structures 230 to form inversion regions, that is, to form channel regions. Compared with the related art, the present application is beneficial to avoid the problem of sacrificing the channel on one side of the groove in the related art, and increases the number of conducting channels, thereby helping to ensure a higher channel mobility when the silicon carbide power device cell is forward-conducted, thereby increasing the channel area when forward-conducted, increasing the active area, thereby reducing the channel resistance when forward-conducted to the greatest extent, thereby reducing the on-resistance, and improving the working performance and reliability of the silicon carbide power device cell.

[0147] In this embodiment, refer to Figure 1 As shown, two sub-gate structures 230 are symmetrically distributed on both sides of the extension 810. In this way, there are channels on both sides of the trench, so that the current can flow along the two symmetrical channels, increasing the channel area during forward conduction, thereby minimizing the channel resistance during forward conduction. At the same time, compared with the single channel of the related art, the present application helps to avoid deeper ion injection in the P-type source region, thereby helping to save materials and further help save costs.

[0148] In the embodiment of the present application, the end of the extension portion 810 facing the bottom surface of the substrate 100 may extend into the second source structure 320 , or may have other structures.

[0149] In an example, see Figure 1 As shown, the end of the extension portion 810 toward the bottom surface of the substrate 100 extends into the second source structure 320; for example, the end of the extension portion 810 toward the bottom surface of the substrate 100 extends into the second source layer 321 of the first conductivity type, or extends into the second source active layer 322 of the second conductivity type, or extends to the interface between the second source layer 321 of the first conductivity type and the second source active layer 322 of the second conductivity type.

[0150] In another example, see Figure 3 and Figure 6 As shown, the end of the extension portion 810 facing the bottom surface of the substrate 100 extends to the top surface of the second source structure 320 .

[0151] In this way, the size of the extension portion 810 in the direction perpendicular to the substrate 100 can be reasonably adjusted according to the formation position of the ohmic contact layer 600 , thereby improving the design flexibility of the extension portion 810 .

[0152] In a possible implementation, the silicon carbide power device cell further includes an ohmic contact layer 600, the conductivity type of the ohmic contact layer 600 is the second conductivity type; the ohmic contact layer 600 contacts the bottom surface of the extension portion 810 facing the substrate 100, and protrudes from the extension portion 810. In other words, the area of ​​the ohmic contact layer 600 is larger than the area of ​​the extension portion 810, so that the contact area between the ohmic contact layer 600 and the extension portion 810 can be increased as much as possible, thereby reducing the contact resistance between the source electrode layer 800 and the ohmic contact layer 600.

[0153] It should be noted that the area of ​​the ohmic contact layer 600 is not limited to being larger than the area of ​​the extension portion 810, and other options are also possible. Exemplarily, the area of ​​the ohmic contact layer 600 is smaller than, or equal to, the area of ​​the extension portion 810. In this way, the area of ​​the ohmic contact layer 600 can be reasonably set according to the doping concentration of the ohmic contact layer 600 to achieve optimal performance and cost-effectiveness.

[0154] In one possible implementation, referring to Figure 1 As shown, an insulating layer 500 may also be included, and the insulating layer 500 is located between the source electrode layer 800 and the gate structure 200, and between the extension portion 810 and the sub-gate structure 230. The insulating layer 500 has an insulating function, which is beneficial to achieving electrical insulation between the source electrode layer 800 and the gate structure 200, and between the extension portion 810 and the sub-gate structure 230.

[0155] In the embodiment of the present application, the shape, size, position, etc. of the insulating layer 500 are not limited. Exemplarily, the insulating layer 500 may be in an "L" shape, wherein the insulating layer 500 in the horizontal section may be located between the source electrode layer 800 and the gate structure 200, and the insulating layer 500 in the vertical section may be located between the extension 810 and the sub-gate structure 230. Alternatively, the insulating layer 500 may be in other shapes. This is not limited in the present embodiment.

[0156] In the embodiment of the present application, there is no limitation on the number of insulating layers 500. For example, the number of insulating layers 500 includes one, two or more. In the present embodiment, two insulating layers 500 are mainly used as an example for description. The two insulating layers 500 are symmetrically arranged.

[0157] It should be noted that the structure of the silicon carbide power device cell in this embodiment includes but is not limited to the above three structures, and can be specifically configured according to actual needs.

[0158] Reference Figures 7 to 13 As shown, an embodiment of the present application also provides a method for preparing a silicon carbide power device cell.

[0159] Step S100: providing a substrate.

[0160] Step S200: forming a source structure disposed in a substrate; wherein the source structure comprises a first source structure and a second source structure disposed at intervals.

[0161] Step S300: forming a gate structure, the gate structure is disposed in the substrate; a first source structure at least partially surrounds at least a portion of the side surface of the gate structure; a second source structure at least covers the bottom of the gate structure, and a portion of the second source structure serves as an electric field shielding structure.

[0162] Step S400: forming a source electrode layer, wherein the source electrode layer connects the first source structure and the second source structure.

[0163] The first source structure in the silicon carbide power device cell prepared by the preparation method is connected to the second source structure through the source electrode layer; a part of the second source structure is used as an electric field shielding structure. In this way, the sidewall of the groove adds a channel from the bottom of the groove upward, which can further increase the channel density, thereby increasing the channel area of ​​the silicon carbide power device when it is forward-conducted as much as possible and reducing the forward conduction resistance of the device.

[0164] Please refer to Figure 8 In a possible implementation, the method for preparing a silicon carbide power device cell further includes:

[0165] The step of providing a substrate includes:

[0166] providing a substrate;

[0167] An epitaxial layer is formed, wherein the epitaxial layer is disposed on a substrate.

[0168] Exemplarily, an epitaxial layer may be formed on a substrate using an epitaxial process, and the conductivity type of the epitaxial layer is the same as the conductivity type of the substrate. For example, the conductivity type of the substrate and the conductivity type of the epitaxial layer are both the first conductivity type, and the first conductivity type may be N-type or P-type. As an example, the first conductivity type may be N-type.

[0169] Please refer to Figure 8 and Fig. 9 In a possible implementation, the step of forming a source structure includes:

[0170] A first source structure material layer is formed, wherein the first source structure material layer is disposed on the epitaxial layer.

[0171] It should be noted that, in this embodiment, the first source structure material layer can be formed in the epitaxial layer, for example, by ion implantation into the epitaxial layer through a doping process to form the first source structure material layer. For another example, the first source structure material layer can be formed on the epitaxial layer, for example, by depositing the first source structure material layer on the epitaxial layer through a deposition process.

[0172] Part of the first source structure material layer and part of the substrate are removed to form a gate trench; the depth direction of the gate trench is perpendicular to the substrate, and the bottom of the gate trench extends into the epitaxial layer; wherein the retained first source structure material layer constitutes a first source structure.

[0173] In this step, a first photoresist layer 130 having a first mask opening 131 may be formed on the first source structure material layer.

[0174] Afterwards, an etching process is performed using the first photoresist layer 130 as a mask to remove the first source structure material layer and a portion of the substrate 100 exposed in the first mask opening 131 to form a gate trench. It should be noted that when the substrate 100 includes a substrate 110 and an epitaxial layer 120, this step is to remove the first source structure material layer and a portion of the epitaxial layer 120 exposed in the first mask opening 131 to form a gate trench.

[0175] It should be noted that in this embodiment, the shape of the first source structure 310 matches the shape of the gate trench. If the gate trench is cylindrical, the first source structure 310 is annular accordingly; if the gate trench is strip-shaped, the first source structure 310 is strip-shaped accordingly, and is respectively located on both sides along the extension direction perpendicular to the strip shape.

[0176] A second source structure is formed, where the second source structure at least covers a portion of the bottom of the gate trench.

[0177] Illustratively, the first photoresist layer 130 is used as a mask and an ion doping process is used to dope at least the epitaxial layer 120 exposed at the bottom of the gate trench to form a second source active layer 322 of the second conductivity type.

[0178] The second source active layer 322 of the second conductivity type is doped continuously by the ion doping process to form a second source layer 321 of the first conductivity type in the second source active layer 322 of the second conductivity type.

[0179] In a possible implementation, the step of forming a gate structure includes:

[0180] Please refer to Fig.10 A gate dielectric layer 220 is formed on the inner wall of the gate trench by a deposition process, wherein the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0181] Afterwards, the gate 210 is formed by a deposition process, and the gate 210 completely fills the area surrounded by the gate dielectric layer 220 . The gate 210 and the gate dielectric layer 220 constitute the gate structure 200 .

[0182] It should be noted that the gate structure 200 may be an integral structure or may include a plurality of sub-gate structures 230. When the gate structure 200 includes a plurality of sub-gate structures 230, the step of forming the gate structure further includes:

[0183] Please refer to Fig.11 , a second photoresist layer 140 having a second mask opening 141 is formed, and the second mask opening exposes a portion of the gate structure 200 .

[0184] The second photoresist layer 140 is used as a mask to perform an etching process to remove the gate structure 200 exposed in the second mask opening 141, so as to form an etching hole 240 in the gate structure 200. The etching hole 240 extends in a direction perpendicular to the substrate 100, so that the etching hole 240 separates the gate structure 200 into at least two sub-gate structures 230. Fig.11 Taking the illustrated orientation as an example, the blank area above the dotted line is the second mask opening 141 , and the blank area below the dotted line is the etching hole 240 .

[0185] The bottom of the etched hole may be located at the interface between the second source structure 320 and the gate structure 200 , or may be located inside the second source structure 320 , and may be freely set according to the design requirements of the product.

[0186] Afterwards, the second photoresist layer 140 may be removed by an ashing process or a cleaning process.

[0187] Please refer to Fig.12 and Fig.13 , after the step of forming the gate structure and before the step of forming the source electrode layer, the method comprises:

[0188] An ohmic contact layer is formed, and the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer; the first ohmic contact layer is arranged on the first source structure, and the second ohmic contact layer is arranged on the second source structure.

[0189] For example, refer to Fig.12 , forming an insulating layer 500, the insulating layer 500 covers the sidewalls of the etched hole, covers the top surface of the gate structure 200 and a portion of the top surface of the first source structure 310, so that the remaining top surface of the first source structure 310 and the bottom wall of the etched hole are exposed.

[0190] Using the insulating layer 500 as a mask, a doping process is performed to perform ion doping on the exposed first source structure 310 and the second source structure 320 to form a first ohmic contact layer 610 and a second ohmic contact layer 620; wherein the first ohmic contact layer 610 is disposed on the first source structure 310, the second ohmic contact layer 620 is disposed on the second source structure 320, and the first ohmic contact layer 610 and the second ohmic contact layer 620 constitute an ohmic contact layer 600.

[0191] In the embodiment of the present application, the material of the insulating layer 500 includes silicon oxide, silicon nitride, aluminum oxide or other insulating materials.

[0192] Please continue to refer to Fig.13 , a source electrode layer 800 covering the ohmic contact layer 600 and the insulating layer 500 is formed by a deposition process, thereby completing the preparation of the trench gate silicon carbide power device.

[0193] The present application also provides a power device, including the silicon carbide power device cell described in any of the above embodiments. The power device formed by this embodiment is not limited to devices such as metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET), insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, referred to as IGBT), etc. All silicon carbide power device cells are within the scope of this patent.

[0194] It should be noted that the beneficial effects of the power device provided in the embodiment of the present application are the same as the beneficial effects of the silicon carbide power device cell provided in the above embodiment, and this embodiment will not be described in detail here.

[0195] The power device provided in the embodiments of the present application can be applied to vehicles, for example, can be applied to key electric drive and electric control components such as the main drive inverter, converter, on-board charger (OBC) and on-board charging pile of the vehicle. The vehicle can be an electric vehicle, a hybrid vehicle or a new energy vehicle.

[0196] Therefore, the embodiment of the present application provides a silicon carbide power device cell and a preparation method thereof, and a semiconductor device, wherein the source structure includes a first source structure and a second source structure, wherein the first source structure is connected to the second source structure through a source electrode layer; and a portion of the second source structure serves as an electric field shielding structure. In this way, when a portion of the second source structure serves as an electric field shielding structure, it can effectively shield the gate oxide electric field when the device is in a reverse blocking state; at the same time, a channel extending upward from the bottom of the trench is added to the sidewall of the trench, which can further increase the channel density, thereby increasing the channel area of ​​the silicon carbide power device when it is forward-conducted as much as possible, and reducing the forward conduction resistance of the device. Compared with the related art, the present application can ensure the gate oxide reliability when the silicon carbide power device is in a reverse blocking state, while further increasing the channel path on the sidewall of the trench, thereby minimizing the channel resistance during forward conduction, reducing the forward conduction resistance of the silicon carbide power device, and improving the output characteristics of the silicon carbide power device.

[0197] It should be noted that, in the description of the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0198] In the description of the embodiments of the present application, the term "and / or" merely indicates an association relationship that describes associated objects, indicating that three relationships may exist. For example, A and / or B may indicate the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" indicates any combination of at least two of any one or more of a plurality of. For example, at least one of A, B, and C may indicate any one or more elements selected from a set that includes A, B, and C.

[0199] In the description of the embodiments of the present application, the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the term "plurality" means two or more, unless otherwise precisely and specifically specified.

[0200] In the description of the embodiment of the present application, the terms "first", "second", "third", "fourth", etc. (if present) are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0201] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A silicon carbide power device cell, characterized in that: include: Base (100); A gate structure (200), wherein the gate structure (200) is disposed in the substrate (100); A source structure (300), the source structure (300) being disposed in the substrate (100) and surrounding at least a portion of a side surface of the gate structure (200); The source structure (300) comprises a first source structure (310) and a second source structure (320), and the first source structure (310) is connected to the second source structure (320) via a source electrode layer (800); The second source structure (320) at least covers a portion of the bottom of the gate structure (200), and a portion of the second source structure (320) serves as an electric field shielding structure.

2. The silicon carbide power device cell according to claim 1, characterized in that: Along the thickness direction of the substrate (100), the first source structure (310) comprises a first source layer (311) of a first conductivity type and a first source active layer (312) of a second conductivity type; The first source active layer (312) of the second conductivity type is arranged on the substrate (100), and the first source layer (311) of the first conductivity type is arranged on the first source active layer (312) of the second conductivity type; At least one of the first source active layer (312) of the second conductivity type and the first source layer (311) of the first conductivity type is connected to the second source structure (320) through the source electrode layer (800).

3. The silicon carbide power device cell according to claim 2, characterized in that: Along the thickness direction of the substrate, the second source structure (320) comprises a second source layer (321) of the first conductivity type and a second source active layer (322) of the second conductivity type; The second conductive type second source active layer (322) is arranged on the substrate (100), and the first conductive type second source layer (321) is arranged on the second conductive type second source active layer (322); At least one of a second source layer (321) of the first conductivity type and a second source active layer (322) of the second conductivity type is connected to the first source structure (310) through the source electrode layer (800); The second source active layer (322) of the second conductivity type serves as an electric field shielding structure.

4. The silicon carbide power device cell according to claim 3, characterized in that: The second source layer (321) of the first conductivity type covers the bottom and part of the side of the gate structure (200).

5. The silicon carbide power device cell according to claim 4, characterized in that: The second conductive type second source active layer (322) at least covers the bottom and part of the side of the first conductive type second source layer (321).

6. The silicon carbide power device cell according to claim 5, characterized in that: The second source active layer (322) of the second conductivity type also covers a portion of the side of the gate structure and is not connected to the first source structure (310).

7. The silicon carbide power device cell according to any one of claims 2 to 6, characterized in that: The silicon carbide power device cell further comprises an ohmic contact layer (600), and the conductivity type of the ohmic contact layer (600) is the second conductivity type; The first source structure (310) and the second source structure (320) are electrically connected to the source electrode layer (800) through the ohmic contact layer (600), respectively.

8. The silicon carbide power device cell according to claim 7, characterized in that: The ohmic contact layer (600) includes a first ohmic contact layer (610); The first source active layer (312) of the second conductivity type is connected to the source electrode layer (800) via the first ohmic contact layer (610).

9. The silicon carbide power device cell according to claim 8, characterized in that: The first ohmic contact layer (610) is doped into the first source active layer (312) of the second conductivity type.

10. The silicon carbide power device cell according to claim 8, characterized in that: The first ohmic contact layer (610) is doped into the first source layer (311) of the first conductivity type.

11. The silicon carbide power device cell according to any one of claims 8 to 10, characterized in that: The ohmic contact layer (600) includes a second ohmic contact layer (620); The second source active layer (322) of the second conductivity type is connected to the source electrode layer (800) via the second ohmic contact layer (620).

12. The silicon carbide power device cell according to claim 11, characterized in that: The orthographic projection of the first ohmic contact layer (610) on the substrate surrounds the periphery of the orthographic projection of the second ohmic contact layer (620) on the substrate (100).

13. The silicon carbide power device cell according to claim 12, characterized in that: The orthographic projection of the gate structure (200) on the substrate (100) surrounds the periphery of the orthographic projection of the second ohmic contact layer (620) on the substrate (100).

14. The silicon carbide power device cell according to claim 11, characterized in that: The second ohmic contact layer (620) is doped into the second source active layer (322) of the second conductivity type.

15. The silicon carbide power device cell according to claim 11, characterized in that: The second ohmic contact layer (620) is doped into the second source layer (321) of the first conductivity type.

16. The silicon carbide power device cell according to any one of claims 1 to 6, characterized in that: The first source structure (310) surrounds the top of the gate structure (200).

17. The silicon carbide power device cell according to any one of claims 8 to 10, characterized in that: On a plane parallel to the substrate (100), the gate structure (200) is a ring-shaped structure.

18. The silicon carbide power device cell according to claim 17, characterized in that: On a plane parallel to the substrate (100), the first ohmic contact layer (610) is a ring-shaped structure and surrounds the gate structure (200).

19. The silicon carbide power device cell according to any one of claims 8 to 10, characterized in that: On a plane parallel to the substrate (100), the gate structure (200) is a strip-shaped structure.

20. The silicon carbide power device cell according to claim 19, characterized in that: The first ohmic contact layer (610) and the second ohmic contact layer (620) each include a plurality of ohmic contact portions; The plurality of ohmic contact portions are arranged at intervals along the extension direction of the gate structure (200).

21. The silicon carbide power device cell according to any one of claims 1 to 6, characterized in that: The gate structure (200) comprises at least two sub-gate structures (230), and the at least two sub-gate structures (230) are isolated from each other.

22. The silicon carbide power device cell according to claim 21, characterized in that: The source electrode layer (800) comprises an extension portion (810), wherein the extension portion (810) is located in the gate structure (200) and separates the gate structure (200) into at least two sub-gate structures (230); The extension portion (810) is electrically insulated from each of the sub-gate structures (230).

23. The silicon carbide power device cell according to claim 22, characterized in that: The number of the sub-gate structures (230) is two; the two sub-gate structures (230) are symmetrically distributed on both sides of the extension portion (810).

24. The silicon carbide power device cell according to claim 23, characterized in that: The end of the extension portion (810) facing the bottom surface of the substrate (100) extends into the second source structure (320); Alternatively, the end of the extension portion (810) facing the bottom surface of the substrate (100) extends to the top surface of the second source structure (320).

25. The silicon carbide power device cell according to claim 24, characterized in that: The silicon carbide power device cell further comprises an ohmic contact layer (600), and the conductivity type of the ohmic contact layer (600) is the second conductivity type; The ohmic contact layer (600) contacts the bottom surface of the extension portion (810) facing the substrate (100) and protrudes from the extension portion (810).

26. The silicon carbide power device cell according to any one of claims 22 to 25, characterized in that: It also includes an insulating layer (500), wherein the insulating layer (500) is located between the source electrode layer (800) and the gate structure (200), and between the extension portion (810) and the sub-gate structure (230).

27. The silicon carbide power device cell according to any one of claims 1 to 6, characterized in that: The gate structure (200) comprises a gate (210) and a gate dielectric layer (220), wherein the gate dielectric layer (220) covers the bottom surface and side surfaces of the gate (210).

28. The silicon carbide power device cell according to any one of claims 1 to 6, characterized in that: The base (100) comprises a substrate (110) and an epitaxial layer (120), wherein the epitaxial layer (120) is arranged on the substrate (110).

29. A method for preparing a silicon carbide power device cell, characterized in that: include: providing a substrate; Forming a source structure disposed in the substrate; wherein the source structure comprises a first source structure and a second source structure disposed at intervals; forming a gate structure, wherein the gate structure is disposed in the substrate; the first source structure surrounds at least a portion of a side surface of the gate structure; the second source structure at least covers a bottom of the gate structure, and a portion of the second source structure serves as an electric field shielding structure; A source electrode layer is formed, wherein the source electrode layer connects the first source structure and the second source structure.

30. The method for preparing a silicon carbide power device cell according to claim 29, characterized in that: The step of providing a substrate includes: providing a substrate; An epitaxial layer is formed, wherein the epitaxial layer is disposed on the substrate.

31. The method for preparing a silicon carbide power device cell according to claim 30, characterized in that: The steps of forming a source structure include: forming a first source structure material layer, wherein the first source structure material layer is disposed on the epitaxial layer; Removing part of the first source structure material layer and part of the substrate to form a gate trench; the depth direction of the gate trench is perpendicular to the substrate, and the bottom of the gate trench extends into the epitaxial layer; wherein the first source structure material layer that remains constitutes a first source structure; A second source structure is formed, wherein the second source structure at least covers a portion of the bottom of the gate trench.

32. The method for preparing a silicon carbide power device cell according to claim 31, characterized in that: The step of forming the second source structure includes: Using an ion doping process, at least doping the epitaxial layer exposed at the bottom of the gate trench to form a second source active layer of a second conductivity type; The second source active layer of the second conductivity type is doped continuously by using the ion doping process to form a second source layer of the first conductivity type in the second source active layer of the second conductivity type.

33. The method for preparing a silicon carbide power device cell according to any one of claims 29 to 32, characterized in that: The step of forming the gate structure further includes: forming a second photoresist layer having a second mask opening, wherein the second mask opening exposes a portion of the gate structure; The second photoresist layer is used as a mask to remove the gate structure exposed in the second mask opening to form an etching hole in the gate structure, wherein the etching hole separates the gate structure into at least two sub-gate structures.

34. The method for preparing a silicon carbide power device cell according to any one of claims 29 to 32, characterized in that: After the step of forming the gate structure and before the step of forming the source electrode layer, the method includes: An ohmic contact layer is formed, wherein the ohmic contact layer includes a first ohmic contact layer and a second ohmic contact layer; the first ohmic contact layer is disposed on the first source structure, and the second ohmic contact layer is disposed on the second source structure.

35. A semiconductor device, characterized in that: A silicon carbide power device comprising any one of claims 1-28.

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