A dual-channel superjunction silicon carbide MOSFET

Abstract

The present invention discloses a double-channel superjunction silicon carbide MOSFET, which includes a type-A substrate, a type-A epitaxial layer, a type-B second well region, a first trench, a second trench, a drain metal, a gate metal, a source metal, and a Schottky metal; the conduction types of A and B are different; a superjunction region and two type-B first well regions are provided in the type-A epitaxial layer; the superjunction region includes type-A columnar bars and two type-B columnar bars; the two type-B first well regions are provided at the tops of the two type-B columnar bars; the first trench and the second trench are provided on both sides of the type-B second well region; the Schottky metal is provided at the bottom of the second trench; the gate metal is suspended in the insulating medium, and a first conduction channel is formed at the top of the type-B first well region below the gate metal, and a second conduction channel is formed on the side wall of the type-B second well region adjacent to the gate metal. The present invention can ensure high breakdown voltage and low specific on-resistance while also having excellent dynamic performance, and has strong freewheeling ability and high reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductors, and particularly to a double-channel superjunction silicon carbide MOSFET. Background Art

[0002] Silicon carbide (SiC) has become a popular material in the field of power devices operating in high-voltage and high-temperature scenarios due to its wide bandgap, high thermal conductivity, etc. Silicon carbide metal-oxide-semiconductor field effect transistor (MOSFET) is widely popular in application scenarios such as electric vehicles, industrial automation, and power transmission due to its advantages such as faster switching speed and lower switching losses.

[0003] However, precisely because of the wider bandgap of the material itself, the on-state voltage drop of the body diode of the silicon carbide MOSFET is too high, resulting in too high switching losses of the device. At the same time, the conduction of the body diode of the silicon carbide MOSFET will increase the defects in the drift region, increasing the on-resistance of the device and bringing the problem of bipolar degradation.

[0004] To solve the above problems, traditional structures often use a silicon carbide MOSFET in anti-parallel connection with a Schottky barrier diode (SBD). The extremely low on-state voltage drop of the SBD can effectively suppress the conduction of the device body diode and provide a new path for device freewheeling at the same time. However, the external SBD will introduce additional parasitic inductance and capacitance, thereby affecting the dynamic performance of the device. In addition, it will also increase the layout area and cost.

[0005] On the other hand, the low channel mobility of the planar-gate silicon carbide MOSFET limits the conduction ability of the device. Selecting a trench-gate structure can achieve higher channel mobility in different crystal orientations. However, for silicon carbide MOSFETs in high-voltage and high-power application scenarios, the trench bottom corner is prone to electric field concentration, resulting in premature breakdown of the device and reducing the reliability of the gate oxide. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a double-channel superjunction silicon carbide MOSFET in view of the deficiencies of the above-mentioned prior art. While ensuring high breakdown voltage and low specific on-resistance, the double-channel superjunction silicon carbide MOSFET can have excellent dynamic performance, strong freewheeling ability, and high reliability.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A double-channel superjunction silicon carbide MOSFET includes an A-type substrate, an A-type epitaxial layer, a B-type second well region, a first trench, a second trench, a drain metal, a gate metal, a source metal, and a Schottky metal; wherein, the A-type is an N-type or P-type conductive semiconductor, the B-type is a P-type or N-type conductive semiconductor, and the conduction types of A and B are different.

[0009] The drain metal, the A-type substrate, the A-type epitaxial layer, the B-type second well region, and the source metal are arranged in sequence from bottom to top.

[0010] A superjunction region and two B-type first well regions located on both sides of the top of the superjunction region are arranged in the A-type epitaxial layer.

[0011] The superjunction region includes A-type columnar bars and two B-type columnar bars located on both sides of the A-type columnar bars; wherein, the two B-type columnar bars are respectively a first B-type columnar bar and a second B-type columnar bar.

[0012] The two B-type first well regions are respectively arranged on the tops of the two B-type columnar bars.

[0013] The first trench and the second trench are arranged on both sides of the B-type second well region; wherein, the bottom of the first trench is in contact with the B-type first well region at the top of the first B-type columnar bar, and the bottom of the second trench is in contact with the B-type first well region at the top of the second B-type columnar bar.

[0014] The Schottky metal is arranged at the bottom of the second trench.

[0015] The source metal is in an inverted U shape and has a first side leg and a second side leg; wherein, the first side leg extends into the first trench and is in contact with the top of the B-type first well region below, and an insulating medium is filled between the inner side wall of the first side leg and the B-type second well region; the second side leg extends into the second trench and is in contact with the top of the Schottky metal.

[0016] The gate metal is suspended in the insulating medium, a first conductive channel is formed at the top of the B-type first well region below the gate metal, and a second conductive channel is formed on the side wall of the B-type second well region adjacent to the gate metal.

[0017] A B-type first ohmic contact region and an A-type first source contact region are embedded side by side from the outside to the inside at the top of the B-type first well region located at the top of the first B-type columnar bar; wherein, the A-type first source contact region is in contact with the first side leg and is partially located directly below the gate metal; the top of the B-type first well region inside the A-type first source contact region is formed as the first conductive channel.

[0018] A B-type first ohmic contact region is embedded at the top of the B-type first well region located at the top of the second B-type columnar bar; the B-type first ohmic contact region is in contact with the Schottky metal.

[0019] The top of the second well region of type B is provided with a second source contact region of type A and a second ohmic contact region of type B side by side; wherein, the second source contact region of type A is in contact with the source metal at the top and is adjacent to the gate metal; the side wall of the second well region of type B directly below the second source contact region of type A forms the second conductive channel.

[0020] The length L1 of the first conductive channel is equal to the length L2 of the second conductive channel.

[0021] The thickness of the insulating medium between the gate metal and the first conductive channel is equal to the thickness of the insulating medium between the gate metal and the second conductive channel.

[0022] It further includes a type A JFET region, and the type A JFET region is arranged between the type A epitaxial layer and the second well region of type B and is located between the first trench and the second trench.

[0023] The bottom depths of the first trench and the second trench are the same.

[0024] It further includes a type A buffer layer, and the type A buffer layer is arranged between the type A substrate and the superjunction region.

[0025] The gate metal is a monolithic metal or a split metal.

[0026] The source metal further includes a horizontal cross part connecting the first side leg and the second side leg, and a dielectric trench is arranged at the bottom of the horizontal cross part corresponding to the gate metal for filling an insulating medium; the top surface height of the gate metal is higher than the top surface height of the second well region of type B.

[0027] The present invention has the following beneficial effects:

[0028] 1. For the double-channel superjunction silicon carbide MOSFET proposed by the present invention, the second trench set therein can, on the one hand, reduce the depletion capacitance of the device and improve the dynamic performance of the device; on the other hand, a Schottky metal is integrated on the side wall of the second trench, saving the layout area compared with the planar Schottky metal.

[0029] 2. For the double-channel superjunction silicon carbide MOSFET proposed by the present invention, a type B first well region and type B columnar bars are introduced under both the first trench and the second trench, improving the reliability of the gate oxide; in addition, the setting of the superjunction region can optimize the electric field distribution, enhance the blocking ability of the device, and at the same time increase the doping concentration of the drift region, significantly reducing the specific on-resistance of the device, thereby reconciling the contradictory relationship between the specific on-resistance and the breakdown voltage of the device. Further, the shielding effect of the type B columnar bars can reduce the gate-drain capacitance of the device, thereby reducing the switching loss of the device.

[0030] 3. The dual-channel superjunction silicon carbide MOSFET proposed by the present invention introduces a dual-conductive channel. A first conductive channel is additionally provided at the inner top of the B-type first well region located at the top of the first B-type columnar strip, providing an additional conduction path for carriers, compensating for the saturation current of the device during forward conduction, and overcoming the problem of narrow current paths brought about by the superjunction region. At the same time, the design of the dual-conductive channel disperses the current path, avoids the formation of local hot spots, and improves the overall heat dissipation capacity of the device. Especially in the case of short circuits, the additional first conductive channel can reduce the instantaneous thermal stress and improve the device's anti-burning ability. Description of the Drawings

[0031] Figure 1 Schematic diagram of the structure of the dual-channel superjunction silicon carbide MOSFET provided in Embodiment 1 of the present invention.

[0032] Figure 2 Schematic diagram of the structure of Embodiment 1 of the present invention marked with the superjunction region, the first conductive channel, and the second conductive channel.

[0033] Figure 3 Graph showing the relationship between the breakdown voltage, specific on-resistance, and figure of merit of Embodiment 1 of the present invention with the thickness of the superjunction region; among them, (a) is the graph showing the relationship between the breakdown voltage and the specific on-resistance with the thickness of the superjunction region; (b) is the graph showing the relationship between the figure of merit and the thickness of the superjunction region.

[0034] Figure 4 Schematic diagram for comparing the forward conduction characteristics of Embodiment 1 of the present invention and a traditional SiC MOSFET.

[0035] Figure 5 Schematic diagram for comparing the reverse conduction characteristics of Embodiment 1 of the present invention and a traditional SiC MOSFET.

[0036] Figure 6 Schematic diagram for comparing the capacitance characteristics of Embodiment 1 of the present invention and a traditional SiC MOSFET.

[0037] Figure 7 Schematic diagram for comparing the switching energy losses of Embodiment 1 of the present invention and a traditional SiC MOSFET.

[0038] Figure 8 Schematic diagram of Embodiment 2 of the present invention.

[0039] Figure 9 Schematic diagram of Embodiment 3 of the present invention.

[0040] Figure 10 Schematic diagram after the growth of a partial A-type epitaxial layer in Step 1 when preparing Embodiment 1.

[0041] Figure 11Schematic diagram after the preparation of the superjunction region in Step 2 during the preparation of Example 1.

[0042] Figure 12 Schematic diagram after the preparation of a partial Type-A JFET region in Step 3 during the preparation of Example 1.

[0043] Figure 13 Schematic diagram after the preparation of the Type-B first well region in Step 4 during the preparation of Example 1.

[0044] Figure 14 Schematic diagram after the preparation of the Type-B first ohmic contact region in Step 5 during the preparation of Example 1.

[0045] Figure 15 Schematic diagram after the preparation of the Type-A first source contact region in Step 6 during the preparation of Example 1.

[0046] Figure 16 Schematic diagram after the preparation of the Type-A JFET region in Step 7 during the preparation of Example 1.

[0047] Figure 17 Schematic diagram after the preparation of the Type-B second well region in Step 8 during the preparation of Example 1.

[0048] Figure 18 Schematic diagram after the preparation of the Type-A second source contact region in Step 9 during the preparation of Example 1.

[0049] Figure 19 Schematic diagram after the preparation of the Type-B second ohmic contact region in Step 10 during the preparation of Example 1.

[0050] Figure 20 Schematic diagram after the preparation of the first trench and the second trench in Step 11 during the preparation of Example 1.

[0051] Figure 21 Schematic diagram after the deposition of the Schottky metal in Step 12 during the preparation of Example 1.

[0052] Figure 22 Schematic diagram after the preparation of the L-shaped insulating dielectric in Step 13 during the preparation of Example 1.

[0053] Figure 23 Schematic diagram after the complete deposition of the gate metal and the insulating dielectric in Step 14 during the preparation of Example 1.

[0054] Figure 24 Schematic diagram after the deposition of the source metal and the drain metal in Step 15 during the preparation of Example 1.

[0055] Figure 25 Schematic diagram of the structure of a traditional SiC MOSFET.

[0056] Among them are:

[0057] 1. Drain metal; 2. Type A substrate; 3. Type A epitaxial layer; 4. Type B columnar bar; 5. Type B first well region; 6. Type B first ohmic contact region; 7. Type A first source contact region; 8. Type A JFET region; 9. Type B second well region; 10. Type A second source contact region; 11. Type B second ohmic contact region; 12. Insulating medium; 13. Gate metal; 14. Schottky metal; 15. Source metal; 16. Type B shielding layer; 17. Superjunction region; 18. Type A buffer layer. Detailed implementation manners

[0058] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific preferred implementation manners.

[0059] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "left side", "right side", "upper part", "lower part", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. "First", "second", etc. do not represent the importance of components, so it cannot be understood as a limitation to the present invention. The specific dimensions adopted in this embodiment are only for illustrating the technical solution by way of example and do not limit the protection scope of the present invention.

[0060] Embodiment 1

[0061] As Figure 1 shown, a dual-channel superjunction silicon carbide MOSFET includes a Type A substrate 2, a Type A epitaxial layer 3, a Type A JFET region 8, a Type B second well region 9, a first trench, a second trench, a drain metal 1, a gate metal 13, a source metal 15, and a Schottky metal 14; wherein, Type A is an N-type or P-type conductive semiconductor, and Type B is a P-type or N-type conductive semiconductor, and the conductive types of A and B are different. In this Embodiment 1, the preferred setting method is: Type A is an N-type conductive semiconductor, and Type B is a P-type conductive semiconductor.

[0062] The drain metal 1, the Type A substrate 2, the Type A epitaxial layer 3, the Type A JFET region 8, the Type B second well region 9, and the source metal 15 are arranged in sequence from bottom to top. As an alternative, the Type A JFET region 8 may not be arranged. In this case, Figure 1 all of the Type A JFET regions 8 in

[0063] As Figure 2 shown, the Type A epitaxial layer is provided with a superjunction region 17 and two Type B first well regions 5 located on both sides of the top of the superjunction region.

[0064] The superjunction region includes two B-type columnar bars 4 and an A-type columnar bar between the two B-type columnar bars. The two B-type columnar bars are respectively a first B-type columnar bar and a second B-type columnar bar. In this embodiment, the width of the first B-type columnar bar is greater than the width of the second B-type columnar bar.

[0065] Two B-type first well regions are respectively disposed on the tops of the two B-type columnar bars; wherein, the B-type first well region 5 located on the top of the first B-type columnar bar is preferably disposed with the same width as the first B-type columnar bar; the B-type first well region 5 located on the top of the second B-type columnar bar is preferably disposed with the same width as the second B-type columnar bar.

[0066] On the top of the B-type first well region 5 located on the top of the first B-type columnar bar, a B-type first ohmic contact region 6 and an A-type first source contact region 7 with end contacts and the same height are preferably embedded side by side from outside to inside; wherein, on the top of the B-type first well region inside the A-type first source contact region, a first conductive channel is formed.

[0067] On the top of the B-type first well region 5 located on the top of the second B-type columnar bar, a B-type first ohmic contact region 6 is embedded. Further, the first ohmic contact region 6 here is preferably disposed with the same width as the second B-type columnar bar.

[0068] Further, the two B-type first ohmic contact regions 6 and one A-type first source contact region 7 embedded on the tops of the two B-type first well regions 5 are all disposed with the same height, and the bottom surfaces are preferably disposed with the same height as the bottom surface of the A-type JFET region 8, and the top surfaces are flush with the top surfaces of the corresponding B-type first well regions 5. At this time, a part of the bottom of the A-type JFET region is embedded in the top of the A-type epitaxial layer. As an alternative, the bottom of the A-type JFET region may not be embedded in the A-type epitaxial layer either.

[0069] The first trench and the second trench are disposed on both sides of the B-type second well region 9. Further, the bottom depths of the first trench and the second trench are preferably the same. In this embodiment, the bottom of the first trench is in contact with the B-type first well region 5 on the top of the first B-type columnar bar, and is preferably disposed with the same width as the first B-type columnar bar; the bottom of the second trench is in contact with the B-type first well region 5 on the top of the second B-type columnar bar, and is preferably disposed with the same width as the second B-type columnar bar.

[0070] The above-mentioned Schottky metal 14 is disposed at the bottom of the second trench, the bottom of the Schottky metal 14 is in contact with the B-type first ohmic contact region 6 directly below, and the top surface of the Schottky metal 14 is preferably disposed with the same height as the top surface of the A-type JFET region 8.

[0071] An A-type second source contact region 10 and a B-type second ohmic contact region 11 are embedded side by side on the top of the above-mentioned B-type second well region 9; wherein, the A-type second source contact region is used to contact the source metal and is adjacent to the first trench; the side wall of the B-type second well region directly below the A-type second source contact region forms a second conductive channel.

[0072] As Figure 2 shown, the first conductive channel length L1 and the second conductive channel length L2 are preferably equal, both being 0.4 mm.

[0073] The source metal is in an inverted U shape, having a first side leg, a second side leg, and a horizontal cross portion connecting the first side leg and the second side leg; wherein, the first side leg extends into the first trench and can contact the A-type first source contact region 7 at the top of the B-type first well region 5 below, the outer side surface of the first side leg is aligned with the outer side wall of the B-type first well region 5 below, the width of the first side leg is smaller than the B-type first well region 5 below, and an insulating medium is filled between the inner side wall of the first side leg and the B-type second well region 9 (i.e., in the first trench inside the first side leg); the second side leg extends into the second trench and contacts the top of the Schottky metal 14.

[0074] Furthermore, a dielectric trench is preferably provided at the bottom of the horizontal cross portion corresponding to the gate metal for filling an insulating medium.

[0075] The gate metal is suspended in the insulating medium, located above the first conductive channel, and at least partially above the A-type first source contact region 7. In this embodiment, the gate metal is preferably a monolithic metal.

[0076] Furthermore, the thickness of the insulating medium between the gate metal and the first conductive channel is equal to the thickness of the insulating medium between the gate metal and the second conductive channel, both preferably being 50 nm.

[0077] Furthermore, the top surface height of the gate metal is preferably higher than the top surface height of the B-type second well region 9.

[0078] Working principle of Embodiment 1

[0079] In Embodiment 1, the Schottky metal is disposed on the side wall of the second trench, saving layout area while increasing the Schottky contact area; when reverse-conducting, the Schottky metal is short-circuited with the source metal to be at a high potential, effectively suppressing the turn-on of the SiC MOSFET body diode. In this embodiment, a B-type first well region and a B-type columnar bar are introduced under both the first trench and the second trench. In the reverse blocking state, the auxiliary depletion effect of the B-type columnar bar and the B-type first well region effectively improves the reverse breakdown voltage of the device; in the reverse-conducting state, the longitudinal Schottky metal contact on the side wall of the second trench can achieve good freewheeling ability, greatly improving the performance of the device in the third quadrant.

[0080] The traditional SiC MOSFET structure (hereinafter referred to as the traditional device) is provided with a planar SBD, as Figure 25 shown. In contrast, for the double-channel superjunction silicon carbide MOSFET provided in Embodiment 1 (hereinafter referred to as the device provided in this embodiment), due to the existence of the superjunction region, the blocking ability and the forward conduction ability of the device are improved. As Figure 3As shown, as the thickness of the superjunction region increases, the entire device can achieve better charge balance, and thus the breakdown voltage gradually increases. At the same time, precisely because of the increase in the thickness of the superjunction region, the current path is gradually compressed, resulting in a gradual increase in the specific on-resistance. However, the superjunction region itself increases the doping concentration of the drift region, so the specific on-resistance of the device remains at a relatively low level. When the thickness of the superjunction region is 7.5 mm, the device provided in this embodiment reaches the highest figure of merit of 2630 MW / cm 2 , at this time the breakdown voltage of the device is 1871 V, and the specific on-resistance is 1.331 mΩ–cm 2 .

[0081] As Figure 4 shown, the device provided in this embodiment is additionally provided with a horizontal first conductive channel, which overcomes the problem of the narrow current path brought by the superjunction region to a certain extent, compensates for the saturation current of the device during forward conduction, making it only slightly lower than the saturation current of the traditional device, and at the same time the saturation speed is faster than that of the traditional device. In contrast, if the first conductive channel of the device provided in this example is removed, the saturation current will be greatly reduced.

[0082] As Figure 5 shown, whether it is a traditional device or the device provided in this embodiment, SBD is selected to be integrated into the SiCMOSFET, which improves the freewheeling ability of the device and the ability to suppress the turn-on of the body diode, and greatly enhances the performance of the device in the third quadrant. When the gate-source voltage is -5 V and the drain-source current is -100 A / cm 2 , both devices have a low reverse conduction voltage drop of 1.2 V.

[0083] As Figure 6 shown, due to the provision of the second trench in the device provided in this embodiment, the depletion capacitance of the device is reduced. At the same time, due to the shielding effect of the B-type columnar bars, the gate-drain capacitance (reverse recovery capacitance) of the device is greatly reduced, and as the drain-source voltage increases, the superjunction region is gradually depleted and the shielding effect weakens, so the gate-drain capacitance increases slowly. When the gate-drain voltage is 800 V, compared with the traditional device, the gate-drain capacitance of the device provided in this embodiment is reduced by 79%.

[0084] As Figure 7 shown, the device provided in this embodiment has lower depletion capacitance and gate-drain capacitance, so the switching loss of the device is lower. The comparison of the switching energy losses between the device provided in this embodiment and the traditional device is shown in the following table:

[0085]

[0086] As can be seen from the above table, compared with the traditional device, the turn-on energy loss of the device provided in this embodiment is reduced by 36%, and the turn-off energy loss is reduced by 45%.

[0087] Example 2

[0088] As Figure 8 shown, compared with Example 1, the difference in Example 2 is only that in this example, the gate metal 13 is separated into two parts by the insulating medium 12, that is, split into two split metals. Example 2 can effectively reduce the gate-drain capacitance of the device and further improve the dynamic performance of the device.

[0089] Example 3

[0090] As Figure 9 shown, compared with Example 1, the difference in Example 3 is only that in this example, an A-type buffer layer 18 is inserted between the A-type substrate 2 and the superjunction region 17, further improving the static performance of the device, such as increasing the breakdown voltage and reducing the specific on-resistance, etc.

[0091] Taking Example 1 as an example, the preparation method of the double-channel superjunction silicon carbide MOSFET will be described in detail.

[0092] A preparation method of a double-channel superjunction silicon carbide MOSFET includes the following steps.

[0093] Step 1, grow a part of the A-type epitaxial layer: As Figure 10 shown, grow an A-type epitaxial layer 3 with a set thickness on the A-type substrate 2 by epitaxy.

[0094] Step 2, prepare the superjunction region: As Figure 11 shown, on the A-type epitaxial layer, a superjunction region with alternating A-type columnar bars and B-type columnar bars is formed through multiple epitaxial growths and ion implantations. Among them, for the convenience of subsequent description, the B-type columnar bar on the left is called the first B-type columnar bar, and the B-type columnar bar on the right is called the second B-type columnar bar.

[0095] Step 3, continue to grow the A-type epitaxial layer and form a part of the A-type JFET region: As Figure 12 shown, for the device prepared in Step 2, first etch off a thin layer of SiC, then continue to grow SiC on the surface of the device, then form a specific ion implantation mask layer on the surface, perform ion implantation to form a part of the A-type JFET region, and perform high-temperature annealing, and then remove the mask layer.

[0096] Step 4, prepare the B-type first well region: As Figure 13As shown, specific ion implantation mask layers are formed on both sides of the surface of the device prepared in Step 3. Ion implantation is performed to form a B-type first well region 5, followed by high-temperature annealing, and then the mask layer is removed. For the convenience of subsequent description, the B-type first well region located above the first B-type columnar strip is referred to as the first B-type first well region, and the B-type first well region located above the second B-type columnar strip is referred to as the second B-type first well region. Among them, the width of the first B-type first well region is equal to the width of the first B-type columnar strip, the second B-type first well region is equal to the width of the second B-type columnar strip, and the width of the first B-type first well region is greater than the width of the second B-type first well region.

[0097] Step 5: Fabricate the B-type first ohmic contact region: As Figure 14 shown, specific ion implantation mask layers are formed on the left side of the top surface of the first B-type first well region and the top surface of the second B-type first well region. Then, high-dose ion implantation is performed to form the B-type first ohmic contact region 6, followed by high-temperature annealing and removal of the mask layer.

[0098] Step 6: Fabricate the A-type first source contact region: As Figure 15 shown, a specific ion implantation mask layer is formed at the center of the top surface of the first B-type first well region. High-dose ion implantation is performed to form the A-type first source contact region 7. The A-type first source contact region and the B-type first ohmic contact region are at the same height and their ends are connected. Then, high-temperature annealing is carried out and the mask layer is removed. At this time, the top surface of the first B-type first well region on the right side of the A-type first source contact region forms the first conductive channel.

[0099] Step 7: Fabricate the A-type JFET region: As Figure 16 shown, for the device prepared in Step 6, a thin layer of SiC is first etched away, and then SiC is continuously epitaxially grown on the surface of the device. After that, ion implantation is performed in the epitaxially grown SiC layer above a part of the A-type JFET region prepared in Step 3 to form a complete A-type JFET region 8, and high-temperature annealing is carried out.

[0100] Step 8: Fabricate the B-type second well region: As Figure 17 shown, for the device prepared in Step 7, a thin layer of SiC is first etched away, and then SiC is continuously epitaxially grown. Next, ion implantation is performed on the epitaxially grown SiC layer directly above the A-type JFET region to form the B-type second well region 9, and then high-temperature annealing is carried out.

[0101] Step 9: Fabricate the A-type second source contact region: As Figure 18 shown, a specific ion implantation mask layer is formed on the surface of the device prepared in Step 8. High-dose ion implantation is performed to form the A-type second source contact region 10, and then high-temperature annealing is carried out and the mask layer is removed. Among them, the left side wall of the B-type second well region below the A-type second source contact region forms the second conductive channel.

[0102] Step 10: Prepare the second ohmic contact region of type B: As Figure 19 shown, form a specific ion implantation mask layer on the top surface of the second well region of type B on the right side of the second source contact region of type A, perform high-dose ion implantation to form the second ohmic contact region 11 of type B, then perform high-temperature annealing, and then remove the mask layer.

[0103] Step 11: Prepare the first trench and the second trench: Form a specific etching mask layer on both sides of the second well region of type B, and use the etching mask layer to perform reactive ion etching on the second well region of type B and the left and right sides of the JFET region of type A to form the first trench and the second trench with the same depth as Figure 20 shown, and then remove the etching mask layer.

[0104] Step 12: Deposit Schottky metal: Deposit the Schottky metal 14 preferably by chemical vapor deposition at the bottom of the second trench, as Figure 21 shown.

[0105] Step 13: Deposit the insulating medium for the first time: In the first trench, complete the first deposition of the insulating medium 12 by chemical vapor deposition, and then etch the insulating medium 12 into an L-shaped configuration. The horizontal part of the L-shaped insulating medium contacts the first conductive channel, and the vertical part of the L-shaped insulating medium contacts the second conductive channel. Specifically, as Figure 22 shown.

[0106] Step 14: Deposit the gate metal and the insulating medium: Deposit the gate metal 13 on the L-shaped insulating medium, and then, deposit the insulating medium 12 for the second time to suspend the gate metal in the insulating medium. Specifically, as Figure 23 shown. Among them, the gate metal is located above the first conductive channel and at least partially above the first source contact region of type A.

[0107] Step 15: Deposit the source metal and the drain metal: Deposit the source metal 15 on the outer side of the insulating medium in the first trench, on the top surface of the second well region of type B, and on the top surface of the second trench, and deposit the drain metal 1 on the bottom surface of the type A substrate. Specifically, as Figure 24 shown.

[0108] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A double-channel superjunction silicon carbide MOSFET, characterized in that: It includes an A-type substrate, an A-type epitaxial layer, a B-type second well region, a first trench, a second trench, a drain metal, a gate metal, a source metal, and a Schottky metal; wherein, the A-type is an N-type or P-type conductive semiconductor, the B-type is a P-type or N-type conductive semiconductor, and the conduction types of A and B are different; The drain metal, the A-type substrate, the A-type epitaxial layer, the B-type second well region, and the source metal are arranged in sequence from bottom to top; There is a superjunction region and two B-type first well regions located on both sides of the top of the superjunction region in the A-type epitaxial layer; The thickness of the superjunction region is less than the thickness of the A-type epitaxial layer, and it is specifically selected according to the highest figure of merit achieved by the device; The superjunction region includes A-type columnar bars and two B-type columnar bars located on both sides of the A-type columnar bars; wherein, the two B-type columnar bars are respectively the first B-type columnar bar and the second B-type columnar bar; The two B-type first well regions are respectively arranged on the tops of the two B-type columnar bars; The first trench and the second trench are arranged on both sides of the B-type second well region; wherein, the bottom of the first trench is in contact with the B-type first well region at the top of the first B-type columnar bar and is arranged with the same width as the first B-type columnar bar; the bottom of the second trench is in contact with the B-type first well region at the top of the second B-type columnar bar and is arranged with the same width as the second B-type columnar bar; The Schottky metal is arranged at the bottom of the second trench; The source metal is in an inverted U shape and has a first side leg and a second side leg; wherein, the first side leg extends into the first trench and is in contact with the top of the B-type first well region below, and an insulating medium is filled between the inner side wall of the first side leg and the B-type second well region; the second side leg extends into the second trench and is in contact with the top of the Schottky metal; The gate metal is suspended in the insulating medium, a first conductive channel is formed at the top of the B-type first well region below the gate metal, and a second conductive channel is formed on the side wall of the B-type second well region adjacent to the gate metal; The length L1 of the first conductive channel and the length L2 of the second conductive channel are equal; The first conductive channel can overcome the problem of narrow current path brought by the superjunction region and compensate the saturation current of the device during forward conduction.

2. The double-channel superjunction silicon carbide MOSFET according to claim 1, wherein: A B-type first ohmic contact region and an A-type first source contact region are embedded side by side from outside to inside at the top of the B-type first well region located on the top of the first B-type columnar bar; wherein, the A-type first source contact region is in contact with the first side leg and is partially located directly below the gate metal; the top of the B-type first well region inside the A-type first source contact region is formed as the first conductive channel; A B-type first ohmic contact region is embedded at the top of the B-type first well region located on the top of the second B-type columnar bar; the B-type first ohmic contact region is in contact with the Schottky metal.

3. The double-channel superjunction silicon carbide MOSFET according to claim 2, wherein: An A-type second source contact region and a B-type second ohmic contact region are embedded side by side at the top of the B-type second well region; wherein, the A-type second source contact region is in contact with the source metal at the top and is adjacent to the gate metal; the side wall of the B-type second well region directly below the A-type second source contact region is formed as the second conductive channel.

4. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The thickness of the insulating medium between the gate metal and the first conductive channel is equal to the thickness of the insulating medium between the gate metal and the second conductive channel.

5. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: It further includes an A-type JFET region, and the A-type JFET region is arranged between the A-type epitaxial layer and the B-type second well region and is located between the first trench and the second trench.

6. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The bottom depths of the first trench and the second trench are the same.

7. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: It further includes a type-A buffer layer, which is disposed between the type-A substrate and the superjunction region.

8. The double-channel superjunction silicon carbide MOSFET according to claim 1, characterized in that: The gate metal is a monolithic metal or a split metal.

9. The double-channel superjunction silicon carbide MOSFET according to claim 1, wherein: The source metal further includes a horizontal cross portion connecting the first side leg and the second side leg. A dielectric trench is provided at the bottom of the horizontal cross portion corresponding to the gate metal for filling an insulating dielectric; the top height of the gate metal is higher than the height of the type-B second well region.

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