Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device may include: a first gate structure including stacked first gate lines; first contact plugs extending through the first gate structures and connected to the first gate lines, respectively; a second gate structure including stacked second gate lines; second contact plugs extending through the second gate structures and connected to the second gate lines, respectively; and a slit structure between the first gate structure and the second gate structure and including a lower sidewall having a waveform shape and an upper sidewall having a linear shape.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0139013, filed on October 17, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] In semiconductor technology, the integration level of a semiconductor device refers to how many components or functions can be incorporated into a single integrated circuit (IC) or chip. The integration level is mainly determined by the area occupied by a unit memory cell. Higher integration levels mean more powerful and compact electronic devices. However, recently, further improvements in the integration level of two-dimensional semiconductor devices in which memory cells are formed in a single layer on a substrate have reached their limits. In order to overcome this problem, three-dimensional semiconductor devices in which memory cells are stacked in multiple layers on a substrate have been proposed. In addition, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the invention

[0005] The present invention provides a three-dimensional semiconductor device (hereinafter referred to as a semiconductor device) that exhibits improved structural and electrical stability and performance characteristics.

[0006] In an embodiment of the present disclosure, a semiconductor device may include: a first gate structure including stacked first gate lines; a first contact plug extending through the first gate structure, the first contact plugs being respectively connected to the first gate lines, wherein at least one first contact plug is connected to each of the first gate lines; a second gate structure including stacked second gate lines; a second contact plug extending through the second gate structure, the second contact plug being respectively connected to the second gate lines, wherein at least one second contact plug is connected to each of the second gate lines; and a slit structure located between the first gate structure and the second gate structure, electrically isolating the first gate structure from the second gate structure, the slit structure including a lower sidewall having a wavy shape and an upper sidewall having a straight line shape.

[0007] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a first stack including alternately stacked first material layers and second material layers; forming a hole in the first stack; forming a second stack on the first stack, the second stack including alternately stacked third material layers and fourth material layers; forming a groove extending through the second stack and the first stack and connected to the hole; forming a slit by connecting the holes to each other, the slit including a lower side wall having a wavy shape and an upper side wall having a straight line shape; replacing the first material layer and the third material layer with a fifth material layer through the slit; and forming a slit structure in the slit.

[0008] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a first stack including alternately stacked first material layers and second material layers; forming a hole in the first stack; forming a second stack on the first stack, the second stack including alternately stacked third material layers and fourth material layers; forming an initial trench in the second stack, the bottom surface of the initial trench having a stepped shape; forming contact holes in the second stack, the contact holes exposing the third material layer; extending some of the contact holes into the first stack; forming trenches connected to the holes by extending the initial trenches into the first stack; and forming slits by connecting the holes to each other.

[0009] These and other features and advantages of the present invention will become apparent from the following detailed description of specific embodiments taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 1D is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2A and Figure 2B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A and Fig. 12A , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B and Fig. 12B , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C and Fig. 12C , Figure 5D , Fig.6D , Fig.7D , Fig.8D , Fig.9D , Fig. 10D , Fig.11D and Fig.12D as well as Fig. 7E and Fig. 8E 2 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Various embodiments of the present disclosure are directed to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0014] By stacking memory cells in three dimensions, the integration degree of a semiconductor device can be increased. A semiconductor device having a stable structure and improved reliability can also be provided.

[0015] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0016] Figures 1A to 1D is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 1A It is along Figure 1D A cross-sectional view taken along line AA' of Figure 1B It is along Figure 1D A cross-sectional view taken along line BB' of Figure 1C It is along Figure 1D A cross-sectional view taken along line CC'.

[0017] Reference Figures 1A to 1D The semiconductor device may include a first gate structure GST1, a second gate structure GST2, a first contact plug CT1, a second contact plug CT2, and a slit structure SLS. The semiconductor device may also include at least one of a first channel structure CH1, a second channel structure CH2, a first insulating spacer SP1, and a second insulating spacer SP2.

[0018] The first gate structure GST1 may include stacked first gate lines 11A. The first gate structure GST1 may include alternately stacked first gate lines 11A and first insulating layers 12A. The first gate lines 11A may be word lines, source selection lines, or drain selection lines.

[0019] The first gate structure GST1 may include a cell region CR and a contact region CTR adjacent to each other in a first direction I. The cell region CR may be a region in which memory cells are stacked. Here, a portion of the cell region CR may be an end of a memory block. Dummy memory cells may be stacked in a corresponding region. The contact region CTR may be a region in which an interconnect structure for transmitting a bias for driving the stacked memory cells is formed. The interconnect structure may include a contact plug, wiring, and the like.

[0020] The second gate structure GST2 may include stacked second gate lines 11B. The second gate structure GST2 may include alternately stacked second gate lines 11B and second insulating layers 12B. The second gate line 11B may be a word line, a source selection line, or a drain selection line. The first gate structure GST1 and the second gate structure GST2 may extend in a first direction I. The first gate structure GST1 and the second gate structure GST2 may be adjacent to each other in a second direction II intersecting the first direction I.

[0021] The first channel structure CH1 may extend through the cell region CR of the first gate structure GST1. As an example, the first channel structure CH1 may extend in a third direction III. The third direction III may be perpendicular to a plane defined by the first direction I and the second direction II. The first channel structure CH1 may include at least one of a first channel layer 13A, a first memory layer 14A, and a first insulating core 15A. The first memory layer 14A may include at least one of a tunneling layer, a data memory layer, and a barrier layer. The data memory layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, and the like.

[0022] The second channel structure CH2 may extend through the second gate structure GST2. The second channel structure CH2 may extend in the third direction III. The second channel structure CH2 may include at least one of a second channel layer 13B, a second memory layer 14B, and a second insulating core 15B. The second memory layer 14B may include at least one of a tunneling layer, a data memory layer, and a barrier layer. The data memory layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc.

[0023] The first contact plugs CT1 may extend through the contact regions CTR of the first gate structures GST1 and may be connected to the first gate lines 11A, respectively. The first contact plugs CT1 may extend into the first gate structures GST1 at different depths to be connected to different first gate lines 11A. The first contact plugs CT1 may each include a barrier layer 16 and a gap-filling metal layer 17. The first insulating spacers SP1 may surround sidewalls of the first contact plugs CT1.

[0024] The second contact plugs CT2 may extend through the contact regions CTR of the second gate structures GST2 and may be connected to the second gate lines 11B, respectively. The second contact plugs CT2 may extend into the second gate structures GST2 at different depths. The second contact plugs CT2 may each include a barrier layer 16 and a gap-filling metal layer 17. The second insulating spacers SP2 may surround the sidewalls of the second contact plugs CT2.

[0025] The slit structure SLS may be located between the first gate structure GST1 and the second gate structure GST2. The slit structure SLS may separate the first gate structure GST1 from the second gate structure GST2 and keep them electrically isolated. The slit structure SLS may include at least one of an insulating material, a semiconductor material, and a conductive material. As an example, the slit structure SLS may include a gap-filling insulating layer made of oxide, nitride, etc. As an example, the slit structure SLS may include a gap-filling semiconductor layer made of silicon, germanium, etc. As an example, the slit structure SLS may include a source contact structure including polysilicon, metal, etc.

[0026] According to the above structure, the first and second contact plugs CT1 and CT2 may extend through the first and second gate structures GST1 and GST2, respectively. Therefore, the first and second gate lines 11A and 11B may be connected to the first and second contact plugs CT1 and CT2, respectively, without a step structure.

[0027] In addition, in a plane defined by the first direction I and the second direction II, the slit structure SLS may extend along the first direction I. The first gate structure GST1 and the second gate structure GST2 may be electrically separated from each other by the slit structure SLS.

[0028] Figure 2A and Figure 2B is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. Figure 2A is a plan view of the upper layer LV_U of the gate structure, and Figure 2B is a plan view at a lower layer LV_L of the gate structure. Hereinafter, contents repeated with the previously described contents may be omitted.

[0029] Reference Figure 2A and Figure 2B , the semiconductor device may include at least one of a first gate structure GST1, a second gate structure GST2, a first contact plug CT1, a second contact plug CT2, a slit structure SLS, a first channel structure CH1, a second channel structure CH2, a first insulating spacer SP1, and a second insulating spacer SP2.

[0030] The slit structure SLS may be located between the first gate structure GST1 and the second gate structure GST2 and may electrically isolate the two gate structures. The slit structure SLS may include an upper portion SLS_U and a lower portion SLS_L. The slit structure SLS may have a structure in which the upper portion SLS_U and the lower portion SLS_L are connected to each other.

[0031] The slit structure SLS may include a lower side wall SW_L and an upper side wall SW_U having different shapes. In a plan view, the lower side wall SW_L may have a wavy shape and may extend in a first direction I. As an example, the lower side wall SW_L may have a shape in which convex portions and concave portions are alternately arranged along the first direction. In a plan view, the upper side wall SW_U may have a straight line shape and may extend in the first direction I.

[0032] According to the above structure, the upper portion SLS_U and the lower portion SLS_L of the slit structure SLS may have different shapes. In a plan view, the upper side wall SW_U may extend in a straight line shape, and the lower side wall SW_L may extend in a wave shape.

[0033] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A and Fig. 12A , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B and Fig. 12B , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C and Fig. 12C , Figure 5D , Fig.6D , Fig.7D , Fig.8D , Fig.9D , Fig. 10D , Fig.11D and Fig.12D as well as Fig. 7E and Fig. 8E 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Hereinafter, contents overlapping with previously described contents may be omitted.

[0034] Reference Figure 3A and Figure 3B , a first stack ST1 may be formed. The first stack ST1 may include first material layers 31 and second material layers 32 that are alternately stacked. The first material layers 31 may be used to form gate lines, and the second material layers 32 may be used to insulate the stacked gate lines from each other. As an example, the first material layers 31 may each include a sacrificial material such as nitride or a conductive material such as polysilicon, tungsten, or molybdenum. The second material layers 32 may each include an insulating material such as oxide, nitride, or a void.

[0035] The first stack ST1 may include a cell region CR and a contact region CTR. The cell region CR may be a region where memory cells are to be stacked. The contact region CTR may be a region where an interconnect structure for transmitting a bias voltage for driving the stacked memory cells is to be formed. The interconnect structure may include a contact plug, wiring, etc.

[0036] Subsequently, a hole H may be formed in the first stack ST1. The hole H may be formed in a slit region SLR in which a slit is to be formed. The slit region SLR may be located in the cell region CR and may extend to the contact region CTR. The slit region SLR may extend along a first direction I. The hole H may extend through the first stack ST1 and may extend in a third direction III. In a plan view, the holes H may each have a circular shape, an elliptical shape, a polygonal shape, etc.

[0037] The first sub-channel hole SCH1 may be formed in the first stack ST1. The first sub-channel hole SCH1 may be formed in the cell region CR. When the hole H is formed, the first sub-channel hole SCH1 may also be formed simultaneously. The hole H may have a size larger than that of the first sub-channel hole SCH1 or a size substantially the same as that of the first sub-channel hole SCH1.

[0038] Subsequently, a first sacrificial layer 33 may be formed in the hole H and the first sub-channel hole SCH1 . The first sacrificial layers 33 may each include a material having a high etching selectivity with respect to the first material layer 31 and the second material layer 32 .

[0039] Reference Figure 4A and Figure 4B, a second stack ST2 may be formed. The second stack ST2 may be formed to overlap the first stack ST1. The second stack ST2 may include third material layers 35 and fourth material layers 36 that are alternately stacked. The third material layers 35 may be used to form gate lines, and the fourth material layers 36 may be used to insulate the stacked gate lines from each other. As an example, the third material layers 35 may each include a sacrificial material such as a nitride or a conductive material such as polysilicon, tungsten, or molybdenum. The fourth material layers 36 may each include an insulating material such as an oxide, a nitride, or a void.

[0040] Subsequently, second sub-channel holes SCH2 may be formed in the second stack ST2. The second sub-channel holes SCH2 may be connected to the corresponding first sub-channel holes SCH1, respectively. The second sub-channel holes SCH2 may not be formed in the slit region SLR.

[0041] Subsequently, a second sacrificial layer 37 may be formed in the second sub-channel hole SCH2 . The second sacrificial layers 37 may each include a material having a high etching selectivity with respect to the third material layer 35 and the fourth material layer 36 .

[0042] Reference FIG. 5A to FIG. 5D , a channel structure CH may be formed. First, the first sub-channel hole SCH1 and the second sub-channel hole SCH2 may be reopened by removing the second sacrificial layer 37 and the first sacrificial layer 33. Subsequently, a channel structure CH may be formed in the reopened first sub-channel hole SCH1 and the second sub-channel hole SCH2. The channel structure CH may include at least one of a channel layer 63, a memory layer 64, and an insulating core 65. Subsequently, a fourth material layer 36 may be additionally formed on the second stack ST2.

[0043] Subsequently, a hard mask pattern 41 may be formed on the second stack ST2. As an example, the hard mask pattern 41 may be formed by forming a hard mask layer and then etching the hard mask layer using a photoresist pattern as an etching barrier. The hard mask pattern 41 may cover the channel structure CH and may include an opening exposing a region where a contact plug is to be formed and a slit region SLR. The hard mask pattern 41 may include polysilicon.

[0044] Subsequently, the second stack ST2 may be etched using the hard mask pattern 41 as an etching barrier. Thus, an initial trench PT may be formed in the slit region SLR. The initial trench PT may have a bottom surface BT0 exposing the uppermost third material layer 35. An initial contact hole PCTH may be formed in a region where a contact plug is to be formed. When the initial trench PT is formed, the initial contact hole PCTH may be formed simultaneously. The initial contact hole PCTH and the initial trench PT may both have a depth sufficient to expose the uppermost third material layer 35.

[0045] Reference FIG. 6A to FIG. 6D , a sacrificial layer SC may be formed on the hard mask pattern 41. The sacrificial layer SC may be formed to at least partially fill the initial contact hole PCTH and the initial trench PT. The sacrificial layer SC may include a material having a high etching selectivity relative to the hard mask pattern 41. As an example, the sacrificial layer SC may include amorphous silicon. When the sacrificial layer SC is formed, a void V may be formed in the initial contact hole PCTH and the initial trench PT.

[0046] Subsequently, a first mask pattern 42 may be formed on the sacrificial layer SC. The first mask pattern 42 may include openings that expose some of the initial contact holes PCTH. The first mask pattern 42 may also expose a portion of the initial trench PT. A portion of the initial trench PT located between the exposed initial contact holes PCTH may be exposed.

[0047] Subsequently, the sacrificial layer SC and the second stack ST2 may be etched using the first mask pattern 42 and the hard mask pattern 41 as an etching barrier. Thus, the exposed preliminary contact hole PCTH may be extended into the second stack ST2 to form a second contact hole CTH2 exposing the third material layer 35. The exposed portion of the preliminary trench PT may be extended into the second stack ST2, and a bottom surface having a step shape may be formed.

[0048] Reference 7A to 7E , the opening of the first mask pattern 42 can be enlarged. As an example, the first mask pattern 42 can be reduced by an etching process to enlarge the opening. Thus, the number of exposed initial contact holes PCTH can be increased, and the exposed portion of the initial trench PT can be increased, such as Figure 7B shown.

[0049] Subsequently, the second stack ST2 may be etched using the first mask pattern 42 and the hard mask pattern 41 as an etching barrier. Thus, a second contact hole CTH2 exposing the third material layer 35 may be formed by extending the initial contact hole PCTH into the second stack ST2. In addition, the previously formed second contact hole CTH2 may be further extended into the second stack ST2. The newly exposed portion of the initial trench may be etched, and the bottom surface having a step shape may be extended into the second stack ST2.

[0050] Subsequently, the shrinking and etching process of the first mask pattern 42 may be repeated. The second contact hole CTH2 formed earlier may be etched more times and at a deeper depth than the second contact hole CTH2 formed later. Thus, the second contact hole CTH2 may be formed to extend at various depths and expose different third material layers 35, respectively. Similarly, the earlier exposed portion of the initial trench PT may be etched more times and at a deeper depth than the later exposed portion of the initial trench PT. Thus, the initial trench PT may extend at various depths according to the location, and an initial trench PT having a stepped shape (also referred to as a step or step shape) on the bottom surface may be formed. The second contact hole CTH2 may be formed when the initial trench PT is formed. Subsequently, the first mask pattern 42 and the sacrificial layer SC may be removed.

[0051] The initial trench PT may include a bottom surface having a stepped shape in a portion thereof. As an example, a portion of the initial trench PT located between the channel structures CH may maintain the depth of the initially formed bottom surface BT0 and may not include a bottom surface having a stepped shape. When forming the second contact hole CTH2, a portion of the initial trench PT located between the second contact holes CTH2 may be etched together with the second contact hole CTH2. Therefore, each portion of the initial trench PT may have the same depth as the depth of the second contact hole CTH2 adjacent in the second direction II. The third bottom surface BT3 located between the second contact holes CTH23 having a relatively deep depth may be located at a lower height than the second bottom surface BT2 located between the second contact holes CTH22. The first bottom surface BT1 located between the second contact holes CTH21 having a relatively shallow depth may be located at a higher height than the second bottom surface BT2.

[0052] Reference FIG. 8A to FIG. 8E , a second mask pattern 43 may be formed on the hard mask pattern 41. The second mask pattern 43 may cover the channel structure CH and may expose the slit region SLR. The second mask pattern 43 may expose only some of the second contact holes CTH2 and cover the remaining second contact holes CTH2.

[0053] Subsequently, the second stack ST2 and the first stack ST1 may be etched using the hard mask pattern 41 and the second mask pattern 43 as etching barriers. Thus, the exposed second contact hole CTH2 may be extended into the first stack ST1, and the first contact holes CTH1 respectively exposing the first material layer 31 may be formed. Thus, the preliminary trench PT may be extended into the first stack ST1, and the trench T connected to the hole H may be formed. The first contact hole CTH1 may be formed when the trench T is formed.

[0054] As an example, the first stack ST1 may include n first material layers 31, and the second stack ST2 may include n third material layers 35. In this case, 2n second contacts may be formed by repeatedly performing the etching process using the first mask pattern 42. In addition, by etching the n first material layers 31 and the third material layers 35 using the second mask pattern 43, n second contact holes CTH2 of the 2n second contact holes CTH2 may be extended into the first stack ST1, and n first contact holes CTH1 may be formed.

[0055] The initial trench PT may be formed when forming the 2n second contact holes CTH2, and the trench T may be formed when forming the n first contact holes CTH1. By etching the n first material layers 31 and the third material layers 35 using the second mask pattern 43, the initial trench PT may be extended into the first stack ST1, and the trench T connected to the hole H may be formed. The bottom surface of the trench T may have a stepped shape in which the bottom surface of the initial trench PT is transferred. The bottom surfaces BT0 to BT3 of the initial trench PT may be transferred into the first stack ST1 to form the bottom surfaces BT0' to BT3' of the trench T.

[0056] Reference 9A to 9D , the first sacrificial layer 33 in the hole H may be removed through the trench T. The second mask pattern 43 and the hard mask pattern 41 may be removed.

[0057] Subsequently, a first liner 44 may be formed in the first contact hole CTH1, the second contact hole CTH2, the hole H, and the trench T. The first liner 44 may be formed along the contours of the first contact hole CTH1, the second contact hole CTH2, the hole H, and the trench T. The first liner 44 may include a material having a high etching selectivity with respect to the first material layer 31 and the third material layer 35. As an example, the first liner 44 may include an oxide.

[0058] Subsequently, a sacrificial layer 45 may be formed in the first contact hole CTH1, the second contact hole CTH2, the hole H, and the trench T. Subsequently, a second liner 46 may be formed on the sacrificial layer 45. The sacrificial layer 45 may include a material having a high etching selectivity with respect to the first liner 44 and the second liner 46. As an example, the sacrificial layer 45 may include polysilicon, and the first liner 44 and the second liner 46 may each include oxide.

[0059] Subsequently, a third mask pattern 47 exposing the slit region SLR may be formed The third mask pattern 47 may cover the channel structure CH, the first contact hole CTH1, and the second contact hole CTH2, and may expose the trench T.

[0060] Subsequently, the second liner layer 46 may be etched using the third mask pattern 47 as an etch barrier. Thus, the sacrificial layer 45 and the first liner layer 44 formed in the trench T may be exposed.

[0061] Reference FIG. 10A to FIG. 10D , the sacrificial layer 45 and the first liner 44 exposed by the third mask pattern 47 may be removed. As an example, the sacrificial layer 45 and the first liner 44 in the trench T and the hole H may be selectively etched using a dry cleaning process. Thus, the trench T and the hole H may be reopened.

[0062] Subsequently, the slit SL may be formed by connecting the holes H to each other. The second material layer 32 and the fourth material layer 36 exposed by the trench T and the hole H may be selectively etched so that the holes H are connected to each other. Thus, the hole H may be expanded, and adjacent holes H may be connected to each other. The holes H may be connected to each other in a wavy shape. The holes H may be connected to each other to form a lower portion of the slit SL, and the lower sidewall of the slit SL may have a wavy shape in a plan view. The trench T may be expanded to form an upper portion of the slit SL, and the upper sidewall of the slit SL may have a straight line shape in a plan view.

[0063] Reference FIG. 11A to FIG. 11D , the first material layer 31 and the third material layer 35 may be replaced with the fifth material layer 51 through the slit SL. As an example, the first material layer 31 and the third material layer 35 may be removed through the slit SL. Subsequently, the fifth material layer 51 may be formed in the region where the first material layer 31 and the third material layer 35 are removed. Before forming the fifth material layer 51, a barrier layer may be additionally formed. Here, the fifth material layer 51 may be a gate line, and may both include a metal such as tungsten or molybdenum. Thus, a gate structure GST including the stacked fifth material layer 51 may be formed. For reference, when the first material layer 31 and the third material layer 35 both include a conductive material, the replacement process may be omitted. In this case, the first material layer 31 and the third material layer 35 may be gate lines, and the first stack ST1 and the second stack ST2 may be the gate structure GST.

[0064] Subsequently, a slit structure 52 may be formed in the slit SL. The slit structure 52 may include at least one of an insulating material, a semiconductor material, and a conductive material. As an example, the slit structure 52 may include a gap-filling insulating layer made of oxide, nitride, etc. The slit structure 52 may include a gap-filling semiconductor layer made of silicon, germanium, etc. The slit structure 52 may include a source contact structure having conductivity and an insulating spacer surrounding the sidewall of the source contact structure.

[0065] Reference FIG. 12A to FIG. 12D, the sacrificial layer 45 may be removed. Subsequently, an insulating spacer 44A may be formed by etching the first liner 44. Subsequently, a contact plug CT may be formed in the first contact hole CTH1 and the second contact hole CTH2. As an example, a barrier layer 56 may be formed in the first contact hole CTH1 and the second contact hole CTH2, and a gap-filling metal layer 57 may be formed in the barrier layer 56. Thus, contact plugs CT extending through the gate structure GST and respectively connected to the fifth material layer 51 may be formed.

[0066] According to the above-described manufacturing method, the hole H may be formed when the first sub-channel hole SCH1 is formed. The trench T may be formed when the second contact hole CTH2 and the first contact hole CTH1 are formed. Therefore, the slit SL may be formed using the sub-channel hole forming process and the contact hole forming process.

[0067] Although the embodiments according to the technical concept of the present disclosure have been described above with reference to the accompanying drawings, this is only used to describe the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical concept of the present disclosure defined in the attached claims, various types of replacements, modifications and changes to the embodiments can be made by a technician in the technical field to which the present disclosure belongs, and it should be interpreted that these replacements, modifications and changes belong to the scope of the present disclosure. In addition, the embodiments can be combined to form another embodiment.

Claims

1. A semiconductor device, comprising: a first gate structure, the first gate structure comprising stacked first gate lines; first contact plugs, the first contact plugs extending through the first gate structure, the first contact plugs being respectively connected to the first gate lines, wherein at least one first contact plug is connected to each of the first gate lines; a second gate structure, the second gate structure comprising stacked second gate lines; second contact plugs extending through the second gate structure, the second contact plugs being respectively connected to the second gate lines, wherein at least one second contact plug is connected to each of the second gate lines; and A slit structure is located between the first gate structure and the second gate structure and electrically isolates the first gate structure from the second gate structure, wherein the slit structure includes a lower sidewall having a corrugated shape and an upper sidewall having a straight line shape.

2. The semiconductor device according to claim 1, wherein The slit structure extends in a first direction, and The first gate structure and the second gate structure are adjacent to each other in a second direction intersecting the first direction.

3. The semiconductor device according to claim 2, wherein: The lower side wall has a shape in which concave portions and convex portions are alternately arranged along the first direction.

4. The semiconductor device according to claim 1, wherein The first contact plugs extend into the first gate structure at different depths.

5. The semiconductor device according to claim 1, wherein The second contact plugs extend into the second gate structure at different depths.

6. The semiconductor device according to claim 1, further comprising: first insulating spacers, the first insulating spacers respectively surrounding side walls of the first contact plugs; as well as Second insulating spacers respectively surround sidewalls of the second contact plugs.

7. The semiconductor device according to claim 1, further comprising: a first channel structure extending through the first gate structure; as well as A second channel structure extends through the second gate structure.

8. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first stack including alternating stacks of first material layers and second material layers; forming a hole in the first stack; forming a second stack on the first stack, wherein the second stack includes alternately stacked third material layers and fourth material layers; forming a groove extending through the second stack and the first stack and connected to the hole; forming a slit by connecting the holes to each other, the slit including a lower side wall having a wave shape and an upper side wall having a straight shape; replacing the first material layer and the third material layer with a fifth material layer through the slit; as well as A slit structure is formed in the slit.

9. The manufacturing method according to claim 8, wherein: A first sub-channel hole is formed in the first stack when the hole is formed.

10. The manufacturing method according to claim 9, further comprising the following steps: A second sub-channel hole is formed in the second stack, the second sub-channel hole being connected to the first sub-channel hole.

11. The manufacturing method according to claim 8, wherein: The step of forming the groove comprises the following steps: forming a preliminary groove in the second stack, the bottom surface of the preliminary groove having a stepped shape; and The trench is formed by extending the initial trench into the first stack.

12. The manufacturing method according to claim 11, wherein: A second contact hole exposing the third material layer is formed in the second stack when the initial trench is formed.

13. The manufacturing method according to claim 12, wherein: First contact holes exposing the first material layer are formed by extending some of the second contact holes into the first stack when forming the trench.

14. The manufacturing method according to claim 13, further comprising the following steps: Contact plugs are formed in the first contact hole and the second contact hole.

15. The manufacturing method according to claim 8, wherein: In the step of forming the slits, the second material layer and the fourth material layer exposed through the holes and the trenches are etched so that the holes are connected to each other.

16. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a first stack including alternating stacks of first material layers and second material layers; forming a hole in the first stack; forming a second stack on the first stack, wherein the second stack includes alternately stacked third material layers and fourth material layers; forming a preliminary groove in the second stack, the bottom surface of the preliminary groove having a stepped shape; forming a contact hole in the second stack, the contact hole exposing the third material layer; extending some of the contact holes into the first stack; forming a groove connected to the hole by extending the initial groove into the first stack; as well as A slit is formed by connecting the holes to each other.

17. The manufacturing method according to claim 16, wherein: The initial trench is extended into the first stack while some of the contact holes are extended into the first stack.

18. The manufacturing method according to claim 16, further comprising the following steps: replacing the first material layer and the third material layer with a fifth material layer through the slit; as well as A slit structure is formed in the slit.

19. The manufacturing method according to claim 16, wherein: The preliminary trench exposes the third material layer through the bottom surface having the step shape.

20. The manufacturing method according to claim 16, wherein: In the step of extending some of the contact holes into the first stack, the contact holes are extended to have different depths.

21. The manufacturing method according to claim 16, wherein: The slit includes a lower side wall having a wave shape and an upper side wall having a straight line shape.

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