Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface on an opposite side to the first main surface; an insulated gate bipolar transistor region; a fast recovery diode region; the insulating layer is provided with a first contact hole and a second contact hole which are respectively positioned in the fast recovery diode region and the insulated gate bipolar transistor region; a first semiconductor region located in the fast recovery diode region; the first titanium film is arranged in the first contact hole; the second semiconductor region is located in an insulated gate bipolar transistor region; the second titanium film is arranged in the second contact hole; the depth of the first semiconductor region in the first direction from the first main surface to the semiconductor substrate is A, the depth of the second semiconductor region in the first direction from the first main surface to the semiconductor substrate is B, and A and B satisfy the relational expression: A < = 0.45 B. According to the technical scheme, the reverse recovery performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] For a trench gate reverse conducting insulated gate bipolar transistor (RC-IGBT), in order to avoid poor electrical contact in the contact hole area, a titanium metal layer is usually formed between the tungsten layer and the semiconductor part in the contact hole area. When the contact with the semiconductor part (P-type base region) is formed through the titanium layer, there is a problem of deterioration of the contact with the P-type base region, which leads to deterioration of the forward conduction characteristics of the device. To solve this problem, a P+ layer is usually formed in the contact area.

[0003] In the related art, for the insulated gate bipolar transistor (IGBT) region in the trench gate reverse conducting insulated gate bipolar transistor, the P+ layer can effectively extract holes to prevent the insulated gate bipolar transistor from latching up. However, for the fast recovery diode (FRD) region, the formation of the P+ layer will lead to enhanced hole injection efficiency, resulting in an increase in the peak current during reverse recovery, which will deteriorate the reverse recovery performance.

[0004] Therefore, improvements are needed to at least partially solve the above problems. Summary of the invention

[0005] The present invention aims to at least partially solve the above problems. To this end, one object of the present invention is to provide a semiconductor device that can improve reverse recovery performance without affecting forward conduction. Another object of the present invention is to provide a method for manufacturing the semiconductor device.

[0006] The semiconductor device has a semiconductor substrate, wherein the semiconductor substrate has a drift layer of a first conductivity type between a first main surface and a second main surface, wherein the first main surface and the second main surface are arranged opposite to each other in a first direction, and the semiconductor device includes:

[0007] an insulated gate bipolar transistor region, comprising a trench gate penetrating an emitter layer of a first conductivity type and a base layer of a second conductivity type from the first main surface of the semiconductor substrate to reach the drift layer, and a collector layer of the second conductivity type disposed on the second main surface side relative to the drift layer, wherein the trench gates are multiple, the multiple trench gates are spaced apart in a second direction, the length of the trench gates is extended in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other;

[0008] a fast recovery diode region having an anode layer of the second conductivity type disposed on the first main surface side relative to the drift layer, and a cathode layer of the first conductivity type disposed on the second main surface side relative to the drift layer;

[0009] an insulating layer, which is disposed on the first main surface, the insulating layer is provided with a first contact hole and a second contact hole, the second contact hole is located in the insulated gate bipolar transistor region, and the first contact hole is located in the fast recovery diode region;

[0010] The fast recovery diode region further includes a first semiconductor region of a second conductivity type and a first titanium film;

[0011] A first semiconductor region of a second conductivity type is selectively disposed on the first main surface side of the anode layer, and has a higher impurity concentration of the second conductivity type than the anode layer, wherein a side of the first semiconductor region facing the first main surface constitutes at least a portion of the first main surface, and the first contact hole penetrates the insulating layer and exposes the first semiconductor region;

[0012] A first titanium film is disposed in the first contact hole and contacts the first semiconductor region, and the first semiconductor region is electrically connected to the emitter metal through the first contact hole;

[0013] The insulated gate bipolar transistor region further includes a second semiconductor region of a second conductivity type and a second titanium film;

[0014] The second semiconductor region is selectively disposed on the first main surface side of the base layer, and has a higher impurity concentration of the second conductivity type than the base layer; the emitter layer is selectively disposed on the first main surface side of the base layer; the second semiconductor region and the emitter layer on one side facing the first main surface both constitute at least a portion of the first main surface; the second contact hole penetrates the insulating layer and exposes the second semiconductor region and the emitter layer;

[0015] The second titanium film is disposed in the second contact hole and contacts the second semiconductor region, and the second semiconductor region and the emitter layer are both electrically connected to the emitter metal through the second contact hole;

[0016] The depth of the first semiconductor region from the first main surface to the semiconductor substrate in the first direction is set to A, and the depth of the second semiconductor region from the first main surface to the semiconductor substrate in the first direction is set to B, and A and B satisfy the relationship: A≤0.45B.

[0017] The above technical solution has the following advantages and beneficial effects: for the insulated gate bipolar transistor region, the relatively deep second semiconductor region can have a good effect of reducing the contact resistance, and can effectively extract holes to prevent the semiconductor device from having a latch-up effect; for the fast recovery diode region, the relatively shallow first semiconductor region can, on the one hand, achieve the effect of reducing the contact resistance, and on the other hand, can effectively reduce the hole injection efficiency of the fast recovery diode region, thereby reducing the peak current of reverse recovery and improving the reverse recovery performance of the semiconductor device. By setting the depth of the first semiconductor region and the second semiconductor region in the first direction within the above range, a good balance can be achieved in reducing the contact resistance and reducing the hole injection efficiency.

[0018] In some embodiments, the first titanium film on one side of the first semiconductor region in the first direction in the first contact hole contacts the first semiconductor region to form a first titanium silicide layer, the first titanium silicide layer extends from the first main surface into the semiconductor substrate along the first direction, and the depth of the first titanium silicide layer from the first main surface to the semiconductor substrate in the first direction is set to C, and C, A and B satisfy the relationship: A≤C≤0.5B;

[0019] The second titanium film on the side of the second semiconductor region adjacent to the first direction in the second contact hole contacts the second semiconductor region to form a second titanium silicide layer. The second titanium silicide layer extends along the first direction from the first main surface into the semiconductor substrate. The depth of the second titanium silicide layer from the first main surface to the semiconductor substrate in the first direction is set to D, and D and B satisfy the relationship: D≤B.

[0020] The above technical solution has the following advantages and beneficial effects: when C≥A, since the first semiconductor region is consumed by the generated first titanium silicide layer, on the one hand, the effect of reducing the contact resistance can be achieved, and on the other hand, the hole injection in the fast recovery diode region can be reduced, the reverse recovery peak current can be reduced, and the reverse recovery performance can be improved; when C≤0.5B, the difference between the first titanium silicide layer and the first semiconductor region is not too large, which avoids the increase in the contact resistance of the first titanium silicide layer caused by the first semiconductor region being far from being consumed by the first titanium silicide layer, reduces the contact resistance of the first titanium film, suppresses the increase in the voltage drop when the diode is forward-conducted, and improves the deterioration of the forward conduction characteristics of the fast recovery diode. By setting the depth of the first titanium silicide layer in the first direction within the above range, a good balance can be achieved in reducing the contact resistance and reducing the hole injection efficiency.

[0021] In some embodiments, the region where the first semiconductor region (7) is located is completely located in the region where the first titanium silicide layer (8012) is located.

[0022] In some embodiments, the first titanium film on one side of the first semiconductor region in the first direction in the first contact hole contacts the first semiconductor region to form a first titanium silicide layer, the first titanium silicide layer extends from the first main surface into the semiconductor substrate along the first direction, and the depth of the first titanium silicide layer from the first main surface to the semiconductor substrate in the first direction is set to C, and C and A satisfy the relationship: C<A;

[0023] The second titanium film on the side of the second semiconductor region adjacent to the first direction in the second contact hole contacts the second semiconductor region to form a second titanium silicide layer. The second titanium silicide layer extends along the first direction from the first main surface into the semiconductor substrate. The depth of the second titanium silicide layer from the first main surface to the semiconductor substrate in the first direction is set to D, and D and B satisfy the relationship: D≤B.

[0024] The above technical solution has the following advantages and beneficial effects: when C < A, the first semiconductor region is still left after being consumed by the first titanium silicide layer, thereby reducing the contact resistance of the first titanium film, reducing the forward conduction voltage drop, and reducing the conduction loss. At the same time, the first titanium silicide layer consumes part of the first semiconductor region, so that the hole injection in the fast recovery diode region is reduced, the reverse recovery peak current is reduced, and the reverse recovery performance is improved. By setting the depth of the first titanium silicide layer in the first direction within the above range, a good balance can be achieved in reducing the contact resistance and reducing the hole injection efficiency.

[0025] In some embodiments, the region where the first titanium silicide layer (8012) is located is completely located in the region where the first semiconductor region (7) is located.

[0026] In some embodiments, C and D satisfy the relationship: C=D.

[0027] The above technical solution has the following advantages and beneficial effects: by setting the depth C of the first titanium silicide layer in the first direction and the depth D of the second titanium silicide layer in the first direction to be equal, they can be formed in the same process, thereby effectively simplifying the manufacturing process, reducing production costs, and shortening the production cycle.

[0028] In some embodiments, the doping impurity injection energy of the first semiconductor region is less than the doping impurity injection energy of the second semiconductor region, the doping impurity injection energy of the first semiconductor region is Q, and Q satisfies the relationship: 10KeV≤Q≤40KeV; and / or,

[0029] The impurity doping concentration of the first semiconductor region is less than or equal to the impurity doping concentration of the second semiconductor region; and / or,

[0030] The doping impurity implantation dosage of the first semiconductor region is D, and D satisfies the relationship: 2E14≤D≤8E14.

[0031] In some embodiments, the insulated gate bipolar transistor region includes a first region and a second region, the first region and the second region are both multiple, the emitter layer and the second semiconductor region are both multiple, the multiple emitter layers are arranged one-to-one in the base layers of the multiple first regions, the multiple second semiconductor regions are arranged one-to-one in the base layers of the multiple second regions, and the multiple first regions and the multiple second regions are alternately arranged in sequence in a third direction.

[0032] In some embodiments, the insulated gate bipolar transistor region includes a first region and a second region, the first region and the second region are both multiple, the emitter layer and the second semiconductor region are both multiple, the multiple emitter layers are arranged one-to-one in the base layers of the multiple first regions, the multiple second semiconductor regions are arranged one-to-one in the base layers of the multiple second regions, and the multiple first regions and the multiple second regions are alternately arranged in sequence in the second direction.

[0033] The manufacturing method is applicable to the semiconductor device as described above, and the manufacturing method comprises the following steps:

[0034] A semiconductor substrate is provided, wherein the semiconductor substrate has a first main surface and a second main surface opposite to the first main surface, and the first main surface and the second main surface are spaced apart in a first direction;

[0035] forming a plurality of trench gates extending from the first main surface of the semiconductor substrate toward the second main surface, wherein the plurality of trench gates are arranged at intervals in a second direction, wherein the first direction and the second direction are perpendicular to each other;

[0036] forming a base layer, an anode layer and an emitter layer on a side of the semiconductor substrate facing the first main surface, wherein the base layer is located in the insulated gate bipolar transistor region, and the anode layer is located in the fast recovery diode region;

[0037] Depositing an insulating layer on the first main surface, and etching a first contact hole and a second contact hole on the insulating layer, wherein the first contact hole and the second contact hole both penetrate the insulating layer, the first contact hole is located in the fast recovery diode region, and the second contact hole is located in the insulated gate bipolar transistor region;

[0038] First, doping impurities of the second conductivity type are injected into the anode layer exposed by the first contact hole to form a first semiconductor region of the second conductivity type, and then doping impurities of the second conductivity type are injected into the base layer exposed by the second contact hole to form a second semiconductor region of the second conductivity type, wherein the depth of the second semiconductor region in the first direction is greater than the depth of the first semiconductor region in the first direction; or

[0039] Simultaneously, doping impurities of the second conductivity type are injected into the anode layer exposed by the first contact hole and the base layer exposed by the second contact hole to form a first semiconductor region of the second conductivity type in the anode layer, and a sub-semiconductor region of the second conductivity type having the same depth as the first semiconductor region is formed in the base layer, and doping impurities of the second conductivity type are injected into a portion of the base layer corresponding to the sub-semiconductor region to form a second semiconductor region, wherein the depth of the second semiconductor region is greater than that of the first semiconductor region;

[0040] A first titanium film and a second titanium film are formed in the first contact hole and the second contact hole, respectively, wherein the first titanium film is in contact with the first semiconductor region, and the second titanium film is in contact with the second semiconductor region.

[0041] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The following drawings of the present application are hereby used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the device and principle of the present application. In the drawings,

[0043] Figure 1is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0044] Figure 2 for Figure 1 Schematic diagram of area A in the middle;

[0045] Figure 3 for Figure 2 Schematic diagram of the cross section along the BB direction;

[0046] Figure 4 for Figure 2 Schematic diagram of the cross section in the CC direction;

[0047] Figure 5 for Figure 4 Schematic diagram of the D region in the middle;

[0048] Figure 6 is a schematic cross-sectional view in the CC direction according to some other embodiments of the present invention;

[0049] Figure 7 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0050] Figure 8-Figure 17 2 is a schematic cross-sectional view of various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0051] Description of reference numerals:

[0052] 100, semiconductor device; 1001, insulated gate bipolar transistor region; 10011, first region; 10012, second region; 1002, transition region; 1003, fast recovery diode region;

[0053] 1. semiconductor substrate; 101. first main surface; 102. second main surface;

[0054] 2. drift layer; 3. carrier storage layer; 4. base layer; 5. gate trench; 6. trench gate; 7. first semiconductor region;

[0055] 8. Insulating layer; 801. First contact hole; 8011. First titanium film; 8012. First titanium silicide layer; 802. Second contact hole; 8021. Second titanium film; 8022. Second titanium silicide layer;

[0056] 9. Second semiconductor region; 10. Emitter layer; 11. Field stop layer; 12. Collector layer; 13. Collector metal layer; 14. Cathode layer; 15. Anode layer; 16. Tungsten layer; 17. Emitter metal layer; 18. Virtual gate trench; 19. Virtual gate. DETAILED DESCRIPTION

[0057] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0058] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0059] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0060] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views as schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to display the actual shape of the device and are not intended to limit the scope of the present application.

[0063] Reference below Figure 1-Figure 5 The semiconductor device 100 according to the embodiment of the present invention is exemplarily described. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description. Similarly, the first conductivity type can also be set to P type and the second conductivity type can be set to N type.

[0064] The semiconductor device 100 includes a semiconductor substrate 1. The semiconductor substrate 1 has a first main surface 101 and a second main surface 102, and the first main surface 101 and the second main surface 102 are arranged opposite to each other in a first direction. The semiconductor substrate 1 has a drift layer 2 of a first conductivity type between the first main surface 101 and the second main surface 102. The drift layer 2 usually has a lower doping concentration, so its resistance is higher and it can withstand a higher voltage.

[0065] Furthermore, the semiconductor device 100 includes an insulated gate bipolar transistor region 1001 , a fast recovery diode region 1003 and an insulating layer 8 .

[0066] The insulated gate bipolar transistor region 1001 has a trench gate 6 that penetrates the emitter layer 10 of the first conductivity type and the base layer 4 of the second conductivity type from the first main surface 101 of the semiconductor substrate 1 to reach the drift layer 2, and the collector layer 12 of the second conductivity type is arranged on the second main surface 102 side compared with the drift layer 2. Among them, the base layer 4 of the second conductivity type is located on the side of the drift layer 2 away from the second main surface 102, and the side of the base layer 4 away from the second main surface 102 can constitute a part of the first main surface 101. The emitter layer 10 of the first conductivity type is located on the side of the base layer 4 away from the second main surface 102, and the emitter layer 10 is located on the side of the base layer 4 away from the second main surface 102 and can constitute a part of the first main surface 101. The doping concentration of the emitter layer 10 of the first conductivity type can be higher than the doping concentration of the drift layer 2. Exemplarily, the semiconductor device 100 is formed with a gate trench 5 extending from the first main surface 101 to the second main surface 102, penetrating the emitter layer 10 and the base layer 4 to reach the drift layer 2, and a gate trench electrode is arranged in the gate trench 5 through a gate trench insulating film, thereby forming a trench gate 6. The gate trench electrode faces the drift layer 2 through the gate trench insulating film. The gate trench insulating film of the trench gate 6 is in contact with the base layer 4 and the emitter layer 10. If a gate driving voltage is applied to the gate trench electrode, a channel is formed in the base layer 4 in contact with the gate trench insulating film of the trench gate 6. There are multiple trench gates 6, and the multiple trench gates 6 are arranged at intervals in the second direction, and the length of the trench gate 6 is extended in the third direction. Exemplarily, the materials of the gate trench insulating film and the gate trench electrode can be silicon dioxide and polysilicon, respectively. The first direction, the second direction and the third direction are perpendicular to each other.

[0067] The fast recovery diode region 1003 has an anode layer 15 of the second conductivity type disposed on the first main surface 101 side compared to the drift layer 2, and a cathode layer 14 of the first conductivity type disposed on the second main surface 102 side compared to the drift layer 2. The anode layer 15 on the side away from the second main surface 102 constitutes part of the first main surface 101, and the doping concentration of the anode layer 15 may be the same or substantially the same as that of the base layer 4. The cathode layer 14 on the side away from the first main surface 101 constitutes part of the second main surface 102, and the doping concentration of the cathode layer 14 is greater than the doping concentration of the drift region.

[0068] Exemplarily, the fast recovery diode region 1003 further has a virtual gate 19 that penetrates the anode layer 15 of the second conductivity type from the first main surface 101 of the semiconductor substrate 1 to reach the drift layer 2. Exemplarily, the semiconductor device 100 is formed with a virtual gate trench 18 extending from the first main surface 101 to the second main surface 102, penetrating the anode layer 15 to reach the drift layer 2, and a virtual gate trench electrode is arranged in the virtual gate trench 18 through a virtual gate trench insulating film, thereby forming a virtual gate 19. The virtual gate trench electrode faces the drift layer 2 through the virtual gate trench insulating film. The virtual gate trench insulating film of the virtual trench gate 6 is in contact with the anode layer 15. There are multiple virtual gates 19, and the multiple virtual gates 19 are arranged at intervals in the second direction. Exemplarily, the materials of the virtual gate trench insulating film and the virtual gate trench electrode can be silicon dioxide and polysilicon, respectively.

[0069] The insulating layer 8 is disposed on the first main surface 101. The insulating layer 8 is provided with a first contact hole 801 and a second contact hole 802. The second contact hole 802 is located in the insulated gate bipolar transistor region 1001, and the first contact hole 801 is located in the fast recovery diode region 1003. The first contact hole 801 and the second contact hole 802 both penetrate the insulating layer.

[0070] For further information, see Appendix Figure 4 , 5 The fast recovery diode region 1003 further includes a first semiconductor region 7 of the second conductivity type and a first titanium film 8011 , and the insulated gate bipolar transistor region 1001 further includes a second semiconductor region 9 of the second conductivity type and a second titanium film 8021 .

[0071] The first semiconductor region 7 of the second conductivity type is selectively disposed on the first main surface 101 side of the anode layer 15, and has a higher impurity concentration of the second conductivity type than the anode layer 15. That is, the doping concentration of the first semiconductor region 7 is higher than the doping concentration of the anode layer 15. The side of the first semiconductor region 7 facing the first main surface 101 constitutes at least a portion of the first main surface 101. The first contact hole 801 penetrates the insulating layer 8 and exposes the side of the first semiconductor region 7 away from the second main surface 102.

[0072] The first titanium film 8011 is disposed in the first contact hole 801 and contacts the first semiconductor region 7. The first semiconductor region 7 is electrically connected to the emitter metal 17 through the first contact hole 801. Correspondingly, the anode layer 15 is electrically connected to the emitter metal 17 through the first semiconductor region 7. Exemplarily, the first titanium film 8011 may be disposed on the inner wall of the first contact hole 801. The first titanium film 8011 contacts the inner wall of the first contact hole 801 and is located between the emitter metal 17 and the inner wall of the first contact hole 801. Exemplarily, the material of the first titanium film 8011 may include titanium and / or titanium nitride.

[0073] The second semiconductor region 9 of the second conductivity type is selectively arranged on the first main surface 101 side of the base layer 4, and the impurity concentration of the second conductivity type is higher than that of the base layer 4. That is, the doping concentration of the second semiconductor region 9 is higher than that of the base layer 4. The emitter layer 10 is selectively arranged on the first main surface 101 side of the base layer 4, and the second semiconductor region 9 and the side of the emitter layer 10 facing the first main surface 101 both constitute at least a part of the first main surface 101. The second contact hole 802 penetrates the insulating layer 8 and exposes the second semiconductor region 9 and the emitter layer 10. It should be noted that the exposure of the second semiconductor region 9 and the emitter layer 10 can be exposed at the same second contact hole 802 (the second contact hole 802 exposes the second semiconductor region 9 and the emitter layer 10 adjacent to the second semiconductor region 9 at the same time), or can be exposed at different second contact holes 802 (that is, a part of the second contact hole 802 only exposes the second semiconductor region 9, and a part of the second contact hole 802 only exposes the emitter layer 10).

[0074] The second titanium film 8021 is disposed in the second contact hole 802, in contact with the second semiconductor region 9, and the second semiconductor region 9 and the emitter layer 10 are both electrically connected to the emitter metal 17 through the second contact hole 802. Correspondingly, the base layer 4 is electrically connected to the emitter metal 17 through the second semiconductor region 9. Exemplarily, the second titanium film 8021 can be disposed on the inner wall and bottom of the second contact hole 802, the second contact hole 802 is in contact with the inner wall of the second contact hole 802, and is located between the emitter metal 17 and the inner wall of the second contact hole 802. Exemplarily, the material of the second titanium film 8021 can include titanium and / or titanium nitride.

[0075] The semiconductor device 100 may further include a tungsten layer 16 and an emitter metal 17. The tungsten layer 16 is located in the first contact hole 801 and the second contact hole 802, and is in contact with the first titanium film 8011 or the second titanium film, and the emitter metal 17 is located on a side of the insulating layer 8 away from the first main surface 101, and is in contact with the tungsten layer 16. Exemplarily, the material of the emitter metal 17 may be aluminum, copper, or the like.

[0076] See attached Figure 5 , the first semiconductor region 7 is set from the first main surface 101 to the semiconductor substrate 1 in the first direction (ie Figure 5The depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is A, and the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B, and A and B satisfy the relationship: A≤0.45B. Exemplarily, A can be 0.1B, 0.15B, 0.2B, 0.25B, 0.3B, 0.35B, 0.4B, 0.45B or between any two of the above values. It should be noted that the "depth in the first direction" mentioned in this application refers to the maximum depth of the corresponding region or layer in the first direction, that is, its deepest depth in the first direction.

[0077] For the insulated gate bipolar transistor region 1001, the relatively deep second semiconductor region 9 can have a good effect of reducing the contact resistance, and can effectively extract holes to prevent the semiconductor device 100 from having a latch-up effect; for the fast recovery diode region 1003, the relatively shallow first semiconductor region 7 can, on the one hand, achieve the effect of reducing the contact resistance, and on the other hand, can effectively reduce the hole injection efficiency of the fast recovery diode region 1003, thereby reducing the peak current of reverse recovery and improving the reverse recovery performance of the semiconductor device 100. By setting the depth of the first semiconductor region 7 and the second semiconductor region 9 in the first direction within the above-mentioned range (A≤0.45B), a good balance can be achieved in reducing the contact resistance and reducing the hole injection efficiency.

[0078] See attached Figure 4 , 5 In this embodiment, the materials of the first semiconductor region 7 and the anode region 15 are both silicon. The first titanium film 8011 and the first semiconductor region 7 are in contact with each other in the first contact hole 801 to form a first titanium silicide layer 8012. The first titanium silicide layer 8012 extends from the first main surface 101 to the inside of the semiconductor substrate 1 along the first direction (in Figure 5 The depth of the first titanium silicide layer 8012 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to C, and C, A and B satisfy the relationship: A≤C≤0.5B. In this embodiment, A=C≤0.5B.

[0079] When C≥A, since the first semiconductor region 7 is consumed by the generated first titanium silicide layer 8012, on the one hand, the contact resistance can be reduced, and on the other hand, the hole injection efficiency of the fast recovery diode region 1003 can be reduced, the reverse recovery peak current can be reduced, and the reverse recovery performance can be improved; when C≤0.5B, the depth of the first titanium silicide layer 8012 can be made not too different from the depth of the first semiconductor region 7, thereby avoiding the increase in the contact resistance of the first titanium silicide layer 8012 caused by the first semiconductor region 7 being far from being consumed by the first titanium silicide layer 8012, thereby reducing the contact resistance of the first titanium film 8011, suppressing the increase in the voltage drop when the fast recovery diode is forward-conducted, and improving the deterioration of the forward conduction characteristics of the fast recovery diode. By setting the depth of the first titanium silicide layer 8012 in the first direction within the above range (A≤C≤0.5B), a good balance can be achieved in reducing the contact resistance and reducing the hole injection efficiency.

[0080] Furthermore, when C≥A, there are two situations. One situation is that the area where the first semiconductor region 7 is located is completely located in the area where the first titanium silicide layer 8012 is located, that is, the area where the formed first titanium silicide layer 8012 is located completely overlaps with the area where the first semiconductor region 7 is located (e.g. Figure 5 As shown), or, the region where the first semiconductor region 7 is located is completely located inside the region where the first titanium silicide layer 8012 is formed. At this time, the first semiconductor region 7 is completely confined in the first titanium silicide layer 8012, which can effectively reduce the hole injection efficiency of the fast recovery diode region 1003, reduce the reverse recovery peak current, and improve the reverse recovery performance. Another situation is that the region where the first semiconductor region 7 is located and the region where the first titanium silicide layer 8012 is located partially overlap, and the region where the first semiconductor region 7 is located is not completely located in the region where the first titanium silicide layer 8012 is located. At this time, the hole injection efficiency of the fast recovery diode region 1003 can also be reduced to a certain extent, the reverse recovery peak current can be reduced, and the reverse recovery performance can be improved. It should be noted that the region where the first semiconductor region 7 is located and the region where the first titanium silicide layer 8012 is located refer to the space occupied by the first semiconductor region 7 in the substrate 1 and the space occupied by the first titanium silicide layer 8012 in the substrate 1, respectively.

[0081] In this embodiment, the material of the second semiconductor region 9 includes silicon. The second titanium film 8021 and the second semiconductor region 9 are in contact with each other in the first direction of the second contact hole 802 to form a second titanium silicide layer 8022. The second titanium silicide layer 8022 extends from the first main surface 101 to the semiconductor substrate 1 along the first direction. The depth of the second titanium silicide layer 8022 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to D, and D and B satisfy the relationship: D≤B. Preferably, D<B. By setting the relationship between D and B in the above range, the position of the second semiconductor region 9 can effectively extract holes to prevent the device from having a latch effect.

[0082] In some embodiments, the materials of the first semiconductor region 7 and the anode region 15 both include silicon. The first titanium film 8011 adjacent to the first semiconductor region 7 on the first direction in the first contact hole 801 contacts the first semiconductor region 7 to form a first titanium silicide layer 8012. The first titanium silicide layer 8012 extends from the first main surface 101 into the semiconductor substrate 1 along the first direction (in Figure 5 The depth of the first titanium silicide layer 8012 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to C, and C and A satisfy the relationship: C<A.

[0083] When C<A, the first semiconductor region 7 is still left after being consumed by the first titanium silicide layer 8012, thereby reducing the contact resistance of the first titanium film 8011, reducing the forward conduction voltage drop, and reducing the conduction loss. At the same time, the first titanium silicide layer 8012 consumes part of the first semiconductor region 7, which can reduce the hole injection of the fast recovery diode region 1003, reduce the reverse recovery peak current, and improve the reverse recovery performance. By setting the depth of the first titanium silicide layer 8012 in the first direction within the above range (C<A), a good balance can be achieved in reducing the contact resistance and reducing the hole injection efficiency.

[0084] Further, when C<A, there are two situations. One situation is that the area where the first titanium silicide layer 8012 is located is completely located in the area where the first semiconductor region 7 is located, that is, the area where the first titanium silicide layer 8012 is located is completely located inside the area where the first semiconductor region 7 is located. Another situation is that the area where the first titanium silicide layer 8012 is located and the area where the first semiconductor region 7 is located partially overlap, and the area where the first titanium silicide layer 8012 is located is not completely located in the area where the first semiconductor region 7 is located. In both cases, the forward conduction voltage drop can be reduced, the conduction loss can be reduced, and the hole injection of the fast recovery diode region 1003 can be reduced, the reverse recovery peak current can be reduced, and the reverse recovery performance can be improved. It should be noted that the area where the first titanium silicide layer 8012 is located and the area where the first semiconductor region 7 is located refer to the space occupied by the first titanium silicide layer 8012 in the substrate 1 and the space occupied by the first semiconductor region 7 in the substrate 1, respectively.

[0085] In some embodiments, C (the depth of the first titanium silicide layer 8012 from the first main surface 101 to the semiconductor substrate 1 in the first direction) and D (the depth of the second titanium silicide layer 8022 from the first main surface 101 to the semiconductor substrate 1 in the first direction) satisfy the relationship: C = D. Specifically, when the semiconductor device 100 is prepared, a first titanium film 8011 and a second titanium film 8021 of the same thickness are formed on the sidewall and bottom (the side of the first contact hole 801 facing the second main surface 102) of the first contact hole 801 and the sidewall and bottom (the side of the first contact hole 801 facing the second main surface 102) of the second contact hole 802 by CVD (Chemical Vapor Deposition) process and other suitable deposition processes, and the first titanium film 8011 and the second titanium film 8021 of the same thickness are in contact with the first semiconductor region 7 and the second semiconductor region 9, respectively, to form a first titanium silicide layer 8012 and a second titanium silicide layer 8022 of the same depth. That is, the first titanium silicide layer 8012 and the second titanium silicide layer 8022 can be formed in the same process, thereby effectively simplifying the manufacturing process, reducing production costs, and shortening the production cycle. In some embodiments, the depths of C and D can be different, for example, C can be greater than D.

[0086] In this embodiment, the doping impurity injection energy of the first semiconductor region 7 is less than the doping impurity injection energy of the second semiconductor region 9. The doping impurity injection energy of the first semiconductor region 7 is set to Q, and Q satisfies the relationship: 10KeV≤Q≤40KeV.

[0087] By setting the doping impurity injection energy Q of the first semiconductor region 7 within the above-mentioned range and configuring it to be smaller than the doping impurity injection energy of the second semiconductor region 9, A (the depth of the first semiconductor region 7 from the first main surface 101 to the semiconductor substrate 1 in the first direction) can be made ≤0.45B (the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B), thereby achieving the effect of reducing the contact resistance on the one hand, and effectively reducing the hole injection efficiency of the fast recovery diode region 1003 on the other hand, reducing the peak current of reverse recovery, and improving the reverse recovery performance of the semiconductor device 100, thereby achieving a good balance between reducing the contact resistance and reducing the hole injection efficiency.

[0088] In this embodiment, the impurity doping concentration of the first semiconductor region 7 is less than or equal to the impurity doping concentration of the second semiconductor region 9. Since A (the depth of the first semiconductor region 7 from the first main surface 101 to the semiconductor substrate 1 in the first direction) ≤ 0.45B (the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B), even if the impurity doping concentration of the first semiconductor region 7 is equal to the impurity doping concentration of the second semiconductor region 9, the hole injection efficiency of the fast recovery diode region 1003 can be effectively reduced. When the impurity doping concentration of the first semiconductor region 7 is less than the impurity doping concentration of the second semiconductor region 9, on the one hand, the effect of reducing the contact resistance can be achieved, and on the other hand, the hole injection efficiency of the fast recovery diode region 1003 can be more effectively reduced, thereby reducing the peak current of the reverse recovery and improving the reverse recovery performance of the semiconductor device 100, thereby achieving a good balance between reducing the contact resistance and reducing the hole injection efficiency.

[0089] Exemplarily, the doping impurity implantation dosage of the first semiconductor region 7 is D, and D satisfies the relationship: 2E14≤D≤8E14.

[0090] By setting the doping impurity injection dose D of the first semiconductor region 7 within the above range, on the one hand, the contact degradation problem between the first titanium film 8011 and the semiconductor substrate 1 can be improved, and on the other hand, the hole injection efficiency of the fast recovery diode region 1003 can be reduced, thereby reducing the peak current of reverse recovery and improving the reverse recovery performance of the semiconductor device.

[0091] See attached Figure 2-4In this embodiment, the insulated gate bipolar transistor region 1001 includes a first region 10011 and a second region 10012, the first region 10011 and the second region 10012 are both multiple, the emitter layer 10 and the second semiconductor region 9 are both multiple, the multiple emitter layers 10 are arranged in the base layers 4 of the multiple first regions 10011 in a one-to-one correspondence, and the multiple second semiconductor regions 9 are arranged in the base layers 4 of the multiple second regions 10012 in a one-to-one correspondence. That is, only the emitter layer 10 is arranged on the side of the base layer 4 located in the first region 10011 away from the second main surface 102, and the second semiconductor region 9 is not arranged (such as Figure 3 The base layer 4 located in the second region 10012 is only provided with the second semiconductor region 9 on the side away from the second main surface 102, but the emitter layer 10 is not provided (as shown in FIG. Figure 4 Correspondingly, the second contact hole 802 located in the first region 10011 penetrates the insulating layer 8 and exposes the emitter layer 10, and the second contact hole 802 located in the second region 10012 penetrates the insulating layer 8 and exposes the second semiconductor region 9. The plurality of first regions 10011 and the plurality of second regions 10012 are alternately arranged in sequence in the third direction.

[0092] See attached Figure 6 In another embodiment, the insulated gate bipolar transistor region 1001 includes a first region 10011 and a second region 10012, the first region 10011 and the second region 10012 are both multiple, the emitter layer 10 and the second semiconductor region 9 are both multiple, the multiple emitter layers 10 are arranged in the base layer 4 of the multiple first regions 10011 in a one-to-one correspondence, the multiple second semiconductor regions 9 are arranged in the base layer 4 of the multiple second regions 10012 in a one-to-one correspondence, and the multiple first regions 10011 and the multiple second regions 10012 are arranged alternately in sequence in the second direction. That is, in the second direction (i.e. Figure 6 ), emitter layers 10 are provided on both sides of the second semiconductor region 9, and the second semiconductor region 9 contacts the emitter layers 10 on both sides thereof. The second contact hole 802 penetrates the insulating layer 8, and the second contact hole 802 can expose only the second semiconductor region 9, or the second contact hole 802 can expose the second semiconductor region 9 and part of the emitter layer 10 adjacent to the second semiconductor region 9 at the same time.

[0093] In this embodiment, the semiconductor device 100 further includes a carrier storage layer 3 of a first conductivity type, and the doping concentration of the carrier storage layer 3 is greater than the doping concentration of the drift layer 2. In the first direction, the carrier storage layer 3 is located between the drift layer 2 and the base layer 4, and between the drift layer 2 and the anode layer 15. The gate trench 6 and the virtual gate trench 18 both extend through the carrier storage layer 3 into the drift layer 2. The provision of the carrier storage layer 3 can effectively improve the switching speed of the semiconductor device, stabilize the working state of the semiconductor device, so that the semiconductor device will not generate excessive voltage spikes or current surges due to the rapid change of carriers, reduce switching losses, and allow the semiconductor device to switch between the on state and the off state more quickly and stably. The carrier storage layer 3 can also increase the withstand voltage of the semiconductor device. It can assist the drift layer 2 to withstand a higher reverse voltage and prevent the semiconductor device from being broken down. In some embodiments, the carrier storage layer 3 may not be provided in the semiconductor device 100 , and in the first direction, the drift layer 2 is in direct contact with the base layer 4 , and the drift layer 2 is in direct contact with the anode layer 15 .

[0094] In this embodiment, the semiconductor device 100 further includes a field stop layer 11 of the first conductivity type, and the doping concentration of the field stop layer 11 is greater than the doping concentration of the drift layer 2. In the first direction, the field stop layer 11 is located between the drift layer 2 and the collector layer 12, and between the drift layer 2 and the cathode layer 14. The main function of the field stop layer 11 is to terminate the electric field when the semiconductor device is turned off, and prevent the electric field from penetrating into the collector layer 12, thereby improving the withstand voltage capability. When a high voltage is applied, the field stop layer 11 can withstand a part of the electric field, so that the electric field gradually weakens before reaching the collector layer 12, avoiding the breakdown of the collector layer 12. The field stop layer 11 can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce the turn-off loss. In some embodiments, the conductor device 100 may not be provided with a field stop layer 11 of the first conductivity type, and in the first direction, the drift layer 2 and the collector layer 12 are in direct contact, and the drift layer 2 and the cathode layer 14 are in direct contact.

[0095] Refer to the attached Figure 7-17 An exemplary method for manufacturing a semiconductor device according to an embodiment of the present application is described. The method is applicable to the semiconductor device 100 described above. The method comprises the following steps:

[0096] S10: providing a semiconductor substrate 1.

[0097] The semiconductor substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in a first direction. The substrate is a substrate of a first conductivity type, and the material of the substrate can be silicon.

[0098] S20 : ​​forming a plurality of trench gates 6 extending from the first main surface 101 toward the second main surface 102 of the semiconductor substrate 1 .

[0099] The plurality of trench gates 6 are spaced apart in the second direction, wherein the first direction and the second direction are perpendicular to each other.

[0100] Illustratively, in step S20 , a plurality of dummy gates 19 extending from the first main surface 101 toward the second main surface 102 of the semiconductor substrate 1 may be simultaneously formed.

[0101] Exemplarily, in step S20, see the attached Figure 8 , a patterned mask layer can be first formed on the first main surface 101 of the semiconductor substrate 1; then the semiconductor substrate 1 is etched using the mask layer as a mask to form a plurality of gate trenches 5 and a plurality of virtual gate trenches 18, the gate trenches 5 are located in the insulated gate bipolar transistor region 1001, and the gate trenches 5 are located in the fast recovery diode region 1003. The plurality of trench gates 5 and the virtual gate trenches 18 extend from the first main surface 101 of the semiconductor substrate 1 toward the second main surface 102, and are arranged at intervals in the second direction; then the mask layer is removed, and a gate trench insulating film is formed on the inner surface of the trench gate 5 by a thermal oxidation process or a CVD process, and a virtual gate trench insulating film is formed on the inner surface of the virtual gate trench 18, and then a gate electrode material (for example, polysilicon doped with n-type or p-type impurities) is deposited in the gate trench 5 and the virtual gate trench 18 and planarized to form a gate trench electrode and a virtual gate trench electrode. A gate trench electrode is provided in the gate trench 5 via a gate trench insulating film, thereby forming a trench gate 6. A dummy gate trench electrode is provided in the dummy gate trench 18 via a dummy gate trench insulating film, thereby forming a dummy gate 19.

[0102] S30 : forming the base layer 4 , the anode layer 15 and the emitter layer 10 on the side of the semiconductor substrate 1 facing the first main surface 101 .

[0103] The base layer 4 is located in the insulated gate bipolar transistor region 1001 , and the anode layer 15 is located in the fast recovery diode region 1003 .

[0104] Exemplarily, in step S30, first, see the attached Fig. 9, through the ion implantation process, the first conductive type and the second conductive type doping impurities are implanted and pushed into the semiconductor substrate 1 on the side facing the first main surface 101 to form a carrier storage layer 3, a base layer 4 and an anode layer 15. Exemplarily, before the doping impurities are implanted, a patterned mask layer needs to be formed on the first main surface 101, and the mask layer covers the gate trench 5 and the side of the virtual gate 19 away from the first main surface. After the storage layer 3, the base layer 4 and the anode layer 15 are formed, the mask layer is removed.

[0105] Then, see Appendix Fig.10 , through an ion implantation process, doping impurities of the first conductivity type are implanted on the side of the base layer 4 away from the second main surface 102 to form the emitter layer 10. Exemplarily, before the doping impurities are implanted, a patterned mask layer needs to be formed on the first main surface 101, the mask layer covers the gate trench 5 and the side of the dummy gate 19 away from the first main surface, and covers the anode layer 15 and part of the base layer 4. After the emitter layer 10 is formed, the mask layer is removed.

[0106] S40 : depositing an insulating layer 8 on the first main surface 101 , and etching a first contact hole 801 and a second contact hole 802 on the insulating layer 8 .

[0107] The first contact hole 801 and the second contact hole 802 both penetrate the insulating layer 8, the first contact hole 801 is located in the fast recovery diode region 1003, and the second contact hole 802 is located in the insulated gate bipolar transistor region 1001. The first contact hole 801 and the second contact hole 802 expose the anode layer 15 and the base layer 4 respectively.

[0108] For example, see the attached Fig.11 , 12 (Attached Fig.12 For attachment Fig.11 In step S40, an insulating layer 8 may be deposited on the first main surface 101 by a deposition process such as a CVD process. The insulating layer may be, for example, a silicon dioxide layer. Then, a patterned mask layer may be formed on the insulating layer 8, and the insulating layer 8 may be etched using the mask layer as a mask to form a first contact hole 801 and a second contact hole 802 that penetrate the insulating layer 8. Then, the mask layer may be removed.

[0109] S50: First, doping impurities of the second conductivity type are injected into the anode layer 15 exposed by the first contact hole 801 to form a first semiconductor region 7 of the second conductivity type, and then doping impurities of the second conductivity type are injected into the base layer 4 exposed by the second contact hole 802 to form a second semiconductor region 9 of the second conductivity type.

[0110] The depth of the second semiconductor region 9 in the first direction is greater than the depth of the first semiconductor region 7 in the first direction. Figure 5 The depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is A, and the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B, and A and B satisfy the relationship: A≤0.45B. Exemplarily, the doping impurity injection energy of the first semiconductor region 7 is less than the doping impurity injection energy of the second semiconductor region 9, and the doping impurity injection energy of the first semiconductor region 7 is set to Q, and Q satisfies the relationship: 10KeV≤Q≤40KeV. Exemplarily, the doping impurity injection dose of the first semiconductor region 7 is set to D, and D satisfies the relationship: 2E14≤D≤8E14.

[0111] For example, see the attached Fig.11 , 12 (Attached Fig.12 For attachment Fig.11 (Fig. 8A and 8B) , in step S50, a first mask layer may be first formed in the second contact hole 802 to protect the base layer 4 from entering; then, through an ion implantation process, doped impurities of the second conductivity type are implanted into the anode layer 15 exposed by the first contact hole 801 to form a first semiconductor region 7 of the second conductivity type; then, the first mask layer is removed, and a second mask layer is formed in the first contact hole 801 to protect the first semiconductor region 7; then, through an ion implantation process, doped impurities of the second conductivity type are implanted into the base layer 4 exposed by the second contact hole 802 to form a second semiconductor region 9 of the second conductivity type.

[0112] In some other embodiments, step S50 may be: simultaneously injecting doping impurities of the second conductivity type into the anode layer 15 exposed by the first contact hole 801 and the base layer 4 exposed by the second contact hole 802 to form a first semiconductor region 7 of the second conductivity type in the anode layer 15, and forming a sub-semiconductor region of the second conductivity type with the same depth as the first semiconductor region 7 in the base layer 4, and then injecting doping impurities of the second conductivity type into the portion of the base layer 4 corresponding to the sub-semiconductor region to form a second semiconductor region 9. The depth of the second semiconductor region 9 is greater than the depth of the first semiconductor region 7. Exemplarily, it is assumed that the first semiconductor region 7 extends from the first main surface 101 to the semiconductor substrate 1 in the first direction (i.e., Figure 5The depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is A, and the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is B, and A and B satisfy the relationship: A≤0.45B. Exemplarily, the doping impurity injection energy of the first semiconductor region 7 is less than the doping impurity injection energy of the second semiconductor region 9, and the doping impurity injection energy of the first semiconductor region 7 is set to Q, and Q satisfies the relationship: 10KeV≤Q≤40KeV. Exemplarily, the doping impurity injection dose of the first semiconductor region 7 is set to D, and D satisfies the relationship: 2E14≤D≤8E14.

[0113] S60 : forming a first titanium film 8011 and a second titanium film 8021 respectively located in the first contact hole 801 and the second contact hole 802 .

[0114] The first titanium film 8011 is in contact with the first semiconductor region 7 , and the second titanium film 8021 is in contact with the second semiconductor region 9 .

[0115] For example, see the attached Fig.13 , 14 (Attached Fig.14 For attachment Fig.13 ), a layer of titanium-containing material may be deposited in the first contact hole 801, the second contact hole 802, and the side of the insulating layer 8 away from the first main surface 101 by a CVD process or other suitable deposition process, so as to form a first titanium film 8011 and a second titanium film 8021 in the first contact hole 801 and the second contact hole 802, respectively. Exemplarily, the titanium-containing material may include titanium and / or titanium nitride.

[0116] The first titanium film 8011 is in contact with the first semiconductor region 7 on one side adjacent to the first main surface 101 to form a first titanium silicide layer 8012, and the second titanium film 8021 is in contact with the second semiconductor region 9 on one side adjacent to the first main surface 101 to form a second titanium silicide layer 8022, wherein the depth of the first semiconductor region 7 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to A, the depth of the second semiconductor region 9 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to B, and the depth of the first titanium silicide layer 8012 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to C, and C, A and B satisfy the relationship: A≤C≤0.5B; or C and A satisfy the relationship: C<A. Exemplarily, the region where the first semiconductor region 7 is located is completely located in the region where the first titanium silicide layer 8012 is located, or the region where the first titanium silicide layer 8012 is located is completely located in the region where the first semiconductor region 7 is located,

[0117] In the second contact hole 802, the second titanium film 8021 on the side adjacent to the second semiconductor region 9 in the first direction contacts the second semiconductor region 9 to form a second titanium silicide layer 8022. The second titanium silicide layer 8022 extends from the first main surface 101 into the semiconductor substrate 1 along the first direction. The depth of the second titanium silicide layer 8022 from the first main surface 101 to the semiconductor substrate 1 in the first direction is set to D, and D and B satisfy the relationship: D≤B.

[0118] Exemplarily, after step S60, the method for manufacturing a semiconductor device may further include the following steps:

[0119] See attached Fig.15 , by CVD process or other suitable deposition process, metal tungsten is deposited in the first contact hole 801 and the second contact hole 802 and etched back to form a tungsten layer 16 in the first contact hole 801 and the second contact hole 802, the tungsten layer 16 located in the fast recovery diode area 1003 is in contact with the first titanium film 8011 and the first titanium silicide layer 8012, and the tungsten layer 16 located in the insulated gate bipolar transistor area 1001 is in contact with the second titanium film 8021 and the second titanium silicide layer 8022.

[0120] Afterwards, see Appendix Fig.15 , a layer of metal is deposited on the side of the titanium-containing material and the tungsten layer 16 away from the first main surface 101 by a CVD process or other suitable deposition process to form an emitter metal layer 17. For example, the metal may be aluminum, copper, or the like.

[0121] Afterwards, see Appendix Fig.16 , a side of the semiconductor substrate 1 away from the first main surface 101 is thinned by a thinning process such as a CMP process, and doping impurities of the first conductivity type are implanted by an ion implantation process to form a field stop layer 11.

[0122] Afterwards, see Appendix Fig.17 , through an ion implantation process, doping impurities of the first conductivity type and doping impurities of the second conductivity type are respectively implanted into a side of the field stop layer 11 away from the first main surface to form a cathode layer 14 and a collector layer 12, wherein the doping impurities of the first conductivity type are implanted into the field stop layer 11 located in the fast recovery diode region 1003, and the doping impurities of the second conductivity type are implanted into the field stop layer 11 located in the insulated gate bipolar transistor region 1001.

[0123] Afterwards, see Appendix Fig.17 A layer of metal is deposited on a side of the cathode layer 14 away from the first main surface 101 and a side of the collector layer 12 away from the first main surface 101 by a CVD process or other suitable deposition process to form a collector metal layer 13 .

[0124] At this point, the process steps implemented in the manufacturing method of the semiconductor device according to the embodiment of the present application have been completed. It can be understood that the manufacturing method of the semiconductor device of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0125] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application to this. Those of ordinary skill in the art may make various changes and modifications therein without departing from the scope and spirit of the present application. All these changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0127] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0128] Similarly, it should be understood that in order to streamline the present application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present application should not be interpreted as reflecting the following intention: the claimed application requires more features than the features clearly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby explicitly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present application.

[0129] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0130] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0131] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A semiconductor device (100), comprising a semiconductor substrate (1), wherein the semiconductor substrate (1) has a drift layer (2) of a first conductivity type between a first main surface (101) and a second main surface (102), wherein: The first main surface (101) and the second main surface (102) are arranged opposite to each other in a first direction. The semiconductor device (100) is characterized by comprising: An insulated gate bipolar transistor region (1001), comprising a trench gate (6) penetrating an emitter layer (10) of a first conductivity type and a base layer (4) of a second conductivity type from the first main surface (101) of the semiconductor substrate (1) to reach the drift layer (2), and a collector layer (12) of the second conductivity type arranged on the second main surface (102) side relative to the drift layer (2), wherein the trench gate (6) is multiple, the multiple trench gates (6) are arranged at intervals in the second direction, the length of the trench gate (6) is extended in the third direction, and the first direction, the second direction and the third direction are perpendicular to each other; A fast recovery diode region (1003), comprising an anode layer (15) of the second conductivity type disposed on the first main surface (101) side relative to the drift layer (2), and a cathode layer (14) of the first conductivity type disposed on the second main surface (102) side relative to the drift layer (2); An insulating layer (8) disposed on the first main surface (101), the insulating layer (8) being provided with a first contact hole (801) and a second contact hole (802), the second contact hole (802) being located in the insulated gate bipolar transistor region (1001), and the first contact hole (801) being located in the fast recovery diode region (1003); The fast recovery diode region (1003) further includes a first semiconductor region (7) of a second conductivity type and a first titanium film (8011); The first semiconductor region (7) is selectively arranged on the first main surface (101) side of the anode layer (15), and has a higher impurity concentration of the second conductivity type than the anode layer (15); the side of the first semiconductor region (7) facing the first main surface (101) constitutes at least a part of the first main surface (101); and the first contact hole (801) penetrates the insulating layer (8) and exposes the first semiconductor region (7); The first titanium film (8011) is arranged in the first contact hole (801) and is in contact with the first semiconductor region (7); the first semiconductor region (7) is electrically connected to the emitter metal (17) through the first contact hole (801); The insulated gate bipolar transistor region (1001) further includes a second semiconductor region (9) of a second conductivity type and a second titanium film (8021); The second semiconductor region (9) is selectively arranged on the first main surface (101) side of the base layer (4), and has a higher impurity concentration of the second conductivity type than the base layer (4); the emitter layer (10) is selectively arranged on the first main surface (101) side of the base layer (4); the second semiconductor region (9) and the emitter layer (10) on the side facing the first main surface (101) both constitute at least a part of the first main surface (101); the second contact hole (802) penetrates the insulating layer (8) and exposes the second semiconductor region (9) and the emitter layer (10); The second titanium film (8021) is arranged in the second contact hole (802) and is in contact with the second semiconductor region (9); the second semiconductor region (9) and the emitter layer (10) are both electrically connected to the emitter metal (17) through the second contact hole (802); The depth of the first semiconductor region (7) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to A, and the depth of the second semiconductor region (9) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to B, and A and B satisfy the relationship: A≤0.45B.

2. The semiconductor device (100) according to claim 1, characterized in that The first titanium film (8011) and the first semiconductor region (7) are in contact with each other in the first contact hole (801) on one side adjacent to the first semiconductor region (7) in the first direction to form a first titanium silicide layer (8012), the first titanium silicide layer (8012) extending from the first main surface (101) into the semiconductor substrate (1) along the first direction, the depth of the first titanium silicide layer (8012) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to C, and C, A and B satisfy the relationship: A≤C≤0.5B; The second titanium film (8021) and the second semiconductor region (9) are in contact with each other on the side of the second contact hole (802) adjacent to the second semiconductor region (9) in the first direction to form a second titanium silicide layer (8022), and the second titanium silicide layer (8022) extends from the first main surface (101) into the semiconductor substrate (1) along the first direction, and the depth of the second titanium silicide layer (8022) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to D, and D and B satisfy the relationship: D≤B.

3. The semiconductor device (100) according to claim 2, characterized in that The region where the first semiconductor region (7) is located is completely located in the region where the first titanium silicide layer (8012) is located.

4. The semiconductor device (100) according to claim 1, characterized in that The first titanium film (8011) and the first semiconductor region (7) are in contact with each other on one side of the first contact hole (801) adjacent to the first semiconductor region (7) in a first direction to form a first titanium silicide layer (8012), the first titanium silicide layer (8012) extending from the first main surface (101) into the semiconductor substrate (1) along the first direction, the depth of the first titanium silicide layer (8012) from the first main surface (101) into the semiconductor substrate (1) in the first direction is set to C, and C and A satisfy the relationship: C<A; The second titanium film (8021) and the second semiconductor region (9) are in contact with each other on the side of the second contact hole (802) adjacent to the second semiconductor region (9) in the first direction to form a second titanium silicide layer (8022), and the second titanium silicide layer (8022) extends from the first main surface (101) into the semiconductor substrate (1) along the first direction, and the depth of the second titanium silicide layer (8022) from the first main surface (101) to the semiconductor substrate (1) in the first direction is set to D, and D and B satisfy the relationship: D≤B.

5. The semiconductor device (100) according to claim 4, characterized in that The region where the first titanium silicide layer (8012) is located is completely located in the region where the first semiconductor region (7) is located.

6. The semiconductor device (100) according to any one of claims 2 to 5, characterized in that: C and D satisfy the relationship: C=D.

7. The semiconductor device (100) according to claim 1, characterized in that The doping impurity injection energy of the first semiconductor region (7) is less than the doping impurity injection energy of the second semiconductor region (9), the doping impurity injection energy of the first semiconductor region (7) is Q, and Q satisfies the relationship: 10KeV≤Q≤40KeV; and / or, The impurity doping concentration of the first semiconductor region (7) is less than or equal to the impurity doping concentration of the second semiconductor region (9); and / or, The doping impurity implantation dose of the first semiconductor region (7) is D, and D satisfies the relationship: 2E14≤D≤8E14.

8. The semiconductor device (100) according to claim 1, characterized in that The insulated gate bipolar transistor region (1001) comprises a first region (10011) and a second region (10012), the first region (10011) and the second region (10012) are both multiple, the emitter layer (10) and the second semiconductor region (9) are both multiple, the multiple emitter layers (10) are arranged one-to-one in the base layers (4) of the multiple first regions (10011), the multiple second semiconductor regions (9) are arranged one-to-one in the base layers (4) of the multiple second regions (10012), and the multiple first regions (10011) and the multiple second regions (10012) are arranged alternately in sequence in a third direction.

9. The semiconductor device (100) according to claim 1, characterized in that The insulated gate bipolar transistor region (1001) comprises a first region (10011) and a second region (10012), the first region (10011) and the second region (10012) are both multiple, the emitter layer (10) and the second semiconductor region (9) are both multiple, the multiple emitter layers (10) are arranged one-to-one in the base layers (4) of the multiple first regions (10011), the multiple second semiconductor regions (9) are arranged one-to-one in the base layers (4) of the multiple second regions (10012), and the multiple first regions (10011) and the multiple second regions (10012) are arranged alternately in sequence in a second direction.

10. A method for manufacturing a semiconductor device, applicable to the semiconductor device (100) according to any one of claims 1 to 7, characterized in that: The following steps are involved: A semiconductor substrate (1) is provided, wherein the semiconductor substrate (1) has a first main surface (101) and a second main surface (102) opposite to the first main surface (101), and the first main surface (101) and the second main surface (102) are arranged at intervals in a first direction; forming a plurality of trench gates (6) extending from the first main surface (101) of the semiconductor substrate (1) toward the second main surface (102), wherein the plurality of trench gates (6) are arranged at intervals in a second direction, wherein the first direction and the second direction are perpendicular to each other; A base layer (4), an anode layer (15) and an emitter layer (10) are formed on the side of the semiconductor substrate (1) facing the first main surface (101), wherein the base layer (4) is located in the insulated gate bipolar transistor region (1001), and the anode layer (15) is located in the fast recovery diode region (1003); Depositing an insulating layer (8) on the first main surface (101), and etching a first contact hole (801) and a second contact hole (802) on the insulating layer (8), wherein the first contact hole (801) and the second contact hole (802) both penetrate the insulating layer (8), the first contact hole (801) is located in the fast recovery diode region (1003), and the second contact hole (802) is located in the insulated gate bipolar transistor region (1001); Firstly, doping impurities of the second conductivity type are injected into the anode layer (15) exposed by the first contact hole (801) to form a first semiconductor region (7) of the second conductivity type, and then doping impurities of the second conductivity type are injected into the base layer (4) exposed by the second contact hole (802) to form a second semiconductor region (9) of the second conductivity type, wherein the depth of the second semiconductor region (9) in the first direction is greater than the depth of the first semiconductor region (7) in the first direction; or Simultaneously, doping impurities of a second conductivity type are injected into the anode layer (15) exposed by the first contact hole (801) and the base layer (4) exposed by the second contact hole (802), so as to form a first semiconductor region (7) of a second conductivity type in the anode layer (15), and a sub-semiconductor region of a second conductivity type having the same depth as the first semiconductor region (7) is formed in the base layer (4), and doping impurities of a second conductivity type are injected into a portion of the base layer (4) corresponding to the sub-semiconductor region, so as to form a second semiconductor region (9), wherein the depth of the second semiconductor region (9) is greater than the depth of the first semiconductor region (7); A first titanium film (8011) and a second titanium film (8021) are formed and are located in the first contact hole (801) and the second contact hole (802), respectively, wherein the first titanium film (8011) is in contact with the first semiconductor region (7), and the second titanium film (8021) is in contact with the second semiconductor region (9).

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