High-voltage electrostatic protection structure and electronic device

Abstract

The present invention relates to the technical field of semiconductor manufacturing, and specifically discloses a high-voltage electrostatic protection structure and an electronic device, including: an N-type MOS transistor and a P-type triode unit connected to the N-type MOS transistor. The isolation terminal and the drain terminal of the N-type MOS transistor are both used to connect to a high-voltage pin. The gate terminal, the source terminal, and the substrate terminal of the N-type MOS transistor are short-circuited and then connected to one end of the P-type triode unit, and the other end of the P-type triode unit is connected to a ground pin; the P-type triode unit includes at least one lateral P-type triode, and multiple lateral P-type triodes are connected in series, and the base and the emitter of each lateral P-type triode are short-circuited. The high-voltage electrostatic protection structure provided by the present invention can enable the ESD device to provide effective protection while not affecting the circuit during normal circuit operation.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a high-voltage electrostatic protection structure and electronic equipment. Background Art

[0002] ESD (electrostatic discharge) refers to the accumulation of a certain amount of charge in the external environment or internal structure of an integrated circuit chip during its manufacture, transportation, and use. These accumulated charges will instantly enter the integrated circuit through the pins of the chip, with a peak current of several amperes. This transient high current will burn out the components inside the chip, causing the entire chip to fail. In recent years, with the continuous reduction in the size of integrated circuit components and the increase in integration, the proportion of circuit failures caused by ESD has also gradually increased, approaching 40%. Therefore, how to prevent integrated circuits from being damaged by ESD has become increasingly important.

[0003] At present, smart phones have been widely popularized, and the power chips in their chargers are also widely used in the market. Such power chips generally work in a switching state, which will generate positive and negative tip pulses, which can easily damage the circuit. In particular, the negative pulses generated should be paid more attention. Because when a negative pulse appears on the circuit switch pin, the PN junction formed by the P-type GND and the N-type area at the pin is turned on. At this time, if the other pins are connected to the PN-type area, a PNPN latch effect will be generated, causing the circuit to fail. Therefore, when the high-voltage ESD device of the circuit pin is not designed properly, it is easy to be affected by the above negative tip pulses and trigger latching, causing the circuit to burn out instantly.

[0004] Therefore, in the design of high-voltage ESD devices, how to make the ESD devices provide effective protection while not affecting the circuits when the circuits are operating normally has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] The present invention provides a high-voltage electrostatic protection structure and an electronic device, which solves the problem in the related art that high-voltage ESD devices cannot provide effective protection.

[0006] As a first aspect of the present invention, a high-voltage electrostatic protection structure is provided, which comprises: an N-type MOS tube and a P-type triode unit connected to the N-type MOS tube,

[0007] The N-type MOS tube is a low-voltage isolation structure, the isolation end and the drain end of the N-type MOS tube are both used to connect to the high-voltage pin, the gate end, the source end and the substrate end of the N-type MOS tube are short-circuited and connected to one end of the P-type triode unit, and the other end of the P-type triode unit is connected to the ground pin;

[0008] The P-type triode unit includes at least one lateral P-type triode, and multiple lateral P-type triodes are connected in series. The base and emitter of each lateral P-type triode are short-circuited. After the base and emitter of the first lateral P-type triode are short-circuited, it forms one end of the P-type triode unit, and the collector of the last lateral P-type triode forms the other end of the P-type triode unit;

[0009] When an electrostatic discharge voltage is introduced through the high-voltage pin, the energy of the electrostatic discharge voltage can sequentially break down the drain and source ends of the N-type MOS transistor and reach one end of the P-type triode unit, and sequentially break down the emitter and collector of each lateral P-type triode in the P-type triode unit and reach the ground pin to complete the energy discharge of the positive electrostatic discharge voltage;

[0010] When an electrostatic discharge voltage is introduced through the ground pin, the energy of the electrostatic discharge voltage can sequentially pass through the collector of each lateral P-type triode in the P-type triode unit and the short-circuited end of the base and emitter, reach one end of the P-type triode unit, and pass through two parallel PN junctions formed between the substrate end and the drain end and between the substrate end and the isolation end of the N-type MOS transistor and then reach the high-voltage pin to complete the energy discharge of the negative electrostatic voltage.

[0011] Further, the breakdown voltage of the N-type MOS transistor ranges from 8V to 10V, and the breakdown voltage of each lateral P-type triode in the P-type triode unit ranges from 13V to 17V.

[0012] Further, the structure of the N-type MOS transistor is a first multi-finger structure, and the number of fingers of the first multi-finger structure ranges from 8 to 12, and the total width of the structure of the N-type MOS transistor is at least 400μm.

[0013] Further, the structure of the lateral P-type triode is a second multi-finger structure, and the number of fingers of the second multi-finger structure ranges from 10 to 16, and the total width of the structure of the lateral P-type triode is at least 1200μm.

[0014] Further, the N-type MOS transistor includes: a P-type substrate, an N-type buried layer disposed on the surface of the P-type substrate and extending into the P-type substrate, and a P-type epitaxial layer disposed on the surface of the P-type substrate;

[0015] A plurality of active regions are disposed in the P-type epitaxial layer, and a field region is formed between adjacent active regions;

[0016] An external oxide layer and metal wires are disposed on the surface of the P-type epitaxial layer.

[0017] Further, a first active region to a seventh active region are sequentially and spacedly arranged in the P-type epitaxial layer, a field region is arranged between every two adjacent active regions, and a field oxide layer is arranged at the position of the field region;

[0018] Deep P-well regions extending inward from the surface of the P-type epitaxial layer are formed below both the first active region and the seventh active region. A P-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep P-well region. A P+ implanted diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the P-well region. The P+ implanted diffusion region is connected to a metal wire to serve as an extraction terminal of the P-type epitaxial layer and the P-type substrate, and is connected to the ground pin;

[0019] Deep N-well regions extending inward from the surface of the P-type epitaxial layer are formed below both the second active region and the sixth active region. An N-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep N-well region. An N+ implanted diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the N-well region. The N+ implanted diffusion region is connected to a metal wire to serve as an extraction terminal of the isolation end of the N-type MOS transistor, and is connected to the high-voltage pin;

[0020] Connected P-well regions are formed below the third active region, the fourth active region, and the fifth active region, and P+ implanted diffusion regions are arranged at the positions of the third active region and the fifth active region. The P+ implanted diffusion region is connected to a metal wire to serve as an extraction terminal of the substrate end of the N-type MOS transistor.

[0021] Further, polysilicon is arranged on the surface of the P-type epitaxial layer at a position corresponding to the fourth active region, and the polysilicon is connected to the metal wire to serve as an extraction terminal of the gate of the N-type MOS transistor;

[0022] N+ implanted diffusion regions are arranged on both sides of the polysilicon below the fourth active region, and the N+ implanted diffusion region is connected to the metal wire to serve as an extraction terminal of the source and drain of the N-type MOS transistor.

[0023] Further, the metal wire serving as the extraction terminal of the drain of the N-type MOS transistor and the metal wire serving as the extraction terminal of the isolation end of the N-type MOS transistor are both connected to the high-voltage pin, and the metal wire serving as the extraction terminal of the gate of the N-type MOS transistor, the metal wire serving as the extraction terminal of the source of the N-type MOS transistor, and the metal wire serving as the extraction terminal of the substrate end of the N-type MOS transistor are all shorted together.

[0024] Further, multiple contact holes are formed after the outer oxide layer is removed at positions corresponding to the active regions and the polysilicon, and the metal wire is located in the contact holes;

[0025] Wherein, the bottom end of the metal wire located in the contact hole is in contact with the active region, and the top end of the metal wire located in the contact hole serves as the lead end of the N-type MOS transistor.

[0026] As another aspect of the present invention, there is provided an electronic device, which includes: a power supply circuit and the high-voltage electrostatic protection structure described above. The high-voltage pin of the power supply circuit is connected to the N-type MOS transistor of the high-voltage electrostatic protection structure, and the ground wire pin of the power supply circuit is connected to the P-type triode unit of the high-voltage electrostatic protection structure.

[0027] For the problem that the electrostatic discharge ability of high-voltage devices in the prior art is weak, the high-voltage electrostatic protection structure provided by the present invention adopts a series connection method of a lateral P-type triode and an isolated N-type MOS transistor NMOS, so that its electrostatic discharge level is equivalent to that of a single lateral P-type triode or an isolated N-type MOS transistor NMOS, that is, the ESD discharge ability is strong. At the same time, the present invention connects multiple lateral P-type triodes at one end close to the ground wire pin, that is, utilizes the characteristic that the holding voltage of the lateral P-type triode is relatively high to meet the requirement that this ESD structure can be used in high-voltage pins; in addition, at one end of the high-voltage pin of the present invention, an isolated N-type MOS transistor is used to connect the high-voltage pin and the lateral P-type triode. Since the high-voltage pin of the present invention is connected to an NMOS, that is, the high-voltage pin is not connected to a P-type region, a PNPN latching structure will not be formed with the PN junction (that is, the PN junction formed by the P-type ground and the N-type region at the negative pulse pin), thereby avoiding the failure of the circuit in the case of extreme negative pulses and greatly improving the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation to the present invention.

[0029] Figure 1 It is a circuit structure diagram of the high-voltage electrostatic protection structure provided by the present invention.

[0030] Figure 2 It is a longitudinal sectional view of the N-type MOS transistor provided by the present invention.

[0031] Figure 3 It is a longitudinal sectional view of the lateral P-type triode provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0033] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances for the embodiments of the present invention described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] For the ESD protection of conventional high-voltage pins, a high-voltage NMOS transistor with the same type of voltage as the high-voltage pin is generally selected as its ESD protection device. As is well known, the ESD discharge ability of high-voltage NMOS devices is weak, and its holding voltage is low, so it cannot be used for power pins. If a high-voltage PMOS or high-voltage PNP is selected for ESD protection, although the holding voltage is increased and the ESD discharge ability is also improved compared with high-voltage NMOS. However, when a negative pulse appears at the N-type port connected to the remaining pins, the P-type region of the high-voltage PMOS or high-voltage PNP connected to the high-voltage pin, its N-type substrate or base, and the P-type ground and the aforementioned N-type negative pulse port form a PNPN latch structure, causing the circuit to burn out instantly.

[0036] Based on this, a high-voltage electrostatic protection structure is provided in this embodiment. Figure 1 It is the circuit structure diagram of the high-voltage electrostatic protection structure provided according to the embodiment of the present invention, as Figure 1 shown, including:

[0037] An N-type MOS transistor 10 and a P-type triode unit 20 connected to the N-type MOS transistor 10.

[0038] The N-type MOS transistor 10 is a low-voltage isolation structure. The isolation terminal 102 and the drain terminal 101 of the N-type MOS transistor 10 are both used to connect to the high-voltage pin 100. The gate terminal 103, the source terminal 105, and the substrate terminal 104 of the N-type MOS transistor 10 are short-circuited and then connected to one end of the P-type triode unit 20, and the other end of the P-type triode unit 20 is connected to the ground pin 115.

[0039] The P-type triode unit 20 includes at least one lateral P-type triode, and a plurality of the lateral P-type triodes are connected in series. The base and emitter of each lateral P-type triode are short-circuited. One end of the P-type triode unit is formed after the base and emitter of the first lateral P-type triode are short-circuited, and the other end of the P-type triode unit is formed by the collector of the last lateral P-type triode.

[0040] When the high-voltage pin 100 introduces an electrostatic discharge voltage, the energy of the electrostatic discharge voltage can sequentially break down the drain terminal 101 and the source terminal 105 of the N-type MOS transistor 10 to reach one end of the P-type triode unit 20, and sequentially break down the emitter and collector of each lateral P-type triode in the P-type triode unit 20 to reach the ground wire pin to complete the energy discharge of the positive electrostatic discharge voltage.

[0041] When the ground wire pin 115 introduces an electrostatic discharge voltage, the energy of the electrostatic discharge voltage can sequentially pass through the collector of each lateral P-type triode in the P-type triode unit 20 and the short-circuited end of the base and emitter to reach one end of the P-type triode unit 20, and reach the high-voltage pin through two parallel PN junctions formed between the substrate terminal 104 and the drain terminal 101 of the N-type MOS transistor 10 and between the substrate terminal and the isolation terminal to complete the energy discharge of the negative electrostatic voltage.

[0042] Therefore, for the problem that the electrostatic discharge ability of high-voltage devices in the prior art is weak, the high-voltage electrostatic protection structure provided by the present invention adopts a series connection method of a lateral P-type triode and an isolated N-type MOS transistor NMOS, so that its electrostatic discharge level is equivalent to that of a single lateral P-type triode or an isolated N-type MOS transistor NMOS, that is, the ESD discharge ability is strong. At the same time, in the present invention, at one end close to the ground wire pin, a plurality of lateral P-type triodes are connected, that is, the characteristic of the relatively high holding voltage of the lateral P-type triode is utilized to meet the requirement that this ESD structure can be used for high-voltage pins; in addition, at one end of the high-voltage pin in the present invention, an isolated N-type MOS transistor is used to connect the high-voltage pin and the lateral P-type triode. Since the high-voltage pin in the present invention is connected to an NMOS, that is, the high-voltage pin is not connected to a P-type region, a PNPN latch structure will not be formed with the PN junction (that is, the PN junction formed by the P-type ground and the N-type region at the negative pulse pin), thereby avoiding the failure of the circuit in the case of extreme negative pulses and greatly improving the reliability of the circuit.

[0043] In the embodiment of the present invention, the breakdown voltage range of the N-type MOS transistor 10 is 8V to 10V, and the breakdown voltage range of each lateral P-type triode in the P-type triode unit 20 is 13V to 17V.

[0044] It should be understood that in the embodiments of the present invention, the number of the lateral P-type triodes included in the P-type triode unit 20 is related to the withstand voltage requirement, and can be specifically set according to the requirement, which is not limited herein.

[0045] In the embodiments of the present invention, the structure of the N-type MOS transistor is a first multi-finger bar structure, and the finger bar range of the first multi-finger bar structure is 8 to 12, and the total width of the structure of the N-type MOS transistor is at least 400 μm.

[0046] In the embodiments of the present invention, the structure of the lateral P-type triode is a second multi-finger bar structure, and the finger bar range of the second multi-finger bar structure is 10 to 16, and the total width of the structure of the lateral P-type triode is at least 1200 μm.

[0047] It should be understood that by setting the finger bar structure of the N-type MOS transistor to be 8 to 12 and setting the total width of the structure of the N-type MOS transistor to be at least 400 μm, the basic ESD function of the high-voltage electrostatic protection structure can be realized while ensuring the manufacturing process. Similarly, by setting the finger bar structure of the lateral P-type triode to be 10 to 16 and setting the total width of the structure of the lateral P-type triode to be at least 1200 μm, the basic ESD function of the high-voltage electrostatic protection structure can be realized while ensuring the manufacturing process.

[0048] In the embodiments of the present invention, as Figure 2 shown, the N-type MOS transistor 10 includes: a P-type substrate 200, an N-type buried layer 201 disposed on the surface of the P-type substrate 200 and extending into the P-type substrate 200, and a P-type epitaxial layer 202 disposed on the surface of the P-type substrate 200;

[0049] A plurality of active regions are disposed in the P-type epitaxial layer 202, and a field region is formed between adjacent active regions;

[0050] An external oxide layer and a metal wire are disposed on the surface of the P-type epitaxial layer 202.

[0051] Specifically, a first active region to a seventh active region are sequentially and spaced apart in the P-type epitaxial layer, a field region is disposed between every two adjacent active regions, and a field oxide layer is disposed at the position of the field region;

[0052] Deep P-well regions extending inward from the surface of the P-type epitaxial layer are formed below the first active region and the seventh active region, a P-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep P-well region, a P+ implantation diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the P-well region, and the P+ implantation diffusion region is connected to the metal wire to serve as an extraction terminal of the P-type epitaxial layer and the P-type substrate, and is connected to the ground wire pin;

[0053] Below both the second active region and the sixth active region, a deep N-well region extending inward from the surface of the P-type epitaxial layer is formed. An N-well region extending inward from the surface of the P-type epitaxial layer is formed within the deep N-well region. An N+ implanted diffusion region extending inward from the surface of the P-type epitaxial layer is formed within the N-well region. The N+ implanted diffusion region is connected to a metal wire to serve as the isolation terminal lead-out terminal of the N-type MOS transistor and is connected to the high-voltage pin.

[0054] Below the third active region, the fourth active region, and the fifth active region, a connected P-well region is formed. P+ implanted diffusion regions are provided at the positions of the third active region and the fifth active region. The P+ implanted diffusion region is connected to a metal wire to serve as the substrate terminal lead-out terminal of the N-type MOS transistor.

[0055] Specifically, polysilicon is provided on the surface of the P-type epitaxial layer at the corresponding position of the fourth active region. The polysilicon is connected to the metal wire to serve as the gate terminal lead-out terminal of the N-type MOS transistor.

[0056] Below the fourth active region and on both sides of the polysilicon, N+ implanted diffusion regions are provided. The N+ implanted diffusion region is connected to the metal wire to serve as the source terminal lead-out terminal and the drain terminal lead-out terminal of the N-type MOS transistor.

[0057] In the embodiment of the present invention, the metal wire serving as the drain terminal lead-out terminal of the N-type MOS transistor and the metal wire serving as the isolation terminal lead-out terminal of the N-type MOS transistor are both connected to the high-voltage pin. The metal wire serving as the gate terminal lead-out terminal of the N-type MOS transistor, the metal wire serving as the source terminal lead-out terminal of the N-type MOS transistor, and the metal wire serving as the substrate terminal lead-out terminal of the N-type MOS transistor are all short-circuited together.

[0058] Specifically, the outer oxide layer is removed at the corresponding positions of the active region and the polysilicon to form a plurality of contact holes. The metal wire is located within the contact holes.

[0059] Among them, the bottom end of the metal wire located within the contact hole is in contact with the active region, and the top end of the metal wire located within the contact hole serves as the lead-out terminal of the N-type MOS transistor.

[0060] In the embodiment of the present invention, as Figure 2As shown, it is a longitudinal structure schematic diagram of the N-type MOS transistor 10. Specifically, above the P-type substrate 200, there is a layer of P-type epitaxial layer 202, and the isolation NMOS transistors are fabricated in this P-type epitaxial layer. Between the P-type substrate 200 and the P-type epitaxial layer 202, there is an N-type buried layer 201. On the surface of the P-type epitaxial layer, there are successively a first active region 212, a second active region 213, a third active region 214, a fourth active region 215, a fifth active region 216, a sixth active region 217, and a seventh active region 218. On both sides of each active region, there is a field region, and on the field region, there is a field oxide layer 209 with a thickness of 5500 - 7000 angstroms, serving as the isolation between the active regions.

[0061] In the embodiment of the present invention, at the first active region 212 and the seventh active region 218, there are deep P-well regions 203, serving as the isolation ground terminals of the isolation NMOS transistors. Inside the deep P-well regions 203, there are P+ implanted diffusion regions 207 and shallow P-well regions 205, used to increase the doping concentration at this place, and form good ohmic contacts through contact holes and metal wires, serving as the lead-out terminals of the isolation ground terminals. At the second active region 213 and the sixth active region 217, there are deep N-well regions 204. The deep N-well regions 204 diffuse 5 - 6 micrometers downward from the P-type epitaxial surface and contact and communicate with the N-type buried layer 201. Inside the deep N-well regions 204, there are N+ implanted diffusion regions 208 and shallow N-well regions 206, used to increase the doping concentration at this place, and form good ohmic contacts through contact holes and metal wires, serving as the lead-out terminals of the isolation ports of the isolation NMOS transistors.

[0062] In the embodiment of the present invention, below the third active region 214, the fourth active region 215, and the fifth active region 216, there is a large P-well region 205. At the positions of the third active region 214 and the fifth active region 216 inside the large P-well region 205, there are P+ implanted diffusion regions, used to increase the doping concentration at this place, and form good ohmic contacts through contact holes and metal wires, serving as the contact lead-out of the large P-well region 205, which is the substrate terminal of the isolation NMOS. At the position of the fourth active region 215 inside the large P-well region 205, three N+ implanted diffusion regions 208 and two polysilicon regions 211 are arranged at intervals. Among them, the two N+ implanted diffusion regions 208 close to the two side field oxide layers 209 both form good ohmic contacts through contact holes and metal wires, serving as the source lead-out terminals of the isolation NMOS; the middle N+ implanted diffusion region 208 also forms good ohmic contacts through contact holes and metal wires, serving as the drain lead-out terminal of the isolation NMOS. The two polysilicon regions 211 arranged at intervals between the three N+ implanted diffusion regions 208 both form good ohmic contacts through contact holes and metal wires, serving as the gate lead-out terminals of the isolation NMOS.

[0063] In the embodiment of the present invention, an external oxide layer 210 covering the entire wafer surface is provided above all field oxide layers and active regions, with a thickness of 7000 - 12000 angstroms. The external oxide layer 210 is removed at corresponding positions of the P+ implantation diffusion regions 207 in the first active region 212, the third active region 214, the fifth active region 216, and the seventh active region 218, as well as at corresponding positions of the N+ implantation diffusion regions 208 in the second active region 213, the fourth active region 215, and the sixth active region 217, to form contact holes reaching the silicon surface; at the position of each contact hole, a metal wire 219 is provided to contact the silicon surface, and each port of the isolated NMOS transistor is respectively led out to form a complete isolated NMOS transistor structure.

[0064] Through the structure shown in the embodiment of the present invention Figure 2 and in combination with the foregoing Figure 1 circuit structure diagram, it can be seen that the metal wire of the gate 211 of the isolated NMOS transistor, the metal wire of the source 208 in the fourth active region 215, and the metal wires of the substrates 207 in the third active region 214 and the fifth active region 216 are short-circuited together. The metal wire of the drain 208 in the fourth active region 215 of the isolated NMOS transistor is connected to the high-voltage pin; the metal wires of the isolation terminals 208 in the second active region 213 and the sixth active region 217 of the isolated NMOS transistor are connected to the high-voltage pin.

[0065] In the embodiment of the present invention, the P-type triode unit 20 including three lateral P-type triodes is taken as an example for illustration. As Figure 1 shown, the P-type triode unit 20 includes a first lateral P-type triode LPNP1, a second lateral P-type triode LPNP2, and a third lateral P-type triode LPNP3. The base 108 and the emitter 106 of the first lateral P-type triode LPNP1 are short-circuited and then connected to the source terminal 105 of the isolated N-type MOS transistor NMOS. The collector 107 of the first lateral P-type triode LPNP1 is connected to the short-circuited terminal of the base 111 and the emitter 109 of the second lateral P-type triode LPNP2. The collector 110 of the second lateral P-type triode LPNP2 is connected to the short-circuited terminal of the base 114 and the emitter 112 of the third lateral P-type triode LPNP3. The collector 113 of the third lateral P-type triode LPNP3 is connected to the ground wire pin 115.

[0066] In the embodiment of the present invention, as Figure 3 shown, it is a longitudinal structure diagram of a lateral PNP transistor. Figure 1 The longitudinal structures and sizes of the first lateral PNP transistor LPNP1, the second lateral PNP transistor LPNP2, and the third lateral PNP transistor LPNP3 in

[0067] As Figure 3 shown, above the P-type substrate 300 of the lateral PNP transistor, there is a P-type epitaxial layer 302 of the lateral PNP transistor, and the lateral PNP transistor is fabricated in the P-type epitaxial layer 302 of the lateral PNP transistor. Between the P-type substrate 300 of the lateral PNP transistor and the P-type epitaxial layer 302 of the lateral PNP transistor, there is an N-type buried layer 301 of the lateral PNP transistor. On the surface of the P-type epitaxial layer of the lateral PNP transistor, there are successively the first active region 312 of the lateral PNP transistor, the second active region 313 of the lateral PNP transistor, the third active region 314 of the lateral PNP transistor, the fourth active region 315 of the lateral PNP transistor, the fifth active region 316 of the lateral PNP transistor, the sixth active region 317 of the lateral PNP transistor, the seventh active region 318 of the lateral PNP transistor, the eighth active region 319 of the lateral PNP transistor, and the ninth active region 320 of the lateral PNP transistor. On both sides of the active region of each lateral PNP transistor, there is a field region of the lateral PNP transistor, and on the field region of the lateral PNP transistor, there is a field oxide layer 309 of the lateral PNP transistor with a thickness of 5500 - 7000 angstroms, serving as the isolation between every two active regions of the lateral PNP transistors.

[0068] In this embodiment, deep P-well regions 303 of the lateral PNP transistor are provided at both the first active region 312 and the ninth active region 320 of the lateral PNP transistor, serving as the isolated ground terminal of the lateral PNP transistor. Inside the deep P-well region 303 of the lateral PNP transistor, there are a P+ implantation diffusion region 307 and a shallow P-well region 305 of the lateral PNP transistor, used to increase the doping concentration at this location, and form a good ohmic contact through contact holes and metal wires, serving as the lead-out terminal of the isolated ground terminal. Below the second active region 313 to the eighth active region 319 of the lateral PNP transistor, there is a large deep N-well region 304 of the lateral PNP transistor. The deep N-well region 304 of the lateral PNP transistor diffuses 5 - 6 microns downward from the P-type epitaxial surface of the lateral PNP transistor and contacts and communicates with the N-type buried layer 301 of the lateral PNP transistor. Inside the deep N-well region 304 of the lateral PNP transistor at the positions of the second active region 313 and the eighth active region 319 of the lateral PNP transistor, there are an N+ implantation diffusion region 308 and a shallow N-well region 306 of the lateral PNP transistor, used to increase the doping concentration at this location, and form a good ohmic contact through contact holes and metal wires, serving as the base lead-out terminal of the lateral PNP transistor.

[0069] In an embodiment of the present invention, at the active region position of each lateral PNP transistor from the third active region 314 to the seventh active region 318 of the lateral PNP transistor, a P+ implantation diffusion region 307 of the lateral PNP transistor is provided. Among them, the P+ implantation diffusion regions 307 of the lateral PNP transistor at the third active region 314, the fifth active region 316, and the seventh active region 318 of the lateral PNP transistor all form good ohmic contacts through contact holes and metal wires, serving as the collector lead-out terminal of the lateral PNP transistor. The P+ implantation diffusion regions 307 of the lateral PNP transistor at the fourth active region 315 and the sixth active region 317 of the lateral PNP transistor form good ohmic contacts through contact holes and metal wires, serving as the emitter lead-out terminal of the lateral PNP transistor.

[0070] In an embodiment of the present invention, above the field oxide layer and the active region of all lateral PNP transistors, an external oxide layer 310 of the lateral PNP transistor covering the entire wafer surface is provided, with a thickness of 7000 - 12000 angstroms. The external oxide layer 310 of the lateral PNP transistor will be removed at the corresponding positions of the P+ implantation diffusion regions 307 at the first active region 312, the third active region 314 to the seventh active region 318, and the ninth active region 320 of the lateral PNP transistor, as well as at the corresponding positions of the N+ implantation diffusion regions 308 of the lateral PNP transistor at the second active region 313 and the eighth active region 319 of the lateral PNP transistor, to form contact holes reaching the silicon surface; at the position of each contact hole, a metal wire 321 of the lateral PNP transistor is provided to contact the silicon surface, leading out each port of the lateral PNP transistor respectively to form a complete lateral PNP transistor structure.

[0071] In an embodiment of the present invention, Figure 3 As can be seen from the structure shown and in combination with the aforementioned Figure 1 circuit structure diagram, the metal wires of the base 308 in the second active region 313 and the eighth active region 319 of the lateral PNP transistor of the first lateral PNP transistor LPNP1 are short-circuited together with the metal wires of the emitter 307 in the fourth active region 315 and the sixth active region 317 of the lateral PNP transistor. At the same time, the base metal wires and emitter metal wires of the second lateral PNP transistor LPNP2 and the third lateral PNP transistor LPNP3 are also short-circuited together like those of the first lateral PNP transistor LPNP1, and the first lateral PNP transistor LPNP1 to the third lateral PNP transistor LPNP3 are connected in series.

[0072] Therefore, the high-voltage electrostatic protection structure provided by the embodiments of the present invention can specifically be composed of an isolated low-voltage NMOS and three low-voltage lateral PNP transistors connected in series. Its ESD discharge ability depends on the weakest device in the series path. Since both the low-voltage NMOS and the low-voltage lateral PNP have strong discharge abilities, the discharge ability of the high-voltage electrostatic protection structure of the embodiments of the present invention is relatively strong. Moreover, since the holding voltage of the low-voltage lateral PNP transistor is relatively high (almost the same as its breakdown voltage), the holding voltage of the structure of the present invention is equal to the sum of the holding voltage of the NMOS and the holding voltages of the three PNP transistors. Therefore, the holding voltage of the high-voltage electrostatic protection structure of the embodiments of the present invention is relatively high (about 50V) and can be used for high-voltage pins and power pins. Additionally, when a negative pulse appears at the N-type port connected to the other pins, since the high-voltage pin is connected to the high-voltage electrostatic protection structure of the present invention, that is, the N-type region of the isolated NMOS is connected to the high-voltage pin and cannot form a PNPN latch structure with the negative-pulse N-type ports of the other pins, thus protecting the circuit well. The following will be described in conjunction with Figures 1 to 3 as shown, the process of electrostatic discharge energy from introduction to release will be elaborated.

[0073] According to Figure 1 as shown, the isolated NMOS connected to the high-voltage pin is specifically a structure with the gate, source, and substrate short-circuited. The breakdown voltage between its drain and source is generally 10V, while the breakdown voltage from its isolation port to the ground terminal is greater than 70V (i.e., Figure 2 the junction breakdown between the deep N-well region 204 and the deep P-well region 203 in Figure 3Junction breakdown between the medium-depth N-well region 304 and the deep P-well region 303). LPNP2 and LPNP3 connected in series with LPNP1 have the same structure, connection method, and breakdown voltage at each port as LPNP1. When an electrostatic discharge voltage is introduced to the high-voltage pin 100, the isolation NMOS is in the cut-off state with the gate and source shorted. Since the breakdown voltage from the isolation port to the ground terminal is greater than 70V, the electrostatic discharge energy will break down the drain-source junction (10V) of the isolation NMOS with a lower breakdown voltage, and then the electrostatic discharge energy reaches the emitter of the lateral PNP transistor (LPNP1). At this time, since the emitter and base of LPNP1 are shorted and the breakdown voltage from the shorted terminal to the ground terminal is greater than 70V, the electrostatic discharge energy will break down the emitter and collector of LPNP1 with a lower breakdown voltage, and then the electrostatic discharge energy reaches the emitter of the lateral PNP transistor (LPNP2). Similarly, the electrostatic discharge energy gradually breaks down the emitters and collectors of LPNP2 and LPNP3, and finally reaches the ground pin 115, completing the discharge of the electrostatic discharge energy from the high-voltage pin 100 to the ground pin 115. It should be noted that when the electrostatic discharge current reaches a certain level, the parasitic NPN in the isolation NMOS will be activated, and the ESD energy will be discharged relying on this NPN. Conversely, when electrostatic discharge energy is introduced from the ground pin 115, LPNP3 is in the forward-biased state of the collector and base at this time. The electrostatic discharge energy passes through a PN junction (0.7V) and reaches the shorted terminal of the base and emitter of LPNP3, which is the collector of LPNP2. Similarly, both LPNP2 and LPNP1 are in the forward-biased state of the collector and base. Therefore, the electrostatic discharge energy passes through two PN junctions (1.4V) and reaches the shorted terminal of the source and substrate of the isolation NMOS. Finally, through the two parallel PN junctions of the substrate and drain, and the substrate and isolation port, the electrostatic discharge energy reaches the high-voltage pin, thus completing its discharge from the ground pin 115 to the high-voltage pin 100. Therefore, the high-voltage electrostatic protection structure of the present invention can achieve the discharge of positive and negative ESD energy from the high-voltage pin to the ground pin. When there are negative pulses on the other pins, since the high-voltage pin is connected to the N-type region of the electrostatic discharge structure of the present invention, it will not form a destructive latch-up PNPN structure with the negative pulses on the other pins, thus well ensuring the safety and reliability of the circuit under extremely harsh conditions.

[0074] In summary, the high-voltage electrostatic protection structure provided by the present invention has the following advantages: (1) This structure can perform bidirectional discharge of electrostatic discharge energy between the high-voltage pin and the ground pin; (2) The ESD discharge ability of this high-voltage electrostatic protection structure will not decrease compared with the low-voltage ESD structure, and still has a strong discharge ability; (3) The holding voltage of this high-voltage electrostatic protection structure is equal to the sum of the holding voltages of the isolated NMOS and multiple PNP transistors, which can meet the use of high-voltage power supplies (specifically, in the embodiment of the present invention, it is the sum of the holding voltages of the NMOS and 3 LPNPs, that is: 6 + 15 + 15 + 15 = 51V. Therefore, this structure can meet the use of a 50V high-voltage power supply); (4) When an abnormal negative pulse appears on the remaining pins, the high-voltage pin connected to this high-voltage electrostatic protection structure has strong shielding and will not form a latch structure with the remaining pins, thereby improving the reliability and safety of the circuit under extreme conditions and extending the service life of the circuit. Therefore, the high-voltage electrostatic protection structure of the present invention can fully achieve good electrostatic protection for the high-voltage pins (including power supply pins) of the circuit and has high reliability against negative pulses.

[0075] It should be understood that for the convenience of description, the present invention only exemplifies the ESD protection structure when the high-voltage pin is 50V. For those skilled in the art, it is easy to obtain high-voltage electrostatic protection structures with different voltage levels by increasing or decreasing the number of lateral PNP transistors or increasing the number of isolated NMOS transistors. At the same time, for the convenience of description, the present invention only exemplifies the structure with 2 finger numbers for both the isolated NMOS and the lateral PNP transistors. For those skilled in the art, it is easy to obtain structures with different ESD discharge abilities by increasing the finger numbers. The high-voltage electrostatic protection structure proposed by the present invention can be applied not only between the high-voltage pin and the ground pin described in the text, but also between other different functional pins.

[0076] As another embodiment of the present invention, an electronic device is provided, which includes: a power supply circuit and the high-voltage electrostatic protection structure described above. The high-voltage pin of the power supply circuit is connected to the N-type MOS transistor of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the P-type triode unit of the high-voltage electrostatic protection structure.

[0077] The electronic device according to the embodiment of the present invention adopts the high-voltage electrostatic protection structure described above, can be applied to a high-voltage power supply circuit, can play an electrostatic protection role under high voltage of the power supply circuit, improves the reliability and safety of the power supply circuit under extreme conditions, and extends the service life of the power supply circuit.

[0078] Regarding the specific working principle of the electronic device of the present invention, reference can be made to the specific description of the high-voltage electrostatic protection structure above, and details will not be elaborated here.

[0079] It is understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A high voltage electrostatic protection structure, characterized in that: include: An N-type MOS tube and a P-type triode unit connected to the N-type MOS tube, The N-type MOS tube is a low-voltage isolation structure, the isolation end and the drain end of the N-type MOS tube are both used to connect to the high-voltage pin, the gate end, the source end and the substrate end of the N-type MOS tube are short-circuited and connected to one end of the P-type triode unit, and the other end of the P-type triode unit is connected to the ground pin; The P-type transistor unit includes at least one lateral P-type transistor, a plurality of the lateral P-type transistors are connected in series, the base and emitter of each lateral P-type transistor are short-circuited, wherein the base and emitter of the first lateral P-type transistor are short-circuited to form one end of the P-type transistor unit, and the collector of the last lateral P-type transistor forms the other end of the P-type transistor unit; When the electrostatic discharge voltage is introduced into the high-voltage pin, the energy of the electrostatic discharge voltage can sequentially break through the drain terminal and the source terminal of the N-type MOS tube to reach one end of the P-type triode unit, and sequentially break through the emitter and collector of each lateral P-type triode in the P-type triode unit to reach the ground pin to complete the energy discharge of the forward electrostatic discharge voltage; When an electrostatic discharge voltage is introduced into the ground pin, the energy of the electrostatic discharge voltage can reach one end of the P-type transistor unit through the collector and the short-circuited ends of the base and the emitter of each lateral P-type transistor in the P-type transistor unit in turn, and reach the high-voltage pin after passing through two parallel PN junctions formed between the substrate end and the drain end and between the substrate end and the isolation end of the N-type MOS tube to complete the energy discharge of the negative electrostatic voltage.

2. The high voltage electrostatic protection structure according to claim 1, characterized in that: The breakdown voltage of the N-type MOS tube is in the range of 8V to 10V, and the breakdown voltage of each lateral P-type transistor in the P-type transistor unit is in the range of 13V to 17V.

3. The high voltage electrostatic protection structure according to claim 1, characterized in that: The structure of the N-type MOS transistor is a first multi-finger structure, and the number of fingers of the first multi-finger structure ranges from 8 to 12. The total width of the structure of the N-type MOS transistor is at least 400 μm.

4. The high voltage electrostatic protection structure according to claim 1, characterized in that: The structure of the lateral P-type transistor is a second multi-finger structure, and the fingers of the second multi-finger structure range from 10 to 16. The total width of the structure of the lateral P-type transistor is at least 1200 μm.

5. The high voltage electrostatic protection structure according to any one of claims 1 to 4, characterized in that: The N-type MOS transistor comprises: a P-type substrate, an N-type buried layer arranged on the surface of the P-type substrate and extending into the P-type substrate, and a P-type epitaxial layer arranged on the surface of the P-type substrate; A plurality of active regions are arranged in the P-type epitaxial layer, and a field region is formed between adjacent active regions; An outer oxide layer and a metal wire are arranged on the surface of the P-type epitaxial layer.

6. The high voltage electrostatic protection structure according to claim 5, characterized in that: The first active region to the seventh active region are sequentially arranged in the P-type epitaxial layer, a field region is arranged between every two adjacent active regions, and a field oxide layer is arranged at the position of the field region; A deep P-well region extending inward from the surface of the P-type epitaxial layer is formed below the first active region and the seventh active region, a P-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep P-well region, a P+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the P-well region, the P+ injection diffusion region is connected to a metal wire as a lead-out end of the P-type epitaxial layer and the P-type substrate, and is connected to the ground pin; A deep N-well region extending inward from the surface of the P-type epitaxial layer is formed below the second active region and the sixth active region, an N-well region extending inward from the surface of the P-type epitaxial layer is formed in the deep N-well region, an N+ injection diffusion region extending inward from the surface of the P-type epitaxial layer is formed in the N-well region, and the N+ injection diffusion region is connected to a metal wire as an isolation terminal lead-out terminal of the N-type MOS tube and is connected to the high-voltage pin; A connected P-well region is formed below the third active region, the fourth active region and the fifth active region, and a P+ injection diffusion region is set at the position of the third active region and the fifth active region. The P+ injection diffusion region is connected to a metal wire to serve as a substrate terminal lead-out terminal of the N-type MOS tube.

7. The high voltage electrostatic protection structure according to claim 6, characterized in that: Polysilicon is disposed on the surface of the P-type epitaxial layer and at a position corresponding to the fourth active region, and the polysilicon is connected to the metal wire to serve as a gate lead-out terminal of the N-type MOS tube; N+ implant diffusion regions are arranged below the fourth active region and on both sides of the polysilicon. The N+ implant diffusion regions are connected to the metal wires to serve as source and drain terminals of the N-type MOS tube.

8. The high voltage electrostatic protection structure according to claim 7, characterized in that: The metal wire as the drain lead-out terminal of the N-type MOS tube and the metal wire as the isolation end lead-out terminal of the N-type MOS tube are both connected to the high-voltage pin, and the metal wire as the gate lead-out terminal of the N-type MOS tube, the metal wire as the source lead-out terminal of the N-type MOS tube and the metal wire as the substrate end lead-out terminal of the N-type MOS tube are all short-circuited together.

9. The high voltage electrostatic protection structure according to claim 5, characterized in that: The outer oxide layer is located at the corresponding positions of the active area and the polysilicon, and then a plurality of contact holes are formed, wherein the metal wires are located in the contact holes; The bottom end of the metal wire in the contact hole contacts the active area, and the top end of the metal wire in the contact hole serves as the lead end of the N-type MOS tube.

10. An electronic device, characterized in that: include: A power supply circuit and a high-voltage electrostatic protection structure as described in any one of claims 1 to 9, wherein the high-voltage pin of the power supply circuit is connected to the N-type MOS tube of the high-voltage electrostatic protection structure, and the ground pin of the power supply circuit is connected to the P-type transistor unit of the high-voltage electrostatic protection structure.

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