Image sensor integrated chip structure and manufacturing method thereof

Abstract

The present disclosure relates to an image sensor integrated chip (IC) structure. The image sensor IC structure includes a plurality of image sensing elements respectively disposed within a plurality of pixel regions of a pixel array within a substrate. An interlayer dielectric (ILD) structure is disposed on the surface of the substrate and surrounds the one or more interconnects. A plurality of three-dimensional (3D) capacitors are disposed within respective ones of the plurality of pixel regions and coupled to one of the plurality of image sensing elements through one or more interconnects. The plurality of 3D capacitors includes a base region extending parallel to a surface of the substrate and one or more fingers extending outwardly from the base region in a direction perpendicular to the surface of the substrate. The invention further discloses a method for forming the image sensor integrated chip structure.

Description

Technical Field

[0001] Embodiments of the present application relate to an image sensor integrated chip structure and a method for manufacturing the same. Background Art

[0002] Integrated circuits with image sensors are used in a variety of modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal oxide semiconductor (CMOS) image sensors have begun to be widely used, largely replacing charge coupled device (CCD) image sensors. Compared with CCD image sensors, CMOS image sensors are becoming more and more popular due to their low power consumption, small size, fast data processing speed, direct data output and low manufacturing cost. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an image sensor integrated chip (IC) structure is provided, comprising: a plurality of image sensing elements, respectively arranged in a plurality of pixel regions of a pixel array in a substrate; an interlayer dielectric (ILD) structure, arranged on a surface of the substrate and surrounding one or more interconnects; and a plurality of three-dimensional (3D) capacitors, arranged in corresponding pixel regions among the plurality of pixel regions and coupled to one of the plurality of image sensing elements through one or more interconnects, wherein the plurality of 3D capacitors comprise a base region extending parallel to a surface of the substrate and one or more fingers extending outward from the base region in a direction perpendicular to the surface of the substrate.

[0004] According to another aspect of an embodiment of the present application, an image sensor integrated chip (IC) structure is provided, comprising: a plurality of image sensing elements, respectively arranged in a plurality of pixel regions of a pixel array within a substrate; an interlayer dielectric (ILD) structure, arranged on the substrate and surrounding one or more interconnects, the ILD structure comprising a plurality of ILD layers separated by one or more etch stop layers (ESL); and a plurality of three-dimensional (3D) capacitors, arranged in a corresponding one of a plurality of pixel regions below an image sensing element among the plurality of image sensing elements, wherein the plurality of 3D capacitors comprise a lower surface arranged between an outermost wall and an outer side wall facing the same direction.

[0005] According to another aspect of an embodiment of the present application, a method for forming an image sensor integrated chip (IC) structure is provided, comprising: providing a first substrate, the first substrate having multiple pixel regions within a pixel array; forming one or more ILD layers on the first substrate; forming an opening vertically extending through the one or more ILD layers, wherein the opening is laterally backward at a non-zero distance from an opposite side of a pixel region among the multiple pixel regions; forming a capacitor stack within the opening and above the one or more ILD layers; and patterning the capacitor stack to form a capacitor having a horizontally extending section above the one or more ILD layers and a vertically extending section extending through the one or more ILD layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views of some embodiments of the disclosed image sensor integrated chip (IC) structure are shown, which includes a three-dimensional (3D) capacitor located within a pixel region of a pixel array.

[0008] Figure 2 Plan views of some embodiments of the disclosed image sensor IC structure are shown, the image sensor IC structure including a plurality of 3D capacitors located within a pixel region of a pixel array.

[0009] Figure 3 Cross-sectional views of some additional embodiments of the disclosed image sensor IC structure are shown, the image sensor IC structure including a plurality of 3D capacitors located within a pixel region of a pixel array.

[0010] Figure 4A-4D Plan views of some embodiments of image sensor IC structures including 3D capacitors having fingers of different shapes are shown.

[0011] Figure 5 Plan views of some additional embodiments of image sensor IC structures including a plurality of 3D capacitors located within a pixel region of a pixel array are shown.

[0012] Fig. 6A Cross-sectional views of some embodiments of multi-dimensional image sensor IC structures including 3D capacitors within a pixel array are shown.

[0013] Figure 6B-6C Circuit diagrams of some embodiments of image sensor IC circuits including 3D capacitors located within a pixel array are shown.

[0014] Figures 7A-9D , Figure 10A-10C Some embodiments of cross-sectional views of 3D capacitors arranged at different locations within a multi-dimensional image sensor IC structure are shown.

[0015] Figure 11A-11B Some additional embodiments of cross-sectional views of 3D capacitors arranged at different locations within a multi-dimensional image sensor IC structure are shown.

[0016] Figure 12A-12C Some embodiments of cross-sectional views of the disclosed 3D capacitors with different heights are shown.

[0017] Figure 13-Figure 20 Cross-sectional views of some embodiments of methods of forming a 3D capacitor within a pixel region of an image sensor IC structure are shown.

[0018] Figure 21-Figure 28 Cross-sectional views of some additional embodiments of methods of forming a 3D capacitor within a pixel region of an image sensor IC structure are shown.

[0019] Figure 29-Figure 36 Cross-sectional views of some additional embodiments of methods of forming a 3D capacitor within a pixel region of an image sensor IC structure are shown.

[0020] Fig.37 A flow chart illustrating some embodiments of a method of forming a 3D capacitor within a pixel region of an image sensor IC structure. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0023] The image sensor integrated chip (IC) structure includes a CMOS image sensor (CIS), which includes a plurality of pixel areas arranged in a pixel array. The plurality of pixel areas respectively include image sensing elements arranged in a semiconductor substrate and laterally surrounded by an isolation structure, and the isolation structure is configured to electrically isolate adjacent pixel areas. A plurality of microlenses may be arranged on the plurality of pixel areas. The plurality of microlenses are respectively configured to focus incident radiation (e.g., light) onto the image sensing element below. After receiving the incident radiation, the image sensing element is configured to convert the incident radiation into an electrical signal. The electrical signal from the image sensing element may be processed by a signal processing unit to determine an image captured by the CIS.

[0024] As technology advances, the demands on CIS are also increasing. For example, in recent years, CIS has become an integral part of the development of machine vision applications, automotive applications, and more. In such applications, human health may be at risk, so the CIS used must provide accurate image sensing under a wide range of lighting conditions (e.g., achieving wide dynamic range performance while maintaining a good signal-to-noise ratio). To improve performance, many modern CIS structures use capacitors. For example, some CIS structures use capacitors to implement global shutter behavior, which allows each pixel in the pixel array to simultaneously transfer its charge to a memory within the pixel, thereby providing faster frame rates and improved low-light performance.

[0025] As the size of the integrated chip is scaled (e.g., reduced), the size of the pixel area in the integrated chip is also scaled (e.g., reduced). However, the capacitance of a planar capacitor (e.g., a two-dimensional capacitor) cannot be scaled without reducing the capacitance value. This is because the capacitance of a planar capacitor is proportional to the area of ​​the planar capacitor electrode divided by the distance between the electrodes. As the size of the pixel area becomes smaller (e.g., less than about 0.5 microns, less than about 0.3 microns), it becomes increasingly difficult to install a planar capacitor in the pixel area while still providing a capacitance value that enables the associated image sensing integrated chip to have good performance.

[0026] The present disclosure relates to an image sensor integrated chip (IC) structure, which includes a three-dimensional (3D) capacitor located in a pixel area of ​​a pixel array. In some embodiments, the disclosed image sensor IC structure may include a plurality of image sensing elements in a plurality of pixel areas of a pixel array respectively disposed in a substrate. An interlayer dielectric (ILD) structure is disposed on the surface of the substrate and surrounds one or more interconnects. A plurality of three-dimensional (3D) capacitors are arranged in a corresponding one of the plurality of pixel areas and are coupled to one of the plurality of image sensing elements through one or more interconnects. A plurality of 3D capacitors include a base region extending parallel to the substrate surface and one or more fingers extending outward from the base region in a direction perpendicular to the substrate surface. By extending a plurality of 3D capacitors parallel to and perpendicular to the surface, the surface area of ​​the plurality of 3D capacitors can be increased while still arranging the plurality of 3D capacitors in one of the plurality of pixel areas. The increase in capacitance of the plurality of 3D capacitors can improve the performance of the image sensor IC structure (e.g., providing a higher dynamic range, lower KTC noise, etc.).

[0027] Figure 1 A cross-sectional view of some embodiments of the disclosed image sensor IC structure 100 is shown, which includes a 3D capacitor located within a pixel region of a pixel array.

[0028] The image sensor IC structure 100 includes a plurality of image sensing elements 104 (e.g., photodiodes) disposed within a substrate 102. The substrate 102 has a first surface 103a configured to receive incident radiation and a second surface 103b opposite the first surface 103a. One or more gate structures 108 (e.g., transfer gates) are disposed on the second surface 103b. During operation, the plurality of image sensing elements 104 are each configured to generate a current in response to the incident radiation. The current is provided from the plurality of image sensing elements 104 to the one or more gate structures 108.

[0029] A plurality of image sensing elements 104 are disposed within a pixel array 106 including a plurality of pixel regions 106a-106c. In some embodiments, the plurality of image sensing elements 104 within respective pixel regions of the plurality of pixel regions 106a-106c may be laterally separated from one another by one or more isolation structures 107 disposed within the substrate 102. In some embodiments, the one or more isolation structures 107 may include an insulating material (e.g., silicon dioxide) disposed between sidewalls of the substrate 102.

[0030] An interlayer dielectric (ILD) structure 110 is disposed on the second surface 103b of the substrate 102. The ILD structure 110 surrounds a plurality of interconnects 112. One or more of the plurality of interconnects 112 are electrically coupled to one or more gate structures 108. The ILD structure 110 also surrounds a plurality of three-dimensional (3D) capacitors 114. In some embodiments, the plurality of 3D capacitors 114 are respectively disposed in one of the plurality of pixel regions 106a-106b (e.g., directly below one of the plurality of image sensing elements 104). For example, a first 3D capacitor is disposed in a first pixel region 106a, a second 3D capacitor is disposed in a second pixel region 106b, and so on. In some embodiments, the plurality of 3D capacitors 114 are completely confined to an upper pixel region of the plurality of pixel regions 106a-106b. In some embodiments, the plurality of 3D capacitors 114 may be laterally spaced apart from the relative edges of the corresponding pixel regions (e.g., directly covered pixel regions) by a non-zero distance 115.

[0031] In some embodiments, the ILD structure 110 may laterally separate multiple 3D capacitors 114 from the peripheral interconnect structure 112P in the same pixel region. In some embodiments, the peripheral interconnect structure 112P includes a conductive via 112v. Multiple 3D capacitors 114 extend vertically from below the top of the conductive via 112v to below the bottom of the conductive via 112v. In some embodiments, the peripheral interconnect structure 112P may also include an interconnect line 112w having a width greater than the conductive via 112v. Multiple 3D capacitors 114 extend vertically from above the top of the interconnect line 112w to below the bottom of the interconnect line 112w.

[0032] The plurality of 3D capacitors 114 include first electrodes 116 and second electrodes 120, respectively, the first electrodes 116 being separated by a capacitor dielectric 118 along a first direction 126, along a second direction 128, and along a third direction 130 perpendicular to the first direction 126 and the second direction 28. The first electrodes 116, the second electrodes 120, and the capacitor dielectric 118 are arranged within a body region 122 and within one or more fingers 124 extending outwardly from the body region 122 in a direction perpendicular to the second surface 103b of the substrate 102. Within the body region 122, the first electrodes 116 and the second electrodes 120 extend along a plane extending in the first direction 126 and the second direction 128. Within the one or more fingers 124, the first electrodes 116 and the second electrodes 120 extend outwardly from the plane along the third direction 130.

[0033] By separating the first electrode 116 and the second electrode 120 from each other along the first direction 126, the second direction 128, and the third direction 130, the surface area of ​​the first electrode 116 and the surface area of ​​the second electrode 120 can be increased without increasing the footprint of the corresponding capacitors in the plurality of 3D capacitors 114. By increasing the surface area of ​​the first electrode 116 and the second electrode 120, the capacitance of the plurality of 3D capacitors 114 can be increased while still arranging the plurality of 3D capacitors 114 in one of the plurality of pixel regions 106a-106c. The increased capacitance of the plurality of 3D capacitors can provide a relatively high capacitance density in a pixel array having a small pixel region (e.g., a pixel region between about 0.5 micrometers (μm) and about 3 μm). The relatively high capacitance allows the disclosed capacitor to improve pixel array performance (e.g., higher dynamic range, lower KTC noise, etc.) and / or be implemented in a wide range of image sensor circuits (e.g., global shutter circuits, CDS circuits, lateral overflow integration capacitor (LOFIC) pixels, etc.).

[0034] Figure 2 A plan view of some embodiments of the disclosed image sensor IC structure 200 is shown, the structure including a plurality of 3D capacitors located within a pixel region of a pixel array.

[0035] The image sensor IC structure 200 includes a plurality of pixel regions 106a-106c arranged in a pixel array 106 having rows 202 and columns 204. In a plan view, the rows 202 extend along a first direction 126, and the columns 204 extend along a second direction 128 that is perpendicular to the first direction 126. In some embodiments, the plurality of pixel regions 106a-106c may each have a length 206 and a width 208 between about 0.5 micrometers (μm) and about 3 μm, between about 0.5 μm and about 10 μm, or other similar values.

[0036] Each of the plurality of pixel regions 106a-106c includes one of the plurality of 3D capacitors 114 and the peripheral interconnect structure 112P. The plurality of 3D capacitors 114 each include one or more fingers 124 that are separated from each other by the ILD structure 110. The peripheral interconnect structure 112P extends through the ILD structure 110 at a location separated from the plurality of 3D capacitors 114.

[0037] Figure 3 Cross-sectional views of some additional embodiments of the disclosed image sensor IC structure 300 are shown, which includes a plurality of 3D capacitors located within a pixel region of a pixel array.

[0038] The image sensor IC structure 300 includes an ILD structure 110 disposed on a substrate 102. The ILD structure 110 includes a plurality of interlayer dielectric (ILD) layers 302a-302e alternately stacked with a plurality of etch stop layers 304a-304d. In some embodiments, the ILD structure 110 may include a first ILD layer 302a separated from a second ILD layer 302b by a first ESL 304a, a third ILD layer 302c separated from the second ILD layer 302b by a second ESL 304b, a lower fourth ILD layer 302d separated from the third ILD layer 302c by a third ESL 304c, and a 1 and the upper fourth ILD layer 302d 2 , and through the fourth ESL 304d and the upper fourth ILD layer 302d 2 In some embodiments, the first ILD layer 302a may be separated from the substrate 102 by one or more underlying ILD layers (not shown). The lower interconnect structure 112L is disposed within the first ILD layer 302a. The lower interconnect structure 112L may include interconnect lines and / or interconnect vias.

[0039] In some embodiments, the plurality of ILD layers 302a-302e may include oxide (e.g., silicon dioxide), nitride (e.g., silicon nitride, silicon oxynitride), carbide (e.g., silicon carbide), borosilicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), low-k oxide (e.g., carbon-doped oxide, SiCOH), etc. In some embodiments, the first ILD layer 302a may have a first thickness (e.g., about 1000 nm). and Between, about or other similar values), the second ILD layer 302b may have a second thickness (eg, and Between, about or other similar values), the third ILD layer 302c may have a third thickness (eg, to about or other similar values), the fourth ILD layer 302d may have a fourth thickness (eg, to Between, about or other similar values), and the fifth ILD layer 302e may have a fifth thickness (eg, to between about 6200 angstroms, or other similar values).

[0040] In some embodiments, one or more etch stop layers 304a-304d may include silicon nitride, silicon carbide, etc. In some embodiments, one or more etch stop layers 304a-304d may each have a thickness of about Peace Between or other similar value of thickness.

[0041] A plurality of 3D capacitors 114 are arranged on the lower interconnect structure 112L. The plurality of 3D capacitors 114 include a horizontally extending section 114H and a vertically extending section 114V. The vertically extending section 114V extends outward from the bottom of the horizontally extending section 114H and passes through one or more of the plurality of ILD layers 302a-302e. The plurality of 3D capacitors 114 respectively include a lower surface arranged between the outermost sidewall and the outer sidewall facing the same direction.

[0042] In some embodiments, the plurality of 3D capacitors 114 include a first electrode 116 separated from a second electrode 120 by a capacitor dielectric 118. In some embodiments, the first electrode 116 may include a capacitor barrier 116b and a lower capacitor metal 116a located above the capacitor barrier 116b. In some embodiments, the first electrode 116 and the second electrode 120 may have a spacing of about Peace In some embodiments, the thickness of capacitor dielectric 118 may be in the range of about Peace in the range between.

[0043] The first electrode 116 and the second electrode 120 are respectively disposed in the base region 122 and one or more fingers 124 of the 3D capacitor 114. In some embodiments, the base region 122 is disposed in the lower fourth ILD layer 302d. 1 One or more fingers 124 extend outward from the bottom of the base region 122 and pass through the second ILD layer 302b, the third ILD layer 302c and the lower fourth ILD layer 302d. 1 In some embodiments, one or more fingers 124 may each have a height 305 within a range between about 0.5 μm and about 5 μm.

[0044] The second electrode 120 may be laterally set back from the outermost walls of the first electrode 116 and the capacitor dielectric 118. In some embodiments, the second electrode 120 may include a recess 306 arranged along the top thereof and directly above the plurality of fingers 124. The capacitor cap 307 covers the top of the second electrode 120 and extends into the recess 306. In some embodiments, the capacitor cap 307 may include a first upper dielectric 308, a second upper dielectric 310 above the first upper dielectric 308, and a third upper dielectric 312 above the second upper dielectric 310.

[0045] In some embodiments, the first upper dielectric 308 may include an oxide (eg, silicon oxynitride, silicon oxide, etc.). In some embodiments, the second upper dielectric 310 may include silicon oxynitride, etc. In some embodiments, the thickness of the second upper dielectric 310 may be about 1000 Å. To date (about In some embodiments, the third upper dielectric 312 may include silicon nitride or the like. In some embodiments, the thickness of the third upper dielectric 312 may be about Peace (about or other similar values).

[0046] In some embodiments, one or more sidewall spacers 314 are disposed vertically above the capacitor dielectric 118 and laterally between the outermost walls of the electrode 118 and the second electrode 120. The one or more sidewall spacers 314 may cover the sidewalls of the capacitor cap 307. In some embodiments, the one or more sidewall spacers 314 may include a first dielectric spacer layer 314a and a second dielectric spacer layer 314b.

[0047] In some embodiments, the outermost walls of the first electrode 116 and the capacitor dielectric 118 may be in contact with the lower fourth ILD layer 302d. 1 In such an embodiment, the thickness of the lower fourth ILD layer 302d1 directly below the plurality of 3D capacitors 114 is greater than the thickness of the lower fourth ILD layer 302d1 laterally outside the plurality of 3D capacitors 114. 1 Thickness.

[0048] The upper interconnect structure 112U is arranged on the upper fourth ILD layer 302d. 2 The upper interconnect structure 112U extends through the capacitor cap 307 to contact the second electrode 120 .

[0049] It should be understood that one or more fingers of the disclosed 3D capacitor can have various shapes and / or configurations. Different shapes and / or configurations allow for different capacitance values ​​and / or interconnect routing flexibility. Figure 4A-4D Some embodiments of plan views of image sensor IC structures with different finger arrangements are shown. Figure 4A-4D The plan views shown are not limiting but are merely examples of some arrangements of the fingers.

[0050] Figure 4A A plan view of some embodiments of an image sensor IC structure 400 having a 3D capacitor with rectangular fingers is shown.

[0051] The image sensor IC structure 400 includes pixel regions 106a-106b within an ILD structure 110 on a substrate. A plurality of 3D capacitors 114 are disposed within the pixel regions 106a-106b and are surrounded by the ILD structure 110. The plurality of 3D capacitors 114 include a first electrode 116 separated from a second electrode 120 by a capacitor dielectric 118. The outermost perimeter of the top surfaces of the first electrode 116' and the second electrode 120' is shown in dashed lines. A plurality of fingers 124 are located below the top surfaces of the first electrode 116 and the second electrode 120. The plurality of fingers 124 have a rectangular shape, the rectangular shape extending in a first direction 126 by a length that is less than the length in a second direction 128. Within a corresponding finger of the plurality of fingers 124, the first electrode 116 is separated from the second electrode 120 by the capacitor dielectric 118. In some embodiments, respective fingers of the plurality of fingers 124 may have a width 402 measured along the first direction 126 that is within a range between 0.01 μm and approximately 10 μm, approximately 1 μm and approximately 10 μm, or other similar values.

[0052] Figure 4B A plan view of some embodiments of an image sensor IC structure 404 with a 3D capacitor having circular fingers is shown.

[0053] The image sensor IC structure 404 includes pixel regions 106a-106b within the ILD structure 110 on the substrate. A plurality of 3D capacitors 114 are arranged within corresponding pixel regions in the pixel regions 106a-106b. The plurality of 3D capacitors 114 include a plurality of fingers 124 located below the top surfaces of the first electrode 116 and the second electrode 120. The plurality of fingers 124 are separated from each other along the first direction 126. The plurality of fingers 124 each have a circular shape. In some embodiments, a corresponding finger in the plurality of fingers 124 may have a width 406 measured along the second direction 128, the width 406 being between about 0.01 μm and about 10 μm, about 1 μm and about 10 μm, or other similar values.

[0054] Figure 4C A plan view of some embodiments of an image sensor IC structure 408 having a 3D capacitor with fingers surrounding an interlayer dielectric pillar is shown.

[0055] The image sensor IC structure 408 includes pixel regions 106a-106b within an ILD structure 110 on a substrate. A plurality of 3D capacitors 114 are arranged within corresponding pixel regions in the pixel regions 106a-106b. The plurality of 3D capacitors 114 include fingers 124 arranged below the top surfaces of the first electrode 116 and the second electrode 120. The fingers 124 have a closed shape that continuously surrounds one or more pillars 111 of the ILD structure 110 directly below the top surfaces of the first electrode 116 and the second electrode 120. Within the fingers 124, portions of the first electrode 116, the second electrode 120, and the capacitor dielectric 118 may concentrically surround one or more pillars 111 of the ILD structure 110.

[0056] In some embodiments, fingers 124 include segments extending along first direction 126 that are coupled with segments extending along second direction 128. In some embodiments, segments extending along first direction 126 can have a width 410 measured along second direction 128 that ranges between about 0.01 μm and about 10 μm, between about 1 μm and about 10 μm, or other similar values.

[0057] Figure 4D A plan view of some embodiments of an image sensor IC structure 412 having a 3D capacitor with fingers surrounding an interlayer dielectric pillar is shown.

[0058] The image sensor IC structure 412 includes pixel regions 106a-106b within an ILD structure 110 on a substrate. A plurality of 3D capacitors 114 are arranged within corresponding pixel regions in the pixel regions 106a-106b. The plurality of 3D capacitors 114 include fingers 124 arranged below the top surfaces of the first electrode 116 and the second electrode 120. The fingers 124 have a closed shape that continuously surrounds one or more pillars 111 of the ILD structure 110, which are directly below the top surfaces of the first electrode 116 and the second electrode 120. In some embodiments, the fingers 124 include segments extending along a first direction 126, which are coupled with segments extending along a second direction 128.

[0059] Figure 5 Plan views of some additional embodiments of image sensor IC structures 500 including 3D capacitors within a pixel array are shown.

[0060] Image sensor IC structure 500 includes a plurality of pixel regions 106a-106b arranged in pixel array 106 having rows 202 and columns 204. Rows 202 extend along a first direction 126 and columns 204 extend along a second direction 128 perpendicular to first direction 126 in a plan view.

[0061] Each of the plurality of pixel regions 106a-106b includes two or more of the plurality of 3D capacitors 114 and a peripheral interconnect structure 112P that is separated from the plurality of 3D capacitors 114 by the ILD structure 110. For example, the first pixel region 106a includes a first 3D capacitor and a second 3D capacitor separated by the ILD structure 110. The plurality of 3D capacitors 114 include one or more fingers 124, respectively, that are separated from each other by the ILD structure 110.

[0062] Fig. 6A A cross-sectional view of some embodiments of a multi-dimensional image sensor IC structure 600 including a 3D capacitor within a pixel array is shown.

[0063] The multi-dimensional image sensor IC structure 600 includes a plurality of integrated chip (IC) levels 602a-602b stacked on top of each other. In some embodiments, the multi-dimensional image sensor IC structure 600 may include a three-dimensional integrated chip (3DIC) structure. In some embodiments, the plurality of IC levels 602a-602c include a first level 602a and a second level 602b. In some additional embodiments, the plurality of IC levels 602a-602c include additional layers (e.g., a third level, a fourth level, etc.).

[0064] The first level 602a includes a plurality of image sensing elements 104 disposed within a first substrate 102a. The plurality of image sensing elements 104 are disposed within a pixel array 106 including a plurality of pixel regions 106a-106c. In some embodiments, a floating diffusion region 604 may also be disposed within the first substrate 102a. A plurality of gate structures 108 are disposed on and / or within the first substrate 102a, between one of the plurality of image sensing elements 104 and the floating diffusion region 604. A first ILD structure 110a is also disposed on the first substrate 102a. The first ILD structure 110a surrounds a first plurality of interconnects 112a. One or more of the first plurality of interconnects 112a are electrically coupled to the plurality of gate structures 108.

[0065] The second level 602b includes a plurality of pixel support devices 606 disposed on and / or within the second substrate 102b. In some embodiments, the plurality of pixel support devices 606 may include one or more of a reset transistor, a source follower transistor, a row select transistor, and the like. In other embodiments, the plurality of pixel support devices 606 may include transistors configured to operate as an analog-to-digital converter, an amplifier, a multiplexer, a correlated double sampling circuit, a global shutter circuit, a lateral overflow integral capacitor (LOFIC) pixel, and the like. The plurality of pixel support devices 606 are connected to a second ILD structure 110b surrounding a second plurality of interconnects 112b. In various embodiments, the plurality of pixel support devices 606 may include a planar FET, a FinFET, a gate-all-around (GAA) transistor, a nanosheet transistor, and the like. In some embodiments, the first ILD structure 110a is bonded to the second ILD structure 110b along a bonding interface including one or more conductive interfaces and one or more dielectric interfaces.

[0066] A plurality of color filters 608 are disposed on the back side of the first substrate 102a, and a plurality of micro lenses 610 are arranged above the plurality of color filters 608. The plurality of micro lenses 610 directly cover the plurality of image sensing elements 104 in one of the plurality of pixel regions 106a-106c, respectively.

[0067] It should be appreciated that the disclosed 3D capacitors can be used in a wide range of image sensing applications. Figure 6B-6C Two exemplary circuit diagrams showing applications of the disclosed 3D capacitor are shown. It should be understood that these examples are non-limiting examples and the disclosed 3D capacitor may also be used in other applications.

[0068] In some embodiments, Figure 6B As shown in the exemplary circuit diagram 612 of the multi-dimensional image sensor IC structure, multiple 3D capacitors 114 can be implemented in a lateral overflow integration capacitor (LOFIC) pixel. In some such embodiments, multiple 3D capacitors 114 can be configured to work as a charge storage capacitor CS in each pixel (PIX) area. The charge storage capacitor CS and the charge storage gate SG are arranged between the floating diffusion node FD and the reset transistor RS. In some embodiments, the floating diffusion node MD can be arranged in the first level 602a, and the reset transistor RS can be arranged in the second level 602b.

[0069] During the exposure operation, the potential heights of the transfer gate TG and the charge storage gate SG are designed so that once the photodiode PD is saturated, the overflowing charge from the photodiode PD will be accumulated in the floating diffusion capacitor (CFD). When the floating diffusion node FD is saturated, the excess charge will flow into the charge storage capacitor CS through the charge storage gate SG. Therefore, the LOFIC pixel is configured to accumulate charge after the photodiode PD is saturated to allow a high dynamic range.

[0070] In some embodiments, Figure 6C As shown in the exemplary circuit diagram 614 of FIG. 1 , multiple 3D capacitors 114 in the multi-dimensional image sensor IC structure can be implemented in a global shutter scheme. In some such embodiments, multiple 3D capacitors 114 can be configured to be used as reset capacitors C rst and signal capacitor C sig . Reset capacitor C rst is configured to store the reset value. Signal capacitor C sig is configured to store signal values. During operation, in order to eliminate reset noise, within the pixel, the reset value and the signal value are sampled to C rst and C sig The sampled values ​​are used to generate the rst and C sig The size is inversely proportional to the sampling noise.

[0071] In some embodiments, the photodiode PD may be arranged in the first level 602a, and the reset capacitor C rst and signal capacitor C sig can be arranged in the same pixel region of the second level 602b. In other embodiments, the photodiode PD and the reset capacitor C rst It can be arranged in the first level 602a, the signal capacitor C sig The pixels may be arranged in the same pixel region of the second level 602b.

[0072] Although 3D capacitors Fig. 6A , but it should be understood that the disclosed 3D capacitors can be arranged at different locations within the multi-dimensional image sensor IC structure. For example, Figures 7A-11B Some embodiments of 3D capacitors arranged at different locations within a multi-dimensional image sensor IC structure are shown. Figures 7A-11B The embodiments shown are not limiting but are merely examples of some multi-dimensional image sensor IC structures.

[0073] Fig. 7A A block diagram of a multi-dimensional integrated chip structure 700 having a 3D capacitor array arranged within a first level is shown.

[0074] The multi-dimensional integrated chip structure 700 includes a first level 602a and a second level 602b stacked on the first level 602b. The first level 602a includes a pixel array 106, which includes a plurality of image sensing elements (e.g., photodiodes) within a plurality of pixel regions. The first level 602a also includes a 3D capacitor array 702, which includes a plurality of 3D capacitors.

[0075] Figure 7B Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 704 having a three-dimensional capacitor arranged within a first level are shown.

[0076] The multi-dimensional integrated chip structure 704 includes a first level 602a stacked on a second level 602b. The first level 602a includes a first ILD structure 110a disposed on a first substrate 102a. A plurality of image sensing elements 104 are disposed in a pixel array 106 having a plurality of pixel regions 106a-106c within the first substrate 102a. A 3D capacitor array 702 is disposed within the first ILD structure 110a. The 3D capacitor array 702 includes a plurality of 3D capacitors 114 disposed in one of the plurality of pixel regions 106a-106c, respectively. The plurality of 3D capacitors 114 are arranged between the top and bottom of the first ILD structure 110a. In some embodiments, the second level 602b may include one or more pixel support devices 606 (e.g., for CIS circuits, CDS circuits, global shutter circuits, LOFIC circuits, etc.).

[0077] Figure 7C Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 706 with a 3D capacitor arranged within a first layer are shown.

[0078] The multi-dimensional integrated chip structure 706 includes a first level 602a stacked on a second level 602b. The first level 602a includes a pixel array 106, and the pixel array 106 has a plurality of pixel regions 106a-106c in a first substrate 102a. The first level 602a also includes a 3D capacitor array 702, which includes a plurality of 3D capacitors 114 arranged in a first ILD structure 110a on the first substrate 102a. The second level 602b includes one or more pixel support devices 606.

[0079] The first level 602a is coupled to the second level 602b via a bonding region 708 having a bonding interface 709, which includes a conductive interface and a dielectric interface. In some embodiments, the bonding region 708 includes a first bonding connector 712a and a first bonding link 714a disposed within the first insulating layer 710a. The first bonding connector 712a is connected between a plurality of 3D capacitors 114 and the first bonding link 714a. In some embodiments, one or more of the first bonding connector 712a and the first bonding link 714a are arranged directly below the plurality of 3D capacitors 114. The bonding region 708 also includes a second bonding connector 712b and a second bonding link 714b disposed within the second insulating layer 710b. The first bonding link 714a is connected to the second bonding link 714b along the bonding interface 709.

[0080] Fig.7D Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 716 with a 3D capacitor arranged within a first layer are shown.

[0081] The multi-dimensional integrated chip structure 716 includes a first level 602a coupled to a second level 602b via a bonding region 708. The bonding region 708 includes a first bonding connector 712a, a first bonding link 714a, a second bonding connector 712b, and a second bonding link 714b laterally located outside the plurality of 3D capacitors 114. The bonding region 708 also includes one or more dummy bonding links 718 disposed directly below the plurality of 3D capacitors 114. The one or more dummy bonding links 718 are configured to provide sufficient metal density for providing planarization of the first insulating layer 710a and the second insulating layer 710b.

[0082] Fig. 8A A block diagram of a multi-dimensional integrated chip structure 800 having a three-dimensional capacitor array arranged within a second level is shown.

[0083] The multi-dimensional integrated chip structure 800 includes a first level 602a and a second level 602b stacked on the first level 602b. The first level 602a includes a pixel array 106, which includes a plurality of image sensing elements (e.g., photodiodes) within a plurality of pixel regions. The second level 602b includes a 3D capacitor array 702, which includes a plurality of 3D capacitors.

[0084] Figure 8B A cross-sectional view of a multi-dimensional integrated chip structure 802 with a three-dimensional capacitor arranged within a second level is shown.

[0085] The multi-dimensional integrated chip structure 802 includes a first level 602a and a second level 602b stacked on the first level 602a. The first level 602a includes a plurality of image sensing elements 104, which are arranged in a pixel array 106 having a plurality of pixel regions 106a-106c in a first substrate 102a. A first ILD structure 110a is arranged on the first substrate 102a. The second level 602b includes a second ILD structure 110b arranged on the second substrate 102b. A 3D capacitor array 702 is arranged in the second ILD structure 110b. The 3D capacitor array 702 includes a plurality of 3D capacitors 114 respectively arranged in one of the plurality of pixel regions 106a-106c. The plurality of 3D capacitors 114 are arranged between the top and the bottom of the second ILD structure 110b. In some embodiments, the second level 602b may also include one or more pixel support devices 606 (e.g., for CIS circuits, CDS circuits, global shutter circuits, LOFIC circuits, etc.).

[0086] Figure 8C Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 804 having a three-dimensional capacitor disposed within the second layer are shown.

[0087] The multi-dimensional integrated chip structure 804 includes a first level 602a stacked on a second level 602b. The first level 602a includes a pixel array 106, and the pixel array 106 has a plurality of pixel regions 106a-106c in a first substrate 102a. The second level 602b includes a 3D capacitor array 702, which includes a plurality of 3D capacitors 114 arranged in a second ILD structure 110b on the second substrate 102b.

[0088] The first level 602a is coupled to the second level 602b via a bonding region 708 having a bonding interface including a conductive region and a dielectric region. In some embodiments, the bonding region 708 includes a bonding connector 712 and a bonding link 714 disposed within an insulating layer 710. The bonding connector 712 and the bonding link 714 connect the plurality of 3D capacitors 144 to the first level 602a. The bonding connector 712 is located directly above the plurality of 3D capacitors 114 and is directly connected to the bonding link 714.

[0089] Fig.8D Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 806 having a three-dimensional capacitor arranged within the second level are shown.

[0090] The multi-dimensional integrated chip structure 806 includes a first level 602a stacked on a second level 602b. In some embodiments, the first level 602a is coupled to the second level 602b through a bonding region 708 having a bonding interface including a conductive region and a dielectric region.

[0091] The first level 602a includes a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. The second level 602b includes a 3D capacitor array 702 including a plurality of 3D capacitors 114 disposed within a second ILD structure 110b on the second substrate 102b. The second level 602b may also include a second pixel array 808 having a plurality of pixel regions within the second substrate 102b. In some embodiments, the pixel array 106 includes an image sensing element 104 configured to detect incident radiation having a first frequency range (e.g., within an infrared region of the electromagnetic spectrum), and the second pixel array 808 includes an image sensing element 810 configured to detect incident radiation having a second frequency range different from the first frequency range (e.g., within a near infrared region of the electromagnetic spectrum). Although in Fig.8D The 3D capacitor array 702 is shown as being located directly above the second pixel array 808, but it should be understood that in alternative embodiments, the 3D capacitor array 702 and / or interconnects may be arranged laterally outward of the image sensing elements 810 within the second pixel array 808 to increase the incident radiation reaching the second pixel array 808.

[0092] Fig. 9A A block diagram of a multi-dimensional integrated chip structure 900 having a 3D capacitor array arranged within a first level and a second level is shown.

[0093] The multi-dimensional integrated chip structure 900 includes a first level 602a and a second level 602b stacked on the first level 602b. The first level 602a includes a pixel array 106, which includes a plurality of image sensing elements (e.g., photodiodes) within a plurality of pixel regions. The first level 602a also includes a first 3D capacitor array 702a, which includes a plurality of 3D capacitors. The second level 602b includes a second 3D capacitor array 702b, which includes a plurality of 3D capacitors.

[0094] Fig. 9B A cross-sectional view of a multi-dimensional integrated chip structure 902 having three-dimensional capacitors arranged within a first level and a second level is shown.

[0095] The multi-dimensional integrated chip structure 902 includes a first level 602a stacked on a second level 602b. The first level 602a includes a plurality of image sensing elements 104 disposed in a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. A first ILD structure 110a is disposed on the first substrate 102a. The second level 602b includes a second ILD structure 110b disposed on the second substrate 102b.

[0096] The first 3D capacitor array 702a is disposed in the first ILD structure 110a. The first 3D capacitor array 702a includes a plurality of 3D capacitors 114 respectively disposed in one of the plurality of pixel regions 106a-106c. The plurality of 3D capacitors 114 are arranged between the top and the bottom of the first ILD structure 110a. The second 3D capacitor array 702b is disposed in the second ILD structure 110b. The second 3D capacitor array 702b includes a plurality of 3D capacitors 114 respectively disposed in one of the plurality of pixel regions 106a-106c. The plurality of 3D capacitors 114 are arranged between the top and the bottom of the second ILD structure 110b. In some embodiments, the second level 602b may also include one or more pixel support devices 606 (e.g., for CIS circuits, CDS circuits, global shutter circuits, LOFIC circuits, etc.).

[0097] Fig. 9C Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 904 having three-dimensional capacitors arranged within a first layer and a second layer are shown.

[0098] The multi-dimensional integrated chip structure 904 includes a first level 602a coupled to a second level 602b via a bonding region 708 having a bonding interface including a conductive region and a dielectric region. The first level 602a includes a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. A first 3D capacitor array 702a is disposed within a first ILD structure 110a disposed on the first substrate 102a. The second level 602b includes a second 3D capacitor array 702b including a plurality of 3D capacitors 114 disposed within a second ILD structure 110b disposed on the second substrate 102b.

[0099] Fig.9D Cross-sectional views of some additional embodiments of a multi-dimensional integrated chip structure 906 having three-dimensional capacitors arranged within a first level and a second level are shown.

[0100] The multi-dimensional integrated chip structure 906 includes a first level 602a coupled to a second level 602b via a bonding region 708 having a bonding interface including a conductive region and a dielectric region. The first level 602a includes a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. A first 3D capacitor array 702a is disposed within a first ILD structure 110a disposed on the first substrate 102a. The second level 602b includes a second 3D capacitor array 702 including a plurality of 3D capacitors 114 disposed within a second ILD structure 110b disposed on the second substrate 102b. The second level 602b may also include a second pixel array 808 having a plurality of pixel regions within the second substrate 102b. In some embodiments, pixel array 106 includes image sensing elements 104 configured to detect incident radiation having a first frequency range (e.g., in the infrared region of the electromagnetic spectrum), and second pixel array 808 includes image sensing elements 810 configured to detect incident radiation having a second frequency range (e.g., in the near infrared region of the electromagnetic spectrum).

[0101] Fig. 10A A block diagram of a multi-dimensional integrated chip structure 1000 having a 3D capacitor array arranged within a first level, a second level, and a third level is shown.

[0102] The multi-dimensional integrated chip structure 1000 includes a first level 602a, a second level 602b stacked on the first level 602b, and a third level 602c stacked on the second level 602. The first level 602a includes a pixel array 106, and the pixel array 106 includes a plurality of image sensing elements arranged in a plurality of pixel regions. The first level 602a also includes a first 3D capacitor array 702a, which includes a plurality of 3D capacitors. The second level 602b includes a second 3D capacitor array 702b, which includes a plurality of 3D capacitors. The third level 602c includes a third 3D capacitor array 702c, which includes a plurality of 3D capacitors.

[0103] Fig. 10B A cross-sectional view of a multi-dimensional integrated chip structure 1002 having 3D capacitors arranged within a first level, a second level, and a third level is shown.

[0104] The multi-dimensional integrated chip structure 1002 includes a first level 602a, a second level 602b stacked on the first level 602b, and a third level 602c stacked on the second level 602. In some embodiments, the first level 602a is bonded to the second level 602b along a first bonding region 708a. In some embodiments, the second level 602b is bonded to the third level 602c along a second bonding region 708b. In some embodiments, a through substrate via (TSV) 1004 extends vertically through the second substrate 102b to connect the second level 602b to the third level 602c.

[0105] The first level 602a includes a plurality of image sensing elements 104 disposed in a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. A first 3D capacitor array 702a is disposed within a first ILD structure 110a on the first substrate 102a. The first 3D capacitor array 702a includes a plurality of 3D capacitors 114 disposed within one of the plurality of pixel regions 106a-106c, respectively. The plurality of 3D capacitors 114 within the first 3D capacitor array 702a are arranged between a top portion and a bottom portion of the first ILD structure 110a.

[0106] The second level 602b includes a second ILD structure 110b disposed on a second substrate 102b. A second 3D capacitor array 702b is disposed within the second ILD structure 110b. The second 3D capacitor array 702b includes a plurality of 3D capacitors 114 disposed within one of the plurality of pixel regions 106a-106c, respectively. The plurality of 3D capacitors 114 within the second 3D capacitor array 702b are arranged between the top and bottom of the second ILD structure 110b.

[0107] The third level 602c includes a third interconnect structure 110c disposed on a third substrate 102c. A third 3D capacitor array 702c is disposed within the third interconnect structure 110c. The third 3D capacitor array 702c includes a plurality of 3D capacitors 114 disposed in one of the plurality of pixel regions 106a-106c, respectively. The plurality of 3D capacitors 114 within the third 3D capacitor array 702c are arranged between the top and bottom of the third interconnect structure 110c.

[0108] Fig. 10C A cross-sectional view of a multi-dimensional integrated chip structure 1006 with 3D capacitors arranged within a first level, a second level, and a third level is shown.

[0109] The multi-dimensional integrated chip structure 1006 includes a first level 602a, a second level 602b stacked on the first level 602b, and a third level 602c stacked on the second level 602b. The first level 602a includes a plurality of image sensing elements 104, which are disposed in a pixel array 106 having a plurality of pixel regions 106a-106c in a first substrate 102a. A first 3D capacitor array 702a is disposed in a first ILD structure 110a on the first substrate 102a. The second level 602b includes a plurality of image sensing elements 810, which are disposed in a second pixel array 808 having a plurality of pixel regions in a second substrate 102b. The second 3D capacitor array 702b is disposed in a second ILD structure 110b on the second substrate 102b. The third level 602c includes a plurality of image sensing elements 1008, which are disposed in a third pixel array 1006 having a plurality of pixel regions in a third substrate 102c. The third 3D capacitor array 702c is disposed within the third interconnect structure 110c on the third substrate 102c.

[0110] In some embodiments, image sensing element 104 is configured to detect incident radiation having a first frequency range (e.g., within the infrared region of the electromagnetic spectrum), image sensing element 1008 is configured to detect incident radiation having a second frequency range different from the first frequency range (e.g., within the near infrared region of the electromagnetic spectrum), and image sensing element 1008 is configured to detect incident radiation having a third frequency range different from the first and second frequency ranges (e.g., within the far infrared region of the electromagnetic spectrum).

[0111] Fig.11A A block diagram of a multi-dimensional integrated chip structure 1100 having a 3D capacitor array arranged within a first level, a second level, and a third level is shown.

[0112] The multi-dimensional integrated chip structure 1100 includes a first level 602a, a second level 602b stacked on the first level 602a, and a third level 602c stacked on the second level 602b. The first level 602a includes a plurality of image sensing elements 104 disposed in a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. The first 3D capacitor array 702a includes a plurality of 3D capacitors 114 disposed within a first ILD structure 110a on the first substrate 102a. The second level 602b includes a second 3D capacitor array 702b. The second 3D capacitor array 702b includes a plurality of 3D capacitors 114 disposed within a second ILD structure 110b on the second substrate 102b. The plurality of 3D capacitors 114 within the second 3D capacitor array 702b are configured to extend through the second substrate 102b. In some embodiments, a plurality of 3D capacitors 114 within the second 3D capacitor array 702b are formed within a backside interconnect structure 1102 disposed on the backside of the second substrate 102b. In some embodiments, the backside interconnect structure 1102 may include a plurality of backside ILD layers 1102a-1102b. The third level 602c includes a third 3D capacitor array 702c disposed within a third interconnect structure 110c on the third substrate 102c.

[0113] Fig. 11B A block diagram of a multi-dimensional integrated chip structure 1102 having a 3D capacitor array arranged within a first level, a second level, and a third level is shown.

[0114] The multi-dimensional integrated chip structure 1102 includes a first level 602a, a second level 602b stacked on the first level 602a, and a third level 602c stacked on the second level 602b. The first level 602a includes a plurality of image sensing elements 104 disposed in a pixel array 106 having a plurality of pixel regions 106a-106c within a first substrate 102a. The first 3D capacitor array 702a includes a plurality of 3D capacitors 114 disposed within a first ILD structure 110a on the first substrate 102a and within a second ILD structure 110b on a second substrate 102b. The plurality of 3D capacitors 114 within the first 3D capacitor array 702a are configured to extend through the second substrate 102b. The third level 602c includes a second 3D capacitor array 702b disposed within a third interconnect structure 110c on a third substrate 102c.

[0115] In various embodiments, the disclosed 3D capacitors may have different heights. The different heights of the disclosed 3D capacitors allow the 3D capacitors to provide different capacitance values ​​while still having a small enough footprint to be completely contained within the pixel area of ​​the pixel array. Using 3D capacitors with different heights allows different 3D capacitors to be used for different applications (e.g., for pixel sensors, pixel storage, and CDS (correlated double sampling) circuits, etc.). Figure 12A-12C Some embodiments of the disclosed 3D capacitors are shown having different heights.

[0116] Fig. 12A A cross-sectional view of an integrated chip structure 1200 having a 3D capacitor having a first height is shown.

[0117] The integrated chip structure 1200 includes an ILD structure 110 disposed on a substrate 102. The ILD structure 110 includes a first ILD layer 302a disposed on the substrate 102. A lower interconnect structure 112L is disposed within the first ILD layer 302a. A first etch stop layer (ESL) 304a is disposed above the first ILD layer 302a. A lower second ILD layer 302b 1 The 3D capacitor 114 is disposed above the lower second ILD layer 302b1. The 3D capacitor 114 includes a base region 122 and one or more fingers 124. The one or more fingers 124 extend vertically outward from the bottom of the base region 122 and pass through the lower second ILD layer 302b1. 1 , to contact the lower interconnect structure 112L.

[0118] Upper second ILD layer 302b 2 The second ILD layer 302b is disposed at the bottom 1 and above the 3D capacitor 114. In some embodiments, the upper second ILD layer 302b 2 Along the lower second ILD layer 302b 1 The second ESL 304b is arranged on the upper second ILD layer 302b 2 The third ILD layer 302c is disposed above the second ESL 304b. The upper interconnect structure 112U extends through the third ILD layer 302c, the second ESL 304b, and the upper second ILD layer 302b. 2 , to contact the 3D capacitor 114. The peripheral interconnect structure 112P may be arranged within the ILD structure 110, and through the lower second ILD layer 302b 1 and the upper second ILD layer 302b 2 Laterally spaced apart from the 3D capacitor 114 .

[0119] Fig. 12B A cross-sectional view of an integrated chip structure 1202 with a 3D capacitor of a second height is shown.

[0120] The integrated chip structure 1202 includes an ILD structure 110 disposed over a substrate 102. The ILD structure 110 includes a first ILD layer 302a disposed over the substrate 102. A lower interconnect structure 112L is disposed within the first ILD layer 302a. A first ESL 304a is disposed over the first ILD layer 302a, a second ILD layer 302b is disposed over the first ESL 304a, a second ESL 304b is disposed over the second ILD layer 302b, a third ILD layer 302c is disposed over the second ESL 304b, and a fourth ILD layer 302d is disposed over the fourth ILD layer 302e. 1 Disposed above the third ESL 304c.

[0121] The 3D capacitor 114 is disposed within the ILD structure 110. The 3D capacitor 114 includes a base region 122 and one or more fingers 124. The base region 122 is located in the lower fourth ILD layer 302d. 1 One or more fingers 124 extend vertically outward from the bottom of the base region 122 and pass through the first ESL 304a, the second ILD layer 302b, the second ESL 304b, the third ILD layer 302c, the third ESL 304c and the lower fourth ILD layer 302d. 1 , to contact the lower interconnect structure 112L.

[0122] Upper fourth ILD layer 302d 2 The fourth ILD layer 302d is disposed at the bottom 1 and above the 3D capacitor 114. In some embodiments, the upper fourth ILD layer 302d 2 Along the lower fourth ILD layer 302d 1 The fourth ESL 304d is arranged on the upper fourth ILD layer 302d. 2 Above, the fifth ILD layer 302e is disposed above the fourth ESL 304d. The upper interconnect structure 112U extends through the fifth ILD layer 302e, the fourth ESL 304d, and the upper fourth ILD layer 302d. 2 , to contact the 3D capacitor 114. The peripheral interconnect structure 112P may be arranged within the ILD structure 110, and through the lower fourth ILD layer 302d 1 and the upper fourth ILD layer 302d 2 Laterally spaced apart from the 3D capacitor 114 .

[0123] Fig. 12CA cross-sectional view of an integrated chip structure 1204 with a 3D capacitor of a third height is shown.

[0124] The integrated chip structure 1204 includes an ILD structure 110 disposed over the substrate 102. The ILD structure 110 includes a first ILD layer 302a disposed over the substrate 102. The lower interconnect structure 112L is disposed within the first ILD layer 302a. A first ESL 304a is disposed over the first ILD layer 302a, a second ILD layer 302b is disposed over the first ESL 304a, a second ESL 304b is over the second ILD layer 302b, a third ILD layer 302c is over the second ESL 304b, a third ESL 304c is over the third ILD layer 302c, a fourth ILD layer 302d is over the third ESL 304c, a fourth ESL 304d is over the fourth ILD layer 302d, a fifth ILD layer 302e is over the fourth ESL 304d, a fifth ESL 304e is over the fifth ILD layer 302e, and a lower sixth ILD layer 302f is disposed over the first ILD layer 302a. 1 Above Fifth ESL 304e.

[0125] The 3D capacitor 114 is disposed within the ILD structure 110. The 3D capacitor 114 includes a base region 122 and one or more fingers 124. The base region 122 is located at the lower sixth ILD layer 302f. 1 One or more fingers 124 extend vertically outward from the bottom of the base region 122 and pass through the first ESL 304a, the second ILD layer 302b, the second ESL 304b, the third ILD layer 302c, the third ESL 304c, the fourth ILD layer 302d, the fourth ESL 304d, the fifth ILD layer 302e, the fifth ESL 304e and the lower sixth ILD layer 302f. 1 , to contact the lower interconnect structure 112L.

[0126] Upper sixth ILD layer 302f 2 The sixth ILD layer 302f is disposed at the lower portion 1 and 3D capacitor 114. In some embodiments, the upper sixth ILD layer 302f 2 Along the lower sixth ILD layer 302f 1 The sixth ESL 304f is arranged on the upper sixth ILD layer 302f. 2 The seventh ILD layer 302g is disposed on the sixth ESL 304f. The upper interconnect structure 112U extends through the seventh ILD layer 302g, the sixth ESL 304f, and the upper sixth ILD layer 302f. 2, to contact the 3D capacitor 114. The peripheral interconnect structure 112P may be arranged within the ILD structure 110, and through the lower sixth ILD layer 302f 1 and the upper sixth ILD layer 302f 2 Laterally spaced apart from the 3D capacitor 114 .

[0127] Figure 13-Figure 20 Cross-sectional views 1300-2000 of some embodiments of methods for forming a three-dimensional capacitor within a pixel region of an image sensor integrated chip are shown. Figure 13-Figure 20 It is described with respect to a method, but it should be understood that the structure disclosed in the method is not limited to the method, but can exist independently as a structure independent of the method.

[0128] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 13 , a first substrate 102a is provided. In various embodiments, the first substrate 102a may be any type of semiconductor body (e.g., silicon, SiGe, etc.), such as a semiconductor wafer and / or one or more dies on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith.

[0129] The first substrate 102a includes a plurality of pixel regions 106x arranged within a pixel array. In some embodiments, one or more isolation structures 107 may be formed within the first substrate 102a along the boundaries of the plurality of pixel regions 106x. In some embodiments, the plurality of pixel regions 106x may be included within the pixel array within the first substrate 102a. In some embodiments, the plurality of image sensing elements 104 may include photodiodes formed by implanting one or more dopants into the front side of the first substrate 102a. For example, the plurality of image sensing elements 104 may be formed by selectively performing a first implantation process (e.g., according to a first mask layer) to form a first region having a first doping type (e.g., n-type), followed by performing a second implantation process to form a second region adjacent to the first region and having a second doping type different from the first doping type (e.g., p-type). In other embodiments (not shown), the first substrate 102a may be free of image sensing elements. In some such embodiments, one or more pixel support devices (e.g., reset transistors, source follower transistors, row select transistors, etc.) may be formed on the first substrate 102a.

[0130] The lower interconnect structure 112L is formed in the first ILD layer 302a on the first substrate 102a. In some embodiments, the lower interconnect structure 112L can be formed using a damascene process (e.g., a single damascene process and / or a dual damascene process). For example, the damascene process can be performed by forming the first ILD layer 302a on the first substrate 102a, etching the first ILD layer 302 to form a through hole and / or a groove, filling the through hole and / or the groove with a conductive material, and performing a planarization process (e.g., a chemical mechanical planarization process) to remove excess conductive material from above the first ILD layer 303a. In some embodiments, the first ILD layer 302a can be formed by a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.), and the conductive material can be formed using a deposition process and / or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the conductive material may include tungsten, copper, aluminum, etc.

[0131] The lower ILD structure 1302 is formed on the first ILD layer 302a. In some embodiments, the lower ILD structure 1302 can be formed by forming a first etch stop layer (ESL) 304a on the first ILD layer 302a and forming a lower second ILD layer 302b on the first ESL 304a. 1 In some embodiments, the first ESL 304a and the lower second ILD layer 302b 1 The first ESL 304a may be formed by a deposition technique (eg, PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the first ESL 304a may include a nitride (eg, silicon nitride, silicon oxynitride), a carbide (eg, silicon carbide), etc. In some embodiments, the lower second ILD layer 302b may include a nitride (eg, silicon nitride, silicon oxynitride), a carbide (eg, silicon carbide), etc. 1 It may include oxides (e.g., silicon dioxide), nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), etc.

[0132] like Fig.14 As shown in the cross-sectional view 1400, the lower ILD structure 1302 is selectively patterned by an etching process to form a vertically extending through the lower second ILD layer 302b 1 and the opening 1402 of the first ESL 304a to expose the lower interconnect structure 112L. In some embodiments, the etching process may remove the lower second ILD layer 302b according to the mask 1406. 1 The one or more etchants 1404 are exposed. In some embodiments, the one or more etchants 1404 may include a dry etchant having an etching chemistry including oxygen (O 2 ), nitrogen (N2 ), hydrogen (H 2 ), argon (Ar), fluorine substances (such as CF 4 , CHF 3 , C 4 F 8 In some embodiments, the mask 1406 may include a photoresist, a hard mask, etc.

[0133] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , the capacitor stack 1501 is formed within the opening 1402 and above the top of the lower ILD structure 1302. In some embodiments, the capacitor stack 1501 can be formed by forming a capacitor within the opening 1402 and above the lower second ILD layer 302b. 1 The capacitor barrier layer 1502 is formed on the first ESL 304a and the lower second ILD layer 302b. 1 A first capacitor electrode layer 1504 is formed on the capacitor barrier layer 1502. The first capacitor electrode layer 1504 lines the sidewalls and the upper surface of the capacitor barrier layer 1502. A capacitor dielectric layer 1506 is formed on the first capacitor electrode layer 1504. The capacitor dielectric layer 1506 lines the sidewalls and the upper surface of the first capacitor electrode layer 1504. A second capacitor electrode layer 1508 is formed on the capacitor dielectric layer 1506. The second capacitor electrode layer 1508 lines the sidewalls and the upper surface of the capacitor dielectric layer 1506.

[0134] In some embodiments, the capacitor barrier layer 1502, the first capacitor electrode layer 1504, the capacitor dielectric layer 1506, and the second capacitor electrode layer 1508 can be formed by separate deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the capacitor barrier layer 1502 can include or be tantalum, tantalum nitride, titanium, titanium nitride, etc. In some embodiments, the first capacitor electrode layer 1504 can include or be a metal such as titanium. In some embodiments, the capacitor dielectric layer 1506 can include or be a high-k dielectric material, such as silicon nitride (SiN x ), Tantalum Oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 )、ZrO 2 ), hafnium oxide (HfO 2), hafnium aluminum oxide (HfAlO), zirconium aluminum oxide (ZrAlO), etc. In some embodiments, the capacitor dielectric layer 1506 may include or be a single high-k dielectric material or a stack of multiple high-k dielectric materials. In some embodiments, the second capacitor electrode layer 1508 may include or be a metal such as titanium. In some embodiments, the second capacitor electrode layer 1508 is formed to have one or more inner surfaces that form a recess 306 above the bottom of the second capacitor electrode layer 1508.

[0135] In some embodiments, the capacitor cap stack 1509 can be formed by further forming a first upper capacitor dielectric layer 1510 on the second capacitor electrode layer 1508, forming a second upper capacitor dielectric layer 1512 on the first upper capacitor dielectric layer 1510, and forming a third upper capacitor dielectric layer 1514 on the second upper capacitor dielectric layer 1512.

[0136] In some embodiments, the first upper capacitor dielectric layer 1510, the second upper capacitor dielectric layer 1512, and the third upper capacitor dielectric layer 1514 may be formed by separate deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the first upper capacitor dielectric layer 1510 may include or be an oxide (e.g., silicon oxide, silicon dioxide, etc.), etc. In some embodiments, the second upper capacitor dielectric layer 1512 may include or be an oxide (e.g., silicon oxide, silicon dioxide, etc.), a nitride (e.g., silicon oxynitride, etc.), etc. In some embodiments, the third upper capacitor dielectric layer 1514 may include or be a nitride (e.g., silicon nitride, etc.), etc.

[0137] like Fig.16 As shown in the cross-sectional view 1600, the capacitor cover stack (eg Fig.15 1509) is patterned to form capacitor cap 307. The etching process removes a portion of the first upper capacitor dielectric layer to form a first upper dielectric 308, removes a portion of the second upper capacitor dielectric layer to form a second upper dielectric 310, and removes a portion of the third upper capacitor dielectric layer to form a third upper dielectric 312. In some embodiments, the etching process further removes a portion of the second capacitor electrode layer to form a second electrode 120.

[0138] After patterning the capacitor cap stack to form the capacitor cap 307, a first hard mask 1602 is formed on the capacitor dielectric layer 1506 and along the sidewalls and upper surface of the capacitor cap 107. A second hard mask 1604 is formed along the sidewalls and upper surface of the first hard mask 1602. In some embodiments, the first hard mask 1602 and the second hard mask 1604 can be formed by separate deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the first hard mask 1602 can include or be an oxide (e.g., silicon oxide, silicon dioxide, etc.), etc. In some embodiments, the second hard mask 1604 can include or be a nitride (e.g., silicon nitride, etc.), etc.

[0139] like Fig.17 As shown in the cross-sectional view 1700, the first hard mask (eg Fig.16 1602) and a second hard mask (eg Fig.16 1604) to form one or more sidewall spacers 314. In some embodiments, one or more sidewall spacers 314 can extend continuously from a first side of capacitor cap 307 to an opposite second side of capacitor cap 107. In some embodiments, the first hard mask and the second hard mask can be etched by selectively exposing the first hard mask and the second hard mask to one or more etchants 1702 according to mask 1704.

[0140] In some embodiments, the one or more etchants 1702 may further etch the capacitor dielectric layer to form the capacitor dielectric 118, etch the first capacitor electrode layer to form the lower capacitor metal 116a, and etch the capacitor barrier layer to form the capacitor barrier 116b. In some embodiments, the etchant may also etch the lower second ILD layer 302b. 1 , so that the lower second ILD layer 302b is formed below the outermost wall of the capacitor barrier 116b. 1 A portion of is recessed by a non-zero distance.

[0141] like Fig.18 As shown in the cross-sectional view 1800, the upper ILD structure 1802 is formed on the lower second ILD layer 302b. 1 and above the 3D capacitor 114. In some embodiments, the upper ILD structure 1802 may be formed by placing the lower second ILD layer 302b 1 The upper second ILD layer 302b is formed on 2 , on the upper second ILD layer 302b 2The second ESL 304b is formed on the upper portion of the second ILD layer 302c and the third ILD layer 302c is formed on the second ESL 304b. In some additional embodiments, a dielectric layer 1804 (eg, SiON or other dielectrics) may be formed on the third ILD layer 302c. 2 , the second ESL 304b and the third ILD layer 302c may be formed by separate deposition techniques (eg, PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the upper second ILD layer 302b 2 The third ILD layer 302c may include an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphate silicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), etc. In some embodiments, the second ESL 304b may include a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), etc.

[0142] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 19 , the upper interconnect structure 112U is formed on the 3D capacitor 114. The upper interconnect structure 112U is formed to vertically extend through the third ILD layer 302c, the second ESL 304b, and the upper second ILD layer 302b. 2 In some embodiments, the upper interconnect structure 112U includes conductive vias and / or conductive lines. In some embodiments, the upper interconnect structure 112U may be formed using a damascene process (e.g., a single damascene process and / or a dual damascene process). In various embodiments, the upper interconnect structure 112U may include tungsten, copper, aluminum, copper, etc. In some embodiments, the dielectric layer (e.g., a CMP process) may be removed during a planarization process (e.g., a CMP process) used to form the upper interconnect structure 112U. Fig.18 of 1804).

[0143] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2001 , in some additional embodiments, the first substrate 102a may be bonded to the second substrate 102b to form a multi-layer integrated chip structure 2002. In some embodiments, the first substrate 102a may include a plurality of image sensing elements 104, and the second substrate 102b may include one or more pixel support devices 606 (e.g., reset transistors, source follower transistors, row selection transistors, etc.). In other embodiments (not shown), the first substrate 102a may include one or more pixel support devices, and the second substrate 102b may include a plurality of image sensing elements.

[0144] After bonding, the multi-layer integrated chip structure 2002 can be singulated to form one or more integrated chip tube cores (not shown). In some embodiments, the multi-layer integrated chip structure 2002 can be separated by a cutting process, which mounts the multi-layer integrated chip architecture 2002 on the adhesive surface of a cutting tape. Then, a wafer saw cuts the wafer along the scribe line to separate the wafer into one or more integrated chip tube cores.

[0145] After singulation, a plurality of color filters 608 may be formed on the first substrate 102a. In some embodiments, the plurality of color filters 608 are formed by depositing (e.g., by CVD, PVD, ALD, sputtering, spin coating, etc.) a filter material on the first substrate 102a. The filter material is a material that allows transmission of radiation (e.g., light) having a specific wavelength range while blocking light of wavelengths outside the specified range. Subsequently, in some embodiments, a planarization process (e.g., CMP) may be performed on the plurality of color filters 608 to planarize the upper surfaces of the plurality of color filters 608.

[0146] A plurality of microlenses 610 may be formed above the plurality of color filters 608. In some embodiments, the plurality of microlenses 610 may be formed by depositing a microlens material on the plurality of color filters 608 (e.g., by CVD, PVD, ALD, sputtering, spin coating processes, etc.). A microlens template (not shown) having a curved upper surface is patterned above the microlens material. In some embodiments, the microlens template may include a photoresist material exposed using a distributed exposure light dose (e.g., for a negative photoresist, more light is exposed at the bottom of the curve and less light is exposed at the top of the curve), developed and baked to form an arc shape. Then, the plurality of microlenses 610 are formed by selectively etching the microlens material according to the microlens template.

[0147] Figure 21-Figure 28 Cross-sectional views 2100-2800 of some additional embodiments of methods of forming a three-dimensional capacitor within a pixel region of an image sensor integrated chip are shown. Figure 21-Figure 28 It is described with respect to a method, but it should be understood that the structure disclosed in the method is not limited to the method, but can exist independently as a structure independent of the method.

[0148] like Fig.21As shown in the cross-sectional view 2100 of , a first substrate 102a is provided. The first substrate 102a includes a plurality of pixel regions 106x arranged in a pixel array. In some embodiments, a plurality of image sensing elements 104 are formed in the plurality of pixel regions 106x. In other embodiments (not shown), the first substrate 102a may be free of image sensing elements. In some such embodiments, one or more pixel support devices (e.g., a reset transistor, a source follower transistor, a row select transistor, etc.) may be formed on the first substrate 102a.

[0149] The lower interconnect structure 112L is formed in the first ILD layer 302a formed over the first substrate 102a. The lower ILD structure 1302 is formed on the first ILD layer 302a. In some embodiments, the lower ILD structure 1302 may be formed by forming a first ESL 304a over the first ILD layer 302a, forming a second ILD layer 302b over the first ESL 304a, forming a second ESL 304b over the second ILD layer 302b, forming a third ILD layer 302c over the second ESL 304b, forming a third ESL 304c over the third ILD layer 302c, and forming a lower fourth ILD layer 302d over the third ESL 304c. 1 The peripheral interconnect structure 112P is formed to extend through the first ILD layer 302a, the second ILD layer 302b, the second ESL 304b, and the third ILD layer 302c. In some embodiments, the lower interconnect structure 112L and the peripheral interconnect structure 112P may be formed using a damascene process (eg, a single damascene process and / or a dual damascene process).

[0150] like Fig. 22 As shown in the cross-sectional view 2200, the lower ILD structure 1302 is selectively patterned by an etching process to form a fourth ILD layer 302d extending vertically through the lower ILD layer 302d. 1 , the third ESL 304c, the third ILD layer 302c, the second ESL 304b, the second ILD layer 302b, and the opening 2202 of the first ESL 304a. In some embodiments, the etching process may remove the lower fourth ILD layer 302d according to the mask 2206. 1 Expose to one or more etchants 2204.

[0151] like Fig.23As shown in the cross-sectional view 2300 of FIG. 2 , the capacitor stack 1501 is formed within the opening 2202 and over the top of the lower ILD structure 1302. In some embodiments, the capacitor stack 1501 may include a capacitor barrier layer 1502, a first capacitor electrode layer 1504 formed on the capacitor barrier layer 1502, a capacitor dielectric layer 1506 formed on the first capacitor electrode layer 1504, and a second capacitor electrode layer 1508 formed on the capacitor dielectric layer 1506. In some embodiments, the second capacitor electrode layer 1508 is formed to have one or more inner surfaces that form a recess 306 over the bottom of the second capacitor electrode layer 1508.

[0152] In some embodiments, the capacitor cap stack 1509 can be formed by further forming a first upper capacitor dielectric layer 1510 on the second capacitor electrode layer 1508, forming a second upper capacitor dielectric layer 1512 on the first upper capacitor dielectric layer 1510, and forming a third upper capacitor dielectric layer 1514 on the second upper capacitor dielectric layer 1512.

[0153] like Fig.24 As shown in the cross-sectional view 2400, the capacitor cover stack (eg Fig.23 1509) is patterned to form a capacitor cap 307. The etching process removes a portion of the capacitor upper electrode layer to form the second electrode 120, removes a portion of the first upper capacitor dielectric layer to form a first upper dielectric 308, removes a portion of the second upper capacitor dielectric layer to form a second upper dielectric 310, and removes a portion of the third upper capacitor dielectric layer to form a third upper dielectric 312.

[0154] like Fig.25 As shown in the cross-sectional view 2500 of FIG. 1 , a first hard mask 1602 is formed on the capacitor dielectric layer 1506 and along the sidewalls and upper surface of the capacitor cap 307. A second hard mask 1604 is formed along the sidewalls and upper surface of the first hard mask 1602.

[0155] like Fig.26 As shown in the cross-sectional view 2600 of FIG. 26, the first hard mask (eg, Fig.25 1602) and a second hard mask (such as Fig.25 One or more etchants 2602 remove horizontally extending sections of the first hard mask and the second hard mask to form one or more sidewall spacers 314 along opposite sides of the capacitor cap 307 and the second electrode 120. The one or more sidewall spacers 314 include a first dielectric spacer layer 314a and a second dielectric spacer layer 314b located on the first dielectric spacer layer 314a.

[0156] The one or more etchants 2602 further etches the capacitor dielectric layer to form the capacitor dielectric 118, etches the first capacitor electrode layer to form the lower capacitor metal 116a, and etches the capacitor barrier layer to form the container barrier 116b. In some embodiments, the etchant may also etch the lower fourth ILD layer 302d. 1 , so that the lower fourth ILD layer 302d 1 A portion of is recessed a non-zero distance below the outermost sidewall of capacitor barrier 116b.

[0157] like Fig. 27 As shown in the cross-sectional view 2700, the upper ILD structure 1802 is formed on the lower fourth ILD layer 302d. 1 and above the 3D capacitor 114. In some embodiments, the upper ILD structure 1802 is formed by forming a fourth ILD layer 302d on the lower portion. 1 The upper fourth ILD layer 302d is formed on 2 , in the upper fourth ILD 302d 2 A fourth ESL 304d is formed on the substrate and a fifth ILD layer 302e is formed on the fourth ESL 304d.

[0158] An upper interconnect structure 112U is formed on the 3D capacitor 114. The upper interconnect structure 112U is formed to vertically extend through the fifth ILD layer 302e, the fourth ESL 304d, and the upper fourth ILD layer 302d. 2 In some embodiments, the upper interconnect structure 112U includes conductive vias and conductive lines.

[0159] like Fig.28 As shown in the cross-sectional view 2800 of , in some additional embodiments, the first substrate 102a can be bonded to the second substrate 102b to form a multi-layer integrated chip structure 2802. In some embodiments, the first substrate 102a may include a plurality of image sensing elements 104, and the second substrate 102b may include one or more pixel support devices 606 (e.g., a reset transistor, a source follower transistor, a row select transistor, etc.). In other embodiments (not shown), the first substrate 102a may include one or more pixel support devices, and the second substrate 102b may include a plurality of image sensing elements. After bonding, the multi-layer integrated chip structure 2802 may be singulated to form one or more integrated chip dies (not shown). After singulation, a plurality of color filters 608 may be formed on the first substrate 102a, and a plurality of microlenses 610 may be formed on the plurality of color filters 608.

[0160] Figure 29-Figure 36Cross-sectional views 2900-3600 of some additional embodiments of methods of forming a three-dimensional capacitor within a pixel region of an image sensor integrated chip are shown. Figure 29-Figure 36 It is described with respect to a method, but it should be understood that the structure disclosed in the method is not limited to the method, but can exist independently as a structure independent of the method.

[0161] like Fig.29 As shown in the cross-sectional view 2900 of , a first substrate 102a is provided. The first substrate 102a includes a plurality of pixel regions 106x arranged in a pixel array. In some embodiments, a plurality of image sensing elements 104 are formed in the plurality of pixel regions 106x. In other embodiments (not shown), the first substrate 102a may be free of image sensing elements. In some such embodiments, one or more pixel support devices (e.g., a reset transistor, a source follower transistor, a row select transistor, etc.) may be formed on the first substrate 102a.

[0162] The lower interconnect structure 112L is formed in a first ILD layer 302a formed on the first substrate 102a. The lower ILD structure 1302 is formed on the first ILD layer 302a. In some embodiments, the lower ILD structure 1302 may be formed by forming a first etch stop layer (ESL) 304a on the first ILD layer 302a, forming a second ILD layer 302b on the first ESL 304a, forming a second ESL 304b on the second ILD layer 302b, forming a third ILD layer 302c on the second ESL 304b, forming a third ESL 304c on the third ILD layer 302c, forming a fourth ILD layer 302d on the third ESL 304c, forming a fourth ESL 304d over the fourth ILD layer 302d, forming a fifth ILD layer 302e over the fourth ESL 304d, forming a fifth ESL 304e over the fifth ILD layer 302e, and forming a lower sixth ILD layer 302f over the fifth ESL 304e. 1 The peripheral interconnect structure 112P is formed to extend through the first ILD layer 302a, the second ILD layer 302b, the second ESL 304b, the third ILD layer 302c, the third ESL 304c, the fourth ILD layer 302d, the fourth ESL 304d, and the fifth ILD layer 302e. In some embodiments, the lower interconnect structure 112L and the peripheral interconnect structure 112P may be formed using a damascene process (e.g., a single damascene process and / or a dual damascene process).

[0163] like Fig.30 As shown in the cross-sectional view 3000 of FIG. 3000 , the lower ILD structure 1302 is selectively patterned by an etching process to form a sixth ILD layer 302f extending vertically through the lower ILD layer 302f. 1, the fifth ESL 304e, the fifth ILD layer 302e, the fourth ESL 304d, the fourth ILD layer 302d, the third ESL 304c, the third ILD layer 302c, the second ESL 304b, the second ILD layer 302b and the first ESL 304a. In some embodiments, the etching process can be based on the mask 3006 to remove the lower sixth ILD layer 302f 1 Expose to one or more etchants 3004.

[0164] like Fig.31 As shown in the cross-sectional view 3100 of FIG. 31 , the capacitor stack 1501 is formed within the opening 3002 and over the top of the lower ILD structure 1302. In some embodiments, the capacitor stack 1501 may include a capacitor barrier layer 1502, a first capacitor electrode layer 1504 formed on the capacitor barrier layer 1502, a capacitor dielectric layer 1506 formed on the first capacitor electrode layer 1504, and a second capacitor electrode layer 1508 formed on the capacitor dielectric layer 1506. In some embodiments, the second capacitor electrode layer 1508 is formed to have one or more inner surfaces that form a recess 306 over the bottom of the second capacitor electrode layer 1508.

[0165] In some embodiments, the capacitor cap stack 1509 can be formed by further forming a first upper capacitor dielectric layer 1510 on the second capacitor electrode layer 1508, forming a second upper capacitor dielectric layer 1512 on the first upper capacitor dielectric layer 1520, and forming a third upper capacitor dielectric layer 1514 on the second upper capacitor dielectric layer 1512.

[0166] like Fig.32 As shown in the cross-sectional view 3200, the capacitor cover stack (eg Fig.31 1509) is patterned to form a capacitor cap 307. The etching process removes a portion of the capacitor upper electrode layer to form the second electrode 120, removes a portion of the first upper capacitor dielectric layer to form a first upper dielectric 308, removes a portion of the second upper capacitor dielectric layer to form a second upper dielectric 310, and removes a portion of the third upper capacitor dielectric layer to form a third upper dielectric 312.

[0167] like Fig.33 As shown in the cross-sectional view 3300 of FIG. 3300 , the first hard mask 1602 is formed on the capacitor dielectric layer 1506 and along the sidewalls and upper surface of the capacitor cap 307. The second hard mask 1604 is formed along the sidewalls and upper surface of the first hard mask 1602.

[0168] like Fig.34As shown in the cross-sectional view 3400 of FIG. 1 , the first hard mask (eg, Fig.33 1602) and a second hard mask (eg Fig.33 1604). One or more etchants remove horizontally extending sections of the first hard mask and the second hard mask to form one or more sidewall spacers 314 along opposite sides of the capacitor cap 307 and the second electrode 120. The one or more sidewall spacers 314 include a first dielectric spacer layer 314a and a second dielectric spacer layer 314b located on the first dielectric spacer layer 314a.

[0169] The one or more etchants 3402 further etches the capacitor dielectric layer to form the capacitor dielectric 118, etches the first capacitor electrode layer to form the lower capacitor metal 116a, etches the capacitor barrier layer to form the container barrier 116b. In some embodiments, the etchant may also etch the lower sixth ILD layer 302f. 1 , so that the lower sixth ILD layer 302f is formed below the outermost wall of the capacitor barrier 116b. 1 The portion of is recessed by a non-zero distance.

[0170] like Fig.35 As shown in the cross-sectional view 3500, the upper ILD structure 1802 is formed on the lower sixth ILD layer 302f 1 and above the 3D capacitor 114. In some embodiments, the upper ILD structure 1802 is formed by placing the sixth ILD layer 302f on the lower portion. 1 The sixth ILD layer 302f is formed on the upper 2 , on the upper sixth ILD layer 302f 2 A sixth ESL 304f is formed on the substrate and a seventh ILD layer 302g is formed on the sixth ESL 304f.

[0171] An upper interconnect structure 112U is formed on the 3D capacitor 114. The upper interconnect structure 112U is formed to vertically extend through the seventh ILD layer 302g, the sixth ESL 304f, and the upper sixth ILD layer 302f. 2 In some embodiments, the upper interconnect structure 112U includes conductive vias and conductive lines.

[0172] like Fig.36As shown in the cross-sectional view 3600 of , in some additional embodiments, the first substrate 102a can be bonded to the second substrate 102b to form a multi-layer integrated chip structure 3602. In some embodiments, the first substrate 102a can include a plurality of image sensing elements 104, and the second substrate 102b can include one or more pixel support devices (e.g., a reset transistor, a source follower transistor, a row select transistor, etc.). In other embodiments (not shown), the first substrate 102a can include one or more pixel support devices, and the second substrate 102b can include a plurality of image sensing elements 104. After bonding, the multi-layer integrated chip structure 3602 can be singulated to form one or more integrated chip dies (not shown). After singulation, a plurality of color filters 608 can be formed on the first substrate 104a, and a plurality of microlenses 610 can be formed on the plurality of color filters 608.

[0173] Fig.37 A flow chart illustrating some embodiments of a method 3700 for forming a three-dimensional capacitor within a pixel region of an image sensor integrated chip.

[0174] Although the disclosed method 3700 is shown and described herein as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions may occur in a different order and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, not all of the actions shown are required to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0175] At act 3702, a first substrate having a plurality of pixel regions is provided. Fig.13 A cross-sectional view 1300 of some embodiments corresponding to act 3702 is shown. Fig.21 Cross-sectional view 2100 of some alternative embodiments corresponding to act 3702 is shown. Fig.29 Cross-sectional view 2900 is shown of some additional alternative embodiments corresponding to act 3702 .

[0176] At act 3704, in some embodiments, a plurality of image sensing elements may be formed within a plurality of pixel regions of the first substrate. Fig.13 A cross-sectional view 1300 of some embodiments corresponding to act 3704 is shown. Fig.21 Cross-sectional view 2100 of some alternative embodiments corresponding to act 3704 is shown. Fig.29 Cross-sectional view 2900 is shown of some additional alternative embodiments corresponding to act 3704 .

[0177] At act 3706, a plurality of three-dimensional (3D) capacitors are formed within corresponding pixel regions of the plurality of pixel regions. In some embodiments, a plurality of three-dimensional capacitors may be formed according to acts 3708-3718.

[0178] At act 3708, a lower interlayer dielectric (ILD) structure is formed on the substrate, the structure including a lower ILD layer interleaved with a lower etch stop layer (ESL). Fig.13 A cross-sectional view 1300 of some embodiments corresponding to act 3708 is shown. Fig.21 Cross-sectional view 2100 of some alternative embodiments corresponding to act 3708 is shown. Fig.29 Cross-sectional view 2900 is shown of some additional alternative embodiments corresponding to act 3708 .

[0179] At act 3710 , the lower ILD structure is patterned to form one or more openings extending through the lower ILD structure. Fig.14 A cross-sectional view 1400 of some embodiments corresponding to act 3710 is shown. Fig. 22 Cross-sectional view 2200 of some alternative embodiments corresponding to act 3710 is shown. Fig.30 Cross-sectional view 3000 is shown of some additional alternative embodiments corresponding to act 3710 .

[0180] At act 3712, a capacitor stack is formed within the one or more openings and over the lower ILD structure. Fig.15 A cross-sectional view 1500 of some embodiments corresponding to act 3712 is shown. Fig.23 Cross-sectional view 2300 of some alternative embodiments corresponding to act 3712 is shown. Fig.31 Cross-sectional view 3100 is shown of some additional alternative embodiments corresponding to act 3712 .

[0181] At act 3714, a capacitor cap structure is formed on the capacitor stack. Fig.15 A cross-sectional view 1500 of some embodiments corresponding to act 3714 is shown. Fig.23 Cross-sectional view 2300 of some alternative embodiments corresponding to act 3714 is shown. Fig.31 Cross-sectional view 3100 of some additional alternative embodiments corresponding to act 3714 is shown.

[0182] At act 3716, the capacitor cap structure is patterned to form a capacitor cap. Fig.16 A cross-sectional view 1600 of some embodiments corresponding to act 3716 is shown. Fig.24 Cross-sectional view 2400 of some alternative embodiments corresponding to act 3716 is shown. Fig.32Cross-sectional view 3200 is shown of some additional alternative embodiments corresponding to act 3716 .

[0183] At act 3718, the capacitor stack is patterned to form a 3D capacitor. Fig.17 A cross-sectional view 1700 of some embodiments corresponding to act 3718 is shown. Fig.26 Cross-sectional view 2600 of some alternative embodiments corresponding to act 3718 is shown. Fig.34 Cross-sectional view 3400 is shown of some additional alternative embodiments corresponding to act 3718 .

[0184] At act 3720, an upper ILD structure including one or more upper ILD layers is formed on the 3D capacitor. Fig.18 A cross-sectional view 1800 of some embodiments corresponding to act 3720 is shown. Fig. 27 Cross-sectional view 2700 of some alternative embodiments corresponding to act 3720 is shown. Fig.35 Cross-sectional view 3500 is shown of some additional alternative embodiments corresponding to act 3720 .

[0185] At act 3722, an upper interconnect structure is formed within the upper ILD structure and over the 3D capacitor. Fig.19 A cross-sectional view 1900 of some embodiments corresponding to act 3722 is shown. Fig. 27 Cross-sectional view 2700 of some alternative embodiments corresponding to act 3722 is shown. Fig.35 Cross-sectional view 3500 is shown of some additional alternative embodiments corresponding to action 3722 .

[0186] At act 3724, a second substrate having a plurality of pixel regions is provided.

[0187] At act 3726, in some embodiments, a plurality of image sensing elements may be formed within the plurality of pixel regions of the second substrate.

[0188] At act 3728, the first substrate is bonded to the second substrate to form a multi-layer integrated chip structure. In some embodiments, the first substrate may include a plurality of image sensing elements within a pixel array. In other embodiments, the second substrate may include a plurality of image sensing elements within a pixel array. Fig. 20 A cross-sectional view 2000 of some embodiments corresponding to act 3728 is shown. Fig.28 Cross-sectional view 2800 of some alternative embodiments corresponding to act 3728 is shown. Fig.36 Cross-sectional view 3600 is shown of some additional alternative embodiments corresponding to action 3728 .

[0189] Accordingly, the present disclosure is directed to a method of forming a three-dimensional (3D) capacitor within a pixel region of an image sensor integrated chip.

[0190] In some embodiments, the present disclosure relates to an image sensor integrated chip (IC) structure. The image sensor IC structure includes: a plurality of image sensing elements, respectively arranged in a plurality of pixel regions of a pixel array in a substrate; an interlayer dielectric (ILD) structure, arranged on the surface of the substrate and surrounding one or more interconnects; and a plurality of three-dimensional (3D) capacitors, arranged in corresponding pixel regions in the plurality of pixel regions, and coupled to one of the plurality of image sensing elements through one or more interconnects, wherein the plurality of 3D capacitors include a base region extending parallel to the surface of the substrate and one or more fingers extending outward from the base region in a direction perpendicular to the surface of the substrate. In some embodiments, a corresponding 3D capacitor in the plurality of 3D capacitors is completely confined to an upper pixel region in the plurality of pixel regions. In some embodiments, the ILD structure includes a plurality of interlayer dielectric layers separated by one or more etch stop layers (ESL), and the plurality of 3D capacitors vertically extend through two ILD layers in the plurality of ILDs. In some embodiments, a first 3D capacitor in the plurality of 3D capacitors is arranged in a first pixel region in the plurality of pixel regions; and wherein the peripheral interconnect structure is arranged in the first pixel region, and the first 3D capacitor is laterally separated from the peripheral interconnect structure by the ILD structure. In some embodiments, the peripheral interconnect structure includes a conductive via, and the first 3D capacitor extends vertically from below the top of the conductive via to below the bottom of the conductive via. In some embodiments, the peripheral interconnect structure also includes an interconnect line having a width greater than the conductive via, and the first 3D capacitor extends vertically from above the top of the interconnect line to below the bottom of the interconnect line. In some embodiments, one or more fingers have a rectangular shape in a plan view. In some embodiments, one or more fingers have a circular shape in a plan view. In some embodiments, one or more fingers have a closed shape that extends continuously around the column of the ILD structure in a plan view. In some embodiments, multiple 3D capacitors are respectively implemented in lateral overflow integration capacitor (LOFIC) pixels. In some embodiments, the image sensor IC structure further includes: a second substrate; a second ILD structure located on the second substrate, wherein the ILD structure is bonded to the second ILD structure through a bonding area including a conductive interface and a dielectric interface; and a second plurality of 3D capacitors, wherein the multiple 3D capacitors are arranged in the ILD structure, and the second plurality of 3D capacitors are arranged in the second ILD structure.

[0191] In other embodiments, the present disclosure relates to an image sensor IC structure. The image sensor IC structure includes: a plurality of image sensing elements, respectively disposed in a plurality of pixel regions of a pixel array in a substrate; an interlayer dielectric (ILD) structure disposed on the substrate and surrounding one or more interconnects, the ILD structure including a plurality of ILD layers separated by one or more etch stop layers (ESL); and a plurality of three-dimensional (3D) capacitors, disposed in a corresponding one of a plurality of pixel regions below one of the plurality of image sensing elements, wherein the plurality of 3D capacitors include a lower surface disposed between an outermost wall and an outer wall facing the same direction. In some embodiments, a corresponding 3D capacitor in the plurality of 3D capacitors is set back from a relative edge of a pixel region in the plurality of pixel regions at a non-zero distance. In some embodiments, the ILD structure includes: a first ILD layer having a first upper surface disposed below the lower surface and a second upper surface disposed laterally outside the lower surface, the first upper surface being above the second upper plane; and a second ILD layer disposed along the sidewall of the first ILD layer and disposed above the second upper surface. In some embodiments, the image sensor IC structure further includes: a second substrate; a second ILD structure located on the second substrate and vertically located between the ILD structure and the second substrate; and wherein a plurality of 3D capacitors are arranged in the second ILD structure. In some embodiments, the plurality of 3D capacitors extend vertically from below the second substrate to above the second substrate and into the second ILD structure. In some embodiments, the outer sidewall extends vertically from above one of the ILD layers in the plurality of ILD layers to below one of the ILD layers in the plurality of ILD layers.

[0192] In other embodiments, the present disclosure relates to a method of forming an image sensor IC structure. The method includes: providing a first substrate having a plurality of pixel regions within a pixel array; forming one or more ILD layers on the first substrate; forming an opening extending vertically through the one or more ILD layers, wherein the opening is laterally set back by a non-zero distance from an opposite side of one of the plurality of pixel regions; forming a capacitor stack within the opening and above the one or more ILD layers; and patterning the capacitor stack to form a capacitor having a horizontally extending section above the one or more ILD layers and a vertically extending section extending through the one or more ILD layers. In some embodiments, the vertically extending section includes a first electrode separated from a second electrode by a capacitor dielectric; and wherein the first electrode, the second electrode, and the capacitor dielectric concentrically surround the one or more ILD layers. In some embodiments, the method also includes: forming a plurality of image sensing elements within a second substrate, the plurality of image sensing elements being formed within a plurality of pixel regions; and bonding the first substrate to the second substrate.

[0193] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor integrated chip structure, comprising: A plurality of image sensing elements are respectively disposed in a plurality of pixel regions of a pixel array in the substrate; an interlayer dielectric structure disposed on the surface of the substrate and surrounding one or more interconnects; as well as A plurality of three-dimensional capacitors are arranged in corresponding pixel regions among the plurality of pixel regions and coupled to one image sensing element among the plurality of image sensing elements through the one or more interconnects, wherein the plurality of three-dimensional capacitors include a base region extending parallel to the surface of the substrate and one or more fingers extending outward from the base region in a direction perpendicular to the surface of the substrate.

2. The image sensor integrated chip structure according to claim 1, wherein: A corresponding three-dimensional capacitor among the plurality of three-dimensional capacitors is completely confined within an upper one of the plurality of pixel regions.

3. The image sensor integrated chip structure according to claim 1, wherein: The interlayer dielectric structure includes a plurality of interlayer dielectric layers separated by one or more etch stop layers, and the plurality of three-dimensional capacitors vertically extend through two of the plurality of interlayer dielectric layers.

4. The image sensor integrated chip structure according to claim 1, in, A first three-dimensional capacitor of the plurality of three-dimensional capacitors is disposed in a first pixel region of the plurality of pixel regions; and The peripheral interconnect structure is arranged in the first pixel region, and the first three-dimensional capacitor is laterally separated from the peripheral interconnect structure by the interlayer dielectric structure.

5. The image sensor integrated chip structure according to claim 4, wherein: The peripheral interconnect structure includes a conductive via, and the first three-dimensional capacitor extends vertically from below a top of the conductive via to below a bottom of the conductive via.

6. The image sensor integrated chip structure according to claim 1, wherein: In a plan view, the one or more fingers each have a closed shape extending continuously around a pillar of the interlayer dielectric structure.

7. The image sensor integrated chip structure according to claim 1, further comprising: a second substrate; a second interlayer dielectric structure located on the second substrate, wherein the interlayer dielectric structure is bonded to the second interlayer dielectric structure via a bonding region including a conductive interface and a dielectric interface; and A second plurality of three-dimensional capacitors, wherein the plurality of three-dimensional capacitors are disposed within the interlayer dielectric structure, and wherein the second plurality of three-dimensional capacitors are disposed within the second interlayer dielectric structure.

8. An image sensor integrated chip structure, comprising: A plurality of image sensing elements are respectively disposed in a plurality of pixel regions of a pixel array in the substrate; an interlayer dielectric structure disposed on the substrate and surrounding one or more interconnects, the interlayer dielectric structure comprising a plurality of interlayer dielectric layers separated by one or more etch stop layers; as well as A plurality of three-dimensional capacitors are arranged in a corresponding one of the plurality of pixel regions below one of the plurality of image sensing elements, wherein the plurality of three-dimensional capacitors include a lower surface arranged between an outermost wall and an outer side wall facing the same direction.

9. The image sensor integrated chip structure according to claim 8, wherein: The interlayer dielectric structure comprises: a first interlayer dielectric layer having a first upper surface below the lower surface and a second upper surface laterally outside the lower surface, the first upper surface being above the second upper plane; and A second interlayer dielectric layer is arranged along the sidewall of the first interlayer dielectric layer and is located above the second upper surface.

10. A method for forming an image sensor integrated chip structure, comprising: providing a first substrate having a plurality of pixel regions within a pixel array; forming one or more interlayer dielectric layers on the first substrate; forming an opening extending vertically through the one or more interlayer dielectric layers, wherein the opening is laterally recessed by a non-zero distance from opposite sides of a pixel region in the plurality of pixel regions; forming a capacitor stack within the opening and over the one or more interlayer dielectric layers; and The capacitor stack is patterned to form a capacitor having a horizontally extending segment over the one or more interlayer dielectric layers and a vertically extending segment extending through the one or more interlayer dielectric layers.

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