Selective mosi deposition

Abstract

Methods for forming semiconductor structures and semiconductor structures are described. Some embodiments of the method include patterning a substrate to form a first opening and a second opening, the substrate including an n-type transistor and a p-type transistor, the first opening over the n-type transistor and the second opening over the p-type transistor. The substrate is pre-cleaned. A molybdenum film is selectively deposited on the p-type transistor.

Description

Technical Field

[0001] Embodiments of the present disclosure belong to the field of semiconductor devices and semiconductor device manufacturing. More particularly, embodiments of the present disclosure relate to methods for selectively forming a silicide layer. Background Art

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has increased substantially, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] Transistors are key components of most integrated circuits. Since the drive current of a transistor is proportional to the gate width of the transistor (and therefore the speed of the transistor is proportional to the gate width of the transistor), faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and "fin" field effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region, which greatly increases the size of the transistor without significantly increasing the transistor footprint, and are now being used in many integrated circuits. However, finFETs have their own disadvantages.

[0004] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, it is necessary to improve the transistor device structure to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (finFET) structures, and gate all around (GAA) structures. The performance of the logic gate is related to the properties of the materials used and the thickness and area of ​​the structural layers. However, challenges arise when adjusting some gate characteristics to adapt to device scaling.

[0005] Current double silicide technology requires multiple steps to mask the nMOS junction before the pMOS silicide can be deposited. These processes result in longer and more complex processes, which greatly affects the yield. Therefore, a simplified double silicide process flow is needed, including selective silicide of the pMOS junction without masking and unmasking the nMOS junction. Summary of the invention

[0006] One or more embodiments of the present disclosure relate to a method for selectively depositing a molybdenum film. The method includes exposing a substrate surface including a first material and a second material to a pre-cleaning process and forming a residue on the substrate surface. The first material consists essentially of silicon, and the second material consists essentially of silicon germanium (SiGe). The substrate surface is exposed to a molybdenum precursor and a reducing agent to selectively form the molybdenum film on the second material relative to the first material.

[0007] Another embodiment of the present disclosure relates to a method for selectively depositing a molybdenum silicide film. The method includes: exposing a substrate surface including a first material and a second material to a cleaning agent. The first material is substantially composed of amorphous silicon, and the second material is substantially composed of silicon germanium (SiGe). The cleaning agent includes a plasma of ammonia and NF3, and exposure to the cleaning agent selectively forms a residue on the first material. The molybdenum silicide film is selectively formed on the second material relative to the first material by exposing the substrate to an argon plasma to desorb the substrate, and then exposing the substrate surface to a molybdenum precursor and a silane precursor in sequence. The substrate surface is maintained at a temperature ranging from 300 degrees Celsius to 325 degrees Celsius.

[0008] A further embodiment of the present disclosure relates to a method for selectively depositing a molybdenum silicide film. The method includes exposing a substrate surface including an n-type transistor and a p-type transistor to a cleaning agent. The source / drain material of the n-type transistor is substantially composed of amorphous silicon, and the source / drain material of the p-type transistor is substantially composed of silicon germanium (SiGe). The cleaning agent includes a plasma of ammonia and NF3, and exposure to the cleaning agent selectively forms residues on the source / drain material of the n-type transistor. The substrate is desorbed by exposing the substrate to an argon plasma, and then the substrate surface is sequentially exposed to a molybdenum precursor and a silane precursor, and the molybdenum silicide film is selectively formed on the source / drain material of the p-type transistor relative to the source / drain material of the n-type transistor. The substrate surface is maintained at a temperature ranging from 300 degrees Celsius to 325 degrees Celsius. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to be able to understand the above-mentioned features of the present disclosure in detail, reference may be made to embodiments (some of which are illustrated in the attached drawings) for a more specific description of the present disclosure briefly summarized above. However, it should be noted that the attached drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered to limit the scope of the present disclosure, as the present disclosure may allow for other equivalent embodiments.

[0010] Figure 1 a process flow diagram illustrating a method according to one or more embodiments;

[0011] Figure 2 describing a semiconductor structure according to one or more embodiments of the present disclosure; and

[0012] Figure 3 Semiconductor structures according to one or more embodiments of the present disclosure are described.

[0013] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, components of the same type may be distinguished by following the reference numeral with a dash and a second reference numeral that distinguishes the similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the second reference numeral. DETAILED DESCRIPTION

[0014] Before describing several exemplary embodiments of the present invention, it should be understood that the present invention is not limited to the details of construction or process steps set forth in the following description. The present invention is capable of other embodiments and of being practiced or carried out in various ways.

[0015] As used herein, the term "substrate" refers to a surface (or portion of a surface) upon which a process is performed. Those skilled in the art will also understand that reference to a substrate can also refer to only a portion of a substrate, unless the context clearly indicates otherwise. In addition, reference to "depositing on a substrate" can mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0016] In addition, the term "substrate" used herein refers to any substrate on which film processing is performed during the manufacturing process or the surface of a material formed on the substrate. For example, depending on the application, the substrate surface that can be processed on it includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as metal, metal nitride, metal alloy, dielectric material, other conductive material or a combination of the above materials. In some embodiments, the substrate comprises silicon (Si), ruthenium (Ru), cobalt (Co), tungsten (W), molybdenum (Mo), silicon phosphide (SiP), titanium silicon (TiSi), titanium nitride (TiN), titanium aluminum (TiAl), silicon germanium (SiGe), silicon germanium boron (SiGeB), hafnium oxide (HfO2), aluminum oxide (Al2O3) or a combination of the above materials. The substrate includes but is not limited to semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In addition to performing film treatment directly on the surface of the substrate itself, in the present disclosure, any film treatment steps disclosed may also be performed on an under-layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such under-layer as indicated by the context.

[0017] As used in this specification and the appended claims, the term "selectively" refers to a process that has a greater effect on a first surface than on another second surface. Such a process will be described as acting "selectively" on a first surface relative to (over) a second surface. The term "relative to (over)" as used in this regard does not imply the physical orientation of one surface over another surface, but refers to the relationship between the thermodynamic or kinetic properties of a chemical reaction and one surface relative to another surface.

[0018] According to one or more embodiments, the term "on" with respect to a film or film layer includes a film or layer directly on a surface (e.g., a substrate surface) and one or more underlying layers between the film or layer and the surface (e.g., the substrate surface). Thus, in one or more embodiments, the term "on a substrate surface" is intended to include one or more underlying layers. In other embodiments, the term "directly on" refers to a layer or film in contact with a surface (e.g., a substrate surface) without an intervening layer. Thus, the term "a layer directly on a substrate surface" refers to a layer in direct contact with a substrate surface with no layers in between.

[0019] As used herein, the term "substrate surface" refers to any substrate surface on which a layer can be formed. The substrate surface may have one or more features formed in the substrate surface, one or more layers formed on the substrate surface, and combinations of the above. The shape of the feature can be any suitable shape, including but not limited to peaks, grooves, and cylindrical vias. As used in this regard, the term "feature" refers to any deliberate surface irregularity. Suitable examples of features include, but are not limited to: a groove having a top, two sidewalls, and a bottom; a peak having a top and two sidewalls extending upward from the surface; and a via having sidewalls extending downward from a surface having an open bottom.

[0020] As used herein, the term "processing chamber" includes portions of the processing chamber adjacent to the substrate surface and does not encompass the entire interior space of the processing chamber. For example, in a spatially separated section of the processing chamber, the portion of the processing chamber adjacent to the substrate surface is purged of one or more reactive compounds by any suitable technique, including but not limited to: moving the substrate through a gas curtain to a portion or section of the processing chamber that is free or substantially free of reactive compounds.

[0021] As used herein, the term "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate (or a portion of the substrate surface) is sequentially exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. The sequential exposure of the reactive gases prevents or minimizes gas phase reactions between the reactive gases. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to attach to and / or react on the substrate surface. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds, so that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used in this specification and the appended claims, the term "substantially" used in this regard means that, as understood by those skilled in the art, it is possible that a small portion of the substrate may be exposed to multiple reactive gases simultaneously (due to diffusion), and the simultaneous exposure is unintended.

[0022] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into a reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas such as argon is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process so that only the purge gas flows during the time delay between pulses of the reactive compound. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle may start with compound A or compound B and continue the respective order of cycles until a film having a desired thickness is achieved. In one or more embodiments, a time-domain ALD process may be performed using more than two reactive compounds in a predetermined order.

[0023] In aspects of the spatial ALD process, a first reactive gas and a second reactive gas are delivered to the reaction zone simultaneously, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery device so that any given point on the substrate is exposed to the first reactive gas and the second reactive gas. In one or more embodiments, the spatial ALD process can be performed using more than two reactive compounds in a predetermined order.

[0024] In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially sequentially. As used herein throughout the specification, "substantially sequentially" means that a majority of the duration of exposure of the first reactive compound does not overlap with exposure of the second reactive compound, however there may be some overlap.

[0025] As used herein, the term "chemical vapor deposition" refers to exposing at least one reactive compound to deposit a material layer on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive compounds in a processing chamber to allow gas phase reaction and deposition of reactive compounds. In some embodiments, the CVD process includes exposing the substrate surface to two or more reactive compounds simultaneously. In some embodiments, the CVD process includes exposing the substrate surface to a first reactive compound continuously and intermittently to a second reactive compound. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a film having a predetermined thickness. In the CVD process, the film can be deposited by exposing to a mixed reactive compound once, or can be exposed to a mixed reactive compound multiple times and purged between exposures. In some embodiments, the substrate surface is substantially exposed to a first reactive compound and a second reactive compound simultaneously.

[0026] As used herein throughout the specification, "substantially simultaneously" means that a majority of the duration of exposure of the first reactive compound overlaps with exposure of the second reactive compound.

[0027] As used herein, the term "cleaning" includes any suitable cleaning process for removing unreacted precursors, reaction products, and by-products from a processing area. Suitable cleaning processes include moving the substrate through a gas curtain to a portion or section of the processing area that is free of or substantially free of reactants. In one or more embodiments, cleaning the processing chamber includes applying a vacuum. In some embodiments, cleaning the processing area includes flowing a purge gas over the substrate. In some embodiments, the cleaning process includes flowing an inert gas. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N2), helium (He), and argon (Ar). In some embodiments, the first reactive compound is purged from the reaction chamber for a time course ranging from 0.1 seconds to 30 seconds, 0.1 seconds to 10 seconds, 0.1 seconds to 5 seconds, 0.5 seconds to 30 seconds, from 0.5 seconds to 10 seconds, from 0.5 seconds to 5 seconds, from 1 second to 30 seconds, from 1 second to 10 seconds, from 1 second to 5 seconds, from 5 seconds to 30 seconds, from 5 seconds to 10 seconds, or from 10 seconds to 30 seconds before exposing the substrate to the second reactive compound.

[0028] As used herein, the term "liner" or "barrier layer" means a layer that is conformally formed along at least a portion of the sidewalls and / or lower surface of an opening, such that a majority of the opening prior to deposition of the layer remains unfilled after deposition of the layer. The liner can be formed along the entire sidewalls and lower surface of the opening. The liner can be formed by any process known to those skilled in the art. In some embodiments, the liner comprises a metal nitride, a PVD metal, or a combination of the foregoing materials. In one or more embodiments, the "liner" or "barrier layer" may also be selectively formed at the bottom of the structure.

[0029] A transistor is a circuit component or element that is usually formed on a semiconductor device. In addition to capacitors, inductors, resistors, diodes, wires, or other components, many transistors can be formed on a semiconductor device, depending on the circuit design. A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET). It has an insulated gate whose voltage determines the conductivity of the device. This ability to change conductivity with applied voltage is used to amplify or switch electronic signals.

[0030] Typically, a transistor includes a gate formed between a source region and a drain region. The source region and the drain region may include doped regions of the substrate and may exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and may include a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0031] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are: the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which is the terminal that regulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is designated as I S and the current entering the channel at the drain (D) is designated as I D The drain-to-source voltage is specified as V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0032] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET). It has an insulated gate whose voltage determines the conductivity of the device. This ability to change conductivity with applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the regulation of charge concentration by a metal oxide semiconductor (MOS) capacitor between a body electrode and a gate electrode, which is located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but they are all the same type and opposite to the type of the body region. The source and drain (unlike the body) are highly doped, as indicated by the "+" sign after the doping type.

[0033] If the MOSFET is an n-channel, or nMOSFET, the source and drain are n+ regions and the body is the p region. If the MOSFET is a p-channel, or pMOSFET, the source and drain are p+ regions and the body is the n region. The source is so named because it is the source of charge carriers (electrons for an n-channel and holes for a p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0034] Embodiments of the present disclosure provide semiconductor structures and methods for forming semiconductor structures. However, typical double silicide processes are very complex, requiring separate opening of contacts to n+ and p+ junctions, as well as dual lithography and etching steps. Therefore, one or more embodiments advantageously provide an integrated solution to produce double silicide on pFET contacts. In one or more embodiments, selective molybdenum silicide (MoSi) growth is used to simplify the complexity of current processes.

[0035] Embodiments of the present disclosure are described by way of accompanying drawings that illustrate a process for forming a double silicide on a pFET contact. Figure 1 A process flow diagram illustrating a method 10 of forming a semiconductor structure 100 is shown. Figure 1 Description Formation Figures 2 to 3 Any semiconductor structure method according to one or more embodiments shown.

[0036] In this regard, the term "semiconductor structure" refers not only to a structure completed according to the disclosed method, but also to an intermediate structure during processing by the disclosed method. The semiconductor structure 100 may also be referred to simply as a substrate having an exposed substrate surface. In this regard, although the methodologies disclosed herein are directed to the disclosed semiconductor structure, these methods may be equally applied to other substrates or structures. In an effort to generally describe the process, the source / drain material 120 of the n-type transistor 102 may be referred to as a first material, and the source / drain material of the p-type transistor 104 may be referred to as a second material.

[0037] In one or more embodiments, a method 10 for forming a semiconductor structure includes: at operation 12, patterning a substrate to form a first opening and a second opening, the substrate including an n-type transistor and a p-type transistor, the first opening being located above the n-type transistor and the second opening being located above the p-type transistor. At operation 14, the method 10 includes pre-cleaning the substrate. At operation 16, the method 10 includes selectively depositing a molybdenum silicide (MoSi) layer on the p-type transistor.

[0038] refer to Figure 1 and Figures 2 to 3 In some embodiments, the method includes patterning the substrate 100 to form at least one of the first opening 106 and the second opening 108 at operation 12. In one or more embodiments, patterning the substrate includes using one or more patterning techniques known to those skilled in the art of microelectronic device manufacturing. In some embodiments, the semiconductor structure 100 is provided with the first opening 106 and the second opening 108, so that patterning is not required to form the semiconductor structure 100.

[0039] refer to Figure 2 4 , a semiconductor structure 100 is shown. The semiconductor structure 100 includes an n-type transistor 102 and a p-type transistor 104. In one or more embodiments, each of the n-type transistor 102 and the p-type transistor 104 includes a dielectric material 110, source / drain materials 120, 122, and a substrate material 130.

[0040] In one or more embodiments, the dielectric material 110 may include any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material 110 includes one or more of the following: silicon, silicon oxide, silicon nitride, silicon carbide, and a low-K dielectric. As used herein, terms such as "silicon oxide" and "silicon nitride" refer to materials containing silicon and oxygen or silicon and nitrogen. "Silicon oxide" and "silicon nitride" should not be understood to imply any stoichiometric ratio. In other words, a dielectric material including silicon oxide or silicon nitride can be stoichiometric or non-stoichiometric, silicon-rich or silicon-poor. In some embodiments, the dielectric material 110 includes silicon oxide (SiO2).

[0041] In some embodiments, the n-type transistor 102 and the p-type transistor 104 include source and drain contacts. In one or more embodiments, the source / drain material 120, 122 can have more than one layer.

[0042] In one or more specific embodiments, the source / drain material 120 of the n-type transistor 102 includes silicon (Si). The source / drain 120 material of the n-type transistor 102 can be doped or undoped. In one or more embodiments, the source / drain material 120 of the n-type transistor 102 includes silicon (Si) or consists essentially of silicon (Si). In some embodiments, the source / drain material 120 of the n-type transistor 102 includes amorphous silicon.

[0043] In one or more embodiments, the source / drain material 122 of the p-type transistor 104 includes silicon germanium (SiGe). In one or more embodiments, the silicon germanium (Ge) can have any suitable germanium concentration. In some embodiments, the silicon germanium (SiGe) has a germanium concentration in the range of 10% to 100%, or in the range of 20% to 60%. The source / drain 122 material of the p-type transistor 104 can be doped or undoped. In one or more embodiments, the source / drain material 122 of the p-type transistor 104 consists essentially of undoped silicon germanium (SiGe).

[0044] refer to Figures 2 to 3In one or more embodiments, there is a first opening 106 above the n-type transistor 102, and a second opening 108 above the p-type transistor 104. The first opening 106 and the second opening 108 can have any suitable aspect ratio (the ratio of the depth of the opening to the width of the opening). In one or more embodiments, the first opening 106 and the second opening 108 can independently have an aspect ratio in the range of 3:1 to 15:1, or in the range of 6:1 to 15:1, or in the range of 9:1 to 15:1, or in the range of 12:1 to 15:1. In one or more embodiments, the first opening 106 and the second opening 108 can independently have an aspect ratio greater than 10:1.

[0045] In one or more embodiments, at operation 14, the method includes pre-cleaning the substrate. In one or more embodiments, the pre-cleaning process is maintained under vacuum to ensure that no oxide is introduced / formed on the surface of the substrate after the substrate is pre-cleaned. In some embodiments, pre-cleaning the substrate (or the surface of the substrate) removes oxides from the surface. In some embodiments, the oxide is a native oxide. In some embodiments, the clean surface forms a surface that is substantially free of oxides. As used in this manner, the term "substantially free of oxides" refers to the presence of less than or equal to 5%, 2%, 1% or 0.5% of oxygen atoms on the surface. In one or more embodiments, the pre-cleaned surface forms a source / drain material that is substantially free of oxides.

[0046] In some embodiments, the pre-cleaning process includes exposing the substrate surface to a cleaning agent comprising ammonia. In some embodiments, the cleaning agent further comprises NF3 or HF. In some embodiments, the cleaning agent consists essentially of ammonia and NF3. In some embodiments, the cleaning agent consists essentially of ammonia and HF. In some embodiments, the cleaning agent is ignited to form a clean plasma.

[0047] In some embodiments, the pre-cleaning process forms residues on the source / drain materials 120, 122. In some embodiments, the residues are formed on the source / drain materials 120 of the p-type transistor 104. In some embodiments, the residues are formed on the source / drain materials 122 of the n-type transistor 102. In some embodiments, the residues are selectively formed on the source / drain materials 120. In some embodiments, the residues include ammonium silicate.

[0048] In some embodiments, after exposing the substrate surface to the pre-cleaning process, the method further comprises dechucking the substrate. In some embodiments, dechucking the substrate comprises exposing the substrate to an Ar plasma. In some embodiments, dechucking the substrate comprises exposing the substrate to a plasma that is substantially free of any ammonia.

[0049] Without being bound by theory, it is believed that in some embodiments, the presence of residue on the substrate surface impairs the ability of the molybdenum precursor and the reducing agent to react to form a molybdenum film on the substrate.

[0050] refer to Figure 1 and Figure 3 , at operation 16, a molybdenum film 140 is selectively deposited on the source / drain 122 of the p-type transistor 104. As used in this context, a molybdenum film is any film containing molybdenum. In some embodiments, the molybdenum film consists essentially of molybdenum. In some embodiments, the molybdenum film includes or consists essentially of molybdenum silicide (MoSi).

[0051] In one or more embodiments, it has been advantageously found that molybdenum preferentially grows on silicon germanium (SiGe) (compared to silicon (Si)), thereby allowing an integrated flow without increasing the number of photolithography and etching steps. In one or more embodiments, the molybdenum film is selectively formed on the silicon germanium (SiGe) source / drain 122 of the p-type transistor, but not on the silicon source / drain 120 of the n-type transistor.

[0052] In one or more embodiments, the molybdenum film 140 may be formed by any suitable means. In one or more embodiments, the molybdenum film 140 is formed on the p-type transistor by exposing the substrate surface to a molybdenum precursor and a reducing agent.

[0053] In some embodiments, the molybdenum precursor comprises or consists essentially of a molybdenum halide. In some embodiments, the molybdenum precursor comprises or consists essentially of MoCl5.

[0054] In some embodiments, the reducing agent comprises a silane precursor and the molybdenum film comprises molybdenum silicide. In some embodiments, the silane precursor is selected from one or more of the following: monosilane, disilane, trisilane or other higher order silanes. In some embodiments, the silane precursor consists essentially of monosilane.

[0055] In some embodiments, the reducing agent comprises H2 and the molybdenum film consists essentially of molybdenum. In some embodiments, after forming the molybdenum film consisting essentially of molybdenum, the molybdenum film is exposed to a silane precursor to form a molybdenum silicide film.

[0056] In some embodiments, the substrate surface is exposed to the molybdenum precursor and the reducing agent simultaneously. In some embodiments, the molybdenum precursor is pulsed into a constant flow of the reducing agent.

[0057] In some embodiments, the substrate surface is sequentially exposed to a molybdenum precursor and a reducing agent. In some embodiments, the molybdenum film is formed by a time-based ALD process (with an intermediate substrate surface purge). In some embodiments, the molybdenum film is formed by a spatial ALD process.

[0058] In one or more embodiments, the molybdenum film 140 is selectively deposited on the source / drain material 122 of the p-type transistor and not deposited on the source / drain material 120 of the n-type transistor. As used in this specification and the appended claims, the term "selectively depositing a film on one surface relative to another surface" and similar terms mean that a first amount of film is deposited on the first surface and a second amount of film is deposited on the second surface, wherein the second amount of film is less than the first amount of film, or no film is deposited on the second surface.

[0059] The selectivity of a deposition process is often expressed as a multiple of the growth rate. For example, if the growth (or deposition) rate on one surface is 25 times faster than on another surface, the process would be described as having a selectivity of 25:1, or simply 25. In this regard, a higher ratio indicates a more selective process.

[0060] In some embodiments, the molybdenum film is formed with a selectivity greater than or equal to 5, greater than or equal to 10, greater than or equal to 15, greater than or equal to 20, or greater than or equal to 25.

[0061] In some embodiments, the method 10 enables selective deposition without masking or blocking the source / drain material 120 of the n-type transistor 102. Without being bound by theory, the disclosed method enables the formation of molybdenum films and further processing to be performed more quickly because the method does not rely on masking and revealing surfaces between deposition processes. Therefore, the disclosed method involves a shorter process flow and enables higher processing throughput.

[0062] For example, the temperature of the substrate during exposure to the ruthenium precursor can be controlled by setting the temperature of the substrate support or pedestal. This temperature is also referred to as the deposition temperature. In some embodiments, the substrate is maintained at a temperature in the range of about 300°C to about 325°C, or in the range of about 300°C to about 315°C, or in the range of about 310°C to about 325°C. The inventors were surprised to find that the disclosed method exhibits a narrow range of selectivity. At temperatures above or below the disclosed range, the disclosed method exhibits less selectivity or even no selectivity between the first material and the second material.

[0063] In some embodiments, the deposition process is performed as a thermal process without using plasma reactants. In other words, the method is performed without plasma.

[0064] In some embodiments, the thickness of the molybdenum film on the second material is greater than or equal to about 40 angstroms, greater than or equal to about 60 angstroms, or greater than or equal to about 75 angstroms. In some embodiments, the selectivity of the disclosed method deposits a molybdenum film less than 10 angstroms, less than 5 angstroms, or less than 3 angstroms on the first material.

[0065] Several known clustering tools that may be applicable to the present disclosure are and The above tools are all available from Applied Materials, Inc., Santa Clara, California, USA. The actual arrangement and combination of chambers may be varied to perform specific steps of the processes described herein. Other processing chambers that may be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma treatment, etching, pre-cleaning, chemical cleaning, thermal treatment (such as RTP), plasma nitridation, degassing, hydroxylation, and other substrate processes. By performing the processes in chambers on a cluster tool, contamination of the substrate surface with atmospheric impurities can be avoided and oxidation does not occur prior to deposition of subsequent films.

[0066] According to one or more embodiments, as the substrate moves from one chamber to the next, the substrate is continuously under vacuum or "load lock" conditions and is not exposed to ambient air. Thus, the transfer chamber is in a vacuum state and is "pumped down" at vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants (e.g., reactants). According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent reactants (e.g., reactants) from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, the inert gas flow forms a curtain at the outlet of the chamber.

[0067] It is possible to process substrates in a single substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before another substrate is processed. It is also possible to process substrates in a continuous manner similar to a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and associated conveyor system can form a straight path or a curved path. In addition, the processing chamber can be a carousel, where multiple substrates move around a central axis and are exposed to deposition, etching, annealing, cleaning, etc. processes throughout the carousel path.

[0068] During processing, the substrate can be heated or cooled. Such heating or cooling can be achieved by any suitable means, including but not limited to changing the temperature of the substrate support and flowing heated or cooled gas to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to change the substrate temperature conductively. In one or more embodiments, the gas (reactive gas or inert gas) used is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is positioned within the chamber adjacent to the substrate surface to change the substrate temperature convectively.

[0069] The substrate can also be stationary or rotated during processing. A rotating substrate can be rotated (about the substrate axis) continuously or in discrete steps. For example, the substrate can be rotated throughout the process, or the substrate can be rotated a small amount between exposures to different reactive or purge gases. Rotating the substrate during processing (continuously or stepwise) can help produce a more uniform deposition or etching by minimizing the effects of local variations in, for example, gas flow geometry.

[0070] The use of the terms "a", "an", "the" and similar references in the context of describing the materials and methods discussed herein (particularly in the context of the appended claims) should be interpreted as covering the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the recording of numerical ranges herein is intended only to be used as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually recorded herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by the context. The use of any and all examples or exemplary texts (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and is not intended to limit the scope, unless otherwise stated. Any text in the specification should not be interpreted as indicating that any unrequested element is necessary for the practice of the disclosed materials and methods.

[0071] References throughout the specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that the particular features, structures, materials, or characteristics described in conjunction with that embodiment are included in at least one embodiment of the present disclosure. Thus, the appearance of words such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" in different places throughout the specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0072] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrations of the principles and applications of the disclosure. It is apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, it is desired that the disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for selectively depositing a molybdenum film, the method comprising: exposing a substrate surface including a first material consisting essentially of amorphous silicon and a second material consisting essentially of silicon germanium (SiGe) to a pre-cleaning process and forming a residue on the substrate surface; and The substrate surface is exposed to a molybdenum precursor and a reducing agent to selectively form the molybdenum film on the second material relative to the first material.

2. The method of claim 1, wherein the pre-cleaning process comprises: The substrate surface is exposed to a cleaning agent comprising ammonia or NF3.

3. The method of claim 2, wherein the cleaning agent consists essentially of ammonia and NF3. The method of claim 2 , wherein the cleaning agent is ignited to form a cleaning plasma.

5. The method of claim 2, wherein the residue comprises ammonium silicate. The method of claim 2 , wherein the residue is selectively formed on the first material.

7. The method of claim 2, further comprising: After pre-cleaning, the substrate is desorbed.

8. The method of claim 7, wherein desorbing the substrate comprises: The substrate is exposed to argon plasma.

9. The method of claim 1, wherein the molybdenum film consists essentially of MoCl5.

10. The method of claim 1, wherein the reducing agent comprises a silane precursor.

11. The method of claim 1, wherein the reducing agent comprises H2 and the method further comprises: The molybdenum film is exposed to a silane precursor to form a molybdenum silicide film.

12. The method of claim 1, wherein the substrate surface is exposed to the molybdenum precursor and the reducing agent simultaneously.

13. The method of claim 11, wherein the molybdenum precursor is pulsed into a constant flow of the reducing agent.

14. The method of claim 1, wherein the substrate surface is exposed to the molybdenum precursor and the reducing agent sequentially.

15. The method of claim 1, wherein the molybdenum film is formed with a selectivity greater than or equal to about 20.

16. The method of claim 1, wherein the molybdenum film is selectively formed on the second material without masking or blocking the first material.

17. The method of claim 1, wherein the substrate is maintained at a temperature in a range of 300 degrees Celsius to 325 degrees Celsius.

18. The method of claim 1, wherein the first material comprises a source / drain material for an n-type transistor and the second material comprises a source / drain material for a p-type transistor.

19. A method for selectively depositing a molybdenum silicide film, the method comprising: exposing a surface of a substrate including a first material and a second material to a cleaning agent, wherein the first material consists essentially of amorphous silicon and the second material consists essentially of silicon germanium (SiGe), the cleaning agent comprising a plasma of ammonia and NF3, wherein the exposure to the cleaning agent selectively forms a residue on the first material; desorbing the substrate by exposing the substrate to an argon plasma; and The substrate surface is sequentially exposed to a molybdenum precursor and a silane precursor to selectively form the molybdenum silicide film on the second material relative to the first material, and the substrate surface is maintained at a temperature ranging from 300 degrees Celsius to 325 degrees Celsius.

20. A method for selectively depositing a molybdenum silicide film, the method comprising: Exposing a substrate surface including an n-type transistor and a p-type transistor to a cleaning agent, wherein the source / drain material of the n-type transistor consists essentially of amorphous silicon, and the source / drain material of the p-type transistor consists essentially of silicon germanium (SiGe), wherein the cleaning agent comprises a plasma of ammonia and NF3, wherein the exposure to the cleaning agent selectively forms a residue on the source / drain material of the n-type transistor; desorbing the substrate by exposing the substrate to an argon plasma; and The substrate surface is sequentially exposed to a molybdenum precursor and a silane precursor to selectively form the molybdenum silicide film on the source / drain material of the p-type transistor relative to the source / drain material of the n-type transistor, and the substrate surface is maintained at a temperature ranging from 300 degrees Celsius to 325 degrees Celsius.

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