OLED anti-aging area compensation

Abstract

Aspects presented herein relate to methods and apparatus for display processing, including devices, such as a CPU. The apparatus may obtain an indication of at least one frame including a set of pixels, wherein the at least one frame is associated with at least one layer. The apparatus may also detect a first subset of pixels included in the set of pixels in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold. Further, the device may identify one or more regions of the at least one frame that include all pixels in the first subset of pixels. The apparatus may also increase the brightness value of each pixel in the first subset of pixels or decrease the brightness value of each pixel in the second subset of pixels.

Description

Technical Field

[0001] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing. Background Art

[0002] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may require the use of a GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and may issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0003] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0004] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0005] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may be a central processing unit (CPU), a display processing unit (DPU), a graphics processing unit (GPU), or any device that can perform display processing. The device may obtain an indication of at least one frame associated with the display processing, wherein the at least one frame includes a pixel set, wherein the at least one frame is associated with at least one layer. The device may also detect a first subset of pixels in the pixel set included in the at least one frame, wherein each pixel in the first pixel subset includes an attenuation ratio below an attenuation ratio threshold. Additionally, the device may mark each pixel in the first pixel subset in the pixel set, wherein each pixel in the first pixel subset includes the attenuation ratio below the attenuation ratio threshold. The device may also identify one or more regions of the at least one frame including all pixels in the first pixel subset. In addition, the device may calculate a set of coordinates for each of the one or more regions of the at least one frame including all pixels in the first pixel subset. The device may also analyze multiple windows in the at least one frame based on the set of coordinates for each of the one or more regions of the at least one frame including all pixels in the first pixel subset. The device may also determine that the one or more regions correspond to the entire region of the at least one frame. In addition, the device may avoid increasing the brightness value of each pixel in the first pixel subset and avoid reducing the brightness value of each pixel in the second pixel subset based on the one or more regions corresponding to the entire region of the at least one frame. The device may also increase the brightness value of each pixel in the first pixel subset in the one or more regions or reduce the brightness value of each pixel in the second pixel subset in the one or more regions, wherein each pixel in the second pixel subset is not included in the first pixel subset. The device may also send a second indication that the brightness value of each pixel in the first pixel subset in the one or more regions is increased or the brightness value of each pixel in the second pixel subset in the one or more regions is reduced.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system.

[0008] Figure 2 An example graphics processing unit (GPU) is illustrated.

[0009] Figure 3 An example display framework including a display processor and a display is illustrated.

[0010] Figure 4 is a diagram illustrating an example mask layer for display processing.

[0011] Figure 5 is a diagram illustrating an example layer composition scheme for display processing.

[0012] Figure 6 is a diagram illustrating an example of pixel brightness performance at a display device.

[0013] Figure 7 is a diagram illustrating an example of an anti-aging compensation area at a display.

[0014] Figure 8 is a diagram illustrating an example of an anti-aging compensation scheme at a display.

[0015] Fig. 9 is a communication flow diagram illustrating example communications between the CPU, DPU, and GPU.

[0016] Fig.10 is a flow chart showing an example method of processing.

[0017] Fig.11 is a flow chart showing an example method of processing. DETAILED DESCRIPTION

[0018] Some types of display devices (e.g., mobile devices, computers, TVs, or other consumer devices) may utilize certain types of light-emitting diodes (LEDs) (e.g., organic light-emitting diodes (OLEDs)) in displays. If static bright pixels are displayed for a long time, some types of LEDs (e.g., OLEDs) may have burn-in problems (i.e., pixels will always remain incorrect colors due to long-term exposure to a specific color). For example, static logos, icons, user interfaces (UIs), system UIs, and browsers are the main causes of current OLED pixel burn-in. In addition, there are currently many industry solutions for anti-burn-in or anti-aging. For example, an anti-burn-in or anti-aging solution (i.e., a solution for physically attenuating pixels / sub-pixels) may randomly offset a few pixels (e.g., 1 or 2 pixels) of those image bright objects during runtime. This may apply to certain pixels (e.g., pixels for limited system UI small icons). Additionally, an anti-burn-in or anti-aging solution may record display pixels on time, calculate attenuation factors, and / or apply runtime pixel compensation. This solution may be applicable to all applications and corresponds to improved visual quality. In addition, the solution may require a complex runtime compensation / calibration mechanism to balance display panel visual quality, device power / performance, and anti-burn-in efficiency. Therefore, OLED anti-aging is an important issue in the display industry, which can use complex runtime compensation. As indicated herein, there may be many problems with the pixel brightness performance at the display device. In order to compensate for physical decay pixels / sub-pixels, there may be several solutions. For example, for pixels with low brightness due to decay or pixels with fast or high decay rates (i.e., "bad" pixels), their brightness can be improved. However, this solution may not be suitable for white or bright content images because some brightness values ​​(e.g., 255 brightness) may not be promoted to larger values. The solution can also decay all other appropriate frame pixel brightness to match bad pixels. In some instances, the brightness of pixels with slow or low decay rates (i.e., "good" pixels) can decay, which means that the maximum brightness of the panel can be reduced to the "bad" pixel brightness level. Additionally, in some aspects, the decay / reduction of the maximum brightness of the pixel in the anti-aging solution can be determined based on the pixel with the most severe decay. In addition, the more severe the decay of the "bad" pixel, the lower the maximum brightness of the display panel. The maximum brightness of the display panel may also be a key performance indicator (KPI) and may be important to the end user. Furthermore, reducing the maximum brightness of the panel may severely limit current OLED anti-aging solutions. Therefore, the maximum brightness of the panel can be reduced by global anti-aging in order to attenuate the "good" pixel values ​​to match the "bad" pixels within the frame. Various aspects of the present disclosure can utilize regional anti-burn-in or anti-aging solutions. That is, various aspects presented herein can perform regional adjustments to the brightness of different pixels within a specific area of ​​the frame.For example, various aspects of the present disclosure may utilize regional anti-burn-in or anti-aging solutions for pixels with fast or high decay rates (i.e., bad pixels). For example, various aspects of the present disclosure may enhance the brightness of pixels with fast or high decay rates. In addition, the various aspects presented herein may attenuate or reduce the brightness of pixels with slow or low decay rates (i.e., good pixels) to match bad pixels in a local area. In some instances, the various aspects presented herein may avoid pixels with faster or higher decay rates (i.e., bad pixels) from reducing the maximum brightness of the panel compared to pixels with slower or lower decay rates (i.e., good pixels). The various aspects presented herein may also enhance the maximum brightness and average brightness of the panel when applying anti-aging solutions. In addition, the various aspects presented herein may utilize bad pixel-based compensation, which may be more robust to varying decay factors (e.g., real physical panel decay factors) compared to full pixel-based solutions.

[0019] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method practiced using other structures, functionality, or structure and functionality other than the various aspects of the disclosure set forth herein or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0020] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure rather than limit it, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0021] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0022] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chips (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including a code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0023] Therefore, in one or more examples described herein, the described functions may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media may be any available medium that can be accessed by a computer. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage devices, magnetic disk storage devices, other magnetic storage devices, a combination of computer-readable media of the above types, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0024] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0025] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0026] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to synthesize, blend or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently blended.

[0027] Figure 1 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this situation is referred to as split rendering.

[0028] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (such as display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0029] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0030] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0031] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0032] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagation signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0033] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0034] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0035] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0036] Reference again Figure 1In certain aspects, the display processor 127 may include a compensation component 198 configured to obtain an indication of at least one frame associated with display processing, wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer. The compensation component 198 may also be configured to detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold. The compensation component 198 may also be configured to mark each pixel in the first subset of pixels in the set of pixels, wherein each pixel in the first subset of pixels includes an attenuation ratio below the attenuation ratio threshold. The compensation component 198 may also be configured to identify one or more regions of the at least one frame that include all pixels in the first subset of pixels. The compensation component 198 may also be configured to calculate a set of coordinates for each of the one or more regions of the at least one frame that include all pixels in the first subset of pixels. The compensation component 198 may also be configured to analyze a plurality of windows in the at least one frame based on the set of coordinates for each of the one or more regions of the at least one frame that include all pixels in the first subset of pixels. The compensation component 198 may also be configured to determine that the one or more regions correspond to the entire region of the at least one frame. The compensation component 198 may also be configured to avoid raising the brightness value of each pixel in the first pixel subset and avoid lowering the brightness value of each pixel in the second pixel subset based on the one or more regions corresponding to the entire region of the at least one frame. The compensation component 198 may also be configured to raise the brightness value of each pixel in the first pixel subset of the one or more regions or lower the brightness value of each pixel in the second pixel subset of the one or more regions, wherein each pixel in the second pixel subset is not included in the first pixel subset. The compensation component 198 may also be configured to send a second indication that the brightness value of each pixel in the first pixel subset of the one or more regions is raised or the brightness value of each pixel in the second pixel subset of the one or more regions is lowered. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0037] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, a vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0038] The GPU may process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU may process two types of data or data packets, such as context register packets and draw call data. The context register packet may be a collection of global state information, such as information about global registers, shaders, or constant data, which may adjust how the graphics context is to be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, the context register may define multiple states of the GPU.

[0039] The context state may be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads (e.g., vertex or pixel workloads) in a pipeline based on context register definitions of a mode or state. Certain processing units (e.g., VFDs) may use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. Additionally, the workload corresponding to the mode or state may follow the changed mode or state.

[0040] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220 to 238, but GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and any combination or order of processing units may be used with a GPU according to the present disclosure. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0041] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0042] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs may allow both tile rendering and direct rendering.

[0043] Figure 3is a block diagram 300 illustrating an example display framework including a processing unit 120 , a system memory 124 , a display processor 127 , and a display 131 , as may be identified in connection with device 104 .

[0044] The GPU may be included in a device that provides content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, a mobile phone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of the GPU 310 may be controlled based on one or more graphics processing commands provided by the CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the multiple applications executed concurrently may utilize the GPU 310 at the same time. The processing technology may be performed by outputting frames via the processing unit 120 over a physical or wireless communication channel.

[0045] System memory 124, which may be executed by processing unit 120, may include user space 320 and kernel space 325. User space 320 (sometimes referred to as "application space") may include software applications and / or application frameworks. For example, software applications may include operating systems, media applications, graphics applications, workspace applications, etc. The application framework may include a framework used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. Kernel space 325 may further include a display driver 330. Display driver 330 may be configured to control display processor 127. For example, display driver 330 may cause display processor 127 to synthesize a frame and send data of the frame to a display.

[0046] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 may be configured to manipulate functions of display 131 (e.g., based on input received from display driver 330). Display control block 335 may be further configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of processing unit 120 on system memory 124.

[0047] The display interface 340 may be configured to cause the display 131 to display an image frame. The display interface 340 may output image data to the display 131 according to an interface protocol such as, for example, MIPIDSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display 131 may be configured according to the MIPIDSI standard. The MIPIDSI standard supports a video mode and a command mode. In an example where the display 131 operates in the video mode, the display processor 127 may continuously refresh the graphics content of the display 131. For example, the entire graphics content may be refreshed at each refresh cycle (e.g., line by line). In an example where the display 131 operates in the command mode, the display processor 127 may write the graphics content of the frame to the buffer 350.

[0048] In some such examples, display processor 127 may not continuously refresh the graphics content of display 131. Instead, display processor 127 may use vertical synchronization (Vsync) pulses to coordinate the rendering and consumption of graphics content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 may output new graphics content to buffer 350. Thus, the generation of a Vsync pulse may indicate that current graphics content has been rendered at buffer 350.

[0049] Based on the display controller 345, the display client 355, and the buffer 350, the frame is displayed at the display 131. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

[0050] The display client 355 may be associated with a touch panel that senses interactions between a user and the display 131. When a user interacts with the display 131, one or more sensors in the touch panel may output a signal to the display controller 345 indicating which of the one or more sensors has sensor activity, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. The display controller 345 may use the sensor output to determine the manner in which the user is interacting with the display 131. The display 131 may further be associated with / include other devices that operate in conjunction with the display client 355, such as a camera, a microphone, and / or a speaker.

[0051] Some processing techniques of device 104 may be performed through three stages (e.g., stage 1: rendering stage; stage 2: composition stage; and stage 3: display / delivery stage). However, other processing techniques may combine the composition stage and the display / delivery stage into a single stage, such that the processing technique may be performed based on a total of two stages (e.g., stage 1: rendering stage; and stage 2: composition / display / delivery stage). During the rendering stage, GPU 310 may process a content buffer based on the execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stages, pixel elements may be assembled to form a frame that is delivered to a physical display panel / subsystem (e.g., display 131) that displays the frame.

[0052] Instructions (e.g., software instructions) executed by a CPU or instructions executed by a display processor may cause the CPU or display processor to search and / or generate a synthesis strategy for synthesizing a frame based on dynamic priorities and runtime statistics associated with one or more synthesis strategy groups. A frame to be displayed by a physical display device (such as a display panel) may include multiple layers. In addition, the synthesis of a frame may be based on combining multiple layers into a frame (e.g., based on a frame buffer). After combining multiple layers into a frame, the frame may be provided to a display panel for display on the display panel. The process of combining each layer in a plurality of layers into a frame may be referred to as synthesis, frame synthesis, synthesis procedure, synthesis process, etc.

[0053] The frame synthesis procedure or synthesis strategy may correspond to a technique for synthesizing different layers in a plurality of layers into a single frame. The plurality of layers may be stored in a double data rate (DDR) memory. Each layer in the plurality of layers may further correspond to a separate buffer. A synthesizer or hardware synthesizer (HWC) associated with a block or function may determine the input of each layer / buffer and execute the frame synthesis procedure to generate an output indicating a synthesized frame. That is, the input may be a layer, and the output may be a frame synthesis procedure for synthesizing a frame to be displayed on a display panel.

[0054] Some aspects of display processing may utilize different types of mask layers, such as shape mask layers. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of ​​a mask layer may correspond to an area of ​​a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but a middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of the display area. Additionally, for certain portions of the display area, the content of different mask layers may overlap with each other. Thus, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

[0055] Figure 44 is a diagram illustrating an example mask layer for display processing. More specifically, diagram 400 depicts one type of mask layer that can represent portions of a display panel. Figure 4 As shown, diagram 400 includes a mask layer 402, which includes a top region 410 and a bottom region 420. The top region 410 includes regions 411, 412, 413, and 414, and the bottom region 420 includes regions 421, 422, 423, and 424. Figure 4 As depicted, mask layer 402 may represent different areas displayed on the display panel.

[0056] Some types of displays may use a certain type of mask layer (e.g., a shape mask layer) to reshape the display frame. For example, the mask layer may reshape the display frame to provide a more optimized visual shape at the display panel (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.). These types of mask layers (e.g., shape mask layers) may be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software), or by hardware (e.g., display processing unit (DPU) hardware). In addition, these mask layers may be processed by other specific types of hardware logic modules (e.g., modules in display driver integrated circuits (DDICs) or bridge chips). In some aspects, these types of mask layers (e.g., shape mask layers) may be based on a certain unit, such as a pixel. That is, the shape generation base unit of the shape mask layer may be a single pixel.

[0057] Some aspects of display processing can utilize frame buffers to cache or store the composite output of the GPU. For example, after being synthesized at the GPU, the display layer can be cached or stored in a frame buffer. In some aspects, the synthesis hardware (HW) or software (SW) stack can use a frame buffer target to cache the synthesis output (e.g., GPU synthesis output or CPU synthesis output). The cached synthesis output can then be transmitted to another processor (e.g., DPU) as an input layer. The frame buffer can have multiple different color formats, such as red (R) green (G) blue (B) α (A) (RGBA) format (e.g., RGBA8888 format). Moreover, the frame buffer can have a specific size (e.g., 32-bit triple buffer). For example, at the beginning of the display / graphics subsystem design, the frame buffer can be created as RGBA8888 format and 32-bit triple buffer. In some instances, if the frame layer does not use a specific synthesis (e.g., GPU or client synthesis), the frame buffer can be ignored. Moreover, the layer (e.g., a frame layer or display layer associated with the display process) can be directly extracted and synthesized. For example, a DPU or hardware synthesizer may extract the layers directly and then synthesize the layers.

[0058] Figure 5 5 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 500 depicts layer composition of display layers, where some layers (e.g., layers of a particular composition) are cached in a frame buffer and some layers are fetched and composed directly by the DPU. Figure 5 As shown, diagram 500 includes layer 510 , layer 511 , layer 512 , layer 513 , a frame buffer 530 (eg, an RGBA8888 format frame buffer), a DPU 540 , and a display 550 . Figure 5 It is depicted that layers synthesized at the GPU (i.e., layers associated with GPU synthesis) can be cached or stored in a frame buffer. For example, layer 510, layer 511, and layer 512 can be synthesized at the GPU and then cached / stored at frame buffer 530. Alternatively, layers that are not synthesized at the GPU (i.e., layers associated with non-GPU synthesis) can be directly extracted and synthesized at the DPU. For example, layer 513 can be directly extracted and synthesized at DPU 540. That is, layer 510, layer 511, and layer 512 can be a particular type of synthesis (e.g., GPU synthesis), while layer 513 can be another type of synthesis (non-GPU synthesis). After being cached / stored in frame buffer 530, layer 510, layer 511, and layer 512 can be transmitted to DPU 540. In addition, after processing at DPU 540, layers 510 to 513 can be transmitted to display 550.

[0059] Some types of display devices (e.g., mobile devices, computers, TVs, or other consumer devices) may utilize certain types of light-emitting diodes (LEDs) (e.g., organic light-emitting diodes (OLEDs)) in displays. If static bright pixels are displayed for a long time, some types of LEDs (e.g., OLEDs) may have burn-in problems (i.e., pixels will always remain incorrect colors due to long-term exposure to a specific color). For example, static logos, icons, user interfaces (UIs), system UIs, and browsers are the main causes of current OLED pixel burn-in. In addition, there are currently many industry solutions for anti-burn-in or anti-aging. For example, an anti-burn-in or anti-aging solution (i.e., a solution for physically attenuating pixels / sub-pixels) may randomly offset a few pixels (e.g., 1 or 2 pixels) of those image bright objects during runtime. This may apply to certain pixels (e.g., pixels for limited system UI small icons). Additionally, an anti-burn-in or anti-aging solution may record display pixels on time, calculate attenuation factors, and / or apply runtime pixel compensation. This solution may be applicable to all applications and corresponds to improved visual quality. In addition, the solution may require a complex runtime compensation / calibration mechanism to balance display panel visual quality, device power / performance, and anti-burn-in efficiency. Therefore, OLED burn-in prevention is an important issue in the display industry, which may utilize complex runtime compensation.

[0060] Figure 6 600 is a diagram illustrating an example of pixel brightness performance at a display device. More specifically, diagram 600 depicts some display regions with good pixel brightness attenuation and some display regions with poor pixel brightness compensation. For example, diagram 600 depicts frame 610 and frame 620 (i.e., display frames) in which region 602 with good pixel brightness attenuation and region 604 with poor pixel brightness compensation are located at different positions. Figure 6 As shown, in frame 610, area 602 with good pixel brightness attenuation is located in the middle of the frame, while area 604 with poor pixel brightness compensation is located at the bottom of the frame. In frame 620, area 602 with good pixel brightness attenuation is located in the middle of the frame, while area 604 with poor pixel brightness compensation is located at the top of the frame and at the bottom of the frame. As indicated herein, area 602 with good pixel brightness attenuation corresponds to an area of ​​the frame without pixel burn-in or burn-in issues, while area 604 with poor pixel brightness compensation corresponds to an area of ​​the frame with pixel burn-in or burn-in issues.

[0061] like Figure 6As indicated, there may be many problems with pixel brightness performance at the display device. In order to compensate for physical decay pixels / sub-pixels, there may be several solutions. For example, for pixels with low brightness due to decay or pixels with fast or high decay rates (i.e., "bad" pixels), their brightness can be improved. However, this solution may not be suitable for white or bright content images because some brightness values ​​(e.g., 255 brightness) may not be promoted to a larger value. The solution can also decay all other appropriate frame pixel brightness to match the bad pixels. In some instances, the brightness of pixels with slow or low decay rates (i.e., "good" pixels) can be decayed, which means that the maximum brightness of the panel can be reduced to the "bad" pixel brightness level.

[0062] Additionally, in some aspects, the attenuation / reduction of the maximum brightness of a pixel in an anti-aging solution may be determined based on the pixel with the most severe attenuation. In addition, the more severe the attenuation of the "bad" pixel, the lower the maximum brightness of the display panel. The maximum brightness of the display panel may also be a key performance indicator (KPI) and may be important to the end user. In addition, reducing the maximum brightness of the panel may severely limit current OLED anti-aging solutions. Therefore, the maximum brightness of the panel can be reduced by global anti-aging in order to attenuate the "good" pixel value to match the "bad" pixel within the frame. Therefore, it may be beneficial to utilize a regional anti-burn-in or anti-aging solution. For example, it may be beneficial to perform regional adjustments to the brightness of different pixels within a specific area of ​​a frame.

[0063] Aspects of the present disclosure may utilize regional anti-burn-in or anti-aging solutions. That is, the aspects presented herein may perform regional adjustments to the brightness of different pixels within a specific region of a frame. For example, aspects of the present disclosure may utilize regional anti-burn-in or anti-aging solutions for pixels with fast or high decay rates (i.e., bad pixels). For example, aspects of the present disclosure may enhance the brightness of pixels with fast or high decay rates. In addition, the aspects presented herein may attenuate or reduce the brightness of pixels with slow or low decay rates (i.e., good pixels) to match bad pixels in a local area. In some instances, the aspects presented herein may avoid pixels with faster or higher decay rates (i.e., bad pixels) from reducing the maximum brightness of the panel compared to pixels with slower or lower decay rates (i.e., good pixels). The aspects presented herein may also enhance the maximum brightness and average brightness of the panel when applying an anti-aging solution. In addition, the aspects presented herein may utilize bad attention pixel-based compensation, which may be more robust to varying decay factors (e.g., real physical panel decay factors) compared to full pixel-based solutions.

[0064] In order to implement a regional anti-aging solution, the various aspects presented herein can detect static pixels (or sub-pixels) with fast / high attenuation ratios (i.e., bad pixels) or below a attenuation ratio threshold. The pixel attenuation ratio threshold can be obtained through runtime analysis or preconfigured. For example, the current device pixel brightness attenuation percentage (or ratio) can be 85-98%. Most pixels (e.g., 99% of pixels) may include an attenuation ratio within a specific ratio or percentage (e.g., 96-98%). In addition, several pixels (e.g., less than 1% of pixels) may include an attenuation percentage below the ratio (e.g., 85%-88%). If the attenuation percentage of a pixel (or sub-pixel) is below a specific value (e.g., below 88%), then the various aspects presented herein may mark the pixel (or sub-pixel) as a bad pixel (or bad sub-pixel).

[0065] The various aspects presented herein may also provide runtime regional anti-aging solutions to those areas including bad pixels and ignore other areas (i.e., areas without any bad pixels or "good" areas). In addition, the various aspects of the present disclosure may perform analysis of frame layer stacking and multi-window stacking states. The various aspects presented herein may also identify local anti-aging compensation areas. For example, the various aspects presented herein may identify local anti-aging compensation areas in the following manner: if multiple windows or virtual display or split screen display are present in the current frame, then the various aspects presented herein may select a specific window / virtual display containing a specific area of ​​interest (i.e., a "bad" area) as an anti-aging compensation local area. The various aspects presented herein may also select a layer containing a specific area of ​​interest (i.e., a "bad" area) as an anti-aging compensation local area. In addition, the various aspects presented herein may attenuate the brightness value of a "good" pixel to match the brightness value of a "bad" pixel. The attenuation process for different pixel brightness values ​​may be performed in a specific area of ​​a frame (e.g., an anti-aging compensation local area).

[0066] Additionally, aspects presented herein may identify regions (i.e., "bad" regions) that contain certain pixels of interest (i.e., pixels with faster or higher decay rates or "bad" pixels). There may be several such regions (i.e., "bad" regions) that include pixels of interest (i.e., pixels with faster or higher decay rates) within a frame. For example, there may be two "bad" regions, one in the middle of the frame / panel and another at the bottom of the frame / panel. For example, the middle "bad" region of interest may be 911 x 265 pixels (i.e., width x height in pixels), and the bottom "bad" region of interest may be 221 x 106 pixels (i.e., width x height in pixels).

[0067] Figure 7The present invention includes diagrams 700 and 750, respectively illustrating examples of anti-aging compensation regions at a display. More specifically, diagrams 700 and 750 depict different regions of a pixel (eg, anti-aging compensation region 702 and anti-aging compensation region 752) for anti-aging compensation. Figure 7 As shown, diagram 700 includes frame 710, which includes region 720 (i.e., a pixel region including a decay ratio below a decay ratio threshold). Region 720 can be subjected to anti-aging compensation (i.e., region 720 is a part of anti-aging compensation region 702). Figure 7 As depicted, diagram 750 includes frame 760, which includes region 770 and region 771 (i.e., a region of pixels including a decay ratio below a decay ratio threshold). Regions 770 and 771 may also be subjected to anti-aging compensation (i.e., regions 770 and 771 are part of anti-aging compensation region 752). Regions 770 and 771 may be identified as including all pixels including a decay ratio below a decay ratio threshold (i.e., pixels having a fast decay rate). The decay ratio threshold may distinguish between the types of pixels in frames 710 and 760. For example, pixels having a fast decay rate (i.e., a bad pixel) may include a decay ratio below a decay ratio threshold (i.e., a decay ratio of 0.85-0.88). Pixels having a slow decay rate (i.e., a good pixel) may include a decay ratio above a decay ratio threshold (i.e., a decay ratio of 0.96-0.98). For example, the decay ratio threshold may be equal to a decay ratio of approximately 0.88-0.92.

[0068] In some aspects, if a specific region of interest (i.e., a "bad" pixel region) is extended within a frame or the region is too large (e.g., the "anti-aging compensation local region" is too large), then the various aspects presented herein may not utilize a regional anti-aging solution. For example, if a specific region of interest (i.e., a "bad" pixel region) is extended within a frame or the region is too large (e.g., the "anti-aging compensation local region" is too large), then the various aspects presented herein may skip the regional anti-aging solution and fall back on the traditional frame global anti-aging solution. Regional and / or global anti-aging strategies may be selected based on the application or determined by other device-specific strategies during runtime.

[0069] As indicated herein, aspects of the present disclosure may include regional anti-aging and runtime strategies based on layer regions of interest (layer ROIs). For example, the various aspects presented herein may compensate for pixels with fast or high decay rates (i.e., bad pixels with a decay ratio below a decay ratio threshold). In some instances, the various aspects of the present disclosure may compensate for these specific "bad" pixels, rather than all pixels in the display. The various aspects presented herein may also include multi-window, layer stacking, and / or virtual display adaptive regional anti-aging solutions. In addition, the various aspects presented herein may perform runtime selection (e.g., runtime region and global anti-aging runtime selection) and switching strategies. The runtime selection and switching strategies may be based on applications and other configurations.

[0070] Figure 8 800 is a diagram illustrating an example of an anti-aging compensation scheme for a display device. More specifically, diagram 800 depicts a pixel region (eg, anti-aging compensation region 802) for anti-aging compensation. Figure 8 As shown, diagram 800 includes a frame 810, which includes an area 820 (i.e., a pixel area including a decay ratio below a decay ratio threshold), a CPU 830, and a DPU 850. Area 820 can be subjected to anti-aging compensation (i.e., area 820 is part of the anti-aging compensation area 802). Area 820 can be identified as including all pixels including a decay ratio below the decay ratio threshold (i.e., pixels with a fast decay rate). The decay ratio threshold can distinguish the type of pixels in frame 810. For example, pixels with a fast decay rate (i.e., bad pixels) can include a decay ratio below the decay ratio threshold (i.e., a decay ratio of 0.85-0.88). Pixels with a slow decay rate (i.e., good pixels) can include a decay ratio above the decay ratio threshold (i.e., a decay ratio of 0.96-0.98). For example, the decay ratio threshold can be equal to a decay ratio of approximately 0.88-0.92. The identification of region 820 may be performed at CPU 830 (e.g., by DPU driver software at CPU 830). CPU 830 (e.g., DPU driver software at CPU 830) may then increase the brightness value of each of the “bad” pixels in region 820. CPU 830 may also decrease the brightness value of each of the “good” pixels in region 820. CPU 830 may then send an indication of the brightness value increase or brightness value decrease to DPU 850.

[0071] like Figure 8As shown, the CPU 830 may obtain an indication of a frame 810 including a set of pixels (e.g., obtain the indication from a GPU). The CPU 830 may then detect a first subset of pixels in the set of pixels included in the frame 810, wherein each pixel in the first subset of pixels includes a decay ratio below a decay ratio threshold. The CPU 830 may then identify one or more regions (e.g., region 820) of the frame 810 including all pixels in the first subset of pixels, wherein all pixels in the first subset of pixels include a decay ratio below the decay ratio threshold. The first subset of pixels may include pixels with a fast decay rate (i.e., bad pixels) that include a decay ratio below the decay ratio threshold (i.e., a decay ratio of 0.85-0.88). The CPU 830 may then increase the brightness value of each pixel in the first subset of pixels in the region 820 and / or decrease the brightness value of each pixel in the second subset of pixels in the region 820, wherein each pixel in the second subset of pixels is not included in the first subset of pixels. The second subset of pixels may include pixels with slow decay rates (i.e., good pixels) that include decay ratios above a decay ratio threshold (i.e., a decay ratio of 0.96-0.98). The CPU 830 may also mark each pixel in the first subset of pixels that includes a decay ratio below the decay ratio threshold (i.e., a pixel with a fast decay rate). Additionally, the CPU 830 may calculate a set of coordinates for each of the one or more regions (e.g., region 820) of the frame 810 that include all pixels in the first subset of pixels. The CPU 830 may then analyze multiple windows in the frame 810 based on the set of coordinates for each of the one or more regions (e.g., region 820) of the frame 810 that include all pixels in the first subset of pixels. Furthermore, the CPU 830 may determine that the one or more regions (e.g., region 820) correspond to the entire region of the frame 810. After this determination, the CPU 830 may avoid increasing the brightness value of each pixel in the first pixel subset (e.g., “bad” pixels) and / or avoid decreasing the brightness value of each pixel in the second pixel subset (e.g., “good” pixels) based on the one or more regions (e.g., region 820) corresponding to the entire area of ​​the frame 810.

[0072] Aspects of the present disclosure may include multiple benefits or advantages. The various aspects presented herein may perform regional adjustments to the brightness of different pixels within a specific region of a frame. For example, the various aspects of the present disclosure may utilize regional anti-burn-in or anti-aging solutions for pixels with fast or high decay rates (i.e., bad pixels). For example, the various aspects of the present disclosure may enhance the brightness of pixels with fast or high decay rates. In addition, the various aspects presented herein may attenuate or reduce the brightness of pixels with slow or low decay rates (i.e., good pixels) to match the bad pixels in the local area. In some instances, compared with pixels with slower or lower decay rates (i.e., good pixels), the various aspects presented herein may avoid pixels with faster or higher decay rates (i.e., bad pixels) from reducing the maximum brightness of the panel. The various aspects presented herein may also enhance the maximum brightness and average brightness of the panel when applying the anti-aging solution. In addition, the various aspects presented herein may utilize bad attention pixel basis compensation, which may be more robust to varying decay factors (e.g., real physical panel decay factors) compared to full pixel basis solutions.

[0073] Fig. 9 FIG. 9 is a communication flow diagram 900 showing a process according to one or more techniques of the present disclosure. Fig. 9 As shown, diagram 900 includes example communications between a CPU 902 (DPU driver, other central processing unit, or display processor), a GPU 904, and a DPU 906 according to one or more techniques of this disclosure.

[0074] At 910, CPU 902 may obtain an indication of at least one frame associated with display processing (eg, CPU 902 may obtain indication 912 from GPU 904), wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer.

[0075] At 920, CPU 902 may detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold. In some examples, the attenuation ratio threshold may correspond to an attenuation ratio list of all pixels in the set of pixels included in the at least one frame, and the attenuation ratio list may be sorted in ascending order based on the attenuation ratio of each pixel in the set of pixels or in descending order based on the attenuation ratio of each pixel in the set of pixels.

[0076] At 930, CPU 902 may mark each pixel in a first subset of pixels in the set of pixels, wherein each pixel in the first subset of pixels includes a decay ratio below a decay ratio threshold. In some aspects, the decay ratio threshold may be obtained through runtime analysis, and / or the decay ratio threshold may be preconfigured.

[0077] At 940, CPU 902 may identify one or more regions of the at least one frame including all pixels in the first pixel subset. The one or more regions may correspond to one or more anti-aging compensation regions. Additionally, the one or more regions may include a first region and a second region, wherein the first region and the second region together include all pixels in the first pixel subset. In some instances, the one or more regions of the at least one frame including all pixels in the first pixel subset may be identified based on at least one other application or preconfiguration. In some aspects, the one or more regions of the at least one frame including all pixels in the first pixel subset may be identified by at least one of the following: a display processing unit (DPU) driver, a central processing unit (CPU), a DPU driver software, a DPU, a display driver, or a display driver software.

[0078] At 950, CPU 902 may calculate a set of coordinates for each of the one or more regions of the at least one frame that includes all pixels in the first subset of pixels.

[0079] Additionally, at 950, the CPU 902 may analyze the plurality of windows in the at least one frame based on a set of coordinates of each of the one or more regions of the at least one frame that include all pixels in the first subset of pixels.

[0080] At 960, CPU 902 may determine that the one or more regions correspond to an entire region of the at least one frame.

[0081] Additionally, at 960, the CPU 902 may avoid increasing the brightness value of each pixel in the first subset of pixels and avoid decreasing the brightness value of each pixel in the second subset of pixels based on the one or more regions corresponding to the entire region of the at least one frame.

[0082] At 970, the CPU 902 may increase the brightness value of each pixel in the first subset of pixels in the one or more regions and / or decrease the brightness value of each pixel in the second subset of pixels in the one or more regions, wherein each pixel in the second subset of pixels is not included in the first subset of pixels. In some aspects, increasing the brightness value of each pixel in the first subset of pixels or decreasing the brightness value of each pixel in the second subset of pixels may include: reducing the difference between the brightness value of each pixel in the second subset of pixels and the brightness value of each pixel in the first subset of pixels. Therefore, the CPU may decrease the difference between the brightness value of each pixel in the second subset of pixels and the brightness value of each pixel in the first subset of pixels. Each pixel in the second subset of pixels may include a decay ratio higher than a decay ratio threshold, and the decay ratio higher than the decay ratio threshold may correspond to a pixel that is less likely to decay than a pixel including a decay ratio lower than the decay ratio threshold. In some instances, the brightness value of each pixel in the first subset of pixels may be increased while decreasing the brightness value of each pixel in the second subset of pixels.

[0083] At 980, CPU 902 may send a second indication that the brightness value of each pixel in a first subset of pixels in the one or more regions is increased or the brightness value of each pixel in a second subset of pixels in the one or more regions is decreased (e.g., CPU 902 may send indication 982 to DPU 906).

[0084] Fig.10 1000 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a CPU (or other central processing unit), a DPU driver, a DPU (or other display processor), a GPU (or other graphics processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 9 The examples are performed using any device that displays the process.

[0085] At 1002, the CPU may obtain an indication of at least one frame associated with a display process, wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 910 of the embodiment, CPU 902 may obtain an indication of at least one frame associated with display processing, wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer. In addition, step 1002 may be performed by Figure 1 The display processor 127 in is executed.

[0086] At 1004, the CPU may detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 920 of the embodiment, the CPU 902 may detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio lower than an attenuation ratio threshold. In addition, step 1004 may be performed by Figure 1 Executed by the display processor 127 in the at least one frame. In some examples, the attenuation ratio threshold may correspond to an attenuation ratio list of all pixels in the pixel set included in the at least one frame, and the attenuation ratio list may be sorted in ascending order based on the attenuation ratio of each pixel in the pixel set or in descending order based on the attenuation ratio of each pixel in the pixel set.

[0087] At 1008, the CPU may identify one or more regions of the at least one frame that include all pixels in the first subset of pixels, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 940, CPU 902 may identify one or more regions of the at least one frame that include all pixels in the first pixel subset. In addition, step 1008 may be performed by Figure 1 , and the display processor 127 in the display processor 127 is executed. The one or more regions may correspond to one or more anti-aging compensation regions. Additionally, the one or more regions may include a first region and a second region, wherein the first region and the second region together include all pixels in the first pixel subset. In some instances, the one or more regions of the at least one frame including all pixels in the first pixel subset may be identified based on at least one other application or preconfiguration. In some aspects, the one or more regions of the at least one frame including all pixels in the first pixel subset may be identified by at least one of the following: a display processing unit (DPU) driver, a central processing unit (CPU), a DPU driver software, a DPU, a display driver, or a display driver software.

[0088] At 1014, the CPU may increase the brightness value of each pixel in a first subset of pixels in the one or more regions and / or decrease the brightness value of each pixel in a second subset of pixels in the one or more regions, wherein each pixel in the second subset of pixels is not included in the first subset of pixels, such as in combination with Figures 1 to 9 For example, Fig. 9As described in 970 of the embodiment, the CPU 902 may increase the brightness value of each pixel in the first pixel subset of the one or more regions and / or reduce the brightness value of each pixel in the second pixel subset of the one or more regions, wherein each pixel in the second pixel subset is not included in the first pixel subset. In addition, step 1014 may be performed by Figure 1 , and the display processor 127 in the display processor 127 is executed. In some aspects, raising the brightness value of each pixel in the first pixel subset or lowering the brightness value of each pixel in the second pixel subset may include: reducing the difference between the brightness value of each pixel in the second pixel subset and the brightness value of each pixel in the first pixel subset. Therefore, the CPU may reduce the difference between the brightness value of each pixel in the second pixel subset and the brightness value of each pixel in the first pixel subset. Each pixel in the second pixel subset may include an attenuation ratio higher than an attenuation ratio threshold, and the attenuation ratio higher than the attenuation ratio threshold may correspond to a pixel that is less likely to attenuate than a pixel including an attenuation ratio lower than the attenuation ratio threshold. In some instances, the brightness value of each pixel in the first pixel subset may be raised while the brightness value of each pixel in the second pixel subset is lowered.

[0089] Fig.11 1100 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a CPU (or other central processing unit), a DPU driver, a DPU (or other display processor), a GPU (or other graphics processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 9 The examples are performed using any device that displays the process.

[0090] At 1102, the CPU may obtain an indication of at least one frame associated with a display process, wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in step 910, CPU 902 may obtain an indication of at least one frame associated with display processing, wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer. In addition, step 1102 may be performed by Figure 1 The display processor 127 in is executed.

[0091] At 1104, the CPU may detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold, such as in combination with Figures 1 to 9 For example, Fig. 9As described in 920 of the embodiment, the CPU 902 may detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio lower than an attenuation ratio threshold. In addition, step 1104 may be performed by Figure 1 Executed by the display processor 127 in the at least one frame. In some examples, the attenuation ratio threshold may correspond to an attenuation ratio list of all pixels in the pixel set included in the at least one frame, and the attenuation ratio list may be sorted in ascending order based on the attenuation ratio of each pixel in the pixel set or in descending order based on the attenuation ratio of each pixel in the pixel set.

[0092] At 1106, the CPU may mark each pixel in a first subset of pixels in the set of pixels, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 930 of the embodiment, the CPU 902 may mark each pixel in the first pixel subset of the pixel set, wherein each pixel in the first pixel subset includes an attenuation ratio below the attenuation ratio threshold. In addition, step 1106 may be performed by Figure 1 The display processor 127 in the embodiment of the present invention is executed. In some aspects, the attenuation ratio threshold value can be obtained by runtime analysis, and / or the attenuation ratio threshold value can be preconfigured.

[0093] At 1108, the CPU may identify one or more regions of the at least one frame that include all pixels in the first subset of pixels, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 940, CPU 902 may identify one or more regions of the at least one frame that include all pixels in the first pixel subset. In addition, step 1108 may be performed by Figure 1 , and the display processor 127 in the display processor 127 is executed. The one or more regions may correspond to one or more anti-aging compensation regions. Additionally, the one or more regions may include a first region and a second region, wherein the first region and the second region together include all pixels in the first pixel subset. In some instances, the one or more regions of the at least one frame including all pixels in the first pixel subset may be identified based on at least one other application or preconfiguration. In some aspects, the one or more regions of the at least one frame including all pixels in the first pixel subset may be identified by at least one of the following: a display processing unit (DPU) driver, a central processing unit (CPU), a DPU driver software, a DPU, a display driver, or a display driver software.

[0094] At 1110, the CPU may calculate a set of coordinates for each of the one or more regions of the at least one frame including all pixels in the first subset of pixels, such as in combination with Figures 1 to 9For example, Fig. 9 As described in step 950, CPU 902 may calculate a set of coordinates of each of the one or more regions of the at least one frame including all pixels in the first pixel subset. In addition, step 1110 may be performed by Figure 1 The display processor 127 in is executed.

[0095] Additionally, at 1110, the CPU may analyze multiple windows in the at least one frame based on a set of coordinates of each of the one or more regions of the at least one frame including all pixels in the first subset of pixels, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 950 of the embodiment, the CPU 902 may analyze the plurality of windows in the at least one frame based on a coordinate set of each of the one or more regions of the at least one frame including all pixels in the first pixel subset. In addition, step 1110 may be performed by Figure 1 The display processor 127 in is executed.

[0096] At 1112, the CPU may determine that the one or more regions correspond to the entire region of the at least one frame, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 960, CPU 902 may determine that the one or more regions correspond to the entire region of the at least one frame. In addition, step 1112 may be performed by Figure 1 The display processor 127 in is executed.

[0097] Additionally, at 1112, the CPU may avoid increasing the brightness value of each pixel in the first subset of pixels and avoid decreasing the brightness value of each pixel in the second subset of pixels based on the one or more regions corresponding to the entire region of the at least one frame, such as in combination with Figures 1 to 9 For example, Fig. 9 As described in 960, CPU 902 may avoid increasing the brightness value of each pixel in the first pixel subset and avoid decreasing the brightness value of each pixel in the second pixel subset based on the one or more regions corresponding to the entire region of the at least one frame. In addition, step 1112 may be performed by Figure 1 The display processor 127 in is executed.

[0098] At 1114, the CPU may increase the brightness value of each pixel in a first subset of pixels in the one or more regions and / or decrease the brightness value of each pixel in a second subset of pixels in the one or more regions, wherein each pixel in the second subset of pixels is not included in the first subset of pixels, such as in combination with Figures 1 to 9 For example, Fig. 9As described in 970 of the embodiment, the CPU 902 may increase the brightness value of each pixel in the first pixel subset of the one or more regions and / or decrease the brightness value of each pixel in the second pixel subset of the one or more regions, wherein each pixel in the second pixel subset is not included in the first pixel subset. In addition, step 1114 may be performed by Figure 1 , and the display processor 127 in the display processor 127 is executed. In some aspects, raising the brightness value of each pixel in the first pixel subset or lowering the brightness value of each pixel in the second pixel subset may include: reducing the difference between the brightness value of each pixel in the second pixel subset and the brightness value of each pixel in the first pixel subset. Therefore, the CPU may reduce the difference between the brightness value of each pixel in the second pixel subset and the brightness value of each pixel in the first pixel subset. Each pixel in the second pixel subset may include an attenuation ratio higher than an attenuation ratio threshold, and the attenuation ratio higher than the attenuation ratio threshold may correspond to a pixel that is less likely to attenuate than a pixel including an attenuation ratio lower than the attenuation ratio threshold. In some instances, the brightness value of each pixel in the first pixel subset may be raised while the brightness value of each pixel in the second pixel subset is lowered.

[0099] At 1116, the CPU may send a second indication that the brightness value of each pixel in the first subset of pixels in the one or more regions is increased or the brightness value of each pixel in the second subset of pixels in the one or more regions is decreased, such as in conjunction with Figures 1 to 9 For example, Fig. 9 As described in 980 of the embodiment, CPU 902 may send a second indication that the brightness value of each pixel in the first pixel subset of the one or more regions is increased or the brightness value of each pixel in the second pixel subset of the one or more regions is decreased. In addition, step 1116 may be performed by Figure 1 The display processor 127 in is executed.

[0100] In various configurations, a method or apparatus for display processing is provided. The apparatus may be a CPU (or other central processing unit), a DPU (or other display processor), a GPU (or other graphics processor), a DPU driver, a DDIC, an apparatus for display processing, and / or some other processor that can perform display processing. In various aspects, the apparatus may be a display processor 127 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus, such as the display processor 127, may include a component for obtaining an indication of at least one frame associated with display processing, wherein the at least one frame includes a set of pixels, wherein the at least one frame is associated with at least one layer. The apparatus, such as the display processor 127, may also include a component for detecting a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold. The apparatus, such as the display processor 127, may also include a component for identifying one or more regions of the at least one frame including all pixels in the first subset of pixels. The device, such as the display processor 127, may also include a component for increasing the brightness value of each pixel in the first subset of pixels in the one or more regions and / or a component for decreasing the brightness value of each pixel in the second subset of pixels in the one or more regions, wherein each pixel in the second subset of pixels is not included in the first subset of pixels. The device, such as the display processor 127, may also include a component for calculating a set of coordinates of each of the one or more regions of the at least one frame that includes all pixels in the first subset of pixels. The device, such as the display processor 127, may also include a component for analyzing a plurality of windows in the at least one frame based on the set of coordinates of each of the one or more regions of the at least one frame that includes all pixels in the first subset of pixels. The device, such as the display processor 127, may also include a component for determining that the one or more regions correspond to the entire region of the at least one frame. The device, such as the display processor 127, may also include a component for avoiding increasing the brightness value of each pixel in the first subset of pixels and a component for avoiding decreasing the brightness value of each pixel in the second subset of pixels based on the one or more regions corresponding to the entire region of the at least one frame. The device, such as the display processor 127, may also include means for marking each pixel in a first subset of pixels in the set of pixels, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold. The device, such as the display processor 127, may also include means for sending a second indication that the brightness value of each pixel in the first subset of pixels in the one or more regions is increased or the brightness value of each pixel in the second subset of pixels in the one or more regions is decreased.

[0101] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the display processing technology described can be used by a CPU, a central processing unit, a DPU driver, a DPU, a display processor, a GPU, or some other processors that can perform display processing to implement the anti-aging area compensation technology described herein. Compared with other display processing technologies, this can also be implemented at a low cost. In addition, the display processing technology of this article can improve or accelerate data processing or execution. In addition, the display processing technology of this article can improve resource or data utilization and / or resource efficiency. Additionally, various aspects of the present disclosure can utilize anti-aging area compensation technology to improve memory bandwidth efficiency and / or increase processing speed at the CPU, DPU or GPU.

[0102] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart may be rearranged based on design preferences. In addition, some blocks may be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0103] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0104] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, which may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure that are known or will later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module," "mechanism," "element," "device," etc. cannot replace the word "component." Therefore, no claim element will be understood to be a part plus function unless the element is explicitly stated using the phrase "component for..."

[0105] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent as one or more instructions or codes on a computer-readable medium.

[0106] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for other features, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0107] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. In this way, computer-readable media may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0108] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0109] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0110] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0111] Aspect 1 is a device for display processing, the device comprising a memory and at least one processor, the at least one processor being coupled to the memory and, based at least in part on information stored in the memory, the at least one processor being configured to: obtain an indication of at least one frame associated with the display processing, wherein the at least one frame comprises a set of pixels, wherein the at least one frame is associated with at least one layer; detect a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels comprises an attenuation ratio lower than an attenuation ratio threshold; identify one or more regions of the at least one frame comprising all pixels in the first subset of pixels; and increase the brightness value of each pixel in the first subset of pixels in the one or more regions or decrease the brightness value of each pixel in a second subset of pixels in the one or more regions, wherein each pixel in the second subset of pixels is not included in the first subset of pixels.

[0112] Aspect 2 is an apparatus according to aspect 1, wherein the at least one processor is further configured to: calculate a set of coordinates for each of the one or more regions of the at least one frame that includes all pixels in the first subset of pixels.

[0113] Aspect 3 is an apparatus according to Aspect 2, wherein the at least one processor is further configured to: analyze multiple windows in the at least one frame based on the coordinate set of each of the one or more regions of the at least one frame including all pixels in the first pixel subset.

[0114] Aspect 4 is a device according to any one of Aspects 1 to 3, wherein the at least one processor is further configured to: determine that the one or more regions correspond to the entire area of ​​the at least one frame; and avoid increasing the brightness value of each pixel in the first pixel subset and avoid decreasing the brightness value of each pixel in the second pixel subset based on the one or more regions corresponding to the entire area of ​​the at least one frame.

[0115] Aspect 5 is a device according to any one of Aspects 1 to 4, wherein in order to increase the brightness value of each pixel in the first pixel subset or reduce the brightness value of each pixel in the second pixel subset, the at least one processor is configured to: reduce the difference between the brightness value of each pixel in the second pixel subset and the brightness value of each pixel in the first pixel subset.

[0116] Aspect 6 is a device according to any one of Aspects 1 to 5, wherein each pixel in the second subset of pixels includes the attenuation ratio above the attenuation ratio threshold, and wherein the attenuation ratio above the attenuation ratio threshold corresponds to a pixel that is less likely to attenuate than a pixel including the attenuation ratio below the attenuation ratio threshold.

[0117] Aspect 7 is an apparatus according to any one of Aspects 1 to 6, wherein the at least one processor is further configured to: mark each pixel in the first pixel subset in the pixel set, wherein each pixel in the first pixel subset includes the attenuation ratio lower than the attenuation ratio threshold.

[0118] Aspect 8 is a device according to any one of Aspects 1 to 7, wherein the attenuation ratio threshold corresponds to an attenuation ratio list of all pixels in the pixel set included in the at least one frame, and wherein the attenuation ratio list is sorted in ascending order based on the attenuation ratio of each pixel in the pixel set or in descending order based on the attenuation ratio of each pixel in the pixel set.

[0119] Aspect 9 is an apparatus according to any one of aspects 1 to 8, wherein the brightness value of each pixel in the first subset of pixels is increased while the brightness value of each pixel in the second subset of pixels is decreased.

[0120] Aspect 10 is an apparatus according to any one of Aspects 1 to 9, wherein the at least one processor is further configured to: send a second indication that the brightness value of each pixel in the first pixel subset in the one or more regions is increased or the brightness value of each pixel in the second pixel subset in the one or more regions is decreased.

[0121] Aspect 11 is a device according to any one of aspects 1 to 10, wherein the one or more regions correspond to one or more anti-aging compensation regions.

[0122] Aspect 12 is an apparatus according to any one of aspects 1 to 11, wherein the one or more regions include a first region and a second region, wherein the first region and the second region together include all pixels in the first subset of pixels.

[0123] Aspect 13 is an apparatus according to any one of aspects 1 to 12, wherein the attenuation ratio threshold is obtained by runtime analysis, or wherein the attenuation ratio threshold is preconfigured.

[0124] Aspect 14 is an apparatus according to any one of aspects 1 to 13, wherein the one or more regions of the at least one frame including all pixels in the first subset of pixels are identified based on at least one other application or preconfiguration.

[0125] Aspect 15 is an apparatus according to any one of Aspects 1 to 14, wherein the one or more regions of the at least one frame including all pixels in the first subset of pixels are identified by at least one of the following: a display processing unit (DPU) driver, a central processing unit (CPU), DPU driver software, DPU, display driver, or display driver software.

[0126] Aspect 16 is an apparatus according to any one of Aspects 1 to 15, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor, and wherein the at least one processor is configured to obtain the indication of the at least one frame via at least one of the antenna or the transceiver.

[0127] Aspect 17 is a method for implementing the display processing of any one of aspects 1 to 16.

[0128] Aspect 18 is an apparatus for display processing, the apparatus comprising means for implementing any one of aspects 1 to 16.

[0129] Aspect 19 is a computer-readable medium (eg, non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 16.

Claims

1. A device for display processing, the device comprising: Memory; and at least one processor coupled to the memory and based at least in part on the information stored in the memory, the at least one processor configured to: obtaining an indication of at least one frame associated with the display process, wherein the at least one frame comprises a set of pixels, wherein the at least one frame is associated with at least one layer; detecting a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold; identifying one or more regions of the at least one frame that include all pixels in the first subset of pixels; as well as The brightness value of each pixel in the first pixel subset in the one or more regions is increased or the brightness value of each pixel in the second pixel subset in the one or more regions is decreased, wherein each pixel in the second pixel subset is not included in the first pixel subset.

2. The apparatus of claim 1 , wherein the at least one processor is configured to: A set of coordinates is calculated for each of the one or more regions of the at least one frame that includes all pixels in the first subset of pixels.

3. The apparatus of claim 2, wherein the at least one processor is configured to: A plurality of windows in the at least one frame are analyzed based on the set of coordinates of each of the one or more regions of the at least one frame that include all pixels in the first subset of pixels.

4. The apparatus of claim 1 , wherein the at least one processor is configured to: determining that the one or more regions correspond to an entire region of the at least one frame; and Refraining from boosting the brightness value of each pixel in the first subset of pixels and refraining from lowering the brightness value of each pixel in the second subset of pixels based on the one or more regions corresponding to the entire region of the at least one frame.

5. The device according to claim 1, wherein in order to increase the brightness value of each pixel in the first pixel subset or reduce the brightness value of each pixel in the second pixel subset, the at least one processor is configured to: reduce the difference between the brightness value of each pixel in the second pixel subset and the brightness value of each pixel in the first pixel subset.

6. A device according to claim 1, wherein each pixel in the second subset of pixels includes the attenuation ratio above the attenuation ratio threshold, and wherein the attenuation ratio above the attenuation ratio threshold corresponds to a pixel that is less likely to attenuate than a pixel including the attenuation ratio below the attenuation ratio threshold.

7. The apparatus of claim 1 , wherein the at least one processor is configured to: Each pixel in the first subset of pixels in the set of pixels is marked, wherein each pixel in the first subset of pixels includes the attenuation ratio below the attenuation ratio threshold.

8. An apparatus according to claim 1, wherein the attenuation ratio threshold corresponds to an attenuation ratio list of all pixels in the pixel set included in the at least one frame, and wherein the attenuation ratio list is sorted in ascending order based on the attenuation ratio of each pixel in the pixel set or in descending order based on the attenuation ratio of each pixel in the pixel set.

9. The apparatus of claim 1, wherein the brightness value of each pixel in the first subset of pixels is increased while the brightness value of each pixel in the second subset of pixels is decreased.

10. The apparatus of claim 1, wherein the at least one processor is configured to: A second indication is sent that the luminance value of each pixel in the first subset of pixels in the one or more regions is increased or the luminance value of each pixel in the second subset of pixels in the one or more regions is decreased.

11. The device of claim 1, wherein the one or more regions correspond to one or more anti-aging compensation regions. 12 . The apparatus of claim 1 , wherein the one or more regions include a first region and a second region, wherein the first region and the second region together include all pixels in the first subset of pixels.

13. The apparatus according to claim 1, wherein the attenuation ratio threshold is obtained by runtime analysis, or wherein the attenuation ratio threshold is preconfigured.

14. The apparatus of claim 1, wherein the one or more regions of the at least one frame that include all pixels in the first subset of pixels are identified based on at least one other application or preconfiguration.

15. The apparatus of claim 1, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to obtain the indication of the at least one frame via the antenna or at least one of the transceivers, and wherein the one or more regions of the at least one frame including all pixels in the first subset of pixels are identified by at least one of: a display processing unit (DPU) driver, a central processing unit (CPU), DPU driver software, a DPU, a display driver, or display driver software.

16. A method of display processing, the method comprising: obtaining an indication of at least one frame associated with the display process, wherein the at least one frame comprises a set of pixels, wherein the at least one frame is associated with at least one layer; detecting a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold; identifying one or more regions of the at least one frame that include all pixels in the first subset of pixels; as well as The brightness value of each pixel in the first pixel subset in the one or more regions is increased or the brightness value of each pixel in the second pixel subset in the one or more regions is decreased, wherein each pixel in the second pixel subset is not included in the first pixel subset.

17. The method according to claim 16, further comprising: A set of coordinates is calculated for each of the one or more regions of the at least one frame that includes all pixels in the first subset of pixels.

18. The method according to claim 17, further comprising: A plurality of windows in the at least one frame are analyzed based on the set of coordinates of each of the one or more regions of the at least one frame that include all pixels in the first subset of pixels.

19. The method according to claim 16, further comprising: determining that the one or more regions correspond to an entire region of the at least one frame; as well as Refraining from boosting the brightness value of each pixel in the first subset of pixels and refraining from lowering the brightness value of each pixel in the second subset of pixels based on the one or more regions corresponding to the entire region of the at least one frame.

20. The method of claim 16, wherein increasing the brightness value of each pixel in the first pixel subset or decreasing the brightness value of each pixel in the second pixel subset comprises: The difference between the brightness value of each pixel in the second subset of pixels and the brightness value of each pixel in the first subset of pixels is reduced.

21. The method of claim 16, wherein each pixel in the second subset of pixels comprises the attenuation ratio above the attenuation ratio threshold, and wherein the attenuation ratio above the attenuation ratio threshold corresponds to a pixel that is less likely to attenuate than a pixel comprising the attenuation ratio below the attenuation ratio threshold.

22. The method according to claim 16, further comprising: Each pixel in the first subset of pixels in the set of pixels is marked, wherein each pixel in the first subset of pixels includes the attenuation ratio below the attenuation ratio threshold.

23. A method according to claim 16, wherein the attenuation ratio threshold corresponds to an attenuation ratio list of all pixels in the pixel set included in the at least one frame, and wherein the attenuation ratio list is sorted in ascending order based on the attenuation ratio of each pixel in the pixel set or in descending order based on the attenuation ratio of each pixel in the pixel set.

24. The method of claim 16, wherein the brightness value of each pixel in the first subset of pixels is boosted while the brightness value of each pixel in the second subset of pixels is lowered.

25. The method according to claim 16, further comprising: A second indication is sent that the luminance value of each pixel in the first subset of pixels in the one or more regions is increased or the luminance value of each pixel in the second subset of pixels in the one or more regions is decreased.

26. The method of claim 16, wherein the one or more regions correspond to one or more anti-aging compensation regions, wherein the one or more regions include a first region and a second region, wherein the first region and the second region together include all pixels in the first subset of pixels.

27. The method of claim 16, wherein the attenuation ratio threshold is obtained by runtime analysis, or wherein the attenuation ratio threshold is preconfigured, wherein the one or more regions of the at least one frame including all pixels in the first subset of pixels are identified based on at least one other application or preconfiguration.

28. The method of claim 16, wherein the one or more regions of the at least one frame including all pixels in the first subset of pixels are identified by at least one of: a display processing unit (DPU) driver, a central processing unit (CPU), DPU driver software, a DPU, a display driver, or display driver software.

29. An apparatus for display processing, the apparatus comprising: means for obtaining an indication of at least one frame associated with the display process, wherein the at least one frame comprises a set of pixels, wherein the at least one frame is associated with at least one layer; means for detecting a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold; means for identifying one or more regions of said at least one frame that include all pixels in said first subset of pixels; and A component for increasing the brightness value of each pixel in the first pixel subset in the one or more regions or decreasing the brightness value of each pixel in a second pixel subset in the one or more regions, wherein each pixel in the second pixel subset is not included in the first pixel subset.

30. A computer readable medium storing computer executable code for display processing, the code when executed by a processor causing the processor to: obtaining an indication of at least one frame associated with the display process, wherein the at least one frame comprises a set of pixels, wherein the at least one frame is associated with at least one layer; detecting a first subset of pixels in the set of pixels included in the at least one frame, wherein each pixel in the first subset of pixels includes an attenuation ratio below an attenuation ratio threshold; identifying one or more regions of the at least one frame that include all pixels in the first subset of pixels; as well as The brightness value of each pixel in the first pixel subset in the one or more regions is increased or the brightness value of each pixel in the second pixel subset in the one or more regions is decreased, wherein each pixel in the second pixel subset is not included in the first pixel subset.

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