Dynamic latch over three-dimensional non-volatile memory array

Abstract

Control logic in a memory device causes a pass voltage to be applied to a plurality of word lines of a block of a memory array of the memory device, the block including a plurality of sub-blocks, and the pass voltage boosting a channel potential of each of the plurality of sub-blocks to a boosted voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a bit sequence of respective memory cells to be programmed to the plurality of sub-blocks. In addition, the control logic causes a single program pulse to be applied to a selected word line of the plurality of word lines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to dynamic latches over a three-dimensional nonvolatile memory array in a memory device of a memory subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1A An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0005] Figure 1B is a block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0006] Figure 2 According to some embodiments of the present disclosure, it can be used as a reference Figure 1B A schematic diagram of a portion of a memory cell array of a memory of the type described.

[0007] Figure 3 is a block diagram illustrating a portion of a memory device having a dynamic latch over a three-dimensional nonvolatile memory array according to some embodiments of the present disclosure.

[0008] Figure 4 is a schematic diagram of a portion of a memory cell array with dynamic latches above the array according to some embodiments of the present disclosure.

[0009] Figure 5 is a flow chart of an example method of multi-cell programming in a memory device of a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 6 is a diagram illustrating a portion of a structure formation of a dynamic latch over a three-dimensional nonvolatile memory array according to some embodiments of the present disclosure.

[0011] Figure 7 is a block diagram illustrating a portion of a structure formation of a dynamic latch over a three-dimensional nonvolatile memory array according to some embodiments of the present disclosure.

[0012] Figures 8A to 8L is a diagram illustrating a process flow for forming a dynamic latch over a three-dimensional nonvolatile memory array according to some embodiments of the present disclosure.

[0013] Fig. 9 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to dynamic latches over a three-dimensional (3D) non-volatile memory array in a memory device of a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. Examples of memory devices and memory modules are described below in conjunction with FIG. 1 . In general, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0015] The memory subsystem may include a high-density non-volatile memory device, where it is desired to retain data when power is not supplied to the memory device. For example, NAND memory (such as 3D flash NAND memory) provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each die including one or more planes. For some types of non-volatile memory devices (such as NAND memory), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical state can be represented by a binary value, such as "0" and "1" or a combination of such values.

[0016] A memory device may consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells of a memory device that are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of a memory cell. A block hereinafter refers to a unit of a memory device for storing data and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks may be grouped together to form separate partitions (e.g., planes) of a memory device in order to allow concurrent operations to occur on each plane.

[0017] During a programming operation on a non-volatile memory device, certain phases may be encountered, including programming and program verification. For example, a high programming voltage may be applied to a selected word line of a block of the memory device during the programming phase, followed by a program verification phase in which a verification voltage is applied to the selected word line. Certain programming operations may be single programming operations, in which one sub-block is programmed in each operation. In this single programming operation, a data pattern is read from a temporary storage location (e.g., a page buffer) to determine whether a memory cell associated with the selected word line and located in one sub-block will be programmed, and a single programming pulse may be applied before the program verification phase occurs. This same process may then be repeated for each remaining sub-block to be programmed. For example, other programming operations may be dual programming operations, in which two sub-blocks are programmed in one operation. In this dual programming operation, two sub-blocks may be programmed before the program verification phase occurs (i.e., two separate programming pulses may be applied). Depending on the implementation, certain memory devices may utilize a dual verification operation or a seamless verification operation during a subsequent program verification phase. In either case, programming multiple sub-blocks involves causing multiple separate programming pulses to be applied to the selected word line. There are delays associated with each programming pulse, including multiple ramps up and down of the programming voltage. These delays increase the length of time for programming operations, which is particularly impactful in high priority and time-sensitive operations.

[0018] Therefore, some memory devices implement a dual programming operation so that the memory device can program memory cells in two or more separate sub-blocks using a single programming pulse applied to a selected word line. For example, as part of the programming operation, the control logic of the memory device causes a pass voltage to be applied to each word line in a block of the memory device, including a selected word line (i.e., a word line associated with a memory cell to be programmed) and an unselected word line. The pass voltage boosts the memory pillar channel voltage in each sub-block of the memory device to a higher boost voltage during this stage of the programming operation. Once each pillar channel voltage is boosted, the control logic can selectively discharge the pillars of one or more sub-blocks according to the data pattern of the bits programmed to the block during the programming operation. This process can be repeated for two or more sub-blocks. Once completed, the control logic can cause a single programming pulse to be applied to the selected word line. Those sub-blocks that are discharged to the ground voltage will be programmed, while those sub-blocks that remain at the boost voltage will be disabled, thereby allowing multiple sub-blocks to be programmed concurrently via a single programming pulse. Then, a dual verification operation or a seamless verification operation can be performed during a subsequent programming verification phase.

[0019] As the number of bits to be programmed per memory cell increases (such as, for example, for three-level cell (TLC) memory, where three bits are programmed in each memory cell), the number of latches used to store data associated with the programming operation increases dramatically. For example, to program a memory device configured as TLC memory, each sub-block may require at least five latches (e.g., three latches for holding three bits of data, one program inhibit latch, and one slow programming latch). If multiple sub-blocks are to be programmed using a single programming pulse, the number of latches required also increases by a corresponding multiple. Many memory devices include programming latches disposed in a logic layer below the memory array. However, due to the host system's preference for physically small memory devices (i.e., the size of the logic layer is limited to the same footprint as the associated memory array), the amount of physical space in the logic layer below the array is limited. Therefore, there may not be enough area below the memory array to place a larger number of latches for programming multiple sub-blocks with a single programming pulse.

[0020] Aspects of the present disclosure address the above and other deficiencies by providing dynamic latches above a 3D non-volatile memory array in a memory device of a memory subsystem. In one embodiment, a fixed number of latches may be implemented in a logic layer below the memory array of the memory device (e.g., within a page buffer circuit). For example, those latches may include sense amplifier latches, and a set (e.g., a pair) of even cache register latches and a set (e.g., a pair) of odd cache register latches, which enables each page buffer circuit to be used with multiple sub-blocks of the array. The remaining latches used to program multiple sub-blocks with a single programming pulse (e.g., those latches used to store data patterns to be programmed to multiple sub-blocks) may instead be located in a separate logic layer above the memory array. The latches above the array may be coupled to the latches below the array so that data may be routed therebetween, as described herein. In general, the open area above the memory array is not spatially constrained and multiple layers (e.g., CMOS layers) may be formed to contain associated latches. In one embodiment, each plane of the memory device may further include a hierarchical bit line structure having a master bit line and multiple local bit lines. The number of local bit lines is directly related to the number of sub-blocks that can be programmed with a single programming pulse.

[0021] Advantages of this approach include, but are not limited to, improved performance in the memory device. The arrangement of latches above the array provides the number of latches for concurrently (e.g., simultaneously) programming multiple sub-blocks in the memory device using a single programming pulse without increasing the occupied area of ​​the memory device. This results in fewer programming operations (e.g., half the number of programming operations) being able to be performed for the same amount of data programmed to the memory device without substantially increasing the size and / or area occupied by the memory device. Thus, the increased parallelism provided by the latch structures described herein reduces the delay associated with the entire programming operation, which can improve programming performance.

[0022] Figure 1A An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia card (eMMC) drives, universal flash storage devices (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device including a memory and a processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1A An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1A Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in combination with a stackable cross-gate data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without previously erasing the non-volatile memory cells. For example, NAND-type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example a single level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1A The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, the memory device 130 includes a local controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local controller 135) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, the memory device 130 may represent a single die with some control logic (e.g., the local controller 135) specifically implemented thereon. In some embodiments, one or more components in the memory subsystem 110 may be omitted.

[0038] In one embodiment, the memory subsystem 110 includes a memory interface component 113. The memory interface component 113 is responsible for handling the interaction of the memory subsystem controller 115 with the memory devices (e.g., memory device 130) of the memory subsystem 110. For example, the memory interface component 113 may send a memory access command corresponding to a request received from the host system 120 to the memory device 130, such as a program command, a read command, or other command. In addition, the memory interface component 113 may receive data from the memory device 130, such as data retrieved in response to a read command or confirmation of successful execution of a program command. In some embodiments, the memory subsystem controller 115 includes at least a portion of the memory interface 113. For example, the memory subsystem controller 115 may include a processor 117 (e.g., a processing device) that is configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the memory interface component 113 is part of the host system 110, an application, or an operating system.

[0039] In one embodiment, the memory device 130 includes a local controller 135 and a memory array 104. As described herein, the local controller 135 may perform a programming operation on the memory cells of the memory array 104. For example, the programming operation may include a programming phase and a programming verification phase. During the programming phase, a programming voltage is applied to a selected word line of the memory array 104 so as to program a certain charge level representing a desired value to the selected memory cell on the word line. In one embodiment, by adjusting the channel potential associated with multiple sub-blocks according to the data pattern to be programmed to the memory cells contained therein before applying the programming voltage to the selected word line, multiple memory cells in separate sub-blocks may be accurately programmed using a single programming pulse. For example, at the beginning of the programming operation, the local controller 135 may cause a pass voltage to be applied to multiple word lines of a block of the memory array 104 in the memory device 130. The block may include multiple sub-blocks, and the pass voltage may boost the channel potential of each of the multiple sub-blocks to a boost voltage (Vboost). The local controller 135 may further selectively discharge the boost voltage from one or more of the sub-blocks according to a data pattern representing a bit sequence to be programmed to the corresponding memory cells of the plurality of sub-blocks. This may cause the channel potential of the sub-block containing the memory cells to be programmed to discharge to the ground voltage. In addition, the local controller 135 may cause a single programming pulse to be applied to a selected word line of a plurality of word lines of a block to program the corresponding memory cells of the plurality of sub-blocks according to the data pattern. In one embodiment, the memory cells in those sub-blocks whose channel potential is discharged to ground will be programmed, while the memory cells in those sub-blocks whose channel potential is not discharged and remains at the boost voltage will be inhibited and not programmed. Next, a programming verification phase may be initiated to verify that the memory cells are correctly programmed according to the data pattern.

[0040] In one embodiment, memory device 130 further includes a first logic layer 102 disposed below memory array 104 (e.g., disposed on a substrate and / or between the substrate and memory array 104) and a second logic layer 106 disposed above memory array 104 (e.g., disposed on a side of memory array 104 opposite the substrate). In one embodiment, logic layer 102 (i.e., the logic layer below memory array 104) includes, for example, page buffer circuitry having a fixed number of latches or other data storage elements. In one embodiment, those latches in logic layer 102 include sense amplifier latches, a set (e.g., a pair) of even cache register latches, and a set (e.g., a pair) of even cache register latches. In other embodiments, for example, logic layer 102 may include a logic region on a separate CMOS chip bonded to memory array 104, rather than being disposed below memory array 104. Logic layer 106 (i.e., the logic layer above memory array 104) may include remaining latches for programming multiple sub-blocks with a single programming pulse, including those latches for storing data patterns to be programmed to the multiple sub-blocks. In one embodiment, memory array 104 includes multiple planes, and each plane may further include a hierarchical bit line structure having a master bit line and multiple local bit lines, as described in more detail below.

[0041] Figure 1B is in accordance with an embodiment and presents a memory subsystem (eg, Figure 1A 1 is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 of a memory subsystem 110 of the present invention. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0042] Memory device 130 includes a memory cell array 104 arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line may be associated with more than one logical row of memory cells and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1B ) can be programmed to one of at least two target data states.

[0043] The row decoding circuitry 108 and the column decoding circuitry 109 are configured to decode address signals. The address signals are received and decoded to access the memory cell array 104. The memory device 130 also includes an input / output (I / O) control circuitry 160 for managing the input of commands, addresses, and data to the memory device 130 and the output of data and status information from the memory device 130. The address register 114 communicates with the I / O control circuitry 160 and the row decoding circuitry 108 and the column decoding circuitry 109 to latch the address signals before decoding. The command register 124 communicates with the I / O control circuitry 160 and the local controller 135 to latch incoming commands.

[0044] A controller (e.g., a local controller 135 inside the memory device 130) controls access to the memory cell array 104 in response to commands and generates status information for the external memory subsystem controller 115, i.e., the local controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 109 to control the row decoding circuitry 108 and the column decoding circuitry 109 in response to addresses. In one embodiment, the local controller 135 can perform a multi-cell programming operation to program memory cells in two or more separate sub-blocks of a block of the memory array 104 concurrently (i.e., at least partially overlapping in time) using a single programming pulse.

[0045] The local controller 135 also communicates with a cache register 172. The cache register 172 latches incoming or outgoing data as directed by the local controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from the cache register 172 to the data register 170 for transmission to the memory cell array 104; then, the new data may be latched in the cache register 172 from the I / O control circuit system 160. During a read operation, data may be transferred from the cache register 172 to the I / O control circuit system 160 for output to the memory subsystem controller 115; then, the new data may be transferred from the data register 170 to the cache register 172. The cache register 172 and / or the data register 170 may form a page buffer of the memory device 130 (e.g., may form a part thereof). The page buffer may further include a sensing device ( Figure 1BThe state register 122 may be configured to sense the data state of a memory cell of the memory cell array 104, such as by sensing the state of a data line of the memory cell. The state register 122 may communicate with the I / O control circuitry 160 and the local memory controller 135 to latch state information for output to the memory subsystem controller 115.

[0046] The memory device 130 receives control signals from the local controller 135 at the memory subsystem controller 115 through the control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of the memory device 130, additional or alternative control signals (not shown) may be further received through the control link 132. In one embodiment, the memory device 130 receives a command signal (which represents a command), an address signal (which represents an address), and a data signal (which represents data) from the memory subsystem controller 115 through a multiplexed input / output (I / O) bus 134 and outputs the data to the memory subsystem controller 115 through the I / O bus 134.

[0047] For example, a command may be received at I / O control circuitry 160 through input / output (I / O) pins [7:0] of I / O bus 134 and then the command may be written into command register 124. An address may be received at I / O control circuitry 160 through input / output (I / O) pins [7:0] of I / O bus 134 and then the address may be written into address register 114. Data may be received at I / O control circuitry 160 through input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device and then the data may be written into cache register 172. The data may then be written into data register 170 to program memory cell array 104.

[0048] In an embodiment, cache register 172 may be omitted and data may be written directly into data register 170. Data may also be output through input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference may be made to I / O pins, they may include any conductive node, such as a conventional conductive pad or conductive bump, that provides an electrical connection to memory device 130 by an external device (e.g., memory subsystem controller 115).

[0049] Those skilled in the art will appreciate that additional circuitry and signals may be provided and simplified. Figure 1BIt should be appreciated that reference Figure 1B The functionality of the various block components described may not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1B Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1B Additionally, although specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0050] Figure 2 is according to the embodiment as can be used for reference Figure 1B 1 is a schematic diagram of a portion of a memory cell array 104 (eg, a NAND memory array) in a memory of the type described. The memory array 104 includes access lines (eg, word lines 2020 to 2021). N ) and data lines (e.g., bit lines 2040 to 204 M ). The word lines 202 may be connected to global access lines (eg, global word lines) in a many-to-one relationship ( Figure 2 For some embodiments, memory array 104 may be formed over a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity, such as to form a p-well, or to have a conductivity type, such as n-type conductivity, such as to form an n-well.

[0051] The memory array 104 may be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column may include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N Memory cell 208 may represent a non-volatile memory cell for data storage. The memory cells 208 of each NAND string 206 may be connected in series at a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 210 M ) (eg, it may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M 2100 to 2101) (for example, it can be a drain select transistor, often referred to as a select gate drain). MThe gates 2120 to 2124 may be commonly connected to a select line 214 (eg, a source select line (SGS)), and the select gates 2120 to 2124 may be commonly connected to a select line 214 (eg, a source select line (SGS)). M The select gates 210 and 212 may be commonly connected to a select line 215, such as a drain select line (SGD). Although depicted as conventional field effect transistors, the select gates 210 and 212 may utilize a similar (e.g., identical) structure as the memory cell 208. The select gates 210 and 212 may represent a number of select gates connected in series, where each select gate in the series is configured to receive the same or an independent control signal.

[0052] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of the select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0053] The drain of each select gate 212 can be connected to the bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204. The control gate of each select gate 212 can be connected to a select line 215.

[0054] Figure 2 The memory array 104 in may be a quasi-two-dimensional memory array and may have a substantially planar structure, for example, wherein the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2 The memory array 104 in can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and a plane containing the bit lines 204 can extend substantially parallel to the plane containing the common source 216 .

[0055] The typical construction of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine the data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, such as Figure 2. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases forms) the word line 202.

[0056] A column of memory cells 208 may be a NAND string 206 or a number of NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 may be memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may (but need not) include all of the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may generally be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 that is commonly connected to a word line 202 may be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly connected to a given word line 202. N The memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be one physical page of memory cells 208 (eg, even memory cells), while the memory cells 208 commonly connected to the word line 202 may be one physical page of memory cells 208 (eg, even memory cells). N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be another physical page of the memory cells 208 (eg, odd memory cells).

[0057] although Figure 2 The bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit lines 204 of the memory cell array 104 can be from the bit line 2040 to the bit line 204 M 202. Other groupings of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered a physical page of memory cells. A portion of a physical page of memory cells (which may still be an entire row in some embodiments) read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells configured to be erased together, such as those connected to word lines 2020 through 2021. NAll memory cells of a common word line 202 (e.g., all NAND strings 206 that share a common word line 202). Unless explicitly distinguished, references herein to a page of memory cells refer to memory cells of a logical page of memory cells. Although discussed in conjunction with NAND flash memory Figure 2 Examples of, but the embodiments and concepts described herein are not limited to a particular array architecture or structure, and may include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0058] Figure 3 is a block diagram illustrating a portion of a memory device having dynamic latches above a three-dimensional non-volatile memory array according to some embodiments of the present disclosure. As illustrated, the memory device includes a substrate 310 (e.g., a printed circuit board) on which a first logic layer 102, a memory array 104, and a second logic layer 106 may be formed. In one embodiment, the first logic layer 102 is disposed below the memory array 104 (e.g., disposed on the substrate 310 and / or between the substrate 310 and the memory array 104). In one embodiment, the logic layer 102 includes, for example, a page buffer circuit 320 having a fixed number of latches or other data storage elements (e.g., the data registers 170 and cache registers 172 described above). In one embodiment, the second logic layer 106 is disposed above the memory array 104 (e.g., disposed on the side of the memory array 104 opposite the substrate 310). The logic layer 106 may include the remaining latches for programming multiple sub-blocks (e.g., sub-block 0 through sub-block N) of the memory array 104 with a single programming pulse, including those latches for storing data patterns to be programmed to the multiple sub-blocks. In one embodiment, the logic layer 106 may include a set of even latches and a set of odd latches corresponding to each sub-block in the memory array 104. For example, even latch 330-0 and odd latch 330-1 may be associated with sub-block 0, even latch 330-2 and odd latch 330-3 may be associated with sub-block 1, and even latch 330-4 and odd latch 330-5 may be associated with sub-block N. As described in more detail below, each set of even and / or odd latches may include multiple latches, such as those latches used to store data patterns to be programmed to multiple sub-blocks of the memory array 104 (e.g., one latch per page of data), inhibit latches, sense latches, and one or more other latches. For example, there may be additional latches that store temporary information that can be used to speed up programming operations and reduce programming time (e.g., state information of memory cells on adjacent word lines, SSPC (Selective Slow Program Convergence) data for different sub-blocks).

[0059] In one embodiment, the memory device includes a hierarchical bitline structure having a master bitline 342 and a plurality of local bitlines 352, 354. For example, latches in the logic layer 106 may be coupled between the master bitline 342 (or other voltage signal lines, such as VPRE 344 or PLATE 346) and the respective local bitline 352 or 354. In one embodiment, an even group of latches (e.g., even latches 330-0, 330-2, and 330-4) are coupled to even local bitlines (i.e., LBLeven 352), and an odd group of latches (e.g., odd latches 330-1, 330-3, and 330-5) are coupled to odd local bitlines (i.e., LBLodd 354). Depending on whether the latches in logic layer 106 are ordinary latches or special latches, the latches may be coupled to main bit line 342 and VPLATE 346 or to VPRE 344 and VPLATE 346 (e.g., a ground voltage signal). For example, special latches may be directly coupled to main bit line 342, while ordinary latches may be coupled to VPRE 344 (e.g., a voltage supply signal). In one embodiment, most latches in logic layer 106 are ordinary latches, while only a few special latches are used to transfer data between logic layer 106 and logic layer 102. Even and odd local bit line structures are driven by process integration. The relaxation of spacing and positioning all even latches on one side of logic layer 106 and all odd latches on the other side improves the ability to form connections up to the local bit lines.

[0060] In one embodiment, latches in logic layer 106 are organized to be associated with respective block groups in memory array 104. Block groups may span multiple blocks in memory array 104, such as, for example, 96 blocks, where each block includes a number of sub-blocks, such as sub-block 0 through sub-block N. In one embodiment, logic layer 106 includes a set of even latches and a set of odd latches for each of sub-blocks 0 through sub-block N. As described herein, these sets of latches may hold data that is programmed to multiple sub-blocks in parallel, such as by using a single programming pulse. In one embodiment, while master bit lines 342 may span the entire plane of a memory device, local bit lines, such as LBLeven 352 and LBLodd 354, may be specific to a particular block group. Thus, each block group may include its own local bit lines, where local bit lines are not shared across different block groups.

[0061] In one embodiment, the spacing between local bit lines (e.g., LBLeven 352 and LBLodd 354) is so tight that it is difficult (if not impossible) to place a connection on only one of the bit lines (e.g., a connection to one of the latches in logic layer 106). Therefore, in one embodiment, the local bit line plane ( Figure 3106. Local bit lines may be connected to corresponding local bit lines in a single location, such as the point where the local bit lines terminate between groups of blocks, for example.

[0062] Figure 4 4 is a schematic diagram of a portion of a memory cell array having dynamic latches above the array according to some embodiments of the present disclosure. For example, the portion of a memory cell array (e.g., memory array 104) may be block 400. In one embodiment, block 400 includes strings of memory cells that may be grouped into sub-blocks (e.g., sub-blocks 4050 to 4053). Other numbers of sub-blocks may be included in other embodiments.

[0063] Specifically, in at least some embodiments, block 400 includes a local bit line 404 (e.g., one of local bit lines LBLeven 352 or LBLodd 354), wherein each sub-block is coupled to local bit line 404. A first sub-block 4050 may include a first drain select (SGD) transistor 4120, a first source select (SGS) transistor, and a first memory cell string ( Figure 4 The second sub-block 4051 may include a second SGD transistor 4121, a second SGS transistor, and a second memory cell string ( Figure 4 The third sub-block 4052 may include a third SGD transistor 4122, a third SGS transistor, and a third memory cell string coupled therebetween ( Figure 4 The fourth sub-block 4053 may include a fourth SGD transistor 4123, a fourth SGS transistor, and a fourth memory cell string ( Figure 4 4121). Each SGS transistor may be connected to a common source (SRC), such as a source voltage line, to provide a voltage to the sources of multiple memory cells in each string. In some embodiments, the source voltage line includes a source plate that supplies the source voltage. In at least some embodiments, multiple word lines (WL) are coupled to the gates of the memory cells of each string of memory cells such that one memory cell from the string in each sub-block is connected to each word line and each memory cell in the string of any one sub-block is connected to a different word line. In these embodiments, a first drain select gate line (SGD0) may be connected to the gate of a first SGD transistor 4120, a second drain select gate line (SGD1) may be connected to the gate of a second SGD transistor 4121, a third drain select gate line (SGD2) may be connected to the gate of a third SGD transistor 4122, and a fourth drain select gate line (SGD3) may be connected to the gate of a fourth SGD transistor 4123.

[0064] In one embodiment, logic layer 106 is disposed above memory array 104. Logic layer 106 may include one or more latches located above each block. Figure 4 As shown in FIG. 4 , latch 410 is disposed above block 400. For purposes of illustration, Figure 4 A special latch 430 in the logic layer 106 above the block 400 is also illustrated, however, in other embodiments, the special latch 430 may be disposed above another block of the memory array 104. The latch 410 disposed above the block 400 may be designated as an even latch or an odd latch corresponding to one of the sub-blocks 4050-4053 in the block 400 (i.e., depending on whether the local bit line 404 is an even local bit line or an odd local bit line). It should be noted that there may be another latch associated with one of the sub-blocks of the block 400 (i.e., depending on what the latch 410 is, as opposed to even or odd), which may be disposed above another block in the memory array 104. As illustrated, the latch 410 includes a number of transistors coupled between the precharge voltage (VPRE) line 344, the ground voltage (VPLATE) line 346, and the local bit line 404. Latch 410 may further include storage elements to store charge levels representing data bits to be programmed into memory cells of one of sub-blocks 4050-4053 in block 400. However, special latch 430 includes a number of transistors coupled between master bit line 342, ground voltage (VPLATE) line 346, and local bit line 404. Special latch 430 may further include storage elements to store charge levels representing data bits to be copied into latch 410 or another latch in logic layer 106. In one embodiment, there are only a fixed number of special latches, such as special latch 430, in each block group. Since only special latches 430 are connected to master bit lines 342, while all normal latches (e.g., latches 410) are isolated from master bit lines 342, master bit lines 342 can remain free for data transfer between logic layer 106 (i.e., the logic layer above memory array 104) and logic layer 102 (i.e., the logic layer below memory array 104). For example, all data moved from special latches 430 to latches 410 or from latches 410 to block 400 can be moved via local bit lines 404.

[0065] In one embodiment, latch 410 includes block select transistors 4240 and 4241, which may be controlled by a select signal SEL (e.g., received from local controller 135 or other control logic). Block select transistors 4240 and 4241 may be activated when writing to or reading from latch 410 during a programming operation of a block (e.g., block 400) to which latch 410 corresponds. Latch 410 further includes a precharge transistor 4200 controlled by a precharge signal PRE and a write transistor 4220 controlled by a write signal WR. Local controller 135 or other control logic may activate precharge transistor 4200 to store a value corresponding to precharge signal 344 (e.g., a power supply signal) in latch 410 and / or activate write transistor 4220 to store a value from local bit line 404 (e.g., a value received from special latch 430) in latch 410. In one embodiment, latch 410 includes capacitor 4250 or other storage element to store a charge level representing a data bit to be programmed into a memory cell of one of sub-blocks 4050-4053 in block 400. If the charge level on capacitor 4250 is high enough, transistor 4270 is activated, allowing a signal to flow between read transistors 4260 and 4280. Read transistor 4260 is controlled by read signal RD1 and read transistor 4280 is controlled by read signal RD2. Local controller 135 or other control logic may activate read transistor 4260 to discharge the stored charge to ground (i.e., PLATE signal 346) or activate read transistor 4280 to move the charge level onto local bit line 404 to program a memory cell of one of sub-blocks 4050-4053 in block 400.

[0066] In one embodiment, special latch 430 includes select transistors 4242 and 4243, which may be controlled by a select signal SEL (e.g., received from local controller 135 or other control logic). Select transistors 4242 and 4243 may be activated when writing to or reading from special latch 430 during a programming operation. Special latch 430 further includes transistor 4201 controlled by signal MBL1 and transistor 4221 controlled by signal MBL0. Local controller 135 or other control logic may activate transistor 4201 to store a value from master bit line 342 (e.g., received from logic layer 102) in special latch 430 and / or activate transistor 4221 to store a value from local bit line 404 in special latch 430. In one embodiment, special latch 430 includes capacitor 4251 or other storage element to store a charge level representing a data bit to be copied into latch 410 or another latch in logic layer 106. If the charge level on capacitor 4251 is high enough, transistor 4271 is activated, allowing a signal to flow between read transistors 4261 and 4281. Read transistor 4261 is controlled by read signal RD1 and read transistor 4281 is controlled by read signal RD2. Local controller 135 or other control logic may activate read transistor 4261 to discharge the stored charge to ground (i.e., PLATE signal 346) or activate read transistor 4281 to move the charge level onto local bit line 404 for copying into latch 410 or another latch in logic layer 106.

[0067] In one embodiment, local controller 135 may use a signal applied to a selected word line (eg, WL N ) to concurrently program memory cells in two or more separate sub-blocks of block 400. In one embodiment, as part of the programming operation, control logic causes a pass voltage (Vpass) to be concurrently applied to each word line of block 400. The pass voltage boosts the memory pillar channel voltage in each of sub-blocks 4050-4053 (e.g., due to gate-to-channel capacitive coupling) to a higher boost voltage (Vboost) during this stage of the programming operation.

[0068] Once each pillar channel voltage is boosted, the local controller 135 can selectively discharge the pillars of one or more sub-blocks according to the data pattern of the bits programmed to the block 400 during the programming operation. In one embodiment, the data pattern is read from latches disposed in the logic layer 106 above the memory array and represented by the voltage on the local bit line 404. For example, if the selected word line WL NIf the memory cell associated with and located in sub-block 4051 is to be programmed, the local controller can activate the second SGD transistor 4121 by asserting a signal on the second drain select gate line (SGD1) to allow the boosted voltage to discharge onto the local bit line 404, thereby returning the channel voltage in sub-block 4051 to ground voltage (e.g., 0V). Conversely, if the selected word line WL N If the memory cell associated with and located in sub-block 4050 is not to be programmed, then the local memory controller 135 will not activate the first SGD transistor 4120, thereby causing the pillar channel voltage in sub-block 4050 to remain at the boosted voltage. This sequence may be repeated for two or more sub-blocks, additionally including, for example, sub-blocks 4052 to 4053. Once completed, the local controller 135 may cause a single programming pulse (Vpgm) to be applied to the selected word line WL N Since the channel voltage in sub-block 4051 is at the ground voltage, the gate-to-channel voltage difference (e.g., Vpgm-GND) is large enough that the selected memory cells in sub-block 4051 will be programmed. Since the channel voltage in sub-block 4050 is at the boosted voltage, the gate-to-channel voltage difference (e.g., Vpgm-Vboost) is too small so that the selected memory cells in sub-block 4050 will not be programmed. The local controller 135 may then perform a double verification operation or a seamless verification operation during a subsequent program verification phase to confirm that the memory cells are correctly programmed.

[0069] In general, the latch in logic layer 106 can be characterized as a gain cell having two parallel transistor strings, each formed around a separate pillar. In one embodiment, each string includes three or more devices connected in series. These devices can be formed in several horizontal layers extending above memory array 104. In one embodiment, there is a capacitive gate layer connected between the channel of one pillar and the gate terminal of the device in the other pillar. This capacitive gate layer can include the charge storage device of the latch, such as capacitor 4250 or 4251. Although Figure 4 One example implementation of latches in logic layer 106 is illustrated in FIG. 1 , but in other embodiments, other implementations are possible.

[0070] Figure 5 500 is a flow chart of an example method of multi-cell programming in a memory device of a memory subsystem according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1A and Figure 1BThe local controller 135 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0071] At operation 505, a programming operation is initiated. In one embodiment, the programming operation includes a programming phase and a programming verification phase. In certain embodiments, each of these phases may be repeated several times in a cycle during a single programming operation. During the programming phase, a programming voltage is applied to a selected word line of the memory device 130 so as to program a certain charge level representing a desired value into the selected memory cells on the word line. The desired value may be represented by a multi-bit data pattern (e.g., stored in a page buffer of the memory device 130), where each bit is to be stored in a separate memory cell associated with the selected word line.

[0072] At operation 510, the data pattern is transferred to the logic layer above the memory array. For example, the control logic (e.g., the local controller 135) may store the multi-bit data pattern in a plurality of latches disposed in a logic layer (e.g., logic layer 106) above the memory array 104. In one embodiment, the multi-bit data pattern represents a sequence of bits to be programmed to corresponding memory cells of a plurality of sub-blocks 4050-4053 of a block 400 of the memory array 104. In one embodiment, the memory device includes a substrate 310 and the memory array 104 is disposed between the substrate 310 and the logic layer 106 disposed above the memory array. In one embodiment, storing the multi-bit data pattern in the latches in the logic layer 106 includes transferring the data pattern from a page buffer 320 disposed in a logic layer 102 below the memory array 104 to a logic layer 106 disposed above the memory array via a master bit line (e.g., master bit line 342) of the memory device. In one embodiment, the data pattern is received at the logic layer 106 by special latches (e.g., latches 430) coupled between the master bit lines 342 and the local bit lines 404 associated with the group of blocks that includes the blocks to which the data pattern is to be programmed. In one embodiment, the logic layer 102 disposed below the memory array 104 is disposed between the memory array 104 and the substrate 310.

[0073] At operation 515, the data pattern is transferred to data latches within the logic layer above the memory array. In one embodiment, the control logic transfers each bit in the bit sequence via local bit line 404 to a corresponding one of a plurality of data latches (e.g., latch 410) disposed in the logic layer 106 above the memory array, wherein the plurality of data latches are isolated from the master bit line 342.

[0074] At operation 520, the channel potential of a sub-block of a block of the memory array 104 of the memory device 130 is optionally increased. For example, before causing a pass voltage to be applied to a word line of the block, the control logic may cause the channel potential of at least one of the sub-blocks 4050-4053 to increase to a boost voltage (Vboost) according to a data pattern stored in a latch of the logic layer 106. In one embodiment, a signal on one drain select gate line (e.g., first drain select gate line SGD0) is driven high to activate a corresponding SGD transistor, such as SGD transistor 4120, thereby allowing a voltage representing the data pattern on the bit line (BL) to charge a corresponding pillar channel of the sub-block 4100.

[0075] At operation 525, a pass voltage is applied to word lines of a block of the memory array 104 of the memory device 130. For example, the control logic may cause a pass voltage (Vpass) to be concurrently applied to multiple word lines of a block. In one embodiment, a block (e.g., block 400) includes sub-blocks 4050-4053, each sub-block including a string of memory cells surrounding a pillar of channel material. The pass voltage boosts the memory pillar channel voltage in each of the sub-blocks 4050-4053 (e.g., due to gate-to-channel capacitive coupling) to a higher boost voltage (Vboost) during this stage of the programming operation.

[0076] At operation 530, one or more sub-blocks are selectively discharged. For example, the control logic may selectively discharge the boost voltage from one or more of the sub-blocks 4050 to 4053 according to a data pattern representing a bit sequence to be programmed to corresponding memory cells of the plurality of sub-blocks. For example, if the boost voltage is not present in the selected word line WL N If the memory cell associated with and located in sub-block 4051 is to be programmed, the local controller 135 can activate the second SGD transistor 4121 by asserting a signal on the second drain select gate line (SGD1) to allow the boosted voltage to discharge onto the local bit line 404, thereby returning the channel voltage in sub-block 4051 to ground voltage (e.g., 0V). Conversely, if the selected word line WL N4050 is not programmed, then the local memory controller 135 will not activate the first SGD transistor 4120, thereby causing the pillar channel voltage in the sub-block 4050 to remain at the boosted voltage. This sequence may be repeated for two or more sub-blocks, additionally including, for example, sub-blocks 4052-4053. In one embodiment, the memory device structure described herein allows for parallel operations on different blocks and / or different groups of blocks. For example, programming operations 520, 525, and 530 may be performed on sub-blocks of one block in the memory array 114, while data transfer operations 510 and 515 are concurrently performed (i.e., at least partially overlapped in time) for another block in the same or different group of blocks.

[0077] At operation 535, a programming pulse is applied to the selected word line. For example, the control logic may cause a single programming pulse to be applied to a selected word line WL 1 among the plurality of word lines of block 400. N To program the corresponding memory cells of the plurality of sub-blocks according to the data pattern. Since the channel voltage in sub-block 4051 is at the ground voltage, the gate-to-channel voltage difference (e.g., Vpgm-GND) is large enough so that the selected memory cell will be programmed. Since the channel voltage in sub-block 4050 is at the boost voltage, the gate-to-channel voltage difference (e.g., Vpgm-Vboost) is too small so that the selected memory cell will not be programmed.

[0078] At operation 540, a program verification phase is initiated. During the program verification phase, a read voltage is applied to the selected word line to read the charge level stored at the selected memory cell to confirm that the expected value is correctly programmed. Depending on the implementation, certain memory devices may utilize a double verification operation or a seamless verification operation during the program verification phase.

[0079] Figure 66 is a diagram illustrating a portion of a structure formation of a dynamic latch above a three-dimensional non-volatile memory array according to some embodiments of the present disclosure. In one embodiment, a memory array (e.g., memory array 104) is formed on a source (SRC) plate 605. For example, a number of array pillars 610 may be formed on the source plate 605, wherein each pillar is used to form a string of memory cells, wherein each string forms a sub-block in the memory array. As described herein, each array pillar may be coupled to a corresponding local bit line, such as LBLeven 352 or LBLodd 354. Due to spatial constraints and the associated spacing of the local bit lines, each local bit line may have a corresponding select gate plug coupled at one end, such as SGD plug 615. Above the local bit lines, a number of additional source plates, such as latch source (SRC) plates 620, may be formed. SGD plug 615 may have a relaxed spacing and sufficient space to connect to latch SRC plate 620 using sub-via 625.

[0080] In one embodiment, several logic layer latch pillars 640 may be formed on each respective latch SRC plate 620. Each logic layer latch pillar may be used to form a latch string that makes up a portion of the logic layer 106 above the memory array. Several horizontal layers may be formed across the logic layer latch pillars 630, with separate latches formed at the intersection of each horizontal layer and each vertical logic layer latch pillar. As described herein, some of the logic layer latch pillars 630 are directly coupled to the master bit line 342. Others of the logic layer latch pillars 630 are coupled to other signal lines, such as VPRE or PLATE ( Figure 6 605). Additionally, in one embodiment, a via 635 may be formed to directly couple the primary bit line 342 to the source plate 605. The via 635 may bypass the logic layer 106 and the memory array 104.

[0081] Figure 7 1 is a block diagram illustrating a portion of a structure formation of a dynamic latch over a three-dimensional nonvolatile memory array according to some embodiments of the present disclosure. Specifically, in at least some embodiments, the portion includes a local bit line 404 (e.g., one of the local bit lines LBLeven 352 or LBLodd 354), a common latch source (SRC) plate 620, and a plurality of logic layer latch pillars 6300-6303 formed on and extending vertically over the latch source plate 620. A plurality of devices may be formed where horizontal layers 702, 704, 706, 708, and 710 intersect the logic layer latch pillars 6300-6303. These devices may together form a latch that makes up at least a portion of a logic layer 106 disposed over the memory array 104. Figure 7 The illustrated portion of includes latch 410 and special latch 430, as described above with respect to Figure 4 For example, latch 410 may be formed by devices in pillars 6300 and 6301, while special latch 430 may be formed by devices in pillars 6302 and 6303.

[0082] In one embodiment, a portion of logic layer 106 includes a latch SRC plate 620 formed over local bit line 404. For example, local bit line 404 may represent LBLeven 352 or LBLodd 354. In one embodiment, latch SRC plate 620 is coupled to local bit line 404, for example, through SGD plug 615 and sub-via 625, as shown in FIG. Figure 6 In one embodiment, horizontal layers 702, 704, 706, 708, and 710 may be formed above and substantially parallel to latch SRC plate 620. Horizontal layers 702, 704, 706, 708, and 710 may be formed across (e.g., substantially perpendicular to) logic layer latch pillars 6300-6303. As described below with respect to Figures 8A to 8F Describing in more detail, horizontal layers 702, 704, 706, 708, and 710 may be formed of conductive materials (eg, polysilicon) separated by oxide layers. Main bit lines 342 may be formed above the horizontal layers.

[0083] In one embodiment, horizontal layer 702 includes select devices (SEL), such as select transistors 4240 and 4241 in latch 410, and select transistors 4242 and 4243 in special latch 430. Each of the select devices in horizontal layer 702 may be controlled by a select signal SEL (e.g., received from local controller 135 or other control logic). The select devices may be activated when writing to or reading from latch 410 or special latch 430 during a programming operation.

[0084] In one embodiment, horizontal layer 704 includes a write transistor (WR) and a read transistor (RD2) in latch 410 and a transistor (MBL0) and a read transistor (RD2) in special latch 430. Local controller 135 or other control logic can activate the write transistor to store a value from local bit line 404 or the read transistor in latch 410 to move a value from latch 410 to local bit line 404 to program memory cells in the corresponding sub-block. Local controller 135 or other control logic can activate the transistor to store a value from master bit line 342 or the read transistor in special latch 430 to move a value from special latch 430 to local bit line 404.

[0085] In one embodiment, horizontal layer 706 includes gate terminals of respective capacitive storage devices in latch 410 and special latch 430. Capacitive storage devices, such as capacitor 4250 and capacitor 4251, store respective charge levels representing a data bit to be programmed into the memory cell.

[0086] In one embodiment, horizontal layer 708 includes a precharge transistor (PRE) and a read transistor (RD1) in latch 410 and a transistor (MBL1) and a read transistor (RD1) in special latch 430. Local controller 135 or other control logic can activate the precharge transistor to store a value corresponding to a precharge signal (e.g., a power signal) in latch 410 and can activate the read transistor to discharge the stored charge from latch 410 to ground. Local controller 135 or other control logic can activate the transistor to store a value from master bit line 342 (e.g., received from logic layer 102) in special latch 430 and can activate the read transistor to move the value from special latch 430 onto local bit line 404 for copying to latch 410 or another latch in logic layer 106.

[0087] In one embodiment, horizontal layer 710 includes connections to ground (PLATE) and a precharge voltage (VPRE) in latch 410 and a connection to master bit line 342 (DUM) and a connection to ground (PLATE) in special latch 430 .

[0088] Figures 8A to 8L is a diagram illustrating a process flow for forming a dynamic latch over a three-dimensional nonvolatile memory array according to some embodiments of the present disclosure. Figures 8A to 8L represents a series of processing operations performed when forming the structure of latch 410 and special latch 430, such as Figure 4 and Figure 7 Both latch 410 and special latch 430 may be part of logic layer 106 above memory array 104, such as Figure 3 and Figure 6 As shown in . Figures 8A to 8L The processing operations described in may be part of a manufacturing process performed using semiconductor fabrication equipment.

[0089] exist Fig. 8A, horizontal layers 702 and 704 are formed in a vertical stack above the latch SRC plate 620. The horizontal layers 702 and 704 may be formed of polysilicon or other conductive materials. In one embodiment, an intervening layer of oxide or other non-conductive material is formed in the vertical stack to separate the horizontal layers 702 and 704 from the latch SRC plate 620 and from each other. In one embodiment, cutouts 802 and 804 are formed in the vertical stack through the horizontal layers 702 and 704 and the intervening oxide layer up to the latch SRC plate 620. In addition, cutouts 806 and 808 are formed in the vertical stack through the horizontal layers 702 and 704 and the intervening oxide layer but not reaching the latch SRC plate 620. In one embodiment, the cutouts 802 and 804 have a first size (e.g., width) and the cutouts 806 and 808 have a second size, wherein the first size is greater than the second size. Cutouts 802 and 804 will form two latch pillars, such as two logic level latch pillars 630, while cutouts 806 and 808 will provide isolation between the latch pillars.

[0090] exist Figure 8B 804. In the sidewall fill operation, a non-conductive material (e.g., nitride-converted oxide) 810 is applied to the sidewalls of the cutouts 802 and 804. In one embodiment, the cutouts 806 and 808 are completely filled with the non-conductive material. In addition, in addition to the above-mentioned cutouts 802 and 804, a photoresist layer 812 is applied to the top of the vertical stack. In addition, a perforation operation is performed in the bottom of the cutouts 802 and 804 to form a connection with the latch SRC plate 620.

[0091] exist Figure 8C , another sidewall fill operation is performed on the cutouts 802 and 804. In this sidewall fill operation, a conductive material (e.g., polysilicon) 814 is applied to the sidewalls of the cutouts 802 and 804 on top of the previously applied non-conductive material 810. Additionally, the remaining portions of the cutouts 802 and 804 are completely filled with the non-conductive material (e.g., oxide) and the photoresist layer 812 is removed.

[0092] exist Fig.8D , a horizontal layer 706 is formed on top of the vertical stack. The horizontal layer 706 may be formed of polysilicon or other conductive material. In one embodiment, an intervening layer of oxide or other non-conductive material is formed in the vertical stack to separate the horizontal layer 706 from the other conductive layers. In one embodiment, the cuts 802 and 804 are extended to the top of the vertical stack (i.e., up through the oxide layer above the horizontal layer 706). In one embodiment, the cuts 802 and 804 are extended using patterning in the photoresist layer 818 on top of the vertical stack.

[0093] exist Fig. 8E, a horizontal layer 708 is formed on top of the vertical stack. The horizontal layer 708 may be formed of polysilicon or other conductive material. In one embodiment, an intervening layer of oxide or other non-conductive material is formed in the vertical stack to separate the horizontal layer 708 from the other conductive layers. In one embodiment, the cuts 802 and 804 are also completely filled with polysilicon to create an electrical short between the horizontal layers 706 and 708.

[0094] exist Figure 8F 806. In one embodiment, cutout 802 is extended again to the top of the vertical stack (i.e., up through the oxide layer above horizontal layer 708). In one embodiment, cutout 802 is extended using patterning in photoresist layer 820 on the top of the vertical stack. In one embodiment, cutout 802 extends from the top of the vertical stack down through horizontal layer 708 into the oxide layer between horizontal layers 708 and 706. Additionally, cutouts 822 and 824 are formed in the vertical stack through horizontal layers 702 to 708 and intervening oxide layers to latch SRC plate 620. Cutouts 822 and 824 will form two additional latch pillars.

[0095] exist Figure 8G , a sidewall fill operation is performed on the cutouts 802, 822, and 824. In this sidewall fill operation, a non-conductive material (e.g., nitride-converted oxide) is applied to the sidewalls of the cutouts 802, 822, and 824. In addition, a perforation operation is performed in the bottom of the cutouts 822 and 824 to form a connection with the latch SRC plate 620. Subsequently, another sidewall fill operation is performed, in which a conductive material (e.g., polysilicon) is applied to the sidewalls of the cutouts 802, 822, and 824 on top of the previously applied non-conductive material. In addition, the remaining portions of the cutouts 802, 822, and 824 are completely filled with the non-conductive material (e.g., oxide).

[0096] exist Figure 8H In one embodiment, a horizontal layer 710 is formed on top of the vertical stack. The horizontal layer 710 may be formed of polysilicon or other conductive materials. In one embodiment, an intervening layer of oxide or other non-conductive material is formed in the vertical stack to separate the horizontal layer 710 from the other conductive layers. In one embodiment, an additional oxide layer is formed above the horizontal layer 710 that is thicker (e.g., taller) than the horizontal layer or other oxide layers in the vertical stack.

[0097] exist Fig.8IIn one embodiment, cut 804 is extended again to the top of the vertical stack (i.e., up through the oxide layer above horizontal layer 710). In one embodiment, patterning in the photoresist layer on the top of the vertical stack is used to extend cut 804. In one embodiment, cut 804 extends from the top of the vertical stack down through horizontal layers 710 and 708 into the oxide layer between horizontal layers 708 and 706.

[0098] exist Figure 8J In the embodiment of the present invention, a sidewall fill operation is performed on the cutout 804. In this sidewall fill operation, a non-conductive material (e.g., nitride-converted oxide) is applied to the sidewalls of the cutout 804. Subsequently, another sidewall fill operation is performed in which a conductive material (e.g., polysilicon) is applied to the sidewalls of the cutout 804 on top of the previously applied non-conductive material. In addition, the remaining portion of the cutout 804 is completely filled with the non-conductive material (e.g., oxide).

[0099] exist Figure 8K 806 and 808. In one embodiment, cutouts 802, 804, 806, 808, 822, and 824 are extended to the top of the vertical stack (i.e., up through the oxide layer above horizontal layer 710). In one embodiment, the cutouts are extended using patterning in the photoresist layer on the top of the vertical stack. Additionally, a new cutout 826 is formed in the vertical stack through horizontal layers 702 to 710 and the intervening oxide layer but not reaching SRC plate 620. In one embodiment, cutout 826 has a second size (i.e., the same as cutouts 806 and 808). Cutout 826 will provide isolation between latch pillars formed within cutouts 802 and 804.

[0100] exist Figure 8L , the remaining portions of cutouts 802, 804, 822, and 824 are filled with a conductive material (e.g., polysilicon) to form a connection from the top of the vertical stack to the horizontal layer 710. Additionally, the remaining portions of cutouts 806, 808, and 826 are filled with a non-conductive material (e.g., oxide) to provide isolation between the latch pillars.

[0101] As the vertical stack is fully formed, the intersections between the horizontal layers 702-710 and the vertical latch pillars can form devices that make up latch 410 or special latch 430. For example, the latch pillars in cutouts 802 and 822 can be used to form latch 410 and the latch pillars in cutouts 804 and 824 can be used to form special latch 430. The arrangement of the devices in the horizontal layers 702-710 can be similar to that described with respect to FIG. Figure 7 and Figure 4 The arrangement shown is the same. In other embodiments, Figures 8A to 8LThe process described in the foregoing may be repeated as many times as necessary to form the entire logic layer latch pillar 630 that makes up the logic layer 106 above the memory array 104. In addition, although only the formation of four latch pillars for forming two latches is described, it should be understood that the same processing techniques may be used to form any number of latch pillars and latches.

[0102] Fig. 9 An example machine of a computer system 900 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 900 may correspond to a host system (e.g., the host system 120 of FIG. 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of FIG. 1 ) or may be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the local controller 135 of FIG. 1 ). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0103] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0104] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)), etc.), a static memory 906 (e.g., static random access memory (SRAM)), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0105] The processing device 902 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. The computer system 900 may further include a network interface device 908 to communicate over a network 920.

[0106] The data storage system 918 may include a machine-readable storage medium 924 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functionality described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media. The machine-readable storage medium 924, the data storage system 918, and / or the main memory 904 may correspond to the memory subsystem 110 of FIG. 1 .

[0107] In one embodiment, the instructions 926 include instructions that implement functionality corresponding to the local controller 135 of FIG. 1. Although the machine-readable storage medium 924 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" should accordingly be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0108] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm herein is generally conceived of as a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0109] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0110] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0111] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0112] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0113] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A memory device, comprising: Memory array; and control logic operably coupled to the memory array to perform operations including: storing a multi-bit data pattern in a plurality of latches disposed in a logic layer above the memory array, the multi-bit data pattern representing a sequence of bits to be programmed to corresponding memory cells of a plurality of sub-blocks of a block of the memory array; precharging the plurality of sub-blocks according to the multi-bit data pattern; and A single programming pulse is caused to be applied to a selected word line of a plurality of word lines of the block to program the corresponding memory cells of the plurality of sub-blocks according to the data pattern.

2. The memory device of claim 1 , further comprising: A substrate is provided, wherein the memory array is disposed between the substrate and the logic layer disposed above the memory array.

3. The memory device of claim 2, wherein storing the multi-bit data pattern in the plurality of latches disposed in the logic layer above the memory array comprises: The data pattern is transferred from a page buffer disposed in a logic layer below the memory array to the logic layer disposed above the memory array via a master bit line of the memory device, wherein the data pattern is received at the logic layer disposed above the memory array by special latches coupled between the master bit lines and local bit lines associated with a block group including the block to which the data pattern is to be programmed, and wherein the logic layer disposed below the memory array is disposed between the memory array and the substrate.

4. The memory device of claim 3, wherein storing the multi-bit data pattern in the plurality of latches disposed in the logic layer above the memory array further comprises: Each bit in the sequence of bits is transferred via the local bit line to a respective one of a plurality of data latches disposed in the logic layer above the memory array, wherein the plurality of data latches are isolated from the master bit line.

5. The memory device of claim 1 , wherein precharging the plurality of sub-blocks according to the multi-bit data pattern comprises: causing a pass voltage to be applied to the plurality of word lines of the block of the memory array, the pass voltage boosting a channel potential of each of the plurality of sub-blocks to a boosting voltage; and The boosted voltage is selectively discharged from one or more of the plurality of sub-blocks according to the data pattern stored in the plurality of latches disposed in the logic layer above the memory array.

6. The memory device of claim 5 , wherein each of the plurality of word lines is coupled to a set of corresponding memory cells in the block, and wherein one memory cell from each set of corresponding memory cells is associated with one of the plurality of sub-blocks of the block, wherein each of the plurality of sub-blocks comprises a string of memory cells that share a channel material pillar, and wherein each memory cell in the string of memory cells is associated with a corresponding word line of the plurality of word lines, and wherein the plurality of sub-blocks comprise corresponding select gate devices to couple the string of memory cells to a bit line.

7. The memory device of claim 6, wherein selectively discharging the boosted voltage from one or more of the plurality of sub-blocks according to the data pattern comprises: activating one or more of the respective select gate devices corresponding to one or more first sub-blocks for which the respective memory cells are to be programmed to cause the channel potential of the one or more first sub-blocks to be lowered to ground potential; and One or more of the respective select gate devices corresponding to one or more second sub-blocks for which the respective memory cells are not programmed are not activated to cause the channel potential of the one or more second sub-blocks to remain at the boosted voltage.

8. The memory device of claim 7, wherein the single programming pulse applied to the selected one of the plurality of word lines of the block will program the corresponding memory cells of the one or more first sub-blocks and not program the corresponding memory cells of the one or more second sub-blocks.

9. A method comprising: storing a multi-bit data pattern in a plurality of latches disposed in a logic layer above a memory array, the multi-bit data pattern representing a sequence of bits to be programmed to corresponding memory cells of a plurality of sub-blocks of a block of the memory array; precharging the plurality of sub-blocks according to the multi-bit data pattern; and A single programming pulse is caused to be applied to a selected word line of a plurality of word lines of the block to program the corresponding memory cells of the plurality of sub-blocks according to the data pattern.

10. The memory device of claim 9, further comprising: A substrate is provided, wherein the memory array is disposed between the substrate and the logic layer disposed above the memory array.

11. The method of claim 10, wherein storing the multi-bit data pattern in the plurality of latches disposed in the logic layer above the memory array comprises: The data pattern is transferred from a page buffer disposed in a logic layer below the memory array to the logic layer disposed above the memory array via a master bit line of the memory device, wherein the data pattern is received at the logic layer disposed above the memory array by special latches coupled between the master bit lines and local bit lines associated with a block group including the block to which the data pattern is to be programmed, and wherein the logic layer disposed below the memory array is disposed between the memory array and the substrate.

12. The method of claim 11 , wherein storing the multi-bit data pattern in the plurality of latches disposed in the logic layer above the memory array further comprises: Each bit in the sequence of bits is transferred via the local bit line to a respective one of a plurality of data latches disposed in the logic layer above the memory array, wherein the plurality of data latches are isolated from the master bit line.

13. The method of claim 9, wherein precharging the plurality of sub-blocks according to the multi-bit data pattern comprises: causing a pass voltage to be applied to the plurality of word lines of the block of the memory array, the pass voltage boosting a channel potential of each of the plurality of sub-blocks to a boosting voltage; and The boosted voltage is selectively discharged from one or more of the plurality of sub-blocks according to the data pattern stored in the plurality of latches disposed in the logic layer above the memory array.

14. The method of claim 13, wherein each of the plurality of word lines is coupled to a corresponding set of memory cells in the block, and wherein one memory cell from each set of corresponding memory cells is associated with one of the plurality of sub-blocks of the block, wherein each of the plurality of sub-blocks comprises a string of memory cells that share a channel material pillar, and wherein each memory cell in the string of memory cells is associated with a corresponding word line of the plurality of word lines, and wherein the plurality of sub-blocks comprise corresponding select gate devices to couple the string of memory cells to a bit line.

15. The method of claim 14, wherein selectively discharging the boosted voltage from one or more of the plurality of sub-blocks according to the data pattern comprises: activating one or more of the respective select gate devices corresponding to one or more first sub-blocks for which the respective memory cells are to be programmed to cause the channel potential of the one or more first sub-blocks to be lowered to ground potential; and One or more of the respective select gate devices corresponding to one or more second sub-blocks for which the respective memory cells are not programmed are not activated to cause the channel potential of the one or more second sub-blocks to remain at the boosted voltage.

16. The method of claim 15, wherein the single programming pulse applied to the selected one of the plurality of word lines of the block will program the corresponding memory cells of the one or more first sub-blocks and not program the corresponding memory cells of the one or more second sub-blocks.

17. A memory device comprising: a memory array comprising a plurality of block groups, each block group comprising a plurality of blocks, and each block comprising a plurality of sub-blocks; a logic layer disposed above the memory array, the logic layer disposed above the memory array including a plurality of latches to store multi-bit data patterns representing bit sequences to be programmed to corresponding memory cells of the plurality of sub-blocks of one of the plurality of blocks of the memory array; and Control logic is coupled to the memory array and the logic layer disposed above the memory array, wherein the control logic is to program the respective memory cells of the plurality of sub-blocks according to the multi-bit data pattern using a single programming pulse.

18. The memory device of claim 17, further comprising: a substrate, wherein the memory array is disposed between the substrate and the logic layer disposed above the memory array; a master bitline associated with the plurality of block groups; and a plurality of local bit lines, wherein each local bit line is associated with a respective one of the plurality of block groups, wherein the control logic further stores the multi-bit data pattern in the plurality of latches disposed in the logic layer disposed above the memory array by transferring the data pattern from a page buffer disposed in the logic layer disposed below the memory array to the logic layer disposed above the memory array via the master bit line of the memory device, wherein the data pattern is received at the logic layer disposed above the memory array by special latches coupled between the master bit line and local bit lines associated with a block group including the block to which the data pattern is to be programmed, and wherein the logic layer disposed below the memory array is disposed between the memory array and the substrate.

19. The memory device of claim 18, wherein storing the multi-bit data pattern in the plurality of latches disposed in the logic layer above the memory array further comprises: Each bit in the sequence of bits is transferred via the local bit line to a respective one of a plurality of data latches disposed in the logic layer above the memory array, wherein the plurality of data latches are isolated from the master bit line.

20. The memory device of claim 17, wherein to program the corresponding memory cells of the plurality of sub-blocks according to the multi-bit data pattern using the single programming pulse, the control logic is to: Precharging the plurality of sub-blocks according to the multi-bit data pattern, wherein the precharging comprises: causing a pass voltage to be applied to the plurality of word lines of the block of the memory array, the pass voltage boosting a channel potential of each of the plurality of sub-blocks to a boosting voltage; and The boosted voltage is selectively discharged from one or more of the plurality of sub-blocks according to the data pattern stored in the plurality of latches disposed in the logic layer above the memory array.

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