Fluorine-doped silicon-containing materials

Abstract

An exemplary semiconductor processing method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. The method may include contacting a substrate contained in a processing region with one or more deposition precursors. The method may include forming a silicon-containing material on a substrate. The method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The method may include contacting a silicon-containing material on a substrate with a fluorine-containing precursor to form a fluorine-treated silicon-containing material. The method may include contacting a fluorine-treated silicon-containing material with a plasma effluent of argon or diatomic nitrogen.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application No. 17 / 941,347, filed on September 9, 2022, entitled “FLUORINE-DOPED SILICON-CONTAINING MATERIALS,” which is incorporated herein by reference in its entirety. Technical Field

[0002] The present technology relates to deposition processes and chambers. More particularly, the present technology relates to methods of producing fluorine-doped silicon-containing materials. Background Art

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Producing patterned materials on a substrate requires controlled methods for forming and removing materials. Material properties can affect the operation of the device and can also affect the way films are removed relative to each other. Plasma enhanced deposition can produce films with certain properties. The formation of many films requires additional processing to adjust or enhance the material properties of the film in order to provide suitable properties.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology addresses these and other needs. Summary of the invention

[0005] An exemplary semiconductor processing method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. The method may include contacting a substrate contained in the processing region with the one or more deposition precursors. The method may include forming a silicon-containing material on the substrate. The method may include providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber. The method may include contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material. The method may include contacting the fluorine-treated silicon-containing material with a plasma effluent of argon or diatomic nitrogen.

[0006] In some embodiments, the one or more deposition precursors include a silicon-containing precursor and a boron-containing precursor. During the semiconductor processing method, the pressure within the semiconductor processing chamber may be maintained at less than or about 550°C. The substrate may include features characterized by an aspect ratio greater than or about 3:1. The method may include: stopping the flow of one or more deposition precursors after forming the silicon-containing material on the substrate. The method may include: reducing the pressure within the semiconductor processing chamber before providing the fluorine-containing precursor to the processing area of ​​the semiconductor processing chamber. While contacting the silicon-containing material on the substrate with the fluorine-containing precursor, the pressure within the semiconductor processing chamber may be maintained at less than or about 15 Torr. The method may include: forming a plasma effluent of argon or diatomic nitrogen before contacting the fluorine-treated silicon-containing material with the plasma effluent of argon or diatomic nitrogen. The plasma effluent of argon or diatomic nitrogen may be formed at a plasma power of less than or about 750W. The method may include: contacting the fluorine-treated silicon-containing material with the plasma effluent of argon or diatomic nitrogen to form a fluorine-doped silicon, boron and nitrogen material. The fluorine-doped silicon, boron, and nitrogen-containing material may be characterized by a conformality of greater than or about 90%. The fluorine-doped silicon, boron, and nitrogen-containing material may be characterized by a conformality of less than or about The fluorine-doped silicon, boron, and nitrogen-containing material may be characterized by a dielectric constant of less than or about 4.6.

[0007] Some embodiments of the present technology may include semiconductor processing methods. The methods may include: i) forming a silicon-containing material on a substrate. The methods may include: ii) contacting the silicon-containing material on the substrate with a fluorine-containing precursor to form a fluorine-treated silicon-containing material. The methods may include: iii) contacting the fluorine-treated silicon-containing material with a plasma effluent of argon or diatomic nitrogen to form a fluorine-doped silicon, boron, and nitrogen-containing material. The methods may include: iv) repeating operations i) to iii) for at least five cycles.

[0008] In some embodiments, operations i) and ii) are performed without plasma. The substrate may include features characterized by an aspect ratio greater than or about 3:1. The fluorine-doped silicon, boron, and nitrogen-containing material may be characterized by a conformality greater than or about 90%. During the semiconductor processing method, a temperature may be maintained at less than or about 550° C. During the semiconductor processing method, a pressure may be maintained at less than or about 40 Torr. The method may include: v) annealing the substrate and the fluorine-doped silicon, boron, and nitrogen-containing material.

[0009] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. The one or more deposition precursors may include a silicon-containing precursor. The method may include contacting a substrate contained in the processing region with the one or more deposition precursors. The method may include thermally forming a silicon-containing material layer on the substrate. The method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The method may include thermally contacting the silicon-containing material layer on the substrate with the fluorine-containing precursor to form a fluorine-doped silicon-containing material layer. The method may include providing argon, diatomic nitrogen, or both argon and diatomic nitrogen to a processing region of a semiconductor processing chamber. The method may include forming a plasma effluent of argon, diatomic nitrogen, or both argon and diatomic nitrogen. The method may include contacting the fluorine-doped silicon-containing material layer with a plasma effluent of argon, diatomic nitrogen, or both argon and diatomic nitrogen to form a fluorine-doped silicon-containing material.

[0010] In some embodiments, the fluorine-doped silicon-containing material layer is characterized by a conformality of greater than or about 90%. The plasma effluent of argon, diatomic nitrogen, or both argon and diatomic nitrogen can be formed at a plasma power of less than or about 750 W. The fluorine-doped silicon-containing material layer can be characterized by a dielectric constant of less than or about 4.6, and a dielectric constant of less than or about 5.0×10 -8 A / cm 2 of leakage current.

[0011] Such techniques may provide many benefits over conventional systems and techniques. For example, performing fluorine treatment and plasma treatment may improve deposition characteristics. For example, performing fluorine treatment may enhance conformality of the deposited material, reduce the dielectric constant of the deposited material, and / or reduce leakage current of the deposited material. Additionally, performing plasma treatment may densify the material, further increasing conformality and / or reducing the dielectric constant. These and other embodiments and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the techniques of this disclosure may be realized by reference to the remainder of the specification and the accompanying drawings.

[0013] Figure 1 A top plan view of an exemplary processing system is shown in accordance with some embodiments of the present technology.

[0014] Figure 2 A schematic cross-sectional diagram is shown of an exemplary plasma system according to some embodiments of the present technology.

[0015] Figure 3 Operations of an exemplary method of semiconductor processing in accordance with some embodiments of the present technology are illustrated.

[0016] FIG. 4A to FIG. 4B A cross-sectional view of a substrate being processed is shown in accordance with some embodiments of the present technology.

[0017] Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustration purposes only and should not be considered to be drawn to scale unless specifically noted as being drawn to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustration purposes.

[0018] In the accompanying drawings, similar components and / or features may have the same reference numeral. Further, various components of the same type may be distinguished by appending a letter after the reference numeral that distinguishes the similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0019] When forming an integrated circuit, many material layers are formed and partially or completely removed. Some integrated circuits require the formation of spacers or liner materials to at least partially separate other materials formed on either side of the spacer. Conventional techniques can use pure thermal processes or deposition and etching cycles to form spacers or liner materials with desired conformality. These conventional methods cannot achieve low dielectric constants and high conformality at the same time. As integrated circuits continue to decrease, there is an increasing need for material layers with multiple purposes (such as low dielectric constants and high conformality). Further, these conventional methods may form spacers or liner materials that cannot meet leakage current or breakdown voltage requirements. More importantly, these conventional techniques may be prone to shrinkage during post-formation processing (such as annealing), which may result in the inability to maintain the desired properties of the material.

[0020] The present technology can overcome these problems by performing fluorine treatment and / or plasma treatment after depositing the silicon-containing material. Fluorine treatment can introduce fluorine-containing precursors to perform heat treatment on the formed silicon-containing material, wherein fluorine can dope the silicon-containing material. In the doped silicon-containing material, fluorine can replace hydrogen bonds in the material with fluorine bonds. This replacement can smooth the surface of the silicon-containing material, thereby increasing conformality. Plasma treatment can bombard the film with heavy inert precursors to densify the film, further increasing conformality. Fluorine treatment and / or plasma treatment can also have a positive effect on the electrical properties of the silicon-containing material (such as dielectric constant, leakage current and breakdown voltage). Conventional techniques cannot meet all of these properties of the deposited film, thereby sacrificing one or more desired properties.

[0021] Although the remainder of the disclosure will routinely identify specific deposition processes using the disclosed techniques, it will be readily appreciated that the systems and methods are equally applicable to other deposition chambers, and processes that may occur in the chambers. Therefore, the techniques should not be considered limited to use with only these specific deposition processes or chambers. Before describing additional details of embodiments according to the present technology, the present disclosure will discuss one possible system and chamber that may be used to perform deposition processes according to embodiments of the present technology.

[0022] Figure 1 A top plan view of one embodiment of a processing system 100 of deposition, etching, baking and curing chambers according to an embodiment is shown. In the figure, a pair of front-opening unified cabins 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a to 108f, which are positioned in series sections 109a to 109c. A second robot 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a to 108f and back. Each substrate processing chamber 108a to 108f can be equipped to perform a number of substrate processing operations, including the formation of stacks of semiconductor materials described herein, in addition to plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processes (including annealing, ashing, etc.).

[0023] The substrate processing chambers 108a to 108f may include one or more system components for depositing, annealing, curing and / or etching dielectric films or other films on the substrate. In one configuration, two pairs of processing chambers (e.g., 108c-108d, and 108e-108f) in the processing chambers may be used to deposit dielectric materials on the substrate, and a third pair of processing chambers (e.g., 108a-108b) in the processing chambers may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a to 108f) may be configured to deposit alternating stacks of dielectric films on the substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in different embodiments. It will be understood that the system 100 contemplates additional configurations of deposition, etching, annealing and curing chambers for dielectric films.

[0024] Figure 2A schematic cross-sectional view of an exemplary plasma system 200 according to some embodiments of the present technology is shown. The plasma system 200 may show a pair of processing chambers 108 that may be installed in one or more of the above-described series sections 109 and may include a lid stack component according to embodiments of the present technology, and as may be further explained below. The plasma system 200 may generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an inner sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include the same components.

[0025] For example, the processing region 220B (components of which may also be included in the processing region 220A) may include a pedestal 228 disposed in the processing region through a passage 222 formed in the bottom wall 216 in the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal (such as a body portion). The pedestal 228 may include a heating element 232 (e.g., a resistive heating element) that may heat and control the temperature of the substrate at a desired process temperature. The pedestal 228 may also be heated by a remote heating element such as a bulb assembly or any other heating device.

[0026] The body of the base 228 can be coupled to the shaft 226 by the flange 233. The shaft 226 can electrically couple the base 228 to the power output or power box 203. The power box 203 can include a drive system that controls the elevation and movement of the base 228 within the processing area 220B. The shaft 226 can also include an electrical power interface for providing power to the base 228. The power box 203 can also include an interface for electrical power and a temperature indicator, such as a thermal coupling interface. The shaft 226 can include a base assembly 238 suitable for removably coupling the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 can be a shoulder or platform suitable for acting as a mechanical stop, which is configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0027] A rod 230 may be included that passes through a passage 224 formed in the bottom wall 216 of the processing region 220B, and the rod 230 may be utilized to position a substrate lift pin 261 disposed through the body of the pedestal 228. The substrate lift pin 261 may selectively separate the substrate 229 from the pedestal to facilitate exchanging the substrate 229 with a robot that is used to transfer the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0028] The chamber lid 204 can be coupled to the top portion of the chamber body 202. The lid 204 can house one or more precursor dispensing systems 208 coupled to the lid 204. The precursor dispensing system 208 can include a precursor inlet passage 240 that can deliver reactants and cleaning precursors to the processing region 220B through the dual channel showerhead 218. The dual channel showerhead 218 can include an annular base plate 248 having a baffle plate 244 disposed in the middle of a face plate 246. A radio frequency ("RF") source 265 can be coupled to the dual channel showerhead 218, and the RF source 265 can power the dual channel showerhead 218 to facilitate the generation of a plasma region between the face plate 246 and the pedestal 228 of the dual channel showerhead 218. In some embodiments, the RF source can be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric insulator 258 may be disposed between the cover 204 and the dual channel showerhead 218 to prevent conduction of RF power to the cover 204. A shadow ring 206 may be disposed on a periphery of the pedestal 228 where it engages the pedestal 228.

[0029] An optional cooling channel 247 may be formed in the annular base plate 248 of the precursor distribution system 208 to cool the annular base plate 248 during operation. A heat transfer fluid such as water, glycol, gas, etc. may be circulated through the cooling channel 247 so that the base plate 248 may be maintained at a predetermined temperature. The liner assembly 227 may be disposed in the processing region 220B adjacent to the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment in the processing region 220B. The liner assembly 227 may include a circumferential pumping chamber 225 to which a pumping system 264 may be coupled, the pumping system 264 being configured to exhaust gases and byproducts from the processing region 220B and control the pressure in the processing region 220B. A plurality of exhaust ports 231 may be formed on the liner assembly 227. Exhaust 231 may be configured to allow gas to flow from processing region 220B to circumferential pumping chamber 225 in a manner that facilitates processing within system 200 .

[0030] Figure 3The operations of an exemplary method 300 of a semiconductor process according to some embodiments of the present technology are illustrated. The method may be performed in a variety of processing chambers, including the processing system 200 described above, as well as any other chamber in which plasma deposition may be performed. The method 400 may include one or more operations that may precede the start of the method, including front-end processing, polishing, cleaning, deposition, etching, or any other operation that may be performed before the operations. The method 300 may include a plurality of optional operations that may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of semiconductor processing, but these operations are not critical to the technology or may be performed by alternative methods that will be further described below. The method 300 may describe FIG. 4A to FIG. 4B The operations schematically shown in FIG. 3 will be described in conjunction with the operations of method 300. FIG. 4A to FIG. 4B It should be understood that FIG. 4A to FIG. 4B The figures are only partially schematic, and the substrate may include any number of transistor sections having aspects as shown in the figures.

[0031] like Figure 4A As shown, structure 400 may include substrate 405. Substrate 405 may be made of or include silicon or some other semiconductor substrate material. One or more material layers 410 may be formed over substrate 405. One or more material layers 410 may include or define recesses 415. The aspect ratio of recess 415, or the ratio of hole length to hole diameter, may be greater than or about 2:1, and may be greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 6:1, greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, or greater.

[0032] At operation 305, method 300 may include providing one or more deposition precursors into a processing chamber, which may deliver the precursors into a processing region of the chamber, such as, for example, region 220, that may house substrate 405. The deposition precursors may include, for example, a silicon-containing precursor, a boron-containing precursor, a nitrogen-containing precursor, or any other deposition precursor for forming a silicon-containing material.

[0033] In an embodiment, one or more deposition precursors may include a silicon-containing precursor. The silicon-containing precursor may include an organosilane, which may include silane, disilane and other materials. Additional silicon-containing precursors may include silicon, carbon, oxygen or nitrogen, such as trisilylamine. In an embodiment, one or more deposition precursors may include a boron-containing precursor. The boron-containing precursor may include borane, such as borane, diborane or other multi-center bonded boron materials, and any other boron-containing material that may be used to produce silicon-containing and boron-containing materials. In some embodiments, deposition may utilize a single deposition precursor, such as a precursor including silicon and boron. The precursor may or may not include transporting additional precursors, such as a carrier gas or one or more oxygen-containing precursors for depositing an oxide layer.

[0034] At operation 310, method 300 may include contacting substrate 405 with one or more deposition precursors. Figure 4B As shown, at operation 315 , method 300 may include forming a silicon-containing material 420 . The silicon-containing material may be formed over one or more material layers 410 formed over substrate 405 .

[0035] Process conditions may also affect the operations performed in method 300. In an embodiment, each operation of method 300 may be performed during a constant temperature, while in some embodiments, the temperature may be adjusted during different operations. In some embodiments of the present technology, method 300 may be performed at a substrate, susceptor, and / or chamber temperature of less than or about 550°C, which may be due to thermal budget issues, and method 300 may be performed at a temperature of less than or about 525°C, less than or about 500°C, less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, less than or about 325C, less than or about 300°C, or less. The temperature may also be maintained at any temperature within these ranges, within a smaller range encompassed by these ranges, or within any range within these ranges. Forming the material at an elevated temperature may reduce the deposition rate and thus improve conformality. Therefore, in some embodiments, the pressure may be maintained between about 400°C and about 500°C.

[0036] The pressure in the semiconductor processing chamber may also affect the operations performed. In an embodiment, the pressure can be maintained at less than about 40 Torr. Therefore, the pressure can be maintained at less than or about 35 Torr, less than or about 30 Torr, less than or about 25 Torr, less than or about 20 Torr, less than or about 18 Torr, less than or about 16 Torr, less than or about 14 Torr, less than or about 12 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 4 Torr, less than or about 2 Torr, less than or about 1 Torr or less. The pressure can also be maintained within these ranges, within a smaller range covered by these ranges, or within any range in these ranges. In addition, as described below, the pressure can be adjusted during method 300. Since the precursor can experience more scattering before reaching the substrate, thereby reaching the substrate surface at a more random angle to achieve a more conformal film growth, the conformality can increase with the increase of pressure. Therefore, in some embodiments, the pressure can be maintained between about 10 Torr and about 20 Torr.

[0037] At operation 320, method 300 may include providing a fluorine-containing precursor into a processing chamber, which may deliver the precursor into a processing region of a chamber that may house substrate 405. An exemplary fluorine-containing precursor may be nitrogen trifluoride (NF3). Other fluorine sources may be used in conjunction with nitrogen trifluoride, or may be used in place of nitrogen trifluoride. In some embodiments, the fluorine-containing precursor may be or may include atomic fluorine, diatomic fluorine, hydrogen fluoride, nitrogen trifluoride, carbon tetrafluoride, xenon difluoride, and various other fluorine-containing precursors used or available in semiconductor processing.

[0038] At operation 325, method 300 may include contacting silicon-containing material 420 with a fluorine-containing precursor. The fluorine-containing precursor may dope silicon-containing material 420 to form a silicon-doped fluorine-containing material. Specifically, the fluorine-containing precursor may reorganize bonds in the silicon-containing material, and may replace at least some Si-H bonds and BH bonds with Si-F bonds and BF bonds, respectively. The less polarized fluorine bonds may reduce the dielectric constant of silicon-containing material 420 compared to the previous hydrogen bonds. The fluorine bonds may reduce the leakage current of silicon-containing material 420. In addition, contact of silicon-containing material 420 with the fluorine-containing precursor may form Si-F bonds from dangling silicon bonds on the surface of silicon-containing material 420. Due to the formation of Si-F bonds from dangling silicon bonds, and the increased polarization stability of fluorine, the surface of silicon-containing material 420 may be stabilized, thereby alleviating the distorted portion on the surface. By alleviating the distorted portion on the surface of silicon-containing material 420, conformality may be increased. After contact with the fluorine-containing precursor, the silicon-containing material 420 can be characterized by a fluorine concentration of less than or about 30 atomic percent, and the silicon-containing material 420 can be characterized by a fluorine concentration of less than or about 28 atomic percent, less than or about 26 atomic percent, less than or about 24 atomic percent, less than or about 22 atomic percent, less than or about 20 atomic percent, less than or about 18 atomic percent, less than or about 16 atomic percent, less than or about 14 atomic percent, less than or about 12 atomic percent, less than or about 10 atomic percent, or less.

[0039] In an embodiment, method 300 may include reducing pressure during operations 320 and 325. For example, the pressure may be reduced to less than or about 15 Torr, less than or about 14 Torr, less than or about 13 Torr, less than or about 12 Torr, less than or about 11 Torr, less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, less than or about 7 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, or less. At lower pressures, the residence time of the fluorine-containing precursor may be reduced compared to operations 305 to 315. At lower pressures, the mean free path may be increased, thereby allowing for increased interaction between the fluorine-containing precursor and the silicon-containing material 420.

[0040] The fluorine treatment at operations 320 and 325 may continue for a period of time sufficient to allow the fluorine-containing precursor to interact with the silicon-containing material 420. For example, the fluorine treatment at operations 320 and 325 may continue for a period of time between about 2 seconds and about 60 seconds. However, depending on various conditions (such as temperature, pressure, flow rate of the fluorine-containing precursor, and the properties and characteristics of the silicon-containing material 420), it is contemplated that operations 320 and 325 may continue for a period of time less than about 2 seconds and / or greater than or about 60 seconds.

[0041] In an embodiment, method 300 may include stopping the flow of one or more deposition precursors before providing the fluorine-containing precursor at operation 320. By stopping the flow of the one or more deposition precursors, deposition of the material may be reduced or stopped, thereby allowing the fluorine-containing precursor to dope the formed silicon-containing material 420. However, it is contemplated that the flow of one or more deposition precursors may be alternately reduced and / or maintained during operation 320.

[0042] At operation 330, method 300 may include contacting the fluorine-treated silicon-containing material with the plasma effluent. Note that prior to operation 330, for example, during any or all of operations 305 to 325, the semiconductor processing chamber may be maintained in a plasma-free state. Method 300 may include providing one or more plasma treatment precursors into the processing chamber, which may deliver the precursors into a processing region of the chamber that may house substrate 405. The plasma treatment precursor may include a nitrogen-containing precursor, such as diatomic nitrogen, which may impart nitrogen into the silicon-containing material 420. After treatment with the fluorine-containing precursor, the plasma treatment at operation 330 may form a fluorine-doped silicon- and nitrogen-containing material, such as a fluorine-doped silicon, boron, and nitrogen-containing material. The plasma treatment precursor may also include one or more inert species, such as argon, neon, xenon, or hydrogen.

[0043] Plasma effluents of one or more plasma treatment precursors may be generated at a plasma power of less than or about 750 W. At a plasma power greater than 750 W, the potential for arcing may increase, which may be detrimental to plasma treatment and formation of fluorine-doped silicon-containing materials. Thus, plasma effluents of one or more plasma treatment precursors may be generated at a plasma power of less than or about 700 W, and plasma effluents of one or more plasma treatment precursors may be generated at a plasma power of less than or about 650 W, less than or about 600 W, less than or about 550 W, less than or about 500 W, less than or about 450 W, less than or about 400 W, less than or about 350 W, less than or about 300 W, less than or about 250 W, less than or about 200 W, less than or about 150 W, or less.

[0044] The plasma treatment at operation 330 may impart material to the silicon-containing material 420, such as through plasma effluents of a nitrogen-containing precursor. Also, plasma effluents of an inert precursor may bombard the film and densify the silicon-containing material 420. By densifying the silicon-containing material 420, conformality may be further increased. The film may be bombarded using a heavy inert precursor, such as argon, to densify the silicon-containing material 420. The plasma treatment at operation 330 may be performed at a reduced pressure of operations 320 and 325, which may increase the plasma density and help to more uniformly densify the film, again resulting in increased conformality of the silicon-containing material 420.

[0045] The plasma treatment at operation 330 may continue for a period of time sufficient for the plasma to interact with the silicon-containing material 420. For example, the plasma treatment at operation 330 may continue for a period of time between about 2 seconds and about 60 seconds. However, depending on various conditions (such as temperature, pressure, flow rate of plasma treatment precursors, and the properties and characteristics of the silicon-containing material 420), it is contemplated that operation 330 may continue for a period of time less than about 2 seconds and / or greater than or about 60 seconds.

[0046] After the plasma treatment of operation 330, the fluorine-doped silicon-containing material 420 may be less than or about If the silicon-containing material 420 is formed to be greater than The fluorine treatment of operations 320 and 325 and the plasma treatment of operation 330 may not be as effective. Therefore, the silicon-containing material 420 may be formed to be less than or about Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately Less than or approximately or less thickness.

[0047] like Figure 3 As shown, method 300 may include, at operation 335, repeating operations 300 to 330 for a plurality of cycles. By repeating operations 300 to 330, a silicon-containing material 420 with an increased thickness may be formed. In an embodiment, the operations of method 300 may be repeated for at least two cycles, at least three cycles, at least four cycles, at least five cycles, at least ten cycles, at least fifteen cycles, at least twenty cycles, at least thirty cycles, at least forty cycles, at least fifty cycles, or more. Thus, after repeating the operations for a plurality of cycles, the silicon-containing material may be approximately or Thickness characterization, such as greater than or about Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately Greater than or approximately or larger.

[0048] As previously discussed, the present technology can form silicon-containing materials characterized by reduced dielectric constants and improved electrical properties. For example, silicon-containing materials formed according to the present technology can be characterized by greater than or about 90% conformality, such as greater than or about 91%, greater than or about 92%, greater than or about 93%, greater than or about 94%, greater than or about 95%, or greater. In addition, silicon-containing materials formed according to the present technology can be characterized by a dielectric constant of less than or about 4.6, such as less than or about 4.5, less than or about 4.5, less than or about 4.4, less than or about 4.3, less than or about 4.2, less than or about 4.1, less than or about 4.0, less than or about 3.9, or less. Silicon-containing materials formed according to the present technology can be characterized by a dielectric constant of less than or about 5.0×10 -8 A / cm 2 The leakage current is characterized by less than or about 4.8×10 -8 A / cm 2 , less than or about 4.6×10 -8 A / cm 2 , less than or about 4.4×10 -8 A / cm 2 , less than or about 4.2×10 -8 A / cm 2 , less than or about 4.0×10 -8 A / cm 2 , less than or about 3.9×10 -8 A / cm 2 , less than or about 3.8×10 -8 A / cm 2 Conventional techniques may not be able to produce a film having a conformality of greater than or about 90%, a dielectric constant of less than or about 4.6, and / or a dielectric constant of less than or about 5.0×10 -8 A / cm 2 The fluorine treatment and plasma treatment of the present technology can fully modify the formed silicon-containing material to adjust the properties of the film.

[0049] In an embodiment, after forming the silicon-containing material 420 to a desired thickness, an anneal or other rapid thermal process may be performed at optional operation 340. The anneal or other process may not substantially change the properties of the silicon-containing material, indicating the thermal stability of the silicon-containing material 420.

[0050] In the foregoing description, for the purpose of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0051] After several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessary confusion of the present technology, many well-known processes and components are not described. Therefore, the above description should not be considered to limit the scope of the present technology.

[0052] Where a range of values ​​is provided, it is understood that each intermediate value (unless the context clearly dictates otherwise, the smallest fraction of the lower limit unit) also specifically discloses intermediate values ​​between the upper and lower limits of the range. Any narrower range between any specified value or unspecified intermediate value within a specified range and any other specified or intermediate value within the specified range is included. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range (where one of the limits is included, neither of the limits is included, or both are included in each range in the smaller range) is also included in the technology, subject to any explicitly excluded limits in the range. If the range includes one or both of the limits, those ranges excluding one or both of the included limits are also included.

[0053] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a silicon-containing precursor" includes a plurality of such silicon-containing precursors and reference to "the material layer" includes reference to one or more material layers and equivalents thereof known to those skilled in the art, and so forth.

[0054] Furthermore, when the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)” and “including” are used in this specification and the following claims, they are intended to specify the presence of stated features, integers, components or operations, but do not preclude the presence or addition of one or more other features, integers, components, operations, actions or groups.

Claims

1. A semiconductor processing method, comprising: providing one or more deposition precursors to a processing region of a semiconductor processing chamber; contacting a substrate contained in the processing region with the one or more deposition precursors; forming a silicon-containing material on the substrate; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material; and The fluorine-treated silicon-containing material is contacted with a plasma effluent of argon or diatomic nitrogen.

2. The semiconductor processing method of claim 1, wherein the one or more deposition precursors include a silicon-containing precursor and a boron-containing precursor.

3. The semiconductor processing method of claim 1, wherein during the semiconductor processing method, the temperature within the semiconductor processing chamber is maintained at less than or about 550°C.

4. The semiconductor processing method of claim 1 wherein the substrate comprises features characterized by an aspect ratio of greater than or about 3:

1.

5. The semiconductor processing method of claim 1, further comprising: After forming the silicon-containing material on the substrate, stopping the flow of the one or more deposition precursors; as well as Prior to providing the fluorine-containing precursor to the processing region of the semiconductor processing chamber, a pressure within the semiconductor processing chamber is reduced.

6. The semiconductor processing method of claim 5, wherein the pressure within the semiconductor processing chamber is maintained at less than or about 15 Torr while contacting the silicon-containing material on the substrate with the fluorine-containing precursor.

7. The semiconductor processing method of claim 1, further comprising: Prior to contacting the fluorine-treated silicon-containing material with the plasma effluent of argon or diatomic nitrogen, the plasma effluent of argon or diatomic nitrogen is formed, wherein the plasma effluent of argon or diatomic nitrogen is formed at a plasma power of less than or about 750W.

8. The semiconductor processing method of claim 1, wherein: contacting the fluorine-treated silicon-containing material with the plasma effluent of argon or diatomic nitrogen to form a fluorine-doped silicon, boron, and nitrogen-containing material; and The fluorine-doped silicon, boron, and nitrogen containing material is characterized by a conformality of greater than or about 90%.

9. The semiconductor processing method of claim 8, wherein the fluorine-doped silicon, boron and nitrogen-containing material comprises less than or about Characterization of thickness.

10. The semiconductor processing method of claim 8, wherein the fluorine-doped silicon, boron, and nitrogen containing material is characterized by a dielectric constant of less than or about 4.

6.

11. A semiconductor processing method comprising: i) forming a silicon-containing material on a substrate; ii) contacting the silicon-containing material on the substrate with a fluorine-containing precursor to form a fluorine-treated silicon-containing material; iii) contacting the fluorine-treated silicon-containing material with a plasma effluent of argon or diatomic nitrogen to form a fluorine-doped silicon, boron and nitrogen-containing material; and iv) Repeat operations i) to iii) for at least five cycles.

12. The semiconductor processing method of claim 11, wherein operation i) and operation ii) are performed without plasma.

13. The semiconductor processing method of claim 11 wherein the substrate comprises features characterized by an aspect ratio of greater than or about 3:

1.

14. The semiconductor processing method of claim 11 wherein the fluorine-doped silicon, boron, and nitrogen containing material is characterized by a conformality of greater than or about 90%.

15. The semiconductor processing method of claim 11, wherein: During the semiconductor processing method, the temperature is maintained at less than or about 550° C.; and During the semiconductor processing method, the pressure is maintained at less than or about 40 Torr.

16. The semiconductor processing method of claim 11, further comprising: v) annealing the substrate and the fluorine-doped silicon, boron and nitrogen containing material.

17. A semiconductor processing method comprising: providing one or more deposition precursors to a processing region of a semiconductor processing chamber, wherein the one or more deposition precursors include a silicon-containing precursor; contacting a substrate contained in the processing region with the one or more deposition precursors; thermally forming a silicon-containing material layer on the substrate; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; thermally contacting the silicon-containing material layer on the substrate with the fluorine-containing precursor to form a fluorine-doped silicon-containing material layer; providing argon, diatomic nitrogen, or both argon and diatomic nitrogen to the processing region of the semiconductor processing chamber; forming a plasma effluent of argon, diatomic nitrogen, or both argon and diatomic nitrogen; as well as The fluorine-doped silicon-containing material layer is contacted with the plasma effluent of argon, diatomic nitrogen, or both argon and diatomic nitrogen to form a fluorine-doped silicon-containing material.

18. The semiconductor processing method of claim 17, wherein the fluorine-doped silicon-containing material layer is characterized by a conformality of greater than or about 90%.

19. The semiconductor processing method of claim 17 wherein the plasma effluent of argon, diatomic nitrogen, or both argon and diatomic nitrogen is formed at a plasma power of less than or about 750 W.

20. The semiconductor processing method of claim 17, wherein the fluorine-doped silicon-containing material layer is characterized by: A dielectric constant of less than or about 4.6; and Less than or about 5.0×10 -8 A / cm 2 of leakage current.

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