Particle reduction in physical vapor deposition of amorphous silicon

Abstract

A method of depositing an amorphous silicon film by a physical vapor deposition process is disclosed. In some embodiments, a method of depositing amorphous silicon in a physical vapor deposition (PVD) processing chamber includes: (a) depositing an amorphous silicon layer atop a surface of a substrate disposed on a substrate support by a physical vapor deposition process while amorphous silicon is also deposited atop a component within the PVD processing chamber; and depositing an adhesive layer atop the amorphous silicon deposited on the feature. The adhesive layer may be a silicon compound. The silicon compound may be a compound of silicon with one or more of carbon, nitrogen, or oxygen. In some embodiments, the silicon compound is SiC, SiN, SiO, SiCN, or SiON.

Description

Technical Field

[0001]

[0013] Embodiments of the present disclosure are generally directed to methods of depositing films by physical vapor deposition. Background Art

[0002] Amorphous silicon films are used in a variety of semiconductor manufacturing applications. Typically, amorphous silicon films can be formed by a physical vapor deposition (PVD) process. The inventors have observed that conventional processes for depositing amorphous silicon films may result in the formation of an undesirable amount of particles on the substrate being processed.

[0003] Accordingly, the present inventors have provided improved methods for depositing amorphous silicon films by a physical vapor deposition process. Summary of the invention

[0004] A method for depositing an amorphous silicon film by a physical vapor deposition process is disclosed. In an embodiment, the method disclosed herein includes periodically depositing a glue layer on top of amorphous silicon (α-Si) deposited on top of a component of a processing chamber to suppress particle generation. The method of the present invention provides for suppressing cohesive failure by interlocking the interface between the glue layer and the deposited α-Si layer. The provided deposition technique advantageously improves the particle performance of PVD deposited α-Si.

[0005] Methods for depositing an amorphous silicon film by a physical vapor deposition process are disclosed. In some embodiments, the method of depositing amorphous silicon in a physical vapor deposition (PVD) processing chamber includes: (a) depositing an amorphous silicon layer on top of a surface of a substrate disposed on a substrate support by a physical vapor deposition process, while the amorphous silicon is also deposited on top of a component in the PVD processing chamber; and depositing a glue layer on top of the amorphous silicon deposited on the component. The glue layer can be a silicon compound. The silicon compound can be a compound of silicon and one or more of carbon, nitrogen or oxygen. In some embodiments, the silicon compound is SiC, SiN, SiO, SiCN or SiON.

[0006] In some embodiments, a method of depositing amorphous silicon in a physical vapor deposition (PVD) processing chamber includes: (a) sequentially depositing amorphous silicon layers atop respective surfaces of a plurality of substrates sequentially disposed on a substrate support by a physical vapor deposition process, wherein the amorphous silicon is deposited atop a component within the PVD processing chamber; and (b) placing a baffle plate atop the substrate support of the PVD processing chamber, and depositing a glue layer atop the amorphous silicon deposited on the component.

[0007] In some embodiments, a method for depositing amorphous silicon in a physical vapor deposition (PVD) processing chamber includes: (a) sequentially depositing amorphous silicon layers on top of corresponding surfaces of multiple substrates sequentially arranged on a substrate support by a physical vapor deposition process, wherein the amorphous silicon is deposited on top of a component in the PVD processing chamber, and wherein the sequential deposition continues until the amorphous silicon deposited on top of the component reaches a predetermined thickness; (b) subsequently placing a baffle plate on top of the substrate support of the PVD processing chamber, and depositing a glue layer on top of the amorphous silicon deposited on the component, wherein the glue layer comprises a silicon compound; (c) depositing an adjustment layer on top of the glue layer, wherein the adjustment layer composition is changed from the composition of the glue layer to amorphous silicon; and (e) after depositing the adjustment layer, repeating (a).

[0008] Other and further embodiments of the disclosure are described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, may be understood by reference to the illustrative embodiments of the present disclosure depicted in the accompanying drawings. However, the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope, as the disclosure may admit to other equally effective embodiments.

[0010] Figure 1 Depicted is a schematic cross-sectional view of a processing chamber according to some embodiments of the present disclosure.

[0011] Figure 2 A method of depositing amorphous silicon according to an embodiment of the present disclosure is depicted.

[0012] Figure 3 Depicted are schematic representations of layers deposited according to embodiments of the present disclosure.

[0013] To facilitate understanding, the same reference numerals are used to represent shared elements in the drawings where possible. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further description. DETAILED DESCRIPTION

[0014] The present disclosure relates to methods for depositing amorphous silicon (α-Si) films by a physical vapor deposition (PVD) process. In at least some embodiments, the inventive methods described herein advantageously provide a low-cost, robust, and effective method to improve particle performance during deposition of amorphous silicon films. Embodiments of the inventive methods further have minimal impact on other key single film properties, which ensures flexible tunability of the process window to control defectivity. Although described herein with respect to the deposition of amorphous silicon films, embodiments of the present disclosure may also be advantageously used for the deposition of other dielectric films to control defectivity through interfacial interlocking as disclosed herein.

[0015] Figure 1 A simplified cross-sectional view of an illustrative physical vapor deposition (PVD) processing system 100 suitable for performing methods according to at least some embodiments of the present disclosure is depicted. Figure 1 The PVD processing system shown is illustrative only and is not intended to limit the scope of the present disclosure. Embodiments of the present disclosure may also be performed in other PVD processing systems according to the teachings provided herein. Other examples of PVD processing systems suitable for performing the methods described herein include PVD processing systems commercially available from Applied Materials, Inc., of Santa Clara, California.

[0016] Figure 2 Describes, for example, Figure 1 Flow chart of a method 200 for depositing an amorphous silicon layer atop a substrate disposed in a physical vapor deposition processing system as described in Figure 1 and Figure 3 Method 200 is described.

[0017] Figure 1 The depicted PVD processing chamber 104 includes a substrate support 106, a target assembly 114 with an optional backing plate assembly 160, and a source material 113 disposed on a side of the backing plate assembly 160 that faces the substrate support. The PVD processing chamber 104 further includes a pulsed DC power supply 182 to provide pulsed DC energy to the target assembly 114. Additional details regarding the illustrative PVD processing system 100 are discussed below.

[0018] The method 200 begins at 202 by depositing an amorphous silicon layer atop a surface of a substrate via a physical vapor deposition process, wherein the amorphous silicon is further deposited atop components within a PVD processing chamber (eg, the PVD processing chamber 104 ).

[0019] The substrate may be any suitable substrate having any suitable geometry, such as a circular wafer, a square, a rectangle, etc. The substrate may comprise any suitable material, such as one or more of silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), glass, other dielectric materials, etc., and may have one or more layers of other materials disposed on top of the substrate. The substrate may be a blank substrate (e.g., having no features disposed thereon), or the substrate may have features formed in or on the substrate, such as vias or trenches, or high aspect ratio features.

[0020] In some embodiments, the amorphous silicon layer can be formed by any suitable PVD process for sputtering a silicon source material onto a substrate to form an amorphous silicon layer. For example, depositing the amorphous silicon layer can include providing a plasma-forming gas to a processing region 120 of a physical vapor deposition processing chamber (e.g., a PVD processing chamber 104). The plasma-forming gas can include one or more inert gases, such as a rare gas or other inert gas. DC power can be provided to a target assembly 114 disposed relative to the substrate to form a plasma in the processing region 120 of the PVD processing chamber 104. The DC power is an amount of DC power suitable for forming a plasma in the processing region 120 and can vary depending on the chamber size, geometry, etc. The plasma is used to sputter a source material 113 from the target assembly 114 to deposit an amorphous silicon layer onto the substrate. For example, the source material 113 consists of or substantially consists of silicon, such as single crystal silicon.

[0021] like Figure 3 As depicted, depositing an amorphous silicon layer atop a surface of a substrate results in an amorphous silicon layer 304 being deposited atop a component (e.g., component 302) within a PVD processing chamber (e.g., PVD processing chamber 104) (such as a surface of an internal PVD chamber component that faces a processing volume). Examples of component 302 include shields, cover rings, and the like (e.g., see below with respect to Figure 1 138 and cover ring 146 discussed above). Over time, as substrates are sequentially processed and amorphous silicon films are deposited on the substrates, the thickness of the amorphous silicon coating on the chamber components continues to increase. For example, many substrates (such as dozens of substrates or hundreds of substrates) can be sequentially processed in a PVD chamber to have an amorphous silicon layer deposited as described above.

[0022] The inventors have observed that if the thickness of the amorphous silicon layer deposited on the chamber components becomes too great, the amorphous silicon film deposited on the chamber components may begin to flake off, thereby undesirably causing particle deposition on substrates subsequently processed in the PVD chamber. The inventors have discovered that by depositing a glue layer (e.g., glue layer 306) atop the amorphous silicon layer 304 on the chamber components, particle formation from that source may be reduced or eliminated.

[0023] Therefore, next, at 204, a glue layer 306 is deposited on top of the amorphous silicon layer 304 deposited on the chamber component (e.g., component 302). In an embodiment, the glue layer is a silicon compound. In an embodiment, the silicon compound is a compound of silicon and one or more of carbon, nitrogen, or oxygen. For example, the silicon compound can be SiC, SiN, SiO, SiCN, or SiON, etc.

[0024] In an embodiment, amorphous silicon is sequentially deposited on top of multiple substrates until the thickness of the amorphous silicon deposited on top of the components within the PVD processing chamber reaches a predetermined amount. For example, in some embodiments, up to about 15,000 angstroms of amorphous silicon may accumulate on the PVD chamber components. In an embodiment, after the thickness of the amorphous silicon deposited on top of the components within the PVD processing chamber reaches a predetermined amount, depositing the glue layer occurs. In some embodiments, after depositing the glue layer, the deposition of amorphous silicon on one or more substrates may be repeated (e.g., continued). The inventors believe that the glue layer 306 acts as an interfacial interlock with the amorphous silicon layer 304 to robustly bond together and prevent the amorphous silicon layer 304 and / or the glue layer 306 from peeling off or delaminating from the chamber components and peeling off or delaminating relative to the amorphous silicon layer subsequently deposited on top of the glue layer 306 as the process continues.

[0025] In some embodiments, the subbing layer can be deposited to a thickness of up to about 5,000 angstroms, such as about 5 angstroms to about 5,000 angstroms. In some embodiments, the subbing layer can be deposited in multiple sub-layers in a pulsed DC deposition process.

[0026] The PVD processing chamber (e.g., 104) may be provided with a baffle plate (e.g., described below with respect to a substrate support (e.g., 106) atop the substrate support (e.g., 106) of the PVD processing chamber (e.g., 104). Figure 1 The baffle plate 142 discussed above) is used to perform the deposition of the glue layer. For example, after removing the substrate having the amorphous silicon layer deposited thereon, the baffle plate can be placed above the substrate support. One or more process gases containing elements that will be part of the silicon compound are provided to the PVD processing chamber, and a sticking operation is performed to deposit the glue layer 306 on top of the amorphous silicon layer 304. Non-limiting examples of process gases include nitrogen (N2), ammonia (NH3), methane (CH4), oxygen (O2), etc. The sticking operation can be performed in any suitable manner, such as by providing DC power to the target while flowing one or more process gases as described above. When the deposition of the glue layer 306 is completed, the baffle plate can be removed and further processing can continue, such as continuing to deposit an amorphous silicon layer on a subsequent substrate.

[0027] In some embodiments, a conditioning process may be performed after depositing the glue layer 306 and before repeating the deposition of amorphous silicon. For example, the conditioning process may be used to clean the surface of the source material of the target to obtain a suitably clean surface to resume deposition of the amorphous silicon layer. In some embodiments, the glue layer may be deposited to a thickness of up to about 5,000 angstroms. In some embodiments, the conditioning process may deposit the conditioning layer to a determined thickness, such as up to about 1,000 angstroms. The conditioning process is performed using the same deposition conditions as used to deposit amorphous silicon to transition from the glue layer deposition to the amorphous silicon deposition. For example, the conditioning layer may have a composition that transitions or gradually changes from the glue layer (e.g., a silicon compound layer) to the amorphous silicon. For example, if N2 gas is used to deposit SiN x The adhesive layer can have a SiN x The conversion to N-doped silicon and then to amorphous silicon is similar when other process gases are used to deposit glue layers with other compositions. In some embodiments, the conditioning process may be a pulsed DC deposition process that deposits multiple sub-layers that together form the conditioning layer.

[0028] In some embodiments, a glue layer similar to glue layer 306 (e.g., formed in the same manner as disclosed above) can be deposited before depositing amorphous silicon on the substrate in a PVD processing chamber. For example, when a new target is provided in a PVD chamber, an initial firing and / or conditioning process can be performed to prepare the target for production, and deposition of glue layer 306 can be performed between the firing or conditioning process and the amorphous silicon deposition process.

[0029] In some embodiments, the above method can be repeated periodically as needed. For example, the above method can be repeated periodically during the life of the target material, and repeated again after installing and adjusting a new target material.

[0030] Return to Figure 1 , the PVD processing chamber 104 includes a removable chamber lid 102. The chamber lid 102 may include a target assembly 114 and a grounding assembly 103. The PVD processing chamber 104 contains a substrate support 106 for receiving a substrate 108. The substrate support 106 may be located within a lower grounded enclosure 110.

[0031] The DC power supply 182 is coupled to the target assembly 114, for example, through the electrode 154, to provide DC power to the target assembly 114. In some embodiments, the DC power supply 182 is a pulsed DC power supply to provide pulsed DC energy, for example, to enhance the sputtering rate of the target material (and thus enhance the deposition rate on the substrate). The DC power can range from about 200 W to about 20 kilowatts (kW), but the amount of DC power applied can vary depending on the chamber geometry (e.g., target size, etc.). The DC power can be adjusted to control the deposition rate of the sputtered metal atoms on the substrate. For example, increasing the DC power can result in increased interaction of the plasma with the source material 113 and increased sputtering of metal atoms from the target assembly 114.

[0032] The PVD processing system 100 may include a source distribution plate 158 that is opposite the back side of the target assembly 114 and is electrically coupled to the target assembly 114 along a peripheral edge of the target assembly 114. The PVD processing system 100 may include a cavity 170 that is disposed between the back side of the target assembly 114 and the source distribution plate 158. The cavity 170 is at least partially defined by an inner surface of the conductive support ring 164, a target-facing surface of the source distribution plate 158, and a surface (e.g., a back side) of the target assembly 114 (or the backing plate assembly 160) that faces the source distribution plate.

[0033] The PVD processing system 100 further includes a magnetron assembly. The magnetron assembly provides a rotating magnetic field near the target assembly 114 to assist in plasma processing within the PVD processing chamber 104. The magnetron assembly includes a rotatable magnet assembly 148 disposed within the cavity 170. The rotatable magnet assembly 148 rotates about a central axis 186 of the PVD processing chamber 104. In some embodiments, the magnetron assembly includes a motor 176, a motor shaft 174, a gear assembly 178, and a rotatable magnet assembly 148. The rotatable magnet assembly 148 includes a plurality of magnets 150 and is configured to rotate the plurality of magnets 150 about the central axis 186.

[0034] The substrate support 106 has a material receiving surface facing the major surface of the target assembly 114 and supports a substrate 108 to be sputter coated in a planar position relative to the major surface of the target assembly 114. The substrate support 106 can support the substrate 108 in a processing region 120 of the PVD processing chamber 104. The processing region 120 is defined as the area above the substrate support 106 during processing (e.g., between the target assembly 114 and the substrate support 106 when in a processing position).

[0035] In some embodiments, the substrate support 106 may be vertically movable to allow the substrate 108 to be transferred onto the substrate support 106 through a slit valve (not shown) in a lower portion of the PVD processing chamber 104 and thereafter raised to a deposition or processing position. In some embodiments, the baffle plate 142 may be transferred into and out of the PVD processing chamber 104 through a slit valve to be positioned above the substrate support 106 as needed for the method 200 described above. In some embodiments, the baffle plate 142 may be stored within the PVD processing chamber 104 or may be moved into and out of the PVD processing chamber 104 through an opening other than the slit valve.

[0036] One or more gases may be supplied from a gas source 126 into a lower portion of the PVD processing chamber 104 through a mass flow controller 128. An exhaust port 130 may be provided and coupled to a pump (not shown) through a valve 132 for exhausting the interior of the PVD processing chamber 104 and facilitating maintaining a suitable pressure within the PVD processing chamber 104.

[0037] The PVD processing chamber 104 further includes a process kit shield or shield 138 to surround the processing volume or central area of ​​the PVD processing chamber 104 and protect other chamber components from damage and / or contamination from processing. In some embodiments, the shield 138 can be connected to the ledge 140 of the upper grounded enclosure 116 of the PVD processing chamber 104. The shield 138 extends downwardly and can include a generally tubular portion having a generally constant diameter generally surrounding the processing region 120. The shield 138 extends downwardly along the walls of the upper grounded enclosure 116 and the lower grounded enclosure 110 to below the top surface of the substrate support 106 and back upwardly until reaching the top surface of the substrate support 106 (e.g., forming a U-shaped portion at the bottom of the shield 138). When the substrate support 106 is in the lower loading position, the cover ring 146 rests on top of the upwardly extending inner portion of the shield 138, but when the substrate support is in the upper deposition position, the cover ring 146 rests on the outer periphery of the substrate support 106 to protect the substrate support 106 from sputtering deposition. Additional deposition rings (not shown) may be used to protect the edge of the substrate support 106 from deposition around the edge of the substrate 108.

[0038] The chamber lid 102 generally includes a ground assembly 103 disposed around a target assembly 114. The ground assembly 103 may include a ground plate 156 having a first surface 157 that may be substantially parallel to and opposite a back surface of the target assembly 114. A ground shield 112 may extend from the first surface 157 of the ground plate 156 and surround the target assembly 114. The ground assembly 103 may include a support member 175 to support the target assembly 114 within the ground assembly 103. In some embodiments, a sealing ring 181 may be disposed between the target assembly 114 and the support member 175 to insulate the target assembly 114 from the ground assembly 103.

[0039] The target assembly 114 can include a source material 113, such as silicon, e.g., single crystal silicon, etc., which is to be deposited on a substrate, such as substrate 108, during sputtering. In some embodiments, the target assembly 114 can be substantially made of the source material 113 without any backing plate to support the source material 113. In some embodiments, the target assembly 114 includes a backing plate assembly 160 to support the source material 113. The source material 113 can be disposed on a side of the backing plate assembly 160 that faces the substrate support, such as Figure 1 shown.

[0040] A controller 194 may be provided and coupled to various components of the PVD processing system 100 to control their operation. The controller 194 includes a central processing unit (CPU) 118, a memory 172, and a support circuit 173. The controller 194 may control the PVD processing system 100 directly, or through a computer (or controller) associated with a specific processing chamber and / or support system component. The controller 194 may be a general-purpose computer processor in any form of a general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The memory or computer-readable medium 172 of the controller 194 may be one or more readily available memories, such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, an optical storage medium (e.g., a compact disk or a digital video disk), a flash drive, or any other form of local or remote digital storage device. The support circuit 173 is coupled to the CPU 118 for supporting the processor in a conventional manner. Such circuits include caches, power supplies, clock circuits, input / output circuits and subsystems, etc. Inventive methods as described herein, such as method 200, may be stored in memory 264 as software routines that may be executed or called to control the operation of PVD processing system 100 as described herein. The software routines may also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by CPU 118.

[0041] While the foregoing is directed to particular embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the disclosure.

Claims

1. A method for depositing amorphous silicon in a physical vapor deposition (PVD) processing chamber, the method comprising: (a) depositing an amorphous silicon layer atop a surface of a substrate disposed on a substrate support by a physical vapor deposition process, wherein the amorphous silicon is further deposited atop a component within the PVD processing chamber; and (b) depositing a glue layer on top of the amorphous silicon deposited on the feature.

2. The method of claim 1, wherein the glue layer is a silicon compound.

3. The method of claim 2, wherein the silicon compound is a compound of silicon and one or more of carbon, nitrogen or oxygen.

4. The method of claim 2, wherein the silicon compound is SiC, SiN, SiO, SiCN or SiON.

5. The method of any one of claims 1 to 4, wherein the amorphous silicon is sequentially deposited atop a plurality of substrates until a thickness of the amorphous silicon deposited atop a component within the PVD processing chamber reaches a predetermined amount.

6. The method of claim 5, wherein depositing the glue layer occurs after the thickness of amorphous silicon deposited atop a component within the PVD processing chamber reaches the predetermined amount.

7. The method of claim 6, further comprising: After depositing the glue layer, (a) is repeated.

8. The method according to any one of claims 1 to 4, further comprising: After depositing the glue layer, (a) is repeated.

9. The method of any one of claims 1 to 4, wherein depositing the glue layer is performed using a baffle disk disposed atop a substrate support of the PVD processing chamber.

10. The method according to any one of claims 1 to 4, further comprising: Prior to performing (b), performing (a) repeatedly to deposit a plurality of corresponding amorphous silicon layers atop the surfaces of the corresponding plurality of substrates.

11. The method according to any one of claims 1 to 4, further comprising: A conditioning layer is deposited on top of the glue layer. 12 . The method of claim 11 , wherein the adjustment layer has a composition changed from a composition of the glue layer to amorphous silicon.

13. The method according to any one of claims 1 to 4, further comprising: Repeat (a) multiple times in sequence; as well as Prior to performing (b), placing a baffle disk atop a substrate support of the PVD processing chamber and depositing the glue layer atop the amorphous silicon deposited on the component, wherein the baffle disk is atop the substrate support.

14. The method of claim 13, further comprising: After depositing the glue layer, (a) is repeated.

15. The method of claim 14, further comprising: Before repeating (a), a regulating layer is deposited on top of the subbing layer.

16. The method of claim 15, wherein the composition of the adjustment layer is changed from the composition of the glue layer to amorphous silicon.

17. A non-transitory computer readable medium having stored thereon instructions which, when executed, result in a method of depositing amorphous silicon in a physical vapor deposition (PVD) processing chamber being performed, the method as recited in any one of claims 1-4.

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