Phase shifter construction method and device, electronic equipment and storage medium

Abstract

The invention provides a phase shifter construction method and device, electronic equipment and a storage medium, and relates to the technical field of test circuits. The method comprises the steps that a virtual LFSR dual with an actual LFSR is constructed, the virtual LFSR comprises a plurality of register units connected in sequence, and the register units are divided into a plurality of register groups; and repeatedly executing the following steps until the corresponding relationship between each XOR unit and the register unit is obtained. Controlling the virtual LFSR to continuously run a preset number of clock cycles; obtaining the number of target register groups in which register units with unique unit values of 1 exist in the virtual LFSR; and under the condition that the number of the target register groups is within a preset number range, selecting any XOR unit which does not establish a corresponding relationship with the register unit, and establishing a corresponding relationship between the XOR unit and the register unit with the unit value of 1 in each target register group. According to the invention, the construction speed of the phase shifter can be improved, and the fault coverage rate of the test circuit is improved to a certain extent.

Description

Technical Field

[0001] The present disclosure relates to the field of test circuit technology, and in particular to a phase shifter construction method, device, electronic device and storage medium. Background Art

[0002] Phase shifters are commonly used test circuit structures in large-scale integrated circuit built-in self-test, which can enable the test stimulus generation circuit to drive more scan chains simultaneously and reduce the correlation between the output data of adjacent register units to improve the fault coverage of the test.

[0003] In the related art, the construction method of the phase shifter is relatively complicated and requires a lot of time. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present disclosure provides a phase shifter construction method, device, electronic device and storage medium.

[0005] According to a first aspect of an embodiment of the present disclosure, a phase shifter construction method is provided, the method being used to construct a phase shifter in a test stimulus generation circuit, the test stimulus generation circuit comprising an actual LFSR and a plurality of XOR units;

[0006] The method comprises:

[0007] Constructing a virtual LFSR that is dual to the actual LFSR, wherein the virtual LFSR comprises a plurality of register units connected in sequence; the plurality of register units are divided into a plurality of register groups, and the register units in each register group are connected in series in sequence;

[0008] Repeat the following steps until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generating circuit as a phase shifter:

[0009] Controlling the virtual LFSR to continuously run a preset number of clock cycles;

[0010] Obtaining the number of target register groups in the virtual LFSR; wherein the target register group is a register group having a register unit having a unique unit value of 1;

[0011] When the number of target register groups in the virtual LFSR is within a preset number range, any XOR unit that has not established a corresponding relationship with a register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group.

[0012] In some embodiments, the constructing a virtual LFSR that is dual to the actual LFSR comprises:

[0013] Determine the number of register units and the number of register groups in the virtual LFSR according to the number of objects to be driven; wherein the objects to be driven include: a scan chain and / or a first-stage input port in a circuit to be tested, and the circuit to be tested is a circuit used for testing by the test stimulus generating circuit;

[0014] Dividing the register units in the virtual LFSR into a plurality of register groups according to the number of register units and the number of register groups in the virtual LFSR;

[0015] Based on the number and grouping of register units, a target primitive polynomial is selected from a primitive polynomial library;

[0016] Based on the target primitive polynomial, a virtual LFSR that is dual to the actual LFSR is constructed.

[0017] In some embodiments, the number of register units in the virtual LFSR is calculated as follows:

[0018] Calculating the number of first combinations of m different register units selected from the n register units, wherein m is an upper limit value of the preset number range, and n and m are both positive integers;

[0019] Using the minimum value of n when the first combination number is greater than or equal to the first combination number threshold as the number of register units in the virtual LFSR;

[0020] The first combination number threshold is the product of the order-limited proportional factor α and the number of the objects to be driven, and α≥5.

[0021] In some embodiments, the number of register groups in the virtual LFSR is calculated as follows:

[0022] Calculate the number of second combinations of m different register groups selected from the g register groups, where m is an upper limit value of the preset number range, and g and m are both positive integers;

[0023] When the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is used as the number of register groups in the virtual LFSR;

[0024] The second combination number threshold is the product of the group number limiting proportional factor β and the number of the objects to be driven, 0<β≤1.

[0025] In some embodiments, selecting a target primitive polynomial from a primitive polynomial library based on the number and grouping of register units includes:

[0026] Select any candidate primitive polynomial in the primitive polynomial library, where the order of the candidate primitive polynomial is n, and n is the number of register units in the virtual LFSR;

[0027] If the candidate primitive polynomial meets the preferred condition, the candidate primitive polynomial is used as the target primitive polynomial;

[0028] The preferred condition is that for each register group in the virtual LFSR, there are multiple items with coefficients of 1 corresponding to each register group in the candidate primitive polynomial.

[0029] In some embodiments, the method further comprises:

[0030] If all candidate primitive polynomials in the primitive polynomial library do not meet the preferred condition, the candidate primitive polynomial in the primitive polynomial library with the most items that meet the alternative condition and have a coefficient of 1 is used as the target primitive polynomial;

[0031] The candidate condition is as follows: for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 corresponding to each register group in the candidate primitive polynomial.

[0032] In some embodiments, the preset number range is the number range of input ports of each XOR unit, and the method further includes:

[0033] Determining the range of the number of input ports according to the number of scan chains in the circuit to be tested;

[0034] The circuit to be tested is a circuit that is tested by the test stimulus generating circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

[0035] According to a second aspect of an embodiment of the present disclosure, there is provided a phase shifter construction device, the device being used to construct a phase shifter in a test stimulus generation circuit, the test stimulus generation circuit comprising an actual LFSR and a plurality of XOR units;

[0036] The device comprises:

[0037] A construction module, used to construct a virtual LFSR dual to the actual LFSR, wherein the virtual LFSR comprises a plurality of register units connected in sequence; the plurality of register units are divided into a plurality of register groups, and the register units in each register group are connected in series in sequence;

[0038] An execution module is used to repeatedly execute the following steps until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generating circuit as a phase shifter:

[0039] Controlling the virtual LFSR to continuously run a preset number of clock cycles;

[0040] Obtaining the number of target register groups in the virtual LFSR; wherein the target register group is a register group having a register unit having a unique unit value of 1;

[0041] When the number of target register groups in the virtual LFSR is within a preset number range, any XOR unit that has not established a corresponding relationship with a register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group.

[0042] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0043] Processor; and

[0044] A memory, configured to store executable instructions of the processor;

[0045] The processor is configured to execute the method described in the first aspect by executing the executable instructions.

[0046] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method described in the first aspect is implemented.

[0047] The solution provided by the embodiment of the present disclosure can group the register units in the virtual LFSR during the process of constructing the phase shifter, and make each input end of the same XOR unit correspond to the register units from different register groups. By constructing the phase shifter in this way, the amount of calculation in the process of phase shifter construction can be reduced, the construction speed can be increased, and the fault coverage of the test circuit can be improved to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic structural diagram of a built-in self-test circuit in an embodiment of the present disclosure is shown.

[0049] Figure 2 A schematic diagram of the structure of an XOR unit in an embodiment of the present disclosure is shown.

[0050] Figure 3 A schematic flow chart of a phase shifter construction method in an embodiment of the present disclosure is shown.

[0051] Figure 4 The schematic diagrams of the structures of two types of LFSRs in the embodiments of the present disclosure are shown.

[0052] Figure 5 A schematic structural diagram of a phase shifter constructed in an embodiment of the present disclosure is shown.

[0053] Figure 6 A schematic flow chart of a virtual LFSR construction method in an embodiment of the present disclosure is shown.

[0054] Figure 7 A schematic diagram showing the corresponding relationship between the primitive polynomial and the LFSR in an embodiment of the present disclosure is shown.

[0055] Figure 8 A flow chart showing a method for selecting a primitive polynomial in an embodiment of the present disclosure is shown.

[0056] Fig. 9 A schematic flow chart of a method for determining the number of register units in an embodiment of the present disclosure is shown.

[0057] Fig.10 A logic diagram of a method for determining the number of register units in an embodiment of the present disclosure is shown.

[0058] Fig.11 A schematic flow chart of a method for determining the number of register groups in an embodiment of the present disclosure is shown.

[0059] Fig.12 A logical schematic diagram of a method for determining the number of register groups in an embodiment of the present disclosure is shown.

[0060] Fig.13 A schematic structural diagram of a phase shifter construction device according to an embodiment of the present disclosure is shown.

[0061] Fig.14 A schematic structural diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0062] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0063] Built-In Self-Test (BIST) refers to the process of setting up a self-test circuit inside the circuit in integrated circuit design, so that it can perform fault tests on itself without external test equipment. In built-in self-test technology, scan-based built-in self-test schemes are common schemes. Among them, the test scheme of a single scan chain takes a long time to test. In order to reduce the test time, a built-in self-test scheme of multiple scan chains combined in series and parallel can be used.

[0064] In a built-in self-test circuit based on multiple scan chains, a linear feedback shift register (LFSR) can be used to generate test vectors. Due to the structural dependency of the LFSR itself, the test vectors generated by it are correlated, that is, the value of each register unit in the LFSR is adjusted by simply shifting left or right the value of its adjacent register unit in the previous clock cycle. In this regard, in order to make the built-in self-test circuit have a higher fault coverage, a phase shifter can be added to the built-in self-test circuit to reduce the correlation between the test vectors shifted into the scan chain.

[0065] For example, Figure 1 FIG. 2 shows a schematic diagram of a structure of a built-in self-test circuit in an embodiment of the present disclosure. Figure 1 As shown in FIG. 1 , in the built-in self-test circuit, the phase shifter is located between the LFSR and the scan chain, which can be composed of an XOR unit. Figure 1 In the process, after the pseudo-random numbers generated by the LFSR are input into the phase shifter, the correlation between the outputs of adjacent register units in the LFSR can be further reduced, so that the test data output to the scan chain through the phase shifter can cover more fault test types. The outputs of each scan chain are finally summarized into a multi-input feature register, which can compress the test responses output by each scan chain. Finally, the obtained feature values ​​are compared to determine whether the circuit under test passes the test.

[0066] It is worth noting that although Figure 1 In the phase shifter shown, each XOR unit is an XOR gate including two input terminals. However, in practical applications, the number of input terminals of the XOR unit can be arbitrary.

[0067] For example, Figure 2 FIG. 1 shows a schematic diagram of a structure of an XOR unit including multiple input terminals. It is understandable that a single XOR gate has two input terminals. By cascading multiple XOR gates, an XOR unit including multiple input terminals can be obtained. For example, Figure 2 In the example, by cascading seven XOR gates with two inputs, an XOR unit with eight inputs can be obtained.

[0068] Exemplarily, when it is desired to use an XOR unit including an odd number of input terminals, an XOR unit having an even number of input terminals and having a greater number of input terminals than the desired number may be constructed first, and one or more of the input terminals may be fixedly set to 0. For example, when it is desired to obtain an XOR unit with seven input terminals, any input terminal may be fixedly set to 0 based on the XOR unit with eight input terminals.

[0069] The above introduces the application scenarios of the present disclosure and the basic concepts involved. The specific implementation methods of the present disclosure will be described in detail below.

[0070] First, an embodiment of the present disclosure provides a phase shifter construction method, which can be executed by any electronic device so as to be used to construct a phase shifter in a test stimulus generation circuit. Specifically, the test stimulus generation circuit is a circuit for generating test stimulus in a built-in self-test circuit, which can be composed of an LFSR and an XOR unit (for construction as a phase shifter). By executing the method of the embodiment of the present disclosure, the correspondence between the XOR unit in the test stimulus generation circuit and the register unit (in the LFSR) can be obtained. Subsequently, in the test stimulus generation circuit, the XOR unit and the register unit are connected according to the correspondence, and the XOR unit can be constructed as a phase shifter to improve the randomness of the test vector output by the LFSR.

[0071] Figure 3 A schematic diagram of a process flow of a phase shifter construction method according to an embodiment of the present disclosure is shown. Figure 3 As shown, the method includes the following steps.

[0072] S310, constructing a virtual LFSR that is dual to the actual LFSR, the virtual LFSR comprising a plurality of register units connected in sequence, the plurality of register units being divided into a plurality of register groups, and the register units in each register group being connected in series in sequence.

[0073] It should be noted that the actual LFSR can be understood as the LFSR actually used in the test circuit, while the virtual LFSR is the LFSR simulated by a computer program.

[0074] It is understandable that the method provided by the embodiment of the present disclosure is essentially a program instruction executed by an electronic device. The virtual LFSR is also constructed by computer program instructions, which can be implemented by a circuit simulation program running in a computer. The constructed virtual LFSR can be shown to the user in a visual manner, or it can be embodied as a program code that can describe the LFSR structure, which is not limited by the embodiment of the present disclosure.

[0075] For example, LFSR can be divided into two types, Type I LFSR and Type II LFSR, which are dual to each other. Figure 4 The difference between Type I LFSR and Type II LFSR is that the feedback register unit ( Figure 4The XOR operation mode of the register units (numbered 1, 5 and 6 in the figure) is different. There is only one XOR unit in the type I LFSR, and each feedback register unit is connected to the input end of the XOR unit. In the type II LFSR, each feedback register unit is followed by an independent XOR unit, and each feedback register unit is respectively connected to the input end of the XOR unit set thereafter.

[0076] The following theorem exists between the conversion matrices M and D of the two types of LFSR: Assume m = 2 n -1-q, then [M q ] T =D m , where n is the LFSR order, m and q are the number of simulation cycles of the two types of LFSR respectively, and T represents the matrix transposition operation. This theorem is the basis of the phase shifter construction method disclosed in the present invention, and characterizes the symmetry between the dual LFSRs in state switching. By using a virtual LFSR that is dual to the actual LFSR to perform simulation in a computer, the amount of calculation of the method provided by the present invention can be reduced and the efficiency of the simulation operation can be improved.

[0077] Therefore, when the actual LFSR is a type I LFSR, the virtual LFSR constructed by the computer program instructions is a type II LFSR. When the actual LFSR is a type II LFSR, the virtual LFSR constructed by the computer program instructions is a type I LFSR.

[0078] For example, in the constructed virtual LFSR, the register units are divided into a plurality of register groups. By dividing the register groups, it is possible to achieve inter-group isolation for register units with high correlation to a certain extent, thereby improving the randomness of the test vectors generated by the LFSR.

[0079] S320, repeatedly executing the following steps S321 to S323 until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generating circuit as a phase shifter.

[0080] Those skilled in the art will understand that after obtaining the correspondence between the XOR unit and the register unit, in an actual test stimulus generation circuit, different input terminals of the XOR unit can be connected to the corresponding register units respectively, thereby constructing the XOR unit as a phase shifter.

[0081] S321, controlling the virtual LFSR to continuously run a preset number of clock cycles.

[0082] Exemplarily, the virtual LFSR can be controlled to run continuously in the computer. In one clock cycle, the unit value stored in each register unit in the virtual LFSR will be shifted once.

[0083] Exemplarily, the preset number may be greater than or equal to 3.

[0084] That is to say, after the virtual LFSR "idles" for at least 3 clock cycles each time, the following steps S322 and S323 are executed to establish a corresponding relationship between the XOR unit and the register unit, so as to further reduce the correlation between adjacent output ports (i.e., the output ports of the XOR unit) in the constructed phase shifter.

[0085] Exemplarily, in each clock cycle, the operation of the virtual LFSR is as follows:

[0086] Step 1: According to the specific structure of the feedback register unit in the virtual LFSR, calculate and temporarily store the XOR output results of each feedback register unit. If the virtual LFSR is a type I LFSR, temporarily store the XOR output result of the external feedback register unit. If the virtual LFSR is a type II LFSR, temporarily store the XOR output result of each internal feedback register unit, and temporarily store the value of the penultimate register unit.

[0087] Step 2: Starting from the second to last register unit of the virtual LFSR, shift the current register unit value to the next register unit (overwriting the next register unit value). If the virtual LFSR is a type I LFSR, the data of the feedback register unit involved in the shift is the original register value. If the virtual LFSR is a type II LFSR, the data of the feedback register unit involved in the shift is the XOR output result of the feedback register unit temporarily stored in step 1.

[0088] Step 3: Repeat step 2 and cycle forward until the shift of the first register unit is completed.

[0089] Step 4: If the virtual LFSR is a type I LFSR, then write the XOR output result of the external feedback register unit temporarily stored in step 1 into the first register unit of the LFSR. If the virtual LFSR is a type II LFSR, then write the value of the last register unit of the LFSR temporarily stored in step 1 into the first register unit of the LFSR.

[0090] S322, obtaining the number of target register groups in the virtual LFSR, wherein the target register group is a register group having a register unit having a unique unit value of 1.

[0091] S323, when the number of target register groups in the virtual LFSR is within a preset number range, select any XOR unit that has not established a corresponding relationship with a register unit, and establish a corresponding relationship between the XOR unit and the register unit with a unit value of 1 in each target register group.

[0092] It can be understood that the phase shifter is essentially an XOR network composed of a group of XOR units, each of which can be understood as an "XOR tree". The "root node" of each "XOR tree" is used to drive a scan chain, and the construction process of the phase shifter is the process of connecting the "leaf nodes" of the "XOR tree" to the register unit. Among them, the "root node" can be understood as the output end of the XOR unit, and the "leaf node" can be understood as the input end of the XOR unit.

[0093] According to the related theorem of the two types of LFSR conversion matrices, taking the unit with a register value of 1 in each simulation cycle of the dual LFSR as the input of the XOR unit can obtain a higher state switching traversal efficiency, where the "simulation cycle" is the aforementioned "preset number of clock cycles". In addition, the present disclosure further enables the input end of a single XOR unit to correspond to register units in different register groups, thereby improving the randomness of the XOR unit output.

[0094] In some embodiments, the preset number range may be the number range of input ports of each XOR unit. When the number of target register groups in the virtual LFSR is within the preset number range, the sum of the number of register units with unit values ​​of 1 in all target register groups falls within the number range of input ports of the XOR unit. At this time, a corresponding relationship can be established between these register units and the same XOR unit, so that the XOR unit in the test stimulus generation circuit is constructed as a phase shifter, and the output of the phase shifter can provide a higher fault coverage rate.

[0095] Exemplarily, the range of the number of input ports of the XOR unit can be determined according to the number of scan chains in the circuit to be tested, wherein the circuit to be tested is a circuit used for testing by the test stimulus generation circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

[0096] It is understandable that the more input ports the phase shifter XOR gate has, the more random the test value output to the scan chain. And when the order of the LFSR is constant, the more input ports the XOR unit in the phase shifter has, the more combinations of XOR units there are, and the greater the possibility that different scan chains will obtain different test values ​​during the test process. However, the more input ports the XOR unit has, the more basic XOR gates that need to be cascaded, and the greater the area overhead of the test circuit. Therefore, when selecting the range of the number of input ports of the XOR unit, it is necessary to consider both the randomness of the test value and the area overhead of the test circuit.

[0097] Exemplarily, the mapping relationship between the number of scan chains t and the range of the number of input ports in the embodiment of the present disclosure may be as follows:

[0098] If t≤30, the lower limit of the input port number range is l=1 and the upper limit is m=3;

[0099] If 30<t≤300, the lower limit of the input port number range is l=3 and the upper limit is m=5;

[0100] If 300<t≤1000, the lower limit of the input port number range is l=4, and the upper limit is m=6;

[0101] If t>1000, the lower limit value of the input port quantity range is l=5, and the upper limit value is m=7.

[0102] In some embodiments, after obtaining the correspondence between each XOR unit and the register unit based on the method provided in the embodiments of the present disclosure, a phase shifter may be constructed in a test stimulus generation circuit of actual application in the following manner.

[0103] First, an actual LFSR is constructed which has the same order as the virtual LFSR and is in a dual relationship with the virtual LFSR.

[0104] Specifically, assuming that the virtual LFSR is a type I LFSR, the external loop in the virtual LFSR can be deleted, that is, the loop used to make each feedback register unit generate the input value of the first-stage register unit through an XOR operation. Then, a two-input XOR unit is inserted at the output end of each feedback register, one of the inputs of the XOR unit is the output of the feedback register unit, and the other input is the output of the final-stage register. In this way, the type II LFSR structure in the actual test stimulus generation circuit can be obtained.

[0105] Assuming that the virtual LFSR is a type II LFSR, the XOR unit connected to the output of each feedback register in the virtual LFSR can be deleted and directly connected to the input of the next-level register unit. Then, a multi-input XOR unit is added outside the shift path, and its inputs are the output of each feedback shift register and the output of the LFSR final register. In this way, the type I LFSR structure in the actual test stimulus generation circuit can be obtained.

[0106] It can be understood that the LFSRs in a dual relationship have the same order, that is, the two LFSRs contain the same number of register units, so the register units at the same position on the shift paths of the two LFSRs can correspond one to one.

[0107] Therefore, the correspondence between the XOR unit and the register unit obtained by the virtual LFSR simulation operation can be equivalent to the correspondence between the XOR unit in the actual test circuit and the register unit in the actual LFSR. According to the correspondence, in the actual test stimulus generation circuit, the input end of each XOR unit is connected to the output end of the register unit with which it has a corresponding relationship, and the construction of the phase shifter in the actual test stimulus generation circuit can be completed.

[0108] It is worth noting that the present disclosure does not limit the order of determining the correspondence between the XOR units, that is, in S323, any XOR unit that has not yet established a correspondence can be selected and a correspondence can be established between it and a register unit that meets the conditions.

[0109] However, when connecting the constructed phase shifter to the scan chain, the arrangement order of the scan chain needs to correspond to the order of the corresponding relationship determination of the XOR unit. That is, the first scan chain in the circuit to be tested is connected to the output end of the first XOR unit that has completed the corresponding relationship determination (with the register unit), the second scan chain is connected to the output end of the second XOR unit that has completed the corresponding relationship determination, the third scan chain is connected to the output end of the third XOR unit that has completed the corresponding relationship determination, and so on.

[0110] The number of scan chains is the same as the number of XOR units. By sequentially connecting the scan chains to the XOR units in the phase shifter in this manner, the correlation of the test vectors input into adjacent scan chains can be reduced.

[0111] Therefore, the phase shifter construction method provided by the embodiment of the present disclosure can quickly construct the XOR unit in the test stimulus generation circuit into a phase shifter, while improving the randomness of the output data of each port of the phase shifter, thereby improving the fault coverage of the test circuit.

[0112] For example, based on the method provided in the embodiment of the present disclosure, the following can be constructed: Figure 5 The phase shifter shown. Figure 5 In the figure, the solid circle indicates that the signal line has cross connection. The register group refers to grouping all the register units of the linear shift register into a fixed number, and each register unit associated with the single-channel scan chain input of the phase shifter comes from a different register group.

[0113] For example, for the register unit corresponding to scan chain 1, the register units at its input end come from three different groups: register group 1, register group g-1, and register group g. For the register unit corresponding to scan chain t, the register units at its input end come from three different groups: register group 2, register group g-1, and register group g. In this way, the simulation and search configuration time of the register unit in the phase shifter construction process can be greatly reduced, while the randomness of the output data of each port of the phase shifter is improved, and the fault coverage of the test is improved.

[0114] Next, we will combine Figures 6 to 8 , a method for constructing a virtual LFSR in an embodiment of the present disclosure is described in detail.

[0115] First, please refer to Figure 6 , Figure 6 A schematic diagram of a virtual LFSR construction method in an embodiment of the present disclosure is shown, Figure 6 As shown, the method includes the following steps.

[0116] S610: Determine the number of register units and the number of register groups in the virtual LFSR according to the number of objects to be driven.

[0117] The object to be driven includes: a scan chain and / or a first-stage input port in a circuit to be tested, and the circuit to be tested is a circuit used for testing by a test stimulus generating circuit.

[0118] For example, when the phase shifter in the actual LFSR is used to drive the scan chain, the scan chain can be used as the object to be driven. When the phase shifter in the actual LFSR is used for both the scan chain and the primary input port (PI), the scan chain and the primary input port can be used as the objects to be driven at the same time.

[0119] It is understandable that the more register units there are in the LFSR, the more combinations there are for selecting a fixed number of register units to drive the object to be driven. However, the increase in the number of register units will increase the area overhead of the test circuit and reduce the operating efficiency of the LFSR. Therefore, the number of register units in the LFSR can be determined according to the number of objects to be driven, so as to achieve a relative balance between the above-mentioned influences and make the number of register units relatively reasonable.

[0120] At the same time, since the number of register groups in the LFSR is also closely related to the number of register units, a similar method can also be adopted to determine the number of register groups in the LFSR based on the number of objects to be driven.

[0121] S620: Divide the register units in the virtual LFSR into a plurality of register groups according to the number of register units and the number of register groups in the virtual LFSR.

[0122] For example, the number of register units in each register group is Where n is the total number of register units in the virtual LFSR, g is the total number of register groups in the virtual LFSR, Indicates that the result of division is rounded up.

[0123] After sz is calculated, the register units connected in series can be grouped in order according to the numbers of the register units in the virtual LFSR, wherein the numbers of the register units are consistent with the series order of the register units.

[0124] For example, register units numbered 1 to sz may be divided into register group 1, and register units numbered sz+1 to sz×2 may be divided into register group 2. This process is repeated until the number of remaining register units is less than or equal to sz, and all remaining register units are divided into the last register group.

[0125] S630, selecting a target primitive polynomial from a primitive polynomial library based on the number and grouping of register units.

[0126] It should be noted that primitive polynomials refer to polynomials with certain special properties in finite fields. Specifically, in the finite field GF(2) (i.e., binary field), primitive polynomials refer to irreducible polynomials, and the minimal polynomial of its roots is the generator of the field. Primitive polynomials can be used as characteristic polynomials of LFSR, so that LFSR generates a length of 2 n -1 pseudo-random sequence, where n is the number of register units in the LFSR, that is, the order of the LFSR.

[0127] For example, the corresponding relationship between the primitive polynomial and the LFSR can be referred to Figure 7 , Figure 7 It is shown by way of example that the primitive polynomial is h(x)=x 5 +x 2 +1 (5th order primitive polynomial), the corresponding structure diagram of type I LFSR and type II LFSR. It can generate a length of 31 (2 5 -1) pseudo-random sequence.

[0128] It can be understood that the primitive polynomial determines the position of the feedback register unit in the LFSR. The embodiment of the present disclosure expects that each register group has as many feedback register units as possible to enhance the hopping frequency of the register unit data in each group.

[0129] Exemplarily, the disclosed embodiment can generate and construct a primitive polynomial library of different orders in advance through the M-sequence sampling method. After determining the order of the LFSR, the candidate primitive polynomial that meets the LFSR order requirement can be first searched in the primitive polynomial library. Then, on this basis, the primitive polynomial that makes the number of polynomial coefficients corresponding to each register group "1" as much as possible is used as the target primitive polynomial.

[0130] S640: Construct a virtual LFSR that is dual to the actual LFSR based on the target primitive polynomial.

[0131] As mentioned above, LFSR can be divided into two types: Type I LFSR and Type II LFSR, and Type I LFSR and Type II LFSR are dual to each other.

[0132] If the test stimulus generation circuit used in actual application includes a type I LFSR, the virtual LFSR used for simulation when constructing the phase shifter is a type II LFSR. If the test stimulus generation circuit used in actual application includes a type II LFSR, the virtual LFSR used for simulation when constructing the phase shifter is a type I LFSR.

[0133] Regardless of whether the virtual LFSR is a type I LFSR or a type II LFSR, it can be constructed by selecting a target primitive polynomial. The difference lies in whether, when constructing the LFSR, the XOR operation of the feedback unit is performed on the shift path (corresponding to the type II LFSR) or outside the shift path (corresponding to the type I LFSR).

[0134] Next, we will combine Figure 8 , a method for selecting the primitive polynomial in the embodiment of the present disclosure is described in detail. Figure 8 A method for selecting a primitive polynomial in an embodiment of the present disclosure is shown, such as Figure 8 As shown, the method includes the following steps.

[0135] S810, selecting any candidate primitive polynomial in the primitive polynomial library, where the order of the candidate primitive polynomial is n, and n is the number of register units in the virtual LFSR.

[0136] S820: If the candidate primitive polynomial meets the preferred condition, the candidate primitive polynomial is used as the target primitive polynomial.

[0137] The preferred condition is that for each register group in the virtual LFSR, there are multiple items with coefficients of 1 corresponding to each register group in the candidate primitive polynomial.

[0138] In some embodiments, if all candidate primitive polynomials in the primitive polynomial library do not meet the preferred condition, the candidate primitive polynomial in the primitive polynomial library that meets the alternative condition and has the most items with coefficients of 1 is used as the target primitive polynomial;

[0139] The alternative condition is that for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 corresponding to it in the candidate primitive polynomial.

[0140] That is to say, after determining the order of the virtual LFSR, the preferred target primitive polynomial can make the number of items with primitive polynomial coefficients of 1 corresponding to each register group (register units within the group) not less than two.

[0141] The candidate target primitive polynomial can ensure that the number of items with coefficients of 1 corresponding to the primitive polynomials of each register group is not less than one, and among the candidate primitive polynomials, the total number of items with coefficients of 1 of the target primitive polynomial is the largest.

[0142] Next, we will combine Figures 9 to 12 , describing the method for determining the number of register units and the number of register groups in the embodiment of the present disclosure.

[0143] As mentioned above, the order of LFSR refers to the number of LFSR register units. The more the total number of register units, the more combinations there are for selecting a fixed number of register units to drive the object to be driven. However, the higher the order of LFSR, the greater its area overhead and the longer the simulation run time.

[0144] In some embodiments, in order to balance the effect of the number of register units on the LFSR, the combination number can be calculated. The total number of different combinations of inputs to the phase shifter XOR gate is obtained, and the number of combinations combined with the order-limited proportional factor α is used to determine whether the currently selected LFSR order is appropriate. Among them, n is the currently selected LFSR order; m is the upper limit value of the preset number range in S323, which can also be understood as the maximum number of input ports of the pre-configured XOR unit; the order-limited proportional factor α is used to balance the impact of the number of register units on the LFSR.

[0145] For example, Fig. 9 A method for determining the number of register units in an embodiment of the present disclosure is shown. Fig. 9 As shown, the method includes the following steps.

[0146] S910, calculating the first number of combinations of m different register units selected from n register units.

[0147] Wherein, m is the upper limit of the preset quantity range, and n and m are both positive integers.

[0148] S920: Use the minimum value of n when the first combination number is greater than or equal to the first combination number threshold as the number of register units in the virtual LFSR.

[0149] The first combination number threshold is the product of the order-limited proportional factor α and the number of objects to be driven, α≥5.

[0150] For example, please refer to Fig.10 , Fig.10 The specific process of determining the number of register units in an actual application process is shown by way of example. Fig.10 In order to improve the running speed of the algorithm, the order n of the LFSR is given an initial value of a certain size.

[0151] Specifically, Fig.10 The following steps are shown:

[0152] Step 1: Initialize the order n of the LFSR to 10, and set the order-limited proportional factor α to 8 (in this example, n and α are empirical values).

[0153] Step 2: Calculate the number of first combinations

[0154] Step 3: If the first combination number fi≥α×(t+p), the order of the LFSR is the value of n at this time. Otherwise, set n=n+1.

[0155] Among them, t is the number of scan chains in the circuit to be tested, and p is the number of first-level input ports in the circuit to be tested. That is, in this example, the scan chains and the first-level input ports are used together as the objects to be driven of the test stimulus generation circuit, and t+p is used to represent the number of objects to be driven in the circuit to be tested.

[0156] Step 4: Repeat step 3 above until the order n of the LFSR that meets the conditions is obtained.

[0157] In some embodiments, Fig.11 A method for determining the number of register groups in an embodiment of the present disclosure is shown. In an embodiment of the present disclosure, the core idea of ​​the present disclosure is to group the register units in the virtual LFSR and select a register unit in each group to drive the scan chain.

[0158] Thus, the number of combinations can be calculated The total number of different possible configurations of LFSR register groups is obtained, and the number of combinations is used to determine whether the currently selected number of LFSR groups is appropriate. Since different register units can be selected in the same group to drive the XOR unit, a group number limited proportional factor β is also set in the judgment process to increase the rationality of the judgment and avoid too many register unit groups.

[0159] For details, please refer to Fig.11 , the method comprises the following steps.

[0160] S1111, calculate the second number of combinations of m different register groups selected from g register groups.

[0161] Wherein, m is the upper limit of the preset quantity range, and g and m are both positive integers.

[0162] S1120, when the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is used as the number of register groups in the virtual LFSR.

[0163] The second combination number threshold is the product of the group number limiting proportional factor β and the number of objects to be driven, 0<β≤1.

[0164] For example, please refer to Fig.12 , Fig.12 The specific process of determining the number of register groups in actual application is exemplified.

[0165] Specifically, Fig.12 The following steps are shown:

[0166] Step 1: Initialize the number of groups g=m of the LFSR (m is the upper limit of the preset number range in S323, which can also be understood as the maximum number of input ports of the pre-configured XOR unit), and set the group number limited proportional factor β=0.1 (in this example, β is an empirical value).

[0167] Step 2: Calculate the second combination number

[0168] Step 3: If the second combination number fo≥β×(t+p), the number of groups of the LFSR is the current value of g. Otherwise, g=g+1, and the second combination number fo is recalculated.

[0169] Step 4: Repeat step 3 above until the number of LFSR groups g that meets the conditions is obtained.

[0170] Based on the same inventive concept, the present disclosure also provides a phase shifter construction device, such as the following embodiment. Figure 3 The method embodiment shown is similar to that shown in FIG. 1 , so the implementation of the phase shifter construction device embodiment can refer to the above Figure 3 The implementation of the illustrated method embodiment will not be described in detail in detail.

[0171] Fig.13 A schematic diagram of the structure of a phase shifter construction device in an embodiment of the present disclosure is shown. The device is used to construct a phase shifter in a test stimulus generation circuit, and the test stimulus generation circuit includes an actual LFSR and multiple XOR units.

[0172] Specifically, Fig.13 As shown, the phase shifter construction device 1300 includes:

[0173] The construction module 1310 is used to construct a virtual LFSR that is dual to the actual LFSR. The virtual LFSR includes a plurality of register units connected in sequence. The plurality of register units are divided into a plurality of register groups. The register units in each register group are connected in series in sequence.

[0174] The execution module 1320 is used to repeatedly execute the following steps until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generation circuit as a phase shifter:

[0175] Control the virtual LFSR to run continuously for a preset number of clock cycles;

[0176] Obtain the number of target register groups in the virtual LFSR; wherein the target register group is a register group having a register unit having a unique unit value of 1;

[0177] When the number of target register groups in the virtual LFSR is within a preset number range, any XOR unit that has not established a corresponding relationship with a register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group.

[0178] In some embodiments, the construction module 1310 is specifically used to determine the number of register units and the number of register groups in the virtual LFSR according to the number of objects to be driven; wherein the objects to be driven include: scan chains and / or first-stage input ports in the circuit to be tested, and the circuit to be tested is a circuit used for testing by the test stimulus generation circuit;

[0179] According to the number of register units and the number of register groups in the virtual LFSR, the register units in the virtual LFSR are divided into a plurality of register groups;

[0180] Based on the number and grouping of register units, a target primitive polynomial is selected from a primitive polynomial library;

[0181] Based on the target primitive polynomial, a virtual LFSR that is dual to the actual LFSR is constructed.

[0182] In some embodiments, the construction module 1310 is specifically used to calculate the first number of combinations of m different register units selected from n register units, where m is an upper limit value of a preset number range, and n and m are both positive integers;

[0183] The minimum value of n when the first combination number is greater than or equal to the first combination number threshold is used as the number of register units in the virtual LFSR;

[0184] The first combination number threshold is the product of the order-limited proportional factor α and the number of objects to be driven, α≥5.

[0185] In some embodiments, the construction module 1310 is specifically used to calculate the number of second combinations of m different register groups selected from g register groups, where m is an upper limit value of a preset number range, and g and m are both positive integers;

[0186] When the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is used as the number of register groups in the virtual LFSR;

[0187] The second combination number threshold is the product of the group number limiting proportional factor β and the number of objects to be driven, 0<β≤1.

[0188] In some embodiments, the construction module 1310 is specifically used to select any candidate primitive polynomial in the primitive polynomial library, where the order of the candidate primitive polynomial is n, and n is the number of register units in the virtual LFSR;

[0189] If the candidate primitive polynomial meets the preferred condition, the candidate primitive polynomial is used as the target primitive polynomial;

[0190] The preferred condition is that for each register group in the virtual LFSR, there are multiple items with coefficients of 1 corresponding to each register group in the candidate primitive polynomial.

[0191] In some embodiments, the construction module 1310 is specifically used to, if all candidate primitive polynomials in the primitive polynomial library do not meet the preferred condition, then use the candidate primitive polynomial in the primitive polynomial library that meets the alternative condition and has the most items with coefficients of 1 as the target primitive polynomial;

[0192] The alternative condition is that for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 corresponding to it in the candidate primitive polynomial.

[0193] In some embodiments, the preset number range is the number range of input ports of each XOR unit, and the construction module 1310 is specifically used to determine the number range of input ports according to the number of scan chains in the circuit to be tested;

[0194] The circuit to be tested is a circuit that is tested by the test stimulus generating circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

[0195] Refer to the following Fig.14 1400 capable of implementing the embodiments of the present disclosure is described. Fig.14 The electronic device 1400 shown is merely an example and should not bring any limitation to the functions and scope of application of the embodiments of the present disclosure.

[0196] like Fig.14 As shown, the electronic device 1400 is in the form of a general computing device. The components of the electronic device 1400 may include, but are not limited to: at least one processor 1410, at least one memory 1420, and a bus 1430 connecting different system components (including the memory 1420 and the processor 1410).

[0197] The memory stores program codes, which can be executed by the processor 1410, so that the processor 1410 executes the steps according to various exemplary embodiments of the present disclosure described in the above “Exemplary Method” section of the present disclosure.

[0198] In some embodiments, the processor 1410 may further perform the following steps of the above method embodiment:

[0199] A virtual LFSR dual to the actual LFSR is constructed, the virtual LFSR comprising a plurality of register units connected in sequence; the plurality of register units are divided into a plurality of register groups, and the register units in each register group are connected in series in sequence;

[0200] Repeat the following steps until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generating circuit as a phase shifter:

[0201] Control the virtual LFSR to run continuously for a preset number of clock cycles;

[0202] Obtain the number of target register groups in the virtual LFSR; wherein the target register group is a register group having a register unit having a unique unit value of 1;

[0203] When the number of target register groups in the virtual LFSR is within a preset number range, any XOR unit that has not established a corresponding relationship with a register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group.

[0204] The memory 1420 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 14201 and / or a cache memory 14202 , and may further include a read-only memory (ROM) 14203 .

[0205] Memory 1420 may also include a program / utility 14204 having a set (at least one) of program modules 14205, such program modules 14205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0206] The bus 1430 may be a bus representing one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures.

[0207] The electronic device 1400 may also communicate with one or more external devices 1440 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), one or more devices that enable a user to interact with the electronic device 1400, and / or any device that enables the electronic device 1400 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed through an input / output (I / O) interface 1450. Furthermore, the electronic device 1400 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 1460. Fig.14 As shown, the network adapter 1460 communicates with other modules of the electronic device 1400 via the bus 1430. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 1400, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0208] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0209] In an exemplary embodiment of the present disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. A program product capable of implementing the above-mentioned method of the present disclosure is stored thereon. In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to cause the terminal device to execute the steps according to various exemplary implementations of the present disclosure described in the above-mentioned "Exemplary Method" section of the present disclosure.

[0210] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for constructing a phase shifter, characterized in that: The method is used to construct a phase shifter in a test stimulus generation circuit, wherein the test stimulus generation circuit includes an actual LFSR and a plurality of XOR units; The method comprises: Constructing a virtual LFSR that is dual to the actual LFSR, wherein the virtual LFSR comprises a plurality of register units connected in sequence; the plurality of register units are divided into a plurality of register groups, and the register units in each register group are connected in series in sequence; Repeat the following steps until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generating circuit as a phase shifter: Controlling the virtual LFSR to continuously run a preset number of clock cycles; Obtaining the number of target register groups in the virtual LFSR; wherein the target register group is a register group having a register unit having a unique unit value of 1; When the number of target register groups in the virtual LFSR is within a preset number range, any XOR unit that has not established a corresponding relationship with a register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group.

2. The method according to claim 1, characterized in that The constructing of a virtual LFSR dual to the actual LFSR comprises: Determine the number of register units and the number of register groups in the virtual LFSR according to the number of objects to be driven; wherein the objects to be driven include: a scan chain and / or a first-stage input port in a circuit to be tested, and the circuit to be tested is a circuit used for testing by the test stimulus generating circuit; Dividing the register units in the virtual LFSR into a plurality of register groups according to the number of register units and the number of register groups in the virtual LFSR; Based on the number and grouping of register units, a target primitive polynomial is selected from a primitive polynomial library; Based on the target primitive polynomial, a virtual LFSR that is dual to the actual LFSR is constructed.

3. The method according to claim 2, characterized in that The number of register units in the virtual LFSR is calculated as follows: Calculating the number of first combinations of m different register units selected from the n register units, wherein m is an upper limit value of the preset number range, and n and m are both positive integers; Using the minimum value of n when the first combination number is greater than or equal to the first combination number threshold as the number of register units in the virtual LFSR; The first combination number threshold is the product of the order-limited proportional factor α and the number of the objects to be driven, and α≥5.

4. The method according to claim 2, characterized in that: The number of register groups in the virtual LFSR is calculated as follows: Calculate the number of second combinations of m different register groups selected from the g register groups, where m is an upper limit value of the preset number range, and g and m are both positive integers; When the second combination number is greater than or equal to the second combination number threshold, the minimum value of g is used as the number of register groups in the virtual LFSR; The second combination number threshold is the product of the group number limiting proportional factor β and the number of the objects to be driven, 0<β≤1.

5. The method according to claim 2, characterized in that: The step of selecting a target primitive polynomial from a primitive polynomial library based on the number and grouping of register units includes: Select any candidate primitive polynomial in the primitive polynomial library, where the order of the candidate primitive polynomial is n, and n is the number of register units in the virtual LFSR; If the candidate primitive polynomial meets the preferred condition, the candidate primitive polynomial is used as the target primitive polynomial; The preferred condition is that for each register group in the virtual LFSR, there are multiple items with coefficients of 1 corresponding to each register group in the candidate primitive polynomial.

6. The method according to claim 5, characterized in that The method further comprises: If all candidate primitive polynomials in the primitive polynomial library do not meet the preferred condition, the candidate primitive polynomial in the primitive polynomial library with the most items that meet the alternative condition and have a coefficient of 1 is used as the target primitive polynomial; The candidate condition is as follows: for each register group in the virtual LFSR, there is at least one term with a coefficient of 1 corresponding to each register group in the candidate primitive polynomial.

7. The method according to any one of claims 1 to 4, characterized in that The preset number range is the number range of input ports of each XOR unit, and the method further includes: Determining the range of the number of input ports according to the number of scan chains in the circuit to be tested; The circuit to be tested is a circuit that is tested by the test stimulus generating circuit, and a mapping relationship is pre-established between the number of scan chains and the range of the number of input ports.

8. A phase shifter construction device, characterized in that: The device is used to construct a phase shifter in a test stimulus generation circuit, the test stimulus generation circuit comprising an actual LFSR and a plurality of XOR units; The device comprises: A construction module, used to construct a virtual LFSR dual to the actual LFSR, wherein the virtual LFSR comprises a plurality of register units connected in sequence; the plurality of register units are divided into a plurality of register groups, and the register units in each register group are connected in series in sequence; An execution module is used to repeatedly execute the following steps until a corresponding relationship between each XOR unit and a register unit is obtained, so as to construct the XOR unit in the test stimulus generating circuit as a phase shifter: Controlling the virtual LFSR to continuously run a preset number of clock cycles; Obtaining the number of target register groups in the virtual LFSR; wherein the target register group is a register group having a register unit having a unique unit value of 1; When the number of target register groups in the virtual LFSR is within a preset number range, any XOR unit that has not established a corresponding relationship with a register unit is selected, and a corresponding relationship is established between the XOR unit and the register unit with a unit value of 1 in each target register group.

9. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to perform the method of any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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