Virtual-real address conversion system, virtual-real address conversion method and virtual-real address conversion unit
By introducing first-level bypass cache and second-level bypass cache in the virtual and real address translation system, the problem of large page table entries being replaced by small page table entries in TLB is solved, and the performance and hit rate of virtual and real address translation are improved.
Patent Information
- Application Number
- CN202411954640.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-22
AI Technical Summary
In the existing virtual and real address conversion technology, TLB is prone to the problem that large page table entries are replaced by small page table entries, resulting in large page bumps, increasing the number of memory accesses, and reducing performance.
A virtual and real address translation system is adopted, including first-level bypass cache and second-level bypass cache. The first-level bypass cache stores page groups with different page granularity, and the second-level bypass cache stores leaf table entries. Discrete storage with primary bypass cache reduces large page bumps and increases hit rate with secondary bypass cache.
It significantly improves the hit rate of virtual and real address conversion, reduces large page bumps, and improves the performance of the overall system.
Smart Images
Figure CN119862135A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a virtual-to-real address conversion system, method and virtual-to-real address conversion unit. Background Art
[0002] With the development of computer technology, software programs are getting larger and larger, which makes it impossible for physical memory to store the entire software program at one time. The program code can be put into physical memory for execution in a segmented manner, but this process is time-consuming and labor-intensive. Therefore, the virtual-to-real address conversion technology was born.
[0003] At present, the general solution of virtual-to-real address translation technology is to use a lookaside buffer (TLB) to cache recently used page table entries to increase the speed of address translation. When a virtual-to-real address translation is required, the TLB is first searched to determine whether it can hit. If it hits, the physical address is directly output. Otherwise, the page table walk (PTW) mechanism is used to obtain the corresponding mapping relationship by accessing the main memory multiple times, and then updated to the TLB. Based on the virtual address, the TLB is searched again to obtain the corresponding physical address.
[0004] However, since the TLB includes both large page table entries and small page table entries, the TLB in the above-mentioned general virtual-to-real address conversion scheme is prone to the problem that the newly updated large page table entries are replaced by small page table entries, causing large page thrashing, increasing the number of memory accesses, and reducing the performance of virtual-to-real address conversion. For the many-core architecture that requires multiple virtual-to-real address translation units (ATUs) to carry out different types of data transfer scenarios, the TLB hit rate is further reduced, which has a greater impact on the performance of the entire system. Summary of the invention
[0005] The present invention provides a virtual-to-real address conversion system, method and virtual-to-real address conversion unit, which can solve the problems of large page thrashing, low performance of virtual-to-real address conversion and low hit rate.
[0006] According to one aspect of the present invention, there is provided a virtual-to-real address translation system, comprising: at least one virtual-to-real address translation unit and a secondary bypass cache in communication connection;
[0007] The virtual-to-real address conversion unit includes a first-level bypass cache, and the first-level bypass cache is used to store at least one page group of page granularity, and the page group includes leaf table entries, wherein the leaf table entries in page groups of different page granularities represent different physical memory spaces;
[0008] The secondary bypass cache is used to store leaf table entries;
[0009] The virtual-to-real address conversion unit is used to search the first-level bypass cache according to the virtual address; if the target leaf table entry is not found in the first-level bypass cache, the leaf table entry in the second-level bypass cache is searched based on the virtual address, and the target leaf table entry represents the leaf table entry corresponding to the virtual address; if the target leaf table entry is found in the second-level bypass cache, the target leaf table entry is updated to the page group corresponding to the first-level bypass cache; if the target leaf table entry is found in the first-level bypass cache, the physical address is returned according to the target leaf table entry.
[0010] According to another aspect of the present invention, there is provided a virtual-to-real address translation method, comprising: at least one virtual-to-real address translation unit and a secondary bypass cache in communication connection;
[0011] The virtual-to-real address conversion unit includes a first-level bypass cache, and the first-level bypass cache is used to store at least one page group of page granularity, and the page group includes leaf table entries, wherein the leaf table entries in page groups of different page granularities represent different physical memory spaces;
[0012] The secondary bypass cache is used to store leaf table entries;
[0013] The virtual-to-real address conversion unit searches the first-level bypass cache according to the virtual address;
[0014] In the case that the target leaf table entry is not found in the first-level bypass cache, the virtual-to-real address conversion unit searches for the leaf table entry in the second-level bypass cache based on the virtual address, wherein the target leaf table entry represents the leaf table entry corresponding to the virtual address;
[0015] If the target leaf table entry is found in the secondary bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry into the page group corresponding to the primary bypass cache;
[0016] If the target leaf table entry is found in the first-level bypass cache, the virtual-to-real address conversion unit returns a physical address according to the target leaf table entry.
[0017] According to another aspect of the present invention, a virtual-to-real address conversion unit is provided, and the virtual-to-real address conversion unit is used to implement the virtual-to-real address conversion method as described in any embodiment of the present invention.
[0018] The technical solution of the embodiment of the present invention comprises at least one virtual-to-real address conversion unit and a secondary bypass cache that are communicatively connected. The virtual-to-real address conversion unit comprises a primary bypass cache, in which page groups of different page granularities are stored, and the page groups comprise leaf table entries. The primary bypass cache adopts discrete storage to reduce the problem of large page thrashing. The leaf table entries are stored through the secondary bypass cache, and at least one virtual-to-real address conversion unit shares the same secondary bypass cache. The virtual-to-real address conversion unit searches the primary bypass cache according to the virtual address. If the target leaf table entry is not found in the primary bypass cache, the leaf table entry in the secondary bypass cache is searched based on the virtual address. If the target leaf table entry is found in the secondary bypass cache, the target leaf table entry is updated to the page group of the corresponding page granularity in the primary bypass cache. If the target leaf table entry is found in the primary bypass cache, the physical address is returned according to the target leaf table entry. The technical solution of the embodiment of the present invention can cache more leaf table entries by having all virtual-to-real address conversion units share a large-capacity secondary bypass cache, significantly improving the hit rate of virtual-to-real address conversion and improving virtual-to-real address conversion performance.
[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0021] Figure 1 A virtual-to-real address conversion system is provided for an embodiment of the present invention;
[0022] Figure 2 A schematic diagram of the structure of a virtual-to-real address conversion unit provided by an embodiment of the present invention;
[0023] Figure 3 A flowchart of a continuous writing method for a secondary bypass cache in a virtual-to-real address conversion system provided by an embodiment of the present invention;
[0024] Figure 4 A flowchart of a virtual-to-real address conversion method is provided for an embodiment of the present invention;
[0025] Figure 5 A schematic diagram of a specific process of virtual-to-real address conversion provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0028] To facilitate understanding, technical terms that may appear in the embodiments of the present invention are explained below.
[0029] Virtual-to-real address conversion technology can not only reduce the demand for physical storage capacity, but also make it easier to protect and share programs. From the initial single-level page table that requires a continuous physical space to store the entire page table, that is, the virtual-to-real address mapping relationship, to the multi-level page table that does not require continuous physical space, the page table storage is more flexible, and it is no longer necessary to store the entire page table, greatly reducing the physical memory usage. Then, the introduction of the bypass cache TLB can reduce the problem of multiple memory accesses for multi-level page tables and improve the performance of virtual-to-real address conversion. Large page technology can reduce the number of page table entries, thereby improving the hit rate of TLB. This is particularly prominent in applications that require a large amount of memory. Virtual-to-real address conversion technology is the foundation of modern operating systems and computer architectures, and its effectiveness directly affects system performance and resource utilization.
[0030] Figure 1 A virtual-to-real address conversion system is provided for an embodiment of the present invention. The disclosed embodiment is applicable to the case of a multi-core chip architecture, and is particularly applicable to a scenario of implementing virtual-to-real address conversion of a peripheral device accessing a main memory based on a multi-core chip architecture.
[0031] The system includes: at least one virtual-to-real address translation unit 110 and a second-level bypass buffer (Second Translation Lookaside Buffer, STLB) 120 that are communicatively connected. The virtual-to-real address translation unit 110 includes a first-level bypass buffer (First Translation Lookaside Buffer, FTLB) 130 .
[0032] The virtual-to-real address conversion unit 110 includes a first-level bypass cache 130, and the first-level bypass cache 130 is used to store at least one page group of page granularity, and the page group includes leaf table entries, wherein the leaf table entries in page groups of different page granularities represent different physical memory spaces. The second-level bypass cache 120 is used to store leaf table entries. The virtual-to-real address conversion unit is used to search the first-level bypass cache according to the virtual address; if the target leaf table entry is not found in the first-level bypass cache, search the leaf table entry in the second-level bypass cache based on the virtual address, and the target leaf table entry represents the leaf table entry corresponding to the virtual address; if the target leaf table entry is found in the second-level bypass cache, update the target leaf table entry to the page group corresponding to the first-level bypass cache; if the target leaf table entry is found in the first-level bypass cache, return the physical address according to the target leaf table entry.
[0033] Among them, the virtual-to-real address conversion unit is a hardware device for implementing virtual-to-real address conversion in a computer. The virtual-to-real address conversion unit includes a first-level bypass cache, a page table walker cache (Page Table Walker Cache, PTW_Cache) and a page table walker module (Page Table Walker, PTW). The page group is used to characterize the storage block storing the leaf table entries of the corresponding page granularity in the first-level bypass cache. The first-level bypass cache is divided into page groups of multiple page granularities according to the page size, and page groups of different page granularities correspond to pages of different page sizes. Pages of different page sizes occupy different physical content spaces. For example, the first-level bypass cache includes 512G page groups, 1G page groups, and 2M page groups. By using discrete storage for different page sizes, the problem of large page jitter is reduced.
[0034] Figure 2 A schematic diagram of the structure of a virtual-to-real address conversion unit provided by an embodiment of the present invention. Figure 2 As shown, the virtual-to-real address conversion unit 210 includes a level-one bypass cache 220 , a page table traversal cache 230 , a page table traversal module 240 , etc. The level-one bypass cache 220 includes a 512G page group 250 , a 1G page group 260 , and a 2M page group 270 .
[0035] In an embodiment of the present invention, a first-level bypass cache is located inside each virtual-to-real address conversion unit. The page group in the first-level bypass cache stores the address mapping information of the most recent successful replacement. The address mapping information represents the mapping relationship between the virtual address and the physical address. For example, the first-level bypass cache includes a 512G page group, a 1G page group, and a 2M page group. When the 512G page group is used for cross-chip access, the physical address can be quickly obtained through large page replacement. The 1G page group is used for the system to carry large data blocks. The 2M page group is used to meet the system's needs for carrying normal data.
[0036] Optionally, the implementation method of the page group of at least one page granularity is associated with the number of leaf table entries of the page group, wherein the implementation method includes fully associative mapping and direct mapping; the leaf table entries in the secondary bypass cache are implemented using a group associative mapping method.
[0037] Since the number of leaf table entries of 512G page granularity and 1G page granularity is far less than the number of leaf table entries of 2M page granularity, 512G page groups and 1G page groups are implemented using direct mapping, and 2M page groups are implemented using fully associative mapping. Optionally, the pseudo least recently used (PLRU) replacement algorithm and the first 0 algorithm are used to update the 2M page group, which can further reduce the thrashing of the 2M page group.
[0038] The page table traversal cache is mainly used to cache non-leaf table entries in the process of page table traversal, which can effectively reduce the number of memory accesses. Among them, the leaf table entry represents the page table entry that directly points to the actual physical memory page. That is, the leaf table entry contains the mapping information from the virtual address to the physical address. The non-leaf table entry represents the page table entry pointing to the next level page table. That is, the non-leaf table entry contains the physical address pointing to the next level page table.
[0039] For virtual-to-real address conversion requests that miss both the first-level bypass cache and the second-level bypass cache, the page table traversal module performs at least one page table traversal to obtain the corresponding leaf table entry and cache it in the first-level bypass cache.
[0040] The secondary bypass cache stores leaf table entries with a 2M page granularity. Optionally, the secondary bypass cache can be implemented using a set-associative mapping method, which can effectively reduce address jitter. For example, a two-way set-associative mapping method can be used to implement the secondary bypass cache, so that two storage locations share an index. When it is necessary to store a leaf table entry in the storage location corresponding to the index, the leaf table entry can be stored in an idle storage location or a location corresponding to an earlier leaf table entry, avoiding jitter caused by replacing the newly updated leaf table entry.
[0041] Optionally, dividing the storage body into multiple blocks can effectively reduce multi-way request access conflicts.
[0042] In an embodiment of the present invention, the secondary bypass cache includes a mapping relationship between a virtual address and a physical address written into the secondary bypass cache during the software pre-filling process. Multiple leaf table entries can be written continuously at one time during the pre-filling of leaf table entries. The continuous writing method can effectively shorten the configuration time of the software pre-filling process. Among them, the leaf table entry represents the mapping relationship between the virtual address and the physical address.
[0043] In some embodiments, the secondary bypass cache includes at least two memory banks, a continuous write status register, a continuous write address register, and a continuous write count register;
[0044] Wherein, the continuous writing mode includes:
[0045] During the software pre-filling process, the processor determines the continuous write base address and the number of continuous writes according to the configuration information, and updates the continuous write address register and the continuous write number register according to the continuous write base address and the continuous write number; generates a write request according to the virtual address and the physical address in the base address, and updates one of the at least two storage bodies according to the write request; controls the number of continuous writes in the continuous write number register to be reduced by 1; if the number of continuous writes is not zero, updates the virtual address and the physical address to obtain a new write request; if the number of continuous writes is zero, updates the status flag of the continuous write status register, and the status flag is used to indicate whether the continuous write operation is completed.
[0046] The computer's processor runs the software to pre-fill the secondary bypass cache. Continuous writing can solve the problem of multiple configurations of the software and improve software execution efficiency. Figure 3 A flowchart of a continuous writing method of a secondary bypass cache in a virtual-to-real address conversion system provided by an embodiment of the present invention. Figure 3As shown, the method includes: reading the status identifier of the continuous write status register. If the status identifier indicates that the last continuous write operation is not completed, the current continuous write request is blocked. If the status identifier indicates that the last continuous write operation is completed, the continuous write address register and the continuous write count register are updated according to the continuous write base address and the continuous write count in the current continuous write request. In addition, the continuous write status register is also pulled down (the status identifier is a low level), indicating that the current continuous write request is started. The address in the continuous write address register is sent to the storage body corresponding to the secondary bypass cache for writing. The corresponding storage body can be determined by a pseudo least recently used algorithm, etc. After the address is sent, it is determined whether the count of the continuous write count register is 0. If it is 0, the status identifier of the continuous write status register is updated (for example, the status identifier is a high level). If it is not 0, the virtual page number and the physical page number in the continuous write address register are each added by 1 as a new request, stored in the continuous write register, and the count of the corresponding continuous write count register is reduced by 1, and the execution is returned to send the address in the continuous write address register to the storage body corresponding to the secondary bypass cache for writing, until the count of the continuous write count register becomes 0.
[0047] The technical solution of the embodiment of the present invention comprises at least one virtual-to-real address conversion unit and a secondary bypass cache which are communicatively connected. The virtual-to-real address conversion unit comprises a primary bypass cache, in which page groups of different page granularities are stored, and the page groups comprise leaf entries, and the problem of large page thrashing is reduced by using discrete storage through the primary bypass cache. The leaf entries are stored through the secondary bypass cache, and at least one virtual-to-real address conversion unit shares the same secondary bypass cache. The virtual-to-real address conversion unit searches the primary bypass cache according to the virtual address. In the case where the target leaf entry is not found in the primary bypass cache, the leaf entry in the secondary bypass cache is searched based on the virtual address. If the target leaf entry is found in the secondary bypass cache, the target leaf entry is updated to the page group of the corresponding page granularity in the primary bypass cache. If the target leaf entry is found in the primary bypass cache, the physical address is returned according to the target leaf entry. By all virtual-to-real address conversion units sharing a large-capacity secondary bypass cache, more leaf entries can be cached, the hit rate of virtual-to-real address conversion is significantly improved, and the performance of virtual-to-real address conversion is improved.
[0048] Figure 4A flowchart of a virtual-to-real address conversion method is provided for an embodiment of the present invention, and this embodiment can be executed by the virtual-to-real address conversion system in the above embodiment. The virtual-to-real address conversion system includes at least one virtual-to-real address conversion unit and a secondary bypass cache that are communicatively connected. The virtual-to-real address conversion unit includes a primary bypass cache, and the primary bypass cache is used to store a page group of at least one page granularity, and the page group includes leaf table entries, wherein the leaf table entries in page groups of different page granularities represent different physical memory spaces. The secondary bypass cache is used to store leaf table entries.
[0049] like Figure 4 As shown, the method includes:
[0050] S410. The virtual-to-real address conversion unit searches the first-level bypass cache according to the virtual address.
[0051] The virtual address is the address information carried in the access request of the peripheral device. After obtaining the virtual address, the virtual-to-real address conversion unit first searches the first-level bypass cache based on the virtual address.
[0052] Exemplarily, the virtual-to-real address conversion unit searches the first-level bypass cache according to the virtual address, including:
[0053] The virtual address conversion unit obtains a virtual address sent by a target peripheral device, wherein the target peripheral device has a direct memory access capability and supports a virtual address function.
[0054] For a page group implemented by direct mapping, the virtual-to-real address conversion unit matches the index bit in the virtual address with the index information in the first-level bypass cache. If a candidate leaf table entry is matched, the identifier in the virtual address is matched with the comparison identifier in the candidate leaf table entry. Based on the matching result, it is determined whether the page group implemented by direct mapping includes the target leaf table entry.
[0055] Among them, the index bit represents part of the content of the virtual address. For example, the index bit represents the low bit of the virtual address. The index information in the first-level bypass cache includes part of the content of the virtual address in the leaf table entry. For example, the index information represents the low bit of the virtual address in the leaf table entry. The index information corresponds to the leaf table entry in the first-level bypass cache. A leaf table entry in the first-level bypass cache can be located by the index bit index. The identifier represents part of the content of the virtual address. For example, the identifier represents the high bit of the virtual address. The comparison identifier in the candidate leaf table entry represents part of the content of the virtual address in the candidate leaf table entry. For example, the comparison identifier represents the high bit of the virtual address in the candidate leaf table entry. The target leaf table entry represents the leaf table entry corresponding to the virtual address sent by the target peripheral, and the virtual address sent by the target peripheral can be converted into a physical address through the target leaf table entry.
[0056] For a page group implemented by a fully associative mapping method, the virtual-to-real address conversion unit matches the virtual address with the virtual address in the leaf table entry included in the page group, and determines whether the page group implemented by the fully associative mapping method includes the target leaf table entry based on the matching result.
[0057] S420. When the target leaf table entry is not found in the first-level bypass cache, the virtual-to-real address conversion unit searches for the leaf table entry in the second-level bypass cache based on the virtual address, wherein the target leaf table entry represents the leaf table entry corresponding to the virtual address.
[0058] Exemplarily, the virtual-to-real address conversion unit matches the index bits in the virtual address with the index information in the secondary bypass cache. If at least one valid candidate leaf table entry is matched, the identifier in the virtual address is matched with the comparison identifier in the at least one valid candidate leaf table entry, and it is determined whether the target leaf table entry is included in the secondary bypass cache based on the matching result.
[0059] Optionally, in the case where the target leaf table entry is not found in the first-level bypass cache, the method further includes: returning to the target peripheral device a response message indicating that the target leaf table entry is not found in the first-level bypass cache. By returning to the target peripheral device a response message indicating that the target leaf table entry is not found in the first-level bypass cache, the target peripheral device can be notified of a miss in the current shot, so that the target peripheral device can resend the memory access request at an appropriate time to avoid blocking of the request task.
[0060] S430: If the target leaf table entry is found in the second-level bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry into the page group corresponding to the first-level bypass cache.
[0061] Exemplarily, if the target leaf table entry is found in the second-level bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry to a page group of a corresponding page granularity in the first-level bypass cache.
[0062] For example, if the target leaf entry is found in the L2 bypass cache and is a leaf entry with a 2M page granularity, the virtual-to-real address conversion unit updates the target leaf entry to the 2M page group in the L1 bypass cache.
[0063] Optionally, if there is no leaf table entry corresponding to the virtual address in the secondary bypass cache, a page table traversal module is used to perform a page table traversal, and the primary bypass cache is updated according to the page table traversal result.
[0064] Figure 5 A specific flow chart of virtual-to-real address conversion provided by an embodiment of the present invention. Figure 5 As shown, it includes: the virtual-to-real address conversion unit receives a virtual-to-real address conversion request sent by the target peripheral device, and the virtual-to-real address conversion request includes a virtual address. The virtual-to-real address conversion unit performs parallel searches on three groups of page groups (512G page group, 1G page group and 2M page group) in the first-level bypass cache according to the virtual address. For example, for the 512G page group and the 1G page group, the set low bit of the virtual address is used as the index bit, and the index is located to a leaf table item in the corresponding page group. Further, the set high bit of the virtual address is compared with the comparison identifier of the located leaf table item to determine whether the virtual address hits the leaf table item. For the 2M page group, each leaf table item in the 2M page group is compared with the virtual address to determine whether the virtual address hits the leaf table item. For the 512G page group, the 1G page group and the 2M page group, the above comparison result can only hit one target leaf table item, and it is impossible for multiple leaf table items to be hit at the same time. If there is no hit leaf table entry in the 512G page group, 1G page group, and 2M page group, the next beat returns a miss to the target peripheral, and outputs the virtual address to the secondary bypass cache to continue searching. If a leaf table entry is hit in the 512G page group, 1G page group, or 2M page group, the attributes and error entries are further checked. If the check passes, the physical address is returned and the virtual-to-real address conversion ends. If the check fails, a page fault prompt message indicating that the attribute check failed is reported.
[0065] The leaf table entry corresponding to the virtual address is queried in the secondary bypass cache. If a hit is found, the hit leaf table entry is used as the target leaf table entry and the target leaf table entry is updated to the primary bypass cache. If a miss is found, a page table traversal is performed.
[0066] The page table traversal process includes:
[0067] First, search for non-leaf entries in the page table traversal module. If a 1G non-leaf entry is hit, the third-level substitution memory access is directly executed, and only one memory access is required. If a 1G non-leaf entry is not hit but a 512G non-leaf entry is hit, the second-level substitution memory access and the third-level substitution memory access need to be executed, and two memory accesses are required. If none of them are hit, the third-level substitution memory access (including the first-level substitution memory access, the second-level substitution memory access, and the third-level substitution memory access) is executed, and three memory accesses are required.
[0068] The first-level substitution memory access includes: the physical address of the first substitution memory access is obtained by shifting and splicing the address translation protection register (stap) and the upper 9 bits of the virtual address. Access the main memory based on the physical address of the first-level substitution memory access and return the first-level table entry. Check the first-level table entry attributes to determine whether the first-level table entry is a leaf table entry. If it is a leaf table entry, update the first-level table entry to the 512G page group of the first-level bypass cache. If it is a non-leaf table entry, update the first-level table entry to the page table traversal cache and perform the second-level substitution memory access.
[0069] The second-level substitution memory access includes: the physical address of the second-level substitution memory access is obtained by shifting and splicing the second-highest 9 bits of the first-level table entry and the virtual address. The main memory is accessed based on the physical address of the second-level substitution memory access, and the second-level table entry is returned. The attributes of the second-level table entry are checked to determine whether the second-level table entry is a leaf table entry. If it is a leaf table entry, the second-level table entry is updated to the 1G page group of the first-level bypass cache. If it is a non-leaf table entry, the second-level table entry is updated to the page table traversal cache, and the third-level substitution memory access is performed.
[0070] The third-level substitution memory access includes: the physical address of the third-level substitution memory access is obtained by shifting and splicing the second-level table entry and the upper 9 bits of the virtual address. The main memory is accessed based on the physical address of the third-level substitution memory access, and the third-level table entry is returned. The attributes of the third-level table entry are checked to determine whether the third-level table entry is a leaf table entry. If it is a leaf table entry, the third-level table entry is updated to the 2M page group of the first-level bypass cache and the second-level bypass cache. If it is a non-leaf table entry, an exception is reported.
[0071] It should be noted that, since the above example only discloses a solution for implementing page table traversal by three-level substitution memory access, the present invention can also implement page table traversal by means of more levels of substitution memory access, which will not be described in detail here.
[0072] S440: If the target leaf table entry is found in the first-level bypass cache, the virtual-to-real address conversion unit returns a physical address according to the target leaf table entry.
[0073] In an embodiment of the present invention, if a target leaf table entry is found in a first-level bypass cache, the virtual-to-real address conversion unit determines whether the target leaf table entry is an error entry based on the attributes of the target leaf table entry. If so, a page fault prompt is returned to the target peripheral device. If the target leaf table entry is not an error entry, an attribute check is performed on the target leaf table entry. The attribute type to be checked can be pre-set, and the embodiment of the present invention does not specifically limit it. If the attribute check passes, the physical address is returned to the target peripheral device based on the target leaf table entry. If the attribute check fails, a page fault prompt is returned to the target peripheral device.
[0074] The technical solution of the embodiment of the present invention is that the virtual-to-real address conversion unit searches the first-level bypass cache according to the virtual address; when the target leaf table entry is not found in the first-level bypass cache, the virtual-to-real address conversion unit searches the leaf table entry in the second-level bypass cache based on the virtual address, wherein the target leaf table entry represents the leaf table entry corresponding to the virtual address; if the target leaf table entry is found in the second-level bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry to the page group corresponding to the first-level bypass cache; if the target leaf table entry is found in the first-level bypass cache, the virtual-to-real address conversion unit returns the physical address according to the target leaf table entry. By all virtual-to-real address conversion units sharing a large-capacity second-level bypass cache, more leaf table entries can be cached, which significantly improves the hit rate of virtual-to-real address conversion and improves the performance of virtual-to-real address conversion.
[0075] The embodiment of the present invention further provides a virtual-to-real address conversion unit, which is used to implement the virtual-to-real address conversion method as described in any embodiment of the present invention. For example, the virtual-to-real address conversion unit includes a primary bypass cache, a page table traversal cache, and a page table traversal module.
[0076] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.
[0077] The computer program for implementing the method of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to the virtual-real address conversion unit so that the computer program makes the function / operation specified in the flow chart and / or the block diagram be implemented when the virtual-real address conversion unit is executed.
[0078] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.
[0079] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A virtual-to-real address conversion system, characterized in that: include: At least one virtual-to-real address translation unit and a secondary bypass cache in communication connection; The virtual-to-real address conversion unit includes a first-level bypass cache, and the first-level bypass cache is used to store at least one page group of page granularity, and the page group includes leaf table entries, wherein the leaf table entries in page groups of different page granularities represent different physical memory spaces; The secondary bypass cache is used to store leaf table entries; The virtual-to-real address conversion unit is used to search the first-level bypass cache according to the virtual address; if the target leaf table entry is not found in the first-level bypass cache, the leaf table entry in the second-level bypass cache is searched based on the virtual address, and the target leaf table entry represents the leaf table entry corresponding to the virtual address; if the target leaf table entry is found in the second-level bypass cache, the target leaf table entry is updated to the page group corresponding to the first-level bypass cache; if the target leaf table entry is found in the first-level bypass cache, the physical address is returned according to the target leaf table entry.
2. The system according to claim 1, characterized in that The implementation method of the page group of at least one page granularity is associated with the number of leaf table entries of the page group, wherein the implementation method includes fully associative mapping and direct mapping; the leaf table entries in the secondary bypass cache are implemented using a group associative mapping method.
3. The system according to claim 1, characterized in that The secondary bypass cache includes a mapping relationship between a virtual address and a physical address written into the secondary bypass cache during a software pre-filling process.
4. The system according to claim 1, characterized in that The secondary bypass cache includes at least two storage bodies, a continuous write status register, a continuous write address register and a continuous write times register; Wherein, the continuous writing mode includes: During the software pre-filling process, the processor determines the continuous write base address and the number of continuous writes according to the configuration information, and updates the continuous write address register and the continuous write number register according to the continuous write base address and the continuous write number; generates a write request according to the virtual address and the physical address in the base address, and updates one of the at least two storage bodies according to the write request; controls the number of continuous writes in the continuous write number register to be reduced by 1; if the number of continuous writes is not zero, updates the virtual address and the physical address to obtain a new write request; if the number of continuous writes is zero, updates the status flag of the continuous write status register, and the status flag is used to indicate whether the continuous write operation is completed.
5. A method for converting virtual address to real address, characterized in that: include: At least one virtual-to-real address translation unit and a secondary bypass cache in communication connection; The virtual-to-real address conversion unit includes a first-level bypass cache, and the first-level bypass cache is used to store at least one page group of page granularity, and the page group includes leaf table entries, wherein the leaf table entries in page groups of different page granularities represent different physical memory spaces; The secondary bypass cache is used to store leaf table entries; The virtual-to-real address conversion unit searches the first-level bypass cache according to the virtual address; In the case that the target leaf table entry is not found in the first-level bypass cache, the virtual-to-real address conversion unit searches for the leaf table entry in the second-level bypass cache based on the virtual address, wherein the target leaf table entry represents the leaf table entry corresponding to the virtual address; If the target leaf table entry is found in the secondary bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry into the page group corresponding to the primary bypass cache; If the target leaf table entry is found in the first-level bypass cache, the virtual-to-real address conversion unit returns a physical address according to the target leaf table entry.
6. The method according to claim 5, characterized in that The virtual-to-real address conversion unit searches the first-level bypass cache according to the virtual address, including: The virtual address conversion unit acquires a virtual address sent by a target peripheral device, wherein the target peripheral device has a direct memory access capability and supports a virtual address function; For a page group implemented by direct mapping, the virtual-to-real address conversion unit matches the index bit in the virtual address with the index information in the first-level bypass cache, and if a candidate leaf table entry is matched, matches the identifier in the virtual address with the comparison identifier in the candidate leaf table entry, and determines whether the page group implemented by direct mapping includes the target leaf table entry according to the matching result; For a page group implemented by a fully associative mapping method, the virtual-to-real address conversion unit matches the virtual address with the virtual address in the leaf table entry included in the page group, and determines whether the page group implemented by the fully associative mapping method includes the target leaf table entry based on the matching result.
7. The method according to claim 6, characterized in that In the case that the target leaf table entry is not found in the first-level bypass cache, the method further includes: Returning to the target peripheral device that the target leaf table entry is not found in the first-level bypass cache.
8. The method according to claim 5, characterized in that The virtual-to-real address conversion unit searches for the leaf table entry in the secondary bypass cache based on the virtual address, including: The virtual-to-real address conversion unit matches the index bit in the virtual address with the index information in the secondary bypass cache. If at least one valid candidate leaf table entry is matched, the identifier in the virtual address is matched with the comparison identifier in the at least one valid candidate leaf table entry, and it is determined whether the target leaf table entry is included in the secondary bypass cache based on the matching result.
9. The method according to claim 5, characterized in that If the target leaf table entry is found in the secondary bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry into the page group corresponding to the primary bypass cache, including: If the target leaf table entry is found in the secondary bypass cache, the virtual-to-real address conversion unit updates the target leaf table entry into a page group of a corresponding page granularity in the primary bypass cache.
10. The method according to claim 5, characterized in that Also includes: If there is no leaf table entry corresponding to the virtual address in the secondary bypass cache, a page table traversal module is used to perform a page table traversal, and the primary bypass cache is updated according to the page table traversal result.
11. A virtual-to-real address conversion unit, characterized in that: The virtual-to-real address conversion unit is used to implement the virtual-to-real address conversion method as described in any one of claims 5-10.