A method for evaluating the failure risk of solder columns in a multi-chip CCGA package

Abstract

The present application discloses a method for evaluating the failure risk of solder columns in a multi-chip CCGA package, belonging to the technical field of electronic packaging and reliability analysis. The method includes: establishing a finite element analysis model by obtaining the geometric and material parameters of the multi-chip CCGA package structure; setting non-uniform working conditions and applying boundary conditions and constraints, and obtaining the non-uniformly distributed thermal stress of the solder columns through thermal cycle loading analysis; extracting key data, calculating the fatigue life of the solder columns using the Coffin-Manson thermal fatigue model and determining the life matrix; calculating the damage amount of the solder columns based on the thermal fatigue model and the linear cumulative damage theory and obtaining the damage matrix; determining the failure of the solder columns according to the damage matrix and obtaining the risk level matrix. This method can quickly and accurately evaluate the stress distribution and failure mechanism of solder columns in a multi-chip coupling scenario at the design and early verification stages according to the actual working conditions, providing scientific support for the research and development of high-reliability electronic products.

Description

Technical Field

[0001] This application relates to the technical field of electronic packaging and reliability analysis, and particularly to a method for evaluating the failure risk of solder columns in a multi-chip CCGA package. Background Art

[0002] With the continuous integration of electronic product functions and the increasing requirements for high performance and high reliability, multi-chip packaging technology has gradually become an important trend in the development of the integrated circuit industry. Among them, CCGA (Ceramic Column Grid Array) is an extension of the ceramic ball grid array CBGA concept. Due to its excellent heat dissipation characteristics and good solderability, it is widely used in fields with high environmental adaptability requirements such as aerospace, communication base stations, and automotive electronics; in the multi-chip CCGA package structure, the slender and flexible solder columns not only serve as electrical interconnection channels but also bear the mechanical support between the chip and the substrate, which is crucial for the stability and reliability of the overall package.

[0003] However, with the reduction of package size, the increase in the number of chips, and the superposition of complex working conditions such as temperature cycling, mechanical stress, and vibration shock, the solder columns are prone to failure modes such as cracks and fatigue fractures during use, resulting in serious functional failures or reliability problems. Traditional solder column failure analysis mostly uses experimental or single-chip model inference methods, which cannot accurately evaluate the stress distribution and failure mechanism in the multi-chip coupling scenario, and it is difficult to quickly evaluate and optimize different structure and material schemes at the design stage. There is an urgent need for a comprehensive evaluation method combining finite element analysis, thermal fatigue model, and cumulative damage theory to provide effective guidance for multi-chip CCGA package design and failure risk prediction. Summary of the Invention

[0004] The purpose of this application is to address the above deficiencies in the prior art by providing a method for evaluating the failure risk of solder columns in a multi-chip CCGA package, so as to solve the problems that the actual working conditions lead to an increase in the failure risk of solder columns and the single-chip model inference method is difficult to accurately evaluate the stress distribution and failure mechanism of solder columns in the multi-chip coupling scenario, and to improve the accuracy and evaluation efficiency of failure analysis and evaluation.

[0005] To achieve the above application purpose, the technical solutions adopted in this application include the following:

[0006] S1: Obtain the geometric parameters and material parameters of the multi-chip CCGA package structure;

[0007] S2: Establish a finite element analysis model for multi-chip CCGA packaging: Based on the geometric parameters, establish a geometric model of the multi-chip CCGA packaging structure, and add material parameters to the geometric model to form a finite element analysis model for multi-chip CCGA packaging. Among them, the geometric model is multiple chips, a ceramic substrate, a solder column array, and a printed circuit board stacked in sequence from top to bottom, and the multiple chips are laid flat side by side on the ceramic substrate;

[0008] S3: Use the finite element analysis model to perform a coupled analysis under non-uniform temperature loads: Apply boundary conditions and constraints to the established finite element analysis model, set different working condition temperature conditions for different chips, perform simulations under thermal cycling loading conditions, and obtain the thermal stress distribution of the solder columns;

[0009] S4: According to the finite element analysis model of the multi-chip CCGA packaging and the stress distribution of the solder columns under non-uniformly distributed temperatures, extract key data, obtain the relevant fatigue parameters of the Coffin-Manson thermal fatigue model, and calculate the fatigue life of the solder columns from the Coffin-Manson thermal fatigue model formula to determine the fatigue parameter life matrix of the CCGA packaging solder columns;

[0010] S5: Conduct a risk assessment of non-uniform damage: Based on the Coffin-Manson thermal fatigue model and the linear cumulative damage theory, calculate the damage amount of the solder columns under non-uniformly distributed thermal stresses and obtain the solder column damage matrix of the multi-chip CCGA packaging; Determine the solder column failure and obtain the risk level matrix of the solder columns of the multi-chip CCGA packaging according to the CCGA packaging solder column damage matrix.

[0011] In a possible implementation, in S2, the establishment of the finite element analysis model for multi-chip CCGA packaging includes:

[0012] Create a parametric geometric model of the multi-chip CCGA packaging structure based on finite element simulation: According to the geometric parameters of the components that make up the multi-chip CCGA packaging structure obtained, establish the geometric models of each component, and assemble the geometric models of each component to form a geometric model of the multi-chip CCGA packaging structure;

[0013] Add specific material parameters to each component of the geometric model of the multi-chip CCGA packaging structure to form a finite element analysis model for multi-chip CCGA packaging.

[0014] In a possible implementation, in S3, the application of the boundary condition is to set the overall temperature of the finite element analysis model of the multi-chip CCGA packaging to the initial temperature of , and the highest temperature is ; The applied constraint is that the displacement constraint of the printed circuit board foot points at the bottom is zero, simulating the fixed installation method of the printed circuit board.

[0015] In a possible implementation, the S4 includes:

[0016] S41: Obtain the plastic strain amplitude of the solder column during thermal cycling, which can be calculated by the following formula:

[0017]

[0018] Where, is the plastic strain amplitude of the solder column during thermal cycling, is the thermal expansion coefficient of the solder column material, is the temperature change range of the thermal cycle;

[0019] S42: Use the Coffin-Manson thermal fatigue model formula to calculate the fatigue life of the solder column, and obtain the fatigue life of the solder column in the i row and j column of the multi-chip CCGA package , and the calculation formula is as follows:

[0020]

[0021] Where, is the plastic strain amplitude of the solder column in the i row and j column of the multi-chip CCGA package, is the material fatigue initiation strain amplitude of the solder column in the i row and j column of the multi-chip CCGA package, is the material Coffin-Manson constant of the solder column in the i row and j column of the multi-chip CCGA package;

[0022] S43: Construct the fatigue parameter life matrix of the solder column in the i row and j column as shown in the following formula according to the calculated fatigue parameters of each solder column;

[0023]

[0024] S44: Establish the multi-chip CCGA package solder column fatigue parameter life matrix as shown below according to the calculated fatigue parameter life matrix of each solder column;

[0025]

[0026] Where, KIt is the fatigue parameter life matrix of the solder columns in the multi-chip CCGA package. i It is the i row solder column in the multi-chip CCGA package. j It is the j column solder column in the multi-chip CCGA package. n It is the total number of rows of solder columns in the multi-chip CCGA package. m It is the total number of columns of solder columns in the multi-chip CCGA package. It is the fatigue parameter life matrix of the solder column at the first row and the first column in the multi-chip CCGA package. It is the i row and the j column solder column in the multi-chip CCGA package. It is the n row and the m column solder column in the multi-chip CCGA package.

[0027] In a possible implementation, the obtaining of the solder column damage matrix of the multi-chip CCGA package includes:

[0028] S51: Use the Coffin-Manson thermal fatigue model and the linear cumulative damage theory to calculate the damage amount of the solder columns in the multi-chip CCGA package, which can be calculated by the following formula:

[0029]

[0030] Where, is the cumulative damage amount of the solder column at the i row and the j column, is the fatigue life of the solder column at the i row and the j column, k is the number of thermal cycles;

[0031] S52: According to the calculated cumulative damage amounts, establish the damage matrix of the solder columns in the multi-chip CCGA package as shown below D ;

[0032]

[0033] Where, i is the i row solder column in the multi-chip CCGA package, j is the j column solder column in the multi-chip CCGA package, n is the total number of rows of solder columns in the multi-chip CCGA package, m is the total number of columns of solder columns in the multi-chip CCGA package, The cumulative damage of the solder column at the first row and the first column in the multi-chip CCGA package, in the multi-chip CCGA package i row j and the cumulative damage of the solder column at the column, in the multi-chip CCGA package n row m and the cumulative damage of the solder column at the column, D which is the damage matrix of the solder columns in the multi-chip CCGA package;

[0034] S53: Determine the failure of the solder column according to the damage matrix of the solder columns in the multi-chip CCGA package, and set as low risk, as medium risk, as high risk, and establish the risk level matrix of the solder columns in the multi-chip CCGA package as shown below M ;

[0035]

[0036] Among them, is the risk level of the solder column at the first row and the first column in the multi-chip CCGA package, in the multi-chip CCGA package i row j and the risk level of the solder column at the column, in the multi-chip CCGA package n row m and the risk level of the solder column at the column, M which is the risk level matrix of the solder columns in the multi-chip CCGA package.

[0037] Compared with the prior art, in this application, by establishing a finite element analysis model of the multi-chip CCGA package, information such as multiple chips, substrates, solder columns, and their material properties and geometric parameters are incorporated into the overall coupled analysis to achieve a full-field simulation of the thermal-mechanical environment. The accurate modeling of this multi-chip structure can more realistically reflect the actual packaging situation, making the obtained thermal stress distribution of the solder columns more in line with the actual situation and avoiding the deviation caused by the single-chip and uniform temperature assumptions in the traditional method; at the same time, the key parameters of solder column thermal fatigue are obtained, the stress-strain amplitude of the solder column is extracted based on the simulation results, as well as the fatigue damage index required for the thermal fatigue model, providing accurate data support for subsequent life prediction. Since multi-chip coupling and non-uniform thermal stress are considered, these parameters can more accurately reflect the fatigue characteristics of the solder column under actual working conditions; in addition, a thermal fatigue life model and the cumulative damage theory are introduced to calculate the fatigue life and damage amount of different solder columns under non-uniformly distributed thermal stress, which can more carefully evaluate the damage situation of the solder columns.

[0038] Through the above technical means, the present application can quickly and accurately quantify the failure risk of the solder columns in the multi-chip CCGA package during the design stage and early verification, providing scientific technical support for the research and development and production of high-reliability electronic products. Description of the Drawings

[0039] Figure 1 It is a schematic structural diagram of a multi-chip CCGA package structure provided by an embodiment of the present application;

[0040] Figure 2 It is a front view of a multi-chip CCGA package structure provided by an embodiment of the present application;

[0041] Figure 3 It is a top view of a multi-chip CCGA package structure provided by an embodiment of the present application;

[0042] Figure 4 It is a schematic flowchart of a method for evaluating the failure risk of solder columns in a multi-chip CCGA package provided by an embodiment of the present application.

[0043] Reference numerals: 1 - ceramic substrate, 2 - solder column array, 3 - printed circuit board, 4 - chip. Detailed Embodiments

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0045] In order to more clearly illustrate the method for evaluating the failure risk of solder columns in the multi-chip CCGA package provided by the embodiments of the present application, an exemplary description will be given below of a possible application scenario of the method for evaluating the failure risk of solder columns in the multi-chip CCGA package provided by the embodiments of the present application. It can be understood that the following examples are only a possible application scenario of the method for evaluating the failure risk of solder columns in the multi-chip CCGA package provided by the embodiments of the present application. In other possible embodiments, the method for evaluating the failure risk of solder columns in the multi-chip CCGA package provided by the embodiments of the present application can also be applied to other possible application scenarios, and the following examples do not impose any restrictions on this.

[0046] Traditional solder column failure analysis mostly uses the single-chip model inference method, mainly calculating the boundary conditions for the case of uniform temperature distribution. For the case of multiple chips, the thermal stress caused by non-uniform temperature distribution needs to be considered. Thermal stress is generated when materials are constrained during expansion or contraction due to temperature changes. Under uniform temperature distribution, the thermal stress may be relatively uniform, but when the temperature distribution is non-uniform, the degree of expansion in different regions is different, resulting in complex internal stresses and possibly greater local stresses, which in turn accelerates fatigue failure.

[0047] It can be understood that the multi-chip packaging technology has gradually become an important trend in the development of the integrated circuit industry. Chips with different processes and functions are integrated into a single package through advanced packaging technology to form a complete system function. In the multi-chip CCGA packaging structure, the slender and flexible solder columns serve both as electrical interconnection channels and bear the mechanical support between the chips and the substrate, which is crucial for the stability and reliability of the overall package.

[0048] However, traditional CCGA solder column failure analysis is mostly based on the assumption of uniform temperature or the single-point heat source model. The failure analysis only considers the stress impact of the overall temperature cycle on the solder joints and does not involve the local thermal coupling effect caused by the multi-chip layout, which is not very close to the actual scenario.

[0049] Based on this, the embodiment of the present application provides a method for evaluating the failure risk of solder columns in a multi-chip CCGA package. The multi-chip CCGA packaging structure is as Figures 1 - 3 shown. In this embodiment, the multi-chip CCGA packaging structure used takes the ceramic substrate 1 as the substrate, and a solder column array 2 is welded on the bottom surface of the ceramic substrate. The other side of the solder column array 2 is connected to the printed circuit board (PCB) 3. Multiple chips 4 are provided on the upper surface of the ceramic substrate 1. Taking three chips as an example.

[0050] As Figure 4 shown, the specific implementation of the present application is as follows:

[0051] S1: Obtain the geometric parameters and material parameters of the multi-chip CCGA packaging structure.

[0052] Collect the geometric parameters and material parameters of each component device for constructing the multi-chip CCGA packaging structure. The devices include the printed circuit board, solder columns, ceramic substrate, and chips. Among them, the solder column is a cylindrical shape with a height of 0.2 mm and a diameter of 0.2 mm. The size parameter table of each device is shown in Table 1:

[0053] Table 1 Device size parameter table

[0054]

[0055] The solder columns used in this embodiment are tin-lead solder. This example involves a 10×10 solder column array with a pitch of 0.6 mm, a total of 100. The printed circuit board is made of FR-4 material, the ceramic substrate is made of ceramic material, and the chip is made of silicon material. This embodiment takes 3 chips as an example, and the material parameter table of each device is shown in Table 2:

[0056] Table 2 Material Parameter Table of Devices

[0057]

[0058] There are 4 types of devices in Table 2. Each row represents the material parameters of a device, and each column represents a material property parameter and the corresponding specific parameter.

[0059] S2: Establish a finite element analysis model for multi-chip CCGA packaging.

[0060] S21: According to the size parameters in Table 1, draw the geometric models of each device based on finite element simulation. Then, starting from the bottom is the printed circuit board 3, followed by the solder column matrix 2 formed by 100 columnar solder columns arranged in a 10×10 array with a pitch of 0.6 mm above it. Further above is the ceramic substrate 1, and on the ceramic substrate are 3 chips 4. The sizes of each chip are as shown in Table 1.

[0061] S22: According to the material properties of each device, use Abaqus finite element simulation software to add specific material properties to the corresponding devices in the geometric model to obtain the finite element analysis model of multi-chip CCGA packaging.

[0062] S3: Use the finite element analysis model to perform a coupled analysis under non-uniform temperature loads: Apply boundary conditions and constraints to the established finite element analysis model, set different working condition temperature conditions for different chips, and perform simulation under thermal cycle loading conditions to obtain the thermal stress distribution of the solder columns.

[0063] Set the working condition temperature table of different chips as shown in Table 3. The overall initial temperature of the model is , is the overall highest temperature. Then, the temperatures of the 3 chips change differently. It is set that the temperature of chip 1 rises from 40°C to 140°C, the temperature of chip 2 rises from 40°C to 130°C, and the temperature of chip 3 rises from 40°C to 120°C. The ceramic substrate, solder columns, and printed circuit board undergo temperature changes due to the heat transfer of the chips.

[0064] Table 3 Chip Working Condition Temperature Table

[0065]

[0066] Among them, the boundary condition applied to the established model is to set the overall temperature of the model to the initial temperature , is 40 °C, and the maximum temperature is ; The applied constraint is to apply full constraints to the bottom printed circuit board foot points, that is, the displacement constraint of the foot points is zero, simulating its fixed installation method.

[0067] S4: According to the finite element analysis model of the multi-chip CCGA package and the stress distribution of the solder columns under non-uniform temperature distribution, extract key data, obtain the relevant fatigue parameters of the Coffin-Manson thermal fatigue model, and calculate the fatigue life of the solder columns from the Coffin-Manson thermal fatigue model formula to determine the fatigue parameter life matrix of the multi-chip CCGA package solder columns.

[0068] Specifically: S41: Obtain the plastic strain amplitude of the solder column in the thermal cycle, which can be calculated by the following formula:

[0069]

[0070] Among them, is the plastic strain amplitude of the solder column in the thermal cycle, is the thermal expansion coefficient of the solder column material, is the temperature change range of the thermal cycle;

[0071] S42: Use the Coffin-Manson thermal fatigue model formula to calculate the fatigue life of the solder column, and obtain the fatigue life of the solder column in the i th row and the j th column of the multi-chip CCGA package , and the calculation formula is as follows:

[0072]

[0073] Among them, is the plastic strain amplitude of the solder column in the i th row and the j th column of the multi-chip CCGA package, is the material fatigue initiation strain amplitude of the solder column in the i th row and the j th column of the multi-chip CCGA package, taking 0.5, is the material Coffin-Manson constant of the solder column in the i th row and the j th column of the multi-chip CCGA package, taking -0.5;

[0074] S43: According to the calculated fatigue parameters of each solder column, construct the fatigue parameter life matrix of the solder column in the i th row and the j th column as shown in the following formula;

[0075]

[0076] S44: Establish the fatigue parameter life matrix of the multi-chip CCGA package solder columns as shown below based on the calculated fatigue parameter life matrix of each solder column. The fatigue parameter life matrix table of each solder column is shown in Table 4:

[0077]

[0078] where, K is the fatigue parameter life matrix of the multi-chip CCGA package solder columns, i is the i th row solder column in the multi-chip CCGA package, j is the j th column solder column in the multi-chip CCGA package, n is the total number of rows of the solder columns in the multi-chip CCGA package, m is the total number of columns of the solder columns in the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in the first row and first column of the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in the i th row and j th column of the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in the n th row and m th column of the multi-chip CCGA package.

[0079] Table 4 Fatigue parameter life matrix table of solder columns

[0080]

[0081] Continued Table 4

[0082]

[0083] Continued Table 4

[0084]

[0085] Continued Table 4

[0086]

[0087] Continued Table 4

[0088]

[0089] S5: Conduct a risk assessment of non-uniform damage: Calculate the damage amount of the solder columns under non-uniformly distributed thermal stress based on the Coffin-Manson thermal fatigue model and the linear cumulative damage theory, and obtain the damage matrix of the multi-chip CCGA package solder columns; Determine the failure of the solder columns based on the damage matrix of the multi-chip CCGA package solder columns and obtain the risk level matrix of the multi-chip CCGA package solder columns.

[0090] Specifically, S51: Use the Coffin-Manson thermal fatigue model and the linear cumulative damage theory to calculate the damage amount of the multi-chip CCGA package solder columns, which can be calculated by the following formula:

[0091]

[0092] Where, is the cumulative damage amount of the solder column in the i th row and the j th column, is the fatigue life of the solder column in the i th row and the j th column, k is the number of thermal cycles;

[0093] S52: Based on the calculated cumulative damage amounts, establish the damage matrix of the multi-chip CCGA package solder columns as shown below D :

[0094]

[0095] Where, i is the solder column in the i th row of the multi-chip CCGA package, j is the solder column in the j th column of the multi-chip CCGA package, n is the total number of rows of the solder columns in the multi-chip CCGA package, m is the total number of columns of the solder columns in the multi-chip CCGA package, is the cumulative damage of the solder column in the first row and the first column of the multi-chip CCGA package, is the cumulative damage of the solder column in the i th row and the j th column of the multi-chip CCGA package, is the cumulative damage of the solder column in the n th row and the m th column of the multi-chip CCGA package, D is the damage matrix of the multi-chip CCGA package solder columns;

[0096] The cumulative damage matrix D of the multi-chip CCGA package solder columns is shown in Table 5:

[0097] Table 5 Cumulative Damage Matrix Table of Solder Columns

[0098]

[0099] Continued Table 5

[0100]

[0101] S53: Determine the failure of the solder columns according to the solder column damage matrix of the multi-chip CCGA package, and set as low risk, as medium risk, as high risk, and establish the risk level matrix of the solder columns of the multi-chip CCGA package as shown below M ;

[0102]

[0103] Among them, is the risk level of the solder column in the first row and first column of the multi-chip CCGA package, is the risk level of the solder column in the i th row and j th column of the multi-chip CCGA package, is the risk level of the solder column in the n th row and m th column of the multi-chip CCGA package, M is the risk level matrix of the solder columns of the multi-chip CCGA package.

[0104] The risk level matrix M of the solder columns of the multi-chip CCGA package is shown in Table 6.

[0105] Table 6 Risk Level Matrix Table of Solder Columns

[0106]

[0107] Continued Table 6

[0108]

[0109] The purpose of this application is to overcome the influence of ignoring the actual working conditions on the risk assessment of solder column failure in the prior art, and the difficulty of accurately evaluating the stress distribution and failure mechanism of solder columns in the multi-chip coupling scenario by traditional single-chip model inference methods. A method for evaluating the failure risk of solder columns in multi-chip CCGA packages is provided. This method realizes the accurate analysis of the stress, strain, displacement distribution and potential failure points of solder columns under thermal cycling and other complex working conditions through the following technical means, and quantifies the overall failure risk of multi-chip CCGA packages. First, a finite element analysis model of multi-chip CCGA packages is established, and information such as chips, substrates, solder columns and their material properties and geometric parameters is incorporated into the overall coupled analysis to achieve the full-field simulation of the thermal-mechanical environment. The accurate modeling of this multi-chip structure can more realistically reflect the actual packaging situation, making the obtained solder column thermal stress distribution more in line with the actual situation and avoiding the deviation caused by the traditional method using a single chip and uniform temperature assumptions. Secondly, the key parameters of solder column thermal fatigue are obtained. Based on the simulation results, the stress-strain amplitude of the solder column and the fatigue damage index required by the thermal fatigue model are extracted, providing accurate data support for subsequent life prediction. Since multi-chip coupling and non-uniform thermal stress are considered, these parameters can more accurately reflect the fatigue characteristics of solder columns under actual working conditions. In addition, a thermal fatigue life model and cumulative damage theory are introduced to calculate the fatigue life and damage amount of different solder columns under non-uniformly distributed thermal stress, which can more carefully evaluate the damage situation of solder columns.

[0110] Through the above technical means, this application can quickly and accurately quantify the failure risk assessment of solder columns in multi-chip CCGA packages in the design stage and early verification, providing scientific technical support for the research and production of high-reliability electronic products.

[0111] Those of ordinary skill in the art will realize that the embodiments described herein are for helping readers understand the principles of this application, and it should be understood that the protection scope of this application is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of this application based on the technical revelations disclosed in this application, and these deformations and combinations are still within the protection scope of this application.

Claims

1. A multi-chip CCGA package solder column failure risk assessment method, characterized in that: The method comprises: S1: Obtain geometric parameters and material parameters of a multi-chip CCGA packaging structure; S2: Establishing a finite element analysis model of a multi-chip CCGA package: establishing a geometric model of the multi-chip CCGA package structure based on the geometric parameters, and adding material parameters to the geometric model to form a finite element analysis model of the multi-chip CCGA package, wherein the geometric model is a plurality of chips, a ceramic substrate, a solder column array and a printed circuit board stacked sequentially from top to bottom, and the plurality of chips are laid side by side on the ceramic substrate; S3: Using the finite element analysis model, a coupling analysis is performed under non-uniform temperature loads: boundary conditions and constraints are applied to the constructed finite element analysis model, different operating temperature conditions are set for different chips, and thermal stress distribution of solder columns is simulated and obtained under thermal cycle loading conditions; S4: extract key data according to the finite element analysis model of the multi-chip CCGA package and the stress distribution of the solder column under the non-uniform distribution temperature, obtain the relevant fatigue parameters of the Coffin-Manson thermal fatigue model, calculate the fatigue life of the solder column by the Coffin-Manson thermal fatigue model formula, and determine the fatigue parameter life matrix of the solder column of the multi-chip CCGA package; S5: Perform risk assessment of non-uniform damage: Based on the Coffin-Manson thermal fatigue model and linear cumulative damage theory, calculate the damage amount of the solder column under non-uniformly distributed thermal stress and obtain the multi-chip CCGA package solder column damage matrix; perform solder column failure judgment based on the multi-chip CCGA package solder column damage matrix and obtain the risk level matrix of the multi-chip CCGA package solder column.

2. The method for evaluating the failure risk of solder pillars in a multi-chip CCGA package according to claim 1, characterized in that: In S2, the step of establishing a finite element analysis model of a multi-chip CCGA package includes: Creating a parametric geometric model of the multi-chip CCGA packaging structure based on finite element simulation: establishing a geometric model of each device according to the acquired geometric parameters of the components of the multi-chip CCGA packaging structure, assembling the geometric models of each device to form a geometric model of the multi-chip CCGA packaging structure; Specific material parameters are added to each device of the geometric model of the multi-chip CCGA packaging structure to form a meta-analysis model of the multi-chip CCGA packaging.

3. The multi-chip CCGA package solder column failure risk assessment method according to claim 1, characterized in that: In S3, the applied boundary condition is that the overall temperature of the element analysis model of the multi-chip CCGA package is set to the initial temperature , the maximum temperature is The imposed constraint is that the displacement constraint of the bottom foot point of the printed circuit board is zero, simulating the fixed installation method of the printed circuit board.

4. The method for evaluating the failure risk of solder pillars in a multi-chip CCGA package according to claim 1, characterized in that: The S4 includes: S41: Obtain the plastic strain amplitude of the weld column during the thermal cycle, which can be calculated by the following formula: in, is the plastic strain amplitude of the weld column during thermal cycling, is the thermal expansion coefficient of the solder column material, is the temperature variation amplitude of the thermal cycle; S42: The fatigue life of the weld column is calculated using the Coffin-Manson thermal fatigue model formula. i Line j Fatigue life of solder pillars in multi-chip CCGA packages , the calculation formula is as follows: in, It is i Line j The plastic strain amplitude of the solder column of the multi-chip CCGA package is shown in Figure 2. It is i Line j The material fatigue onset strain amplitude of the solder column of the multi-chip CCGA package is shown in the figure. It is i Line j The Coffin-Manson constants of the materials for the solder pillars of the multi-chip CCGA package; S43: Based on the calculated fatigue parameters of each welding column, the following formula is constructed: i Line j The fatigue parameter life matrix of the column weld is listed; S44: establishing a fatigue parameter life matrix of solder pillars for a multi-chip CCGA package as shown below based on the calculated fatigue parameter life matrix of each solder pillar; in, K is the fatigue parameter life matrix of solder pillars in multi-chip CCGA package, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Welding column, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the fatigue parameter life matrix of the solder column in row 1 and column 1 in the multi-chip CCGA package, It is the first in the multi-chip CCGA package i Line j The fatigue parameter life matrix of the weld column is: It is the first in the multi-chip CCGA package n Line m Fatigue parameter life matrix of the column weld.

5. The multi-chip CCGA package solder column failure risk assessment method according to claim 1, characterized in that: The step of obtaining a multi-chip CCGA package solder column damage matrix includes: S51: The Coffin-Manson thermal fatigue model and linear cumulative damage theory are used to calculate the damage amount of the solder column of the multi-chip CCGA package, which can be calculated by the following formula: in, It is i Line j The accumulated damage of the weld column is It is i Line j Fatigue life of weld column, k is the number of thermal cycles; S52: Based on the calculated accumulated damage amounts, a damage matrix of the solder column of the multi-chip CCGA package is established as shown below D ; in, i It is the first in the multi-chip CCGA package i Welding column, j It is the first in the multi-chip CCGA package j Welding column, n is the total number of solder column rows in the multi-chip CCGA package, m is the total number of solder column columns in the multi-chip CCGA package, is the accumulated damage of the solder column in row 1 and column 1 of the multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The accumulated damage of the weld column, It is the first in the multi-chip CCGA package n Line m The accumulated damage of the weld column, D The damage matrix of solder pillars for multi-chip CCGA packages; S53: Perform solder column failure determination according to the multi-chip CCGA package solder column damage matrix, and set For low risk, For medium risk, As high risk, a risk level matrix for multi-chip CCGA package solder pillars is established as shown below M ; in, is the risk level of the solder column in row 1 and column 1 in a multi-chip CCGA package. It is the first in the multi-chip CCGA package i Line j The risk level of the weld column is listed as follows, It is the first in the multi-chip CCGA package n Line m The risk level of the weld column is listed as follows, M Risk level matrix for solder pillars in multi-chip CCGA packages.

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