Test method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a test method and device, electronic equipment and a readable storage medium, and the method comprises the steps: grouping at least one to-be-controlled clock gate, and determining the number of control registers in a control chain according to the number of groups of the clock gates; inserting the control chain into the scanning chain; determining a to-be-opened target clock gating group according to a clock signal required in the test circuit; and according to the target clock gating group, inputting a scanning enabling signal to the scanning enabling end of the scanning chain, and inputting a test vector to the scanning input end of the scanning chain, so as to control the target clock gating group through the enabling signal output by the demultiplexer. According to the embodiment of the invention, by controlling each group of clock gating in groups, the test power consumption is reduced, and the test time is shortened.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a testing method, device, electronic device and readable storage medium. Background Art

[0002] For large-scale chips, scanning test is an important means to ensure chip yield. With the continuous advancement of manufacturing technology and the development of design technology, the complexity of chips continues to increase, and the power consumption of chip testing has also increased significantly due to the explosive growth of test data volume and test time.

[0003] The factors that affect the effectiveness of testability design are very complex, requiring designers to think about how to effectively perform low-power chip testing during the design phase. The current common practice in the industry is to add test points in the scan chain and use the test points to open the test enable end of the clock gating. However, this approach will control the entire module gating to be fully open, resulting in an excessively high module flip rate, which in turn leads to high power consumption in chip testing. Summary of the invention

[0004] The embodiments of the present application provide a testing method, an apparatus, an electronic device, and a readable storage medium, which can reduce test power consumption and shorten chip testing time.

[0005] In a first aspect, an embodiment of the present application discloses a testing method, the method comprising: At least one clock gating to be controlled is grouped, and the number of control registers in a control chain is determined according to the number of groups of the clock gating; the control chain comprises at least one control register and a demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of test enable ends of the clock gating; Inserting the control chain into a scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence; Determine the target clock gating group to be enabled according to the clock signal required in the test circuit; According to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

[0006] Optionally, determining the number of control registers in the control chain according to the number of clock gating groups includes: Performing a logarithm operation with base 2 on the group of numbers to obtain a first operation result; The number of control registers in the control chain is determined according to the first operation result.

[0007] Optionally, inputting a scan enable signal to a scan enable terminal of the scan chain includes: Inputting a high-level scan enable signal to a scan enable terminal of the scan chain to set the working mode of the scan chain to a shift mode; When the operation modes of the scan registers in the scan chain are switched to the shift mode, the scan enable signal is switched to a low level to set the operation mode of the scan chain to the capture mode.

[0008] Optionally, inputting a scan enable signal to a scan enable end of the scan chain and inputting a test vector to a scan input end of the scan chain according to the target clock gating group, so as to control the target clock gating group through the enable signal output by the demultiplexer, comprises: Determining a target test vector according to the target clock gating group; A low-level scan enable signal is input to the scan enable end of the scan chain, and the target test vector is input to the scan input end, so as to set the test enable end of the target clock gating group to a high level state through the enable signal output by the demultiplexer, and set the test enable ends of the remaining target clock gating groups in the clock gating to be controlled to a low level state.

[0009] Optionally, the method further comprises: When the target clock gating group includes all clock gating groups, a high level scan enable signal is input to the scan enable end of the scan chain to set the test enable ends of the target clock gating group to a high level state through the enable signal output by the demultiplexer.

[0010] Optionally, when the working mode of the scan chain is the shift mode, the data in each scan register in the scan chain is shifted bit by bit; when the working mode of the scan chain is the capture mode, the data in each scan register in the scan chain remains unchanged.

[0011] In a second aspect, an embodiment of the present application discloses a testing device, the device comprising: at least one clock gate to be controlled; A control chain, comprising an input register, at least one control register and a demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock-gated test enable ends; the control chain and the scan chain are connected in series; the number of the control registers is determined according to the number of clock-gated groups to be controlled; The scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence.

[0012] In a third aspect, an embodiment of the present application discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned test method.

[0013] In a fourth aspect, an embodiment of the present application discloses a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the processor to execute the aforementioned test method.

[0014] The embodiments of the present application include the following advantages: The embodiment of the present invention provides a test method, by grouping at least one clock gating to be controlled, according to the number of groups of clock gating, the number of control registers in the control chain is determined; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to a group of test enable ends of clock gating; the control chain is inserted into a scan chain; the scan chain includes at least one scan register, and at least one scan register is connected in series in sequence; according to the clock signal required in the test circuit, the target clock gating group to be turned on is determined; according to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer. The embodiment of the present invention can control each group of clock gating by grouping, reduce test power consumption, and shorten test time. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0016] Figure 1 is a flow chart of steps of an embodiment of a testing method provided by the present invention; Figure 2 is a schematic diagram of a scan chain provided by the present invention; Figure 3 It is a structural block diagram of a testing device provided by the present invention; Figure 4 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0019] Method Embodiment Reference Figure 1 , shows a flow chart of steps of a test method embodiment of the present invention, the test method may include the following steps: Step 101, grouping at least one clock gating to be controlled, and determining the number of control registers in a control chain according to the number of groups of the clock gating; the control chain comprises at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to a group of test enable ends of the clock gating; Step 102: insert the control chain into a scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence; Step 103: Determine the target clock gating group to be enabled according to the clock signal required in the test circuit; Step 104 : According to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

[0020] The test method provided by the embodiment of the present invention can be applied to the fields of integrated circuit design and manufacturing, communication equipment manufacturing and maintenance, consumer electronics, automotive electronics, etc. Specifically, it is used to test chips in various devices such as mobile phones, tablet computers, electronic control units, industrial robots, etc. to ensure the safe operation of various devices.

[0021] Among them, clock gating can also be called gated clock. The structure of clock gating includes a clock input terminal (Clock Input, clk), an enable signal terminal (Enable, en), a test enable terminal (Test enable), and an output terminal. The output terminal of the clock gating is connected to the clock input terminal of the scan register to control whether the scan register receives the clock signal. When grouping clock gating, all clock gatings to be controlled can be grouped evenly, that is, the number of clock gatings in each group after grouping is the same; or even grouping is not performed, that is, the number of clock gatings in each group after grouping is different. The embodiment of the present invention does not limit the grouping method. According to the number of clock gating groups, the required demultiplexer is determined, and the number of output terminals of the demultiplexer needs to be greater than or equal to the number of clock gating groups. The number of control registers is determined according to the number of selection terminals of the demultiplexer, and the number of control registers is equal to the number of selection terminals of the demultiplexer.

[0022] The enable register and the control register are sequentially connected in series to obtain a control chain. The structure of the control register includes a scan input terminal, a clock input terminal, a data input terminal, an output terminal, and a scan enable terminal. The structures of the enable register and the control register are the same. Specifically, the enable register is used as the starting end of the control chain. The output terminal of the enable register is connected to the scan input terminal of a control register. The output terminal of this control register is connected to the scan input terminal of the next control register. The same applies to the remaining control registers.

[0023] like Figure 2As shown, the scan chain (Scan Chain) is composed of scan registers connected in series, and each scan register is a register with a scan input terminal and a scan output terminal. The output terminal of the scan register at the end of the scan chain is the scan output terminal (Scan Output) of the entire scan chain. Specifically, the structure of the scan register includes a scan input terminal (Scan Input, SI), a clock input terminal (Clock), a data input terminal (Data Input), an output terminal (Data Output), and a scan enable terminal (Scan Enable, SE). It should be noted that the clock input terminals of each scan register in the scan chain are uniformly and synchronously controlled, and the scan enable terminals of each scan register are also uniformly and synchronously controlled. For example, a high-level scan enable signal is sent to the scan input terminal of the scan chain, and the scan enable terminals of each scan register on the scan chain are all in a high-level state at the same time. The output terminal of each scan register is connected to the scan input terminal of the next scan register.

[0024] Inserting the control chain into the scan chain means connecting the scan input of the enable register at the start of the control chain to the output of a scan register in the scan chain, and connecting the output of the control register at the end of the control chain to the scan input of another scan register in the scan chain. The control chain can also be placed at both ends of the scan chain, that is, the enable register at the start of the control chain is used as the beginning of the inserted scan chain, or the enable register of the control chain is connected to the scan register at the end of the original scan chain, and the control register at the end of the control chain is used as the end of the inserted scan chain. Among them, the clock input of each register in the control chain and the clock input of each register in the scan chain are uniformly controlled synchronously; the scan enable end of each register in the control chain and the scan enable end of each register in the scan chain are also uniformly controlled synchronously. It should be noted that the scan chain also receives the Scan_mode signal, which is a global test mode switch. When scan_mode is high, the SE signal has the authority to control the scan chain; when scan_mode is low, the SE signal cannot change the working mode of the scan chain. Specifically, when the Scan_mode signal is at a high level, the scan chain is activated and enters the test mode; when the Scan_mode signal is at a low level, the scan chain exits the test mode. In the test mode, when SE is at a high level, the scan chain works in the shift mode; when SE is at a low level, the scan chain works in the capture mode (normal mode).

[0025] Demultiplexer (DEMUX) means that the structure of the demultiplexer includes a data input terminal, a selection terminal, and a data output terminal. The data input terminal is used to receive the input signal, and the selection terminal is used to determine which output terminal the input signal is sent to. According to the different combinations of the high and low level states of the selection terminal, the input signal will be directed to an output terminal corresponding to the combination. If the input signal is high, one output terminal of the demultiplexer outputs a high-level enable signal, the corresponding target clock gating group is turned on, and the remaining output terminals are all in a low-level state. It should be noted that the input signal can also be low, then the output terminals of the demultiplexer are all in a low-level state, and the clock gating connected to all output terminals is closed.

[0026] In an embodiment of the present invention, after the control chain is inserted into the scan chain, a scan enable signal is input to the scan enable end of the scan chain to load the test vector into the scan chain. The test data stored in each control register in the control chain is output to the selection end of the demultiplexer, and the test data stored in the enable register is output to the data input end of the demultiplexer; the demultiplexer determines the target output end of the enable signal according to the control signal received at the selection end, distributes the input signal received at the data input end to the target output end, and controls the target clock gating group connected to the target output end according to the enable signal output by the demultiplexer. According to the characteristics of the demultiplexer, each group of clock gating can be controlled separately to achieve the effect of reducing test power consumption and shortening test time.

[0027] It should be noted that there can be multiple scan chains on the same chip at the same time. The output of the demultiplexer is connected to the clock gating on the current scan chain or the clock gating on other scan chains. A clock gating can be connected to at least one register; the register is flipped by triggering the clock gating, and then the circuit where the register is located is tested.

[0028] In an embodiment of the present invention, at least one clock gating to be controlled is grouped, and the number of control registers in a control chain is determined according to the number of clock gating groups; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock gating test enable ends; the control chain is inserted into a scan chain; the scan chain includes at least one scan register, and at least one scan register is connected in series in sequence; according to the clock signal required in the test circuit, the target clock gating group to be turned on is determined; according to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

[0029] Optionally, determining the number of control registers in the control chain according to the number of clock gating groups includes: Step S11, performing a logarithmic operation with base 2 on the group number to obtain a first operation result; Step S12: Determine the number of control registers in the control chain according to the first operation result.

[0030] Specifically, the relationship between the selection end and the output end of the demultiplexer is that if there are n selection ends, there are corresponding output ends. Demultiplexers generally include 1-2 demultiplexers, 1-4 demultiplexers, and 1-8 demultiplexers, which respectively refer to a demultiplexer with one data input end and two output ends, and the demultiplexer has one selection end; a demultiplexer with one data input end and four output ends, and the demultiplexer has two selection ends; a demultiplexer with one data input end and eight output ends, and the demultiplexer has three selection ends.

[0031] It should be noted that the number of output terminals of the demultiplexer needs to be greater than or equal to the number of groups, and the number of output terminals of the demultiplexer is logarithmically calculated with a base of 2 to obtain a second operation result, and the second operation result is the number of selection terminals of the demultiplexer. The number of selection terminals needs to be greater than or equal to the first operation result, that is, the second operation result needs to be greater than the first operation result. Among them, the output terminal of a control register is connected to a selection terminal of the demultiplexer, that is, the number of selection terminals of the demultiplexer is equal to the number of control registers. Therefore, the number of control registers is greater than or equal to the first operation result. The first operation result is rounded up to obtain a third operation result, and the number of control registers is greater than or equal to the third operation result.

[0032] For example, when the clock gating is divided into 5 groups, the first operation result obtained by performing a logarithm operation with base 2 on 5 is greater than 2, but less than 3. Therefore, a demultiplexer with two selection terminals cannot completely control the 5 groups of clock gating, and a demultiplexer with at least 3 selection terminals is required to control the 5 groups of clock gating.

[0033] In an embodiment of the present invention, a logarithm operation with base 2 is performed on the number of clock gating groups to obtain a first operation result; the number of control registers in the control chain is determined according to the first operation result, and the corresponding clock gating group is controlled by a control signal output by the control register to the demultiplexer selection terminal.

[0034] Optionally, the step of inputting a scan enable signal to the scan enable terminal of the scan chain in step 104 includes: Step 21, inputting a high-level scan enable signal to the scan enable terminal of the scan chain to set the working mode of the scan chain to a shift mode; Step 22: When the working modes of all scan registers in the scan chain are switched to the shift mode, the scan enable signal is switched to a low level to set the working mode of the scan chain to the capture mode.

[0035] The working mode of the scan chain is first set to the shift mode to load the test vectors into each scan register in the scan chain; when all the test vectors are loaded into each scan register in the scan chain, the working mode of the scan chain is set to the capture mode.

[0036] Before switching the scan enable signal from high level to low level, it is necessary to ensure that the shift operation has been completed, that is, the test vector has been completely shifted into each register of the scan chain. For example, if the total length of the scan chain after inserting the control chain is N, it takes N clock cycles to complete the shift operation. At the rising edge of the clock signal in the N+1th clock cycle, the scan enable signal is switched to a low level.

[0037] It should be noted that the switching of the scan enable signal needs to be synchronized with the clock signal. For example, before the next rising edge of the clock signal arrives, the scan enable signal has stabilized at a low level, and the capture mode can be entered in the next clock cycle.

[0038] In an embodiment of the present invention, a high-level scan enable signal is input to the scan enable end of the scan chain to set the working mode of the scan chain to the shift mode; when the working modes of each scan register in the scan chain are switched to the shift mode, the scan enable signal is switched to a low level to set the working mode of the scan chain to the capture mode. The working mode of the scan chain is controlled by the scan enable signal, and the working mode of the scan chain is switched to the capture mode at an appropriate time, so that in the capture mode, the state of each group of clock gating is controlled in groups through the values ​​stored in each control register.

[0039] Optionally, the step 104 of inputting a scan enable signal to a scan enable end of the scan chain and inputting a test vector to a scan input end of the scan chain according to the target clock gating group, so as to control the target clock gating group through the enable signal output by the demultiplexer, includes: Step 31, determining a target test vector according to the target clock gating group; Step 32, input a low-level scan enable signal to the scan enable end of the scan chain, input the target test vector to the scan input end, and set the test enable end of the target clock gating group to a high level state through the enable signal output by the demultiplexer, and set the test enable ends of the remaining target clock gating groups in the clock gating to be controlled to a low level state.

[0040] Specifically, according to the circuit to be tested, the target clock gating group connected to this part of the circuit is determined. According to the corresponding relationship between the output end and the selection end of the demultiplexer connected to the target clock gating group, the control signal combination required by the selection end of the demultiplexer is determined. According to the control signal combination, the position of the control chain on the scan chain, and the length of the scan chain after the control chain is inserted, the test vector is determined. Among them, the length of the test vector is equal to the length of the scan chain after the control chain is inserted, and the test vector loaded into each control register in the control chain can enable the demultiplexer to distribute the signal output by the enable register to the target clock gating group.

[0041] It should be noted that after determining the target test vector according to the target clock gating, a high-level scan enable signal is first input to the scan enable end of the scan chain to put the scan chain in shift mode. In the shift mode, the target test vector is completely loaded into the scan chain. Then, a low-level scan enable signal is input to the scan enable end of the scan chain to put the scan chain in capture mode. In the capture mode, the demultiplexer determines the target output end according to the values ​​stored in each control register in the control chain; the input signal sent by the enable register received by the data input end is output from the target output end to control the corresponding target clock gating group.

[0042] For example, Figure 3 As shown, there is a scan chain with 4 scan registers, there are 16 groups of clock gating, and a demultiplexer with 16 output ports A0...A15 is used. The demultiplexer with 16 output ports has 4 selection terminals, so 4 control registers and 1 enable register are required. The demultiplexer, 4 control registers and one enable register form a control chain, and the control chain is inserted into the scan chain, and the length of the scan chain becomes 9. When the target clock gating group to be turned on is connected to the A1 port, the values ​​stored in the 4 control registers should be 0010; the value stored in the enable register should be 1; the values ​​of the remaining positions in the test vector can be randomly generated, for example, the test vector can be 101001000. It should be noted that Figure 3 In the embodiment, the dft_se signal and the scan enable signal input to the scan chain are controlled by the same signal, and the dft_scan_pclk and the clock signal input to the clock input terminal of the scan chain are controlled by the same clock signal. The dft_syn_gt_se signal and the dft_syn_gt_se_sel signal are used to set the dft_syn_gt_se signal and the dft_syn_gt_se_sel signal to a high level when a fault occurs, so as to force the control to open all clock gating. In the test mode of the embodiment of the present invention, the dft_syn_gt_se signal and the dft_syn_gt_se_sel signal are both in a low level state.

[0043] In an embodiment of the present invention, a target test vector is determined according to a target clock gating group; a low-level scan enable signal is input to a scan enable end of a scan chain, and a target test vector is input to a scan input end, so that the test enable end of the target clock gating group is set to a high-level state through an enable signal output by a demultiplexer, and the test enable ends of the remaining target clock gating groups in the clock gating to be controlled are set to a low-level state, so as to realize group-controlled clock gating, avoid turning on unnecessary clock gating, and unnecessary register flipping, thereby reducing test consumption and shortening test time.

[0044] Optionally, the method further comprises: When the target clock gating group includes all clock gating groups, a high level scan enable signal is input to the scan enable end of the scan chain to set the test enable ends of the target clock gating group to a high level state through the enable signal output by the demultiplexer.

[0045] When the scan enable signal is at a high level, the scan enable signal and the enable signal output by the demultiplexer are both at a high level after a logic AND operation, and each group of clock gating connected to the demultiplexer is turned on.

[0046] In an embodiment of the present invention, when the target clock gating group includes all clock gating groups, a high-level scan enable signal is input to the scan enable end of the scan chain, and the enable signal output by the demultiplexer is used to set the test enable ends of the target clock gating groups to a high-level state to force all clock gatings to be turned on, and a low-level scan enable signal is input to the scan enable end of the scan chain to control the clock gating of each group according to the input test vector group.

[0047] Optionally, when the working mode of the scan chain is the shift mode, the data in each scan register in the scan chain is shifted bit by bit; when the working mode of the scan chain is the capture mode, the data in each scan register in the scan chain remains unchanged.

[0048] When the scan enable signal is at a high level, the scan chain is in shift mode (shift), and the test vector is input to the SI end of the scan chain, and the test vector is shifted between each scan register. Each scan register receives the test data output by the previous scan register at the edge of the clock signal according to the clock signal output by the clock gating, and outputs the stored test data to the next scan register. Specifically, if the scan register is designed to be triggered at the rising edge of the clock signal, then when the clock signal jumps from a low level to a high level, the test data in each scan register is shifted. If the scan register is designed to be triggered at the falling edge of the clock signal, then when the clock signal jumps from a high level to a low level, the test data in each scan register is shifted. For example, the test vector is "0110", there are 4 scan registers, namely A scan register, B scan register, C scan register, and D scan register, and the shift operation is triggered at the rising edge of each clock cycle. As shown in Table 1, the initial states of the 4 scan registers in the scan chain are all 0, and after 4 clock cycles, the test vector is completely loaded into the scan chain.

[0049] Table 1 Scan chain shift pattern

[0050] In an embodiment of the present invention, the output end and the data input end of the control register and the enable register in the control chain are directly connected. When the scan enable signal is at a low level, the scan chain is in a capture mode (capture), and each register no longer shifts, but works as a normal register. In the capture mode, the output result of the combinational logic circuit is captured into each register in the scan chain through the data input end. Since the data input end of each register in the control chain in the present invention is connected to its own output port, a loop is formed. Therefore, when the scan chain is in the capture mode, the value of each register in the scan chain remains unchanged.

[0051] In an embodiment of the present invention, when the scan enable signal is at a high level, the scan chain is in a shift mode, a test vector is input to the scan input end of the scan chain, and the test vector is shifted between each scan register. Each scan register receives the test data output by the previous scan register at the edge of the clock signal according to the clock signal output by the clock gating, and outputs the stored test data to the next scan register. When the scan enable signal is at a low level, the scan chain is in a capture mode, each register is no longer shifted, and the output result of the combinational logic circuit is captured into each register in the scan chain through the data input end. Since the data input end of each register in the control chain in the present invention is connected to its own output port, a loop is formed. Therefore, when the scan chain is in the capture mode, the values ​​of each register in the scan chain remain unchanged for testing and observation, and the demultiplexer is controlled by the values ​​stored in the register to control each group of clock gating.

[0052] In summary, the test method provided by the embodiment of the present invention can group at least one clock gating to be controlled, and determine the number of control registers in the control chain according to the number of clock gating groups; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock gating test enable ends; the control chain is inserted into a scan chain; the scan chain includes at least one scan register, and at least one scan register is connected in series in sequence; according to the clock signal required in the test circuit, the target clock gating group to be turned on is determined; according to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer. Specifically, a target test vector is determined according to a target clock gating group; a low-level scan enable signal is input to a scan enable end of a scan chain, and a target test vector is input to a scan input end, so that a test enable end of the target clock gating group is set to a high-level state through an enable signal output by a demultiplexer, and a test enable end of the remaining target clock gating groups in the clock gating to be controlled is set to a low-level state, so as to realize separate control of clock gating of each group, and turn on the corresponding clock gating according to test requirements, thereby reducing test power consumption and shortening test time.

[0053] Device Embodiment like Figure 3 FIG. 1 is a block diagram of a test device of the present invention, and the device may specifically include: at least one clock gate to be controlled; A control chain, comprising an enable register, at least one control register and a demultiplexer; the output end of the enable register is connected to the data input end of the demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock-gated test enable ends; the control chain and the scan chain are connected in series; the number of the control registers is determined according to the number of clock-gated groups to be controlled; The scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence.

[0054] Optionally, the input end of the enable register at the starting end of the control chain is connected to the output end of the first scan register in the scan chain; the output end of the control register at the end of the control chain is connected to the input end of the second scan register in the scan chain; each register in the control chain is connected in series in sequence; the scan output end of each register in the control chain is loop-connected to its respective data input end.

[0055] In summary, the test device provided by the embodiment of the present invention can group at least one clock gating to be controlled, and determine the number of control registers in the control chain according to the number of clock gating groups; the control chain includes at least one control register and a demultiplexer; the output end of each control register is respectively connected to an input end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock gating test enable ends; the control chain is inserted into a scan chain; the scan chain includes at least one scan register, and at least one scan register is connected in series in sequence; according to the clock signal required in the test circuit, the target clock gating group to be turned on is determined; according to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer. Specifically, a target test vector is determined according to a target clock gating group; a low-level scan enable signal is input to a scan enable end of a scan chain, and a target test vector is input to a scan input end, so that a test enable end of the target clock gating group is set to a high-level state through an enable signal output by a demultiplexer, and a test enable end of the remaining target clock gating groups in the clock gating to be controlled is set to a low-level state, so as to realize separate control of clock gating of each group, and turn on the corresponding clock gating according to test requirements, thereby reducing test power consumption and shortening test time.

[0056] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0057] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0058] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0059] Reference Figure 4 , is a structural block diagram of an electronic device for testing provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the test method of the aforementioned embodiment.

[0060] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0061] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0062] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0063] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 Test method shown.

[0064] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0065] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0066] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0067] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0069] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0070] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0071] The test method, device, electronic device and readable storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A testing method, characterized in that: The method comprises: At least one clock gating to be controlled is grouped, and the number of control registers in a control chain is determined according to the number of groups of the clock gating; the control chain comprises an enable register, at least one control register and a demultiplexer; the output end of the enable register is connected to the data input end of the demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of test enable ends of the clock gating; Inserting the control chain into a scan chain; the scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence; Determine the target clock gating group to be enabled according to the clock signal required in the test circuit; According to the target clock gating group, a scan enable signal is input to the scan enable end of the scan chain, and a test vector is input to the scan input end of the scan chain, so as to control the target clock gating group through the enable signal output by the demultiplexer.

2. The method according to claim 1, characterized in that Determining the number of control registers in the control chain according to the number of groups of clock gating includes: Performing a logarithm operation with base 2 on the group of numbers to obtain a first operation result; The number of control registers in the control chain is determined according to the first operation result.

3. The method according to claim 1, characterized in that The step of inputting a scan enable signal to a scan enable terminal of the scan chain comprises: Inputting a high-level scan enable signal to a scan enable terminal of the scan chain to set the working mode of the scan chain to a shift mode; When the operation modes of the scan registers in the scan chain are switched to the shift mode, the scan enable signal is switched to a low level to set the operation mode of the scan chain to the capture mode.

4. The method according to claim 1, characterized in that: The step of inputting a scan enable signal to a scan enable end of the scan chain and a test vector to a scan input end of the scan chain according to the target clock gating group, so as to control the target clock gating group through the enable signal output by the demultiplexer, comprises: Determining a target test vector according to the target clock gating group; A low-level scan enable signal is input to the scan enable end of the scan chain, and the target test vector is input to the scan input end, so as to set the test enable end of the target clock gating group to a high level state through the enable signal output by the demultiplexer, and set the test enable ends of the remaining target clock gating groups in the clock gating to be controlled to a low level state.

5. The method according to claim 1, characterized in that The method further comprises: When the target clock gating group includes all clock gating groups, a high level scan enable signal is input to the scan enable end of the scan chain to set the test enable ends of the target clock gating group to a high level state through the enable signal output by the demultiplexer.

6. The method according to claim 1, characterized in that When the working mode of the scan chain is the shift mode, the data in each scan register in the scan chain is shifted bit by bit; when the working mode of the scan chain is the capture mode, the data in each scan register in the scan chain remains unchanged.

7. A testing device, characterized in that: Applied to testing a circuit, the testing device comprises: at least one clock gate to be controlled; A control chain, comprising an enable register, at least one control register and a demultiplexer; the output end of the enable register is connected to the data input end of the demultiplexer; the output end of each control register is respectively connected to a selection end of the demultiplexer, and each output end of the demultiplexer is connected to a group of clock-gated test enable ends; the control chain and the scan chain are connected in series; the number of the control registers is determined according to the number of clock-gated groups to be controlled; The scan chain includes at least one scan register, and the at least one scan register is connected in series in sequence.

8. The device according to claim 7, characterized in that The input end of the enable register at the starting end of the control chain is connected to the output end of the first scan register in the scan chain; the output end of the control register at the end of the control chain is connected to the input end of the second scan register in the scan chain; each register in the control chain is connected in series in sequence; the scan output end of each register in the control chain is connected in a loop with its respective data input end.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the testing method according to any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the testing method according to any one of claims 1 to 6.

Images