A logic synthesis parameter optimization method, device, equipment and medium of a circuit

Abstract

Embodiments of the present application provide a circuit logic synthesis parameter optimization method, device, equipment and medium, the method comprises: obtaining initial clock uncertainty parameter and initial clock conversion time parameter; according to initial clock uncertainty parameter, initial clock conversion time parameter and preset optimization model, determine optimization clock uncertainty parameter and optimization clock conversion time parameter;According to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine timing score and area score;In the case where timing score and area score meet the preset score condition, according to optimization clock uncertainty parameter and optimization clock conversion time parameter, determine target clock uncertainty parameter and target clock conversion time parameter;In this way, the optimized clock uncertainty parameter and clock conversion time parameter can be accurately calculated.The problem of parameter setting depending on experience and lacking scientificity is solved, and the accuracy and reliability of clock tree design are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of logic synthesis parameter optimization of circuit, and particularly relates to a logic synthesis parameter optimization method, device, equipment and medium of circuit. BACKGROUND

[0002] The design of integrated circuit is divided into two stages of front-end and back-end. The front-end design mainly focuses on the realization of logic function, and the design idea is converted into a circuit netlist through RTL (Register Transfer Level) code writing and logic synthesis. The back-end design, that is, the physical design, is responsible for further converting the circuit netlist into a specific physical layout, including the placement of components, the planning of wiring, and the construction of clock tree, etc. In the physical design stage, the layout and wiring of the clock tree become the key factors affecting the performance of the chip. The clock signal must be accurately and quickly transmitted to each timing component to ensure the correct transmission and processing of data. However, with the increase of chip size and the increase of clock frequency, the optimization of the clock tree faces more and more challenges. Clock uncertainty and clock transition time are two important parameters in the optimization of the clock tree. Clock uncertainty describes the time difference of the arrival of the clock signal at each timing component due to factors such as process variation and wiring length difference. Clock transition time reflects the transition speed of the clock signal in the clock tree. In the traditional design process, the setting of these two parameters often depends on the experience and intuition of engineers. In the synthesis stage, in order to leave enough timing margin for the subsequent layout and wiring, engineers usually set these parameters to be relatively large. However, this experience-based setting method may lead to unnecessary area waste or timing performance degradation. In addition, the logic synthesis tool will optimize the timing and area according to the given constraint file (such as SDC file) when generating the circuit structure. However, there is often a conflict between timing and area optimization: pursuing better timing performance may increase the circuit area, and overemphasizing area optimization may sacrifice the timing performance. Therefore, how to reasonably set these parameters in the constraint file to achieve the common optimization of timing and area has become an important problem in the design of integrated circuits. SUMMARY

[0003] In view of the above problems, the present application embodiment is proposed to provide a logic synthesis parameter optimization method, device, equipment and medium of circuit which overcomes the above problems or at least partially solves the above problems.

[0004] In order to solve the above problems, the present application embodiment discloses a logic synthesis parameter optimization method of circuit, the method comprises:

[0005] obtaining an initial clock uncertainty parameter and an initial clock slew time parameter; the clock uncertainty parameter is used to describe the influence of layout and routing of a clock tree on clock signal arrival time; the clock slew time parameter is used to describe the slew speed of a clock signal in the clock tree;

[0006] determining an optimized clock uncertainty parameter and an optimized clock slew time parameter according to the initial clock uncertainty parameter, the initial clock slew time parameter and a preset optimization model;

[0007] determining a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock slew time parameter

[0008] in a case where the timing score and the area score satisfy a preset score condition, determining a target clock uncertainty parameter and a target clock slew time parameter according to the optimized clock uncertainty parameter and the optimized clock slew time parameter.

[0009] Optionally, the method further comprises:

[0010] determining at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock slew time parameter; the initial parameter group contains a clock uncertainty parameter and a clock slew time parameter;

[0011] the determining an optimized clock uncertainty parameter and an optimized clock slew time parameter according to the initial clock uncertainty parameter, the initial clock slew time parameter and a preset optimization model comprises:

[0012] determining an optimized parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model;

[0013] the determining a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock slew time parameter comprises:

[0014] determining a corresponding timing score and a corresponding area score for each of the optimized parameter groups respectively;

[0015] the determining a target clock uncertainty parameter and a target clock slew time parameter according to the optimized clock uncertainty parameter and the optimized clock slew time parameter in a case where the timing score and the area score satisfy a preset score condition comprises:

[0016] in a case where the timing score corresponding to the optimized parameter group is greater than a preset timing threshold and the area score corresponding to the optimized parameter group is greater than a preset area threshold, determining a target parameter group according to the optimized parameter group;

[0017] determining the target clock uncertainty parameter and the target clock transition time parameter according to the target parameter group.

[0018] Optionally, the method further comprises:

[0019] In a case where the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the area score corresponding to the optimization parameter group is less than a preset area threshold, returning the step of determining the optimization parameter group corresponding to each of the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model.

[0020] Optionally, the step of returning the step of determining the optimization parameter group corresponding to each of the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model in a case where the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the area score corresponding to the optimization parameter group is less than a preset area threshold comprises:

[0021] In a case where the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the area score corresponding to the optimization parameter group is less than a preset area threshold, determining a first candidate parameter group according to each of the at least one optimization parameter group and the initial parameter group corresponding thereto;

[0022] determining a second candidate parameter group according to the at least one optimization parameter group;

[0023] returning the step of determining the optimization parameter group corresponding to each of the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model.

[0024] Optionally, the step of determining the optimization parameter group corresponding to each of the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model comprises:

[0025] determining the optimization parameter group corresponding to each of the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and a preset optimization model;

[0026] the step of returning the step of determining the optimization parameter group corresponding to each of the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model comprises:

[0027] returning the step of determining the optimization parameter group corresponding to each of the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and a preset optimization model.

[0028] Optionally, in the case that the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding to the optimization parameter group is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group.

[0029] In the case that the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding to the optimization parameter group is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group and the second candidate parameter group.

[0030] Optionally, the method further comprises:

[0031] In the case that the timing score and the area score do not satisfy a preset score condition, returning to the step of determining an optimization clock uncertainty parameter and an optimization clock switching time parameter according to the initial clock uncertainty parameter, the initial clock switching time parameter and a preset optimization model.

[0032] In another aspect, the embodiments of the present application also disclose a logic synthesis parameter optimization device of a circuit, the device comprising:

[0033] An initial parameter acquisition module is configured to acquire an initial clock uncertainty parameter and an initial clock switching time parameter; the clock uncertainty parameter is used to describe the influence of layout and routing of a clock tree on clock signal arrival time; and the clock switching time parameter is used to describe the switching speed of a clock signal in the clock tree.

[0034] An optimization parameter determination module is configured to determine an optimization clock uncertainty parameter and an optimization clock switching time parameter according to the initial clock uncertainty parameter, the initial clock switching time parameter and a preset optimization model.

[0035] A synthesis score determination module is configured to determine a timing score and an area score according to the optimization clock uncertainty parameter and the optimization clock switching time parameter.

[0036] A target parameter determination module is configured to determine a target clock uncertainty parameter and a target clock switching time parameter according to the optimization clock uncertainty parameter and the optimization clock switching time parameter in the case that the timing score and the area score satisfy a preset score condition.

[0037] Optionally, the device further comprises:

[0038] An initial parameter group acquisition submodule is configured to determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock switching time parameter; the initial parameter group contains a clock uncertainty parameter and a clock switching time parameter.

[0039] The determining module of the optimization parameter set comprises:

[0040] The determining module of the optimization parameter set comprises:

[0041] The determining module of the comprehensive score comprises:

[0042] The determining module of the optimization parameter set comprises:

[0043] The determining module of the target parameter set comprises:

[0044] The determining module of the optimization parameter set comprises:

[0045] The determining module of the optimization parameter set comprises:

[0046] Optionally, the apparatus further comprises:

[0047] The repeating iteration module is configured to return to the step of determining the optimization parameter set corresponding to each initial parameter set according to the at least one initial parameter set and the preset optimization model, when the timing score corresponding to the optimization parameter set is less than the preset timing threshold or the area score corresponding to the optimization parameter set is less than the preset area threshold.

[0048] Optionally, the repeating iteration module comprises:

[0049] The first candidate determining unit is configured to determine a first candidate parameter set according to each optimization parameter set in the at least one optimization parameter set and the initial parameter set corresponding to the optimization parameter set, when the timing score corresponding to the optimization parameter set is less than the preset timing threshold or the area score corresponding to the optimization parameter set is less than the preset area threshold.

[0050] The second candidate determining unit is configured to determine a second candidate parameter set according to the at least one optimization parameter set.

[0051] The first optimization iteration unit is configured to return to the step of determining the optimization parameter set corresponding to each initial parameter set according to the at least one initial parameter set and the preset optimization model.

[0052] Optionally, the determining module of the optimization parameter set comprises:

[0053] a first optimization unit, configured to determine an optimization parameter group corresponding to each of the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and a preset optimization model;

[0054] the first optimization iteration unit comprises:

[0055] a second optimization iteration subunit, configured to return the step of determining the optimization parameter group corresponding to each of the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0056] Optionally, the target parameter group determination sub-module comprises:

[0057] a final target parameter group determination unit, configured to determine a target parameter group according to the optimization parameter group and the second candidate parameter group in a case where the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding to the optimization parameter group is greater than a preset area threshold.

[0058] Optionally, the method further comprises:

[0059] the iteration sub-module returns the step of determining the optimization clock uncertainty parameter and the optimization clock transition time parameter according to the initial clock uncertainty parameter, the initial clock transition time parameter and the preset optimization model in a case where the timing score and the area score do not satisfy a preset score condition.

[0060] Correspondingly, an embodiment of the present application discloses an electronic device, comprising a processor, a memory and a computer program stored in the memory and capable of running on the processor, and each step of the logic synthesis parameter optimization method embodiment of the circuit is implemented when the computer program is executed by the processor.

[0061] Correspondingly, an embodiment of the present application discloses a computer readable storage medium, and the computer readable storage medium stores a computer program, and each step of the logic synthesis parameter optimization method embodiment of the circuit is implemented when the computer program is executed by a processor.

[0062] The embodiment of the present application comprises the following advantages: based on the initial clock uncertainty parameter and the initial clock conversion time parameter, by combining with the preset optimization model, the embodiment of the present application can accurately calculate the optimized clock uncertainty parameter and the clock conversion time parameter. The problem of parameter setting depending on experience and lacking of scientificity is solved, and the accuracy and reliability of the clock tree design are improved. Based on the optimized clock uncertainty parameter and the clock conversion time parameter, the timing score and the area score are further determined. The two scores respectively reflect the performance of the clock tree in the timing performance and the area efficiency. By comprehensively considering the timing and the area, the area waste can be maximally reduced under the premise of ensuring the timing performance, and the double optimization of the timing and the area is realized. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the clock conversion time parameter. These target parameters provide clear guidance for the subsequent clock tree layout and wiring, and ensure the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, which provides strong support for the manufacturing of integrated circuits. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 is a step flow chart of an embodiment of a logic synthesis parameter optimization method of a circuit of the present application;

[0064] Figure 2 is a step flow chart of another embodiment of a logic synthesis parameter optimization method of a circuit of the present application;

[0065] Figure 3 is a flowchart of an embodiment of a logic synthesis parameter optimization method of a circuit of the present application;

[0066] Figure 4 is a structural block diagram of an embodiment of a logic synthesis parameter optimization device of a circuit of the present application. DETAILED DESCRIPTION

[0067] In order to make the above-mentioned objects, features and advantages of the present application more apparent and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0068] In the design of integrated circuits, the design of the clock tree is a crucial link. Among them, the clock uncertainty parameter and the clock conversion time parameter are two key concepts, which have a direct impact on the performance of the clock tree.

[0069] The clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal. In the clock tree, due to the difference in layout and routing, the time when the clock signal arrives at each register or flip-flop may be different, and this time difference is called clock uncertainty. The clock uncertainty parameter is an important indicator to measure this time difference, which is crucial for the timing analysis and optimization of the clock tree.

[0070] The clock transition time parameter is used to describe the transition speed of the clock signal in the clock tree. When the clock signal jumps from low to high or from high to low, it takes a certain time to complete this transition process. This time is called clock transition time. The clock transition time parameter is an important indicator to measure the transition speed of the clock signal, which has a direct impact on the performance of the clock tree. Faster clock transition time can improve the working frequency of the clock tree, but may also bring greater power consumption and noise.

[0071] One of the core ideas of the embodiments of the present application is to obtain and optimize the clock uncertainty parameter and the clock transition time parameter by combining scientific methods with preset optimization models, and to quantify the timing and area of the clock tree as assessable indicators by introducing timing scores and area scores, providing a clear direction for subsequent optimization.

[0072] Referring to Figure 1 , a step flowchart of an embodiment of a logic synthesis parameter optimization method of a circuit of the present application is shown, which can specifically include the following steps:

[0073] Step 101, obtaining an initial clock uncertainty parameter and an initial clock transition time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of the clock tree on the arrival time of the clock signal; the clock transition time parameter is used to describe the transition speed of the clock signal in the clock tree;

[0074] The method of obtaining the initial clock uncertainty parameter and the initial clock transition time parameter can be based on the calculation of the physical parameters of the circuit design, or generated by using EDA (Electronic Design Automation) tools and estimated according to experience, etc., which is not limited by the embodiments of the present application.

[0075] Step 102, determining an optimized clock uncertainty parameter and an optimized clock transition time parameter according to the initial clock uncertainty parameter, the initial clock transition time parameter and a preset optimization model;

[0076] After the initial parameters are obtained, the preset optimization model is used to calculate the optimized parameter values in combination with the initial clock uncertainty parameters and the clock conversion time parameters.

[0077] In step 103, a timing score and an area score are determined according to the optimized clock uncertainty parameters and the optimized clock conversion time parameters.

[0078] The timing score indicates whether the circuit can work stably within a specified clock period, i.e., whether the timing requirement is met, based on the optimized clock parameters. A high timing score means that the timing performance of the circuit is good. The area score indicates the circuit area or resource consumption required to implement the clock parameters.

[0079] In step 104, target clock uncertainty parameters and target clock conversion time parameters are determined according to the optimized clock uncertainty parameters and the optimized clock conversion time parameters, in a case where the timing score and the area score meet preset score conditions.

[0080] If the timing score and the area score both meet the preset score conditions, the current optimized clock uncertainty parameters and the optimized clock conversion time parameters are determined as the final target parameters.

[0081] In an embodiment, the method further includes:

[0082] In a case where the timing score and the area score do not meet the preset score conditions, the step of determining the optimized clock uncertainty parameters and the optimized clock conversion time parameters according to the initial clock uncertainty parameters, the initial clock conversion time parameters and the preset optimization model is returned to.

[0083] If the score conditions are not met, it indicates that the current parameter combination is not optimal, and the optimization process needs to be restarted in step 102 until a parameter combination that meets the conditions is found.

[0084] In an embodiment, a termination condition can be set for the iteration of the method to prevent endless iteration of the algorithm due to abnormal reasons; the condition for terminating the iteration can be that the number of iterations reaches a threshold value; for example, the number of iterations threshold value can be set to 8 times, i.e., when the number of iterations is the 8th time, the iteration is terminated.

[0085] Based on the obtained initial clock uncertainty parameter and initial clock conversion time parameter, by combining with a preset optimization model, the embodiment of the application can accurately calculate the optimized clock uncertainty parameter and clock conversion time parameter. This step directly solves the problem of parameter setting depending on experience and lacking of scientificity in the background art, and improves the accuracy and reliability of the clock tree design. Based on the optimized clock uncertainty parameter and clock conversion time parameter, the timing score and area score are further determined. The two scores respectively reflect the performance of the clock tree in terms of timing performance and area efficiency. By comprehensively considering the timing and area, the area waste can be maximally reduced under the premise of ensuring the timing performance, and the double optimization of timing and area is realized. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and clock conversion time parameter. These target parameters provide clear guidance for subsequent clock tree layout and wiring, and ensure the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, which provides strong support for the manufacturing of integrated circuits.

[0086] Referring to Figure 2 , a step flow chart of another embodiment of the method for optimizing logical synthesis parameters of a circuit is shown, which can specifically include the following steps:

[0087] In the embodiment of the application, the preset optimization model can be a particle swarm optimization model. The following are the corresponding steps and explanations of an embodiment of the method for optimizing logical synthesis parameters of a circuit in combination with a particle swarm optimization algorithm.

[0088] Particle swarm optimization (PSO) is an optimization algorithm based on swarm intelligence, which simulates the behavior of biological groups such as bird flocks or fish flocks to solve optimization problems.

[0089] The PSO algorithm simulates the foraging behavior of bird flocks or fish flocks in nature. In this model, each solution is regarded as a "particle" in the search space, representing a potential solution to the problem. Each particle has two key attributes: position and velocity. The position represents the current coordinates of the particle in the solution space, while the velocity determines the direction and speed of the particle movement.

[0090] In step 201, an initial clock uncertainty parameter and an initial clock conversion time parameter are obtained; the clock uncertainty parameter is used to describe the influence of the layout and wiring of the clock tree on the arrival time of the clock signal; and the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0091] The method of obtaining the initial clock uncertainty parameter and the initial clock transition time parameter can be based on calculation of physical parameters of a circuit design, or generated by using an EDA (Electronic Design Automation) tool or estimated according to experience, and the embodiments of the present application do not limit this.

[0092] In combination with the particle swarm optimization algorithm, the initial parameters are generated, and exemplarily, the clock transition time parameter (transition) can be initialized as x i1 , and the range is (0.8, 1.2); and the clock uncertainty parameter (uncertainty) can be initialized as x i2 , and the range is (0.3, 1.7).

[0093] In step 202, at least one initial parameter group is determined according to the initial clock uncertainty parameter and the initial clock transition time parameter; the initial parameter group contains a clock uncertainty parameter and a clock transition time parameter.

[0094] Exemplarily, a group of particles is randomly generated, and each particle represents a combination of an initial clock uncertainty parameter and an initial clock transition time parameter. Here, the number of particles is temporarily set to 5. For each particle i, the position is randomly initialized. X i =(x i1 ,x i2 )

[0095] In an example, the speed V i =(v i1 ,v i2 ) of each particle can also be initialized to control the moving speed of the particle in the search space. Correspondingly, the range of x i1 is smaller, and the range of v i1 is set to (-0.1, 0.1); the range of x i2 is smaller, and the range of v i2 is set to (-0.2, 0.2).

[0096] In step 203, an optimization parameter group corresponding to each initial parameter group is determined according to the at least one initial parameter group and a preset optimization model.

[0097] In combination with the initial position of the particle and the speed of the particle, the initial parameter group is optimized.

[0098] In step 204, a corresponding timing score and area score are determined for each optimization parameter group.

[0099] For each optimization parameter group, their timing score and area score need to be determined in order to better evaluate the performance of the generated parameters; the way to generate timing score and area score can be generated by means of DC (Design Compiler, logic synthesis tool) tool; DC (Design Compiler) is an advanced digital integrated circuit logic synthesis tool developed by Synopsys company, which can convert high-level hardware description language (HDL) code (such as Verilog, VHDL, etc.) into optimized gate-level netlist.

[0100] Step 205, in the case that the timing score corresponding to the optimization parameter group is greater than the preset timing threshold and the area score corresponding to the optimization parameter group is greater than the preset area threshold, determining a target parameter group according to the optimization parameter group;

[0101] Exemplarily, the importance of timing score and area score can be set according to business needs, for this embodiment, the timing score meeting the threshold is the most important, if the timing meets the requirements, the logic synthesis area is A, here A = 450000, then the fitness is defined as If the timing does not meet the requirements, the fitness is set to a minimum value, f = 0.01. The smaller the area, the greater the fitness, and the better the logic synthesis result.

[0102] In an embodiment, the method further comprises:

[0103] In the case that the timing score corresponding to the optimization parameter group is less than the preset timing threshold or the area score corresponding to the optimization parameter group is less than the preset area threshold, returning to the step of determining the optimization parameter group corresponding to the initial parameter group according to the at least one initial parameter group and the preset optimization model.

[0104] When the score does not meet the threshold, it means that the optimization of the model does not reach the predetermined target, at this time it needs to be re-iterated. This process guarantees the quality of the design and enhances the design flexibility.

[0105] In an embodiment, the step of "in the case that the timing score corresponding to the optimization parameter group is less than the preset timing threshold or the area score corresponding to the optimization parameter group is less than the preset area threshold, returning to the step of determining the optimization parameter group corresponding to the initial parameter group according to the at least one initial parameter group and the preset optimization model" can comprise the following sub-steps:

[0106] Sub-step S11, in the case that the timing score corresponding to the optimization parameter group is less than the preset timing threshold or the area score corresponding to the optimization parameter group is less than the preset area threshold, determining a first candidate parameter group according to each optimization parameter group in the at least one optimization parameter group and the initial parameter group corresponding thereto.

[0107] In the particle swarm algorithm, the selection of the individual optimal and the group optimal of the particles is the focus of the algorithm;

[0108] In an example, when determining the individual optimal, it is necessary to compare the score results of the generated parameters this time and the score results of the generated parameters last time, and select the optimal one as the new particle individual optimal to be brought into the next iteration. Illustratively, for each particle i, the current fitness is compared with the individual historical optimal fitness. If the current fitness is better, the individual optimal position Pbest i = X i The individual optimal position of the initial solution is itself.

[0109] Sub-step S12, determining a second candidate parameter group according to the at least one optimal parameter group;

[0110] After the individual optimal position is determined, the group optimal position needs to be further determined;

[0111] In an example, after the optimal position of each individual is selected, the current group optimal position is compared. If the current individual position is superior to the current group optimal position, the new group optimal position is generated by replacing the group optimal position with the current individual position;

[0112] Sub-step S13, returning the step of determining the optimal parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model.

[0113] When the score does not satisfy the threshold value, it indicates that the optimization of the model does not reach the predetermined target, at which time re-iteration needs to be combined. This process guarantees the quality of the design and enhances the design flexibility.

[0114] In an embodiment, step 203 comprises the following sub-steps:

[0115] Sub-step S21, determining the optimal parameter group corresponding to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model;

[0116] Illustratively, the speed of the particle can be updated according to the following formula:

[0117] v ij = w t *v ij (t) + c1*r1*(Pbest ij -x ij (t)) + c2*r2*(Gbest j -x ij (t))

[0118] The position of the particle can be updated according to the following formula combined with the updated example speed:

[0119] x ij (t+1) = x ij (t) + v ij (t+1)

[0120] Wherein, the learning factor is: c1=c2=2, specifically, the value of the learning factor is in [0, 4], the values of c1 and c2 can be adjusted appropriately according to business needs. The inertia weight is set to: w=0.9. max =0.9w min =0.3. r1 and r2 are random numbers in [0, 1]. It should be noted that the values of the learning factor, r1, r2, and the inertia weight can be freely set by other ways and scenarios, and the embodiments of the present application do not limit this.

[0121] For the updated position x i1 (t+1), if it is less than 0.8, it is set to 0.81, and if it is greater than 1.2, it is set to 1.2. For the updated position x i2 (t+1), if it is less than 0.4, it is set to 0.41, and if it is greater than 1.7, it is set to 1.7. If the position is out of range because the speed is too large, the speed can be reversed and its absolute value can be reduced according to the direction of the out-of-range direction. For example, x i1 For example, if x i1 (t+1)>1.2, then v i1 (t+1)=-|v i1 (t+1)|*α, where α is a coefficient less than 1, which can be adjusted according to business needs; if x i1 (t+1)<0.8, then v i1 (t+1)=-|v i1 (t+1)|*α.

[0122] The sub-step S13 includes the following sub-steps:

[0123] The sub-step S131 returns to the step of determining the optimization parameter group corresponding to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group, and the preset optimization model.

[0124] In an embodiment, step 205 includes the following sub-steps:

[0125] In sub-step S31, when the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding to the optimization parameter group is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group and the second candidate parameter group.

[0126] Exemplarily, when the fitness score meets the threshold, the fitness scores of the current optimization parameter group and the second candidate parameter group are compared, and the one with the highest fitness score is taken as the target parameter group.

[0127] In step 206, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the target parameter group.

[0128] In an embodiment, a termination condition can be set for the iteration of the method to prevent endless iteration of the algorithm due to abnormal reasons; the condition for terminating the iteration can be that the number of iterations reaches a threshold or the fitness score reaches a threshold; for example, the iteration number threshold can be set to 8 times, and the score threshold can be set to 0.001, that is, when the number of iterations is the 8th time or when the fitness score is less than 0.001, the iteration is terminated.

[0129] Referring to Figure 3 Fig. 1 shows a flowchart of an embodiment of a logic synthesis parameter optimization method of a circuit of the present application;

[0130] First, the parameter particles are initialized, then the DC tool is applied to perform parallel logic synthesis to obtain the timing score and the area score, then the fitness of the parameter group is evaluated based on the obtained timing score and area score, and the position, speed and iteration number of the corresponding parameter particle are updated according to the evaluation result; then it is checked whether the condition for terminating the iteration is met, if yes, the iteration is stopped and the optimal solution is output, if not, the iteration is continued.

[0131] Based on the initial clock uncertainty parameter and the initial clock conversion time parameter, the embodiment of the application can accurately calculate the optimized clock uncertainty parameter and the clock conversion time parameter by combining with the preset optimization model. This step directly solves the problem of parameter setting depending on experience and lacking of scientificity in the background art, and improves the accuracy and reliability of the clock tree design. Based on the optimized clock uncertainty parameter and the clock conversion time parameter, the timing score and the area score are further determined. The two scores respectively reflect the performance of the clock tree in terms of timing performance and area efficiency. By comprehensively considering the timing and area, the area waste can be minimized on the premise of ensuring the timing performance, and the double optimization of timing and area is realized. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and the clock conversion time parameter. These target parameters provide clear guidance for subsequent clock tree layout and wiring, and ensure the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, which provides strong support for the manufacture of integrated circuits.

[0132] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the application are not limited by the action order described, because according to the embodiments of the application, certain steps can be performed in other order or at the same time. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily necessary for the embodiments of the application.

[0133] Referring to Figure 4 , a structural block diagram of an embodiment of a logic synthesis parameter optimization device of a circuit of the application is shown, which can specifically include the following modules:

[0134] The initial parameter acquisition module 301 is configured to acquire an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and wiring of the clock tree on the arrival time of the clock signal; and the clock conversion time parameter is used to describe the conversion speed of the clock signal in the clock tree;

[0135] The optimization parameter determination module 302 is configured to determine an optimized clock uncertainty parameter and an optimized clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model;

[0136] The comprehensive score determination module 303 is configured to determine a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock conversion time parameter

[0137] The target parameter determination module 304 is configured to determine a target clock uncertainty parameter and a target clock switching time parameter according to the optimized clock uncertainty parameter and the optimized clock switching time parameter when the timing score and the area score meet a preset score condition.

[0138] In an embodiment, the apparatus further comprises:

[0139] An initial parameter group acquisition submodule is configured to determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock switching time parameter, wherein the initial parameter group comprises a clock uncertainty parameter and a clock switching time parameter.

[0140] The initial clock uncertainty parameter and the optimized parameter determination module comprises:

[0141] An optimized parameter group determination submodule is configured to determine an optimized parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model.

[0142] The comprehensive score determination module comprises:

[0143] A comprehensive score group determination submodule is configured to determine a timing score and an area score corresponding to each of the optimized parameter groups.

[0144] The target parameter determination module comprises:

[0145] A target parameter group determination submodule is configured to determine a target parameter group according to the optimized parameter group when the timing score corresponding to the optimized parameter group is greater than a preset timing threshold and the area score corresponding to the optimized parameter group is greater than a preset area threshold.

[0146] A final target parameter determination submodule is configured to determine the target clock uncertainty parameter and the target clock switching time parameter according to the target parameter group.

[0147] In an embodiment, the apparatus further comprises:

[0148] A repeated iteration submodule is configured to return to the step of determining the optimized parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model when the timing score corresponding to the optimized parameter group is less than the preset timing threshold or the area score corresponding to the optimized parameter group is less than the preset area threshold.

[0149] In an embodiment, the repeated iteration submodule comprises:

[0150] The first candidate determining unit is configured to determine a first candidate parameter group according to each of the at least one optimization parameter group and the initial parameter group corresponding thereto, in a case where the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the area score corresponding thereto is less than a preset area threshold.

[0151] The second candidate determining unit is configured to determine a second candidate parameter group according to the at least one optimization parameter group.

[0152] The first optimization iteration unit is configured to return the step of determining the optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model.

[0153] In an embodiment, the optimization parameter group determining submodule comprises:

[0154] The first optimization unit is configured to determine the optimization parameter group corresponding to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0155] The first optimization iteration unit comprises:

[0156] The second optimization iteration subunit is configured to return the step of determining the optimization parameter group corresponding to the at least one first candidate parameter group according to the at least one first candidate parameter group, the second candidate group and the preset optimization model.

[0157] In an embodiment, the target parameter group determining submodule comprises:

[0158] The final target parameter group determining unit is configured to determine a target parameter group according to the optimization parameter group and the second candidate parameter group, in a case where the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding thereto is greater than a preset area threshold.

[0159] In an embodiment, the method further comprises:

[0160] The iteration submodule returns the step of determining the optimization clock uncertainty parameter and the optimization clock transition time parameter according to the initial clock uncertainty parameter, the initial clock transition time parameter and the preset optimization model, in a case where the timing score and the area score do not satisfy a preset score condition.

[0161] Based on the obtained initial clock uncertainty parameter and initial clock conversion time parameter, the embodiment of the application can accurately calculate the optimized clock uncertainty parameter and clock conversion time parameter by combining with the preset optimization model. This step directly solves the problem of parameter setting depending on experience and lacking of scientificity in the background art, and improves the accuracy and reliability of the clock tree design. Based on the optimized clock uncertainty parameter and clock conversion time parameter, the timing score and area score are further determined. The two scores respectively reflect the performance of the clock tree in terms of timing performance and area efficiency. By comprehensively considering the timing and area, the area waste can be maximally reduced under the premise of ensuring the timing performance, and the double optimization of timing and area is realized. Under the condition that the first timing score and the first area score meet the preset score threshold, the target clock uncertainty parameter and the target clock conversion time parameter are determined according to the optimized clock uncertainty parameter and clock conversion time parameter. These target parameters provide clear guidance for subsequent clock tree layout and wiring, and ensure the efficient implementation of the optimization effect. Not only the efficiency of the clock tree design is improved, but also the design cost is reduced, which provides strong support for the manufacture of integrated circuits.

[0162] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts are described in the part of the method embodiment.

[0163] The embodiment of the application further provides an electronic device, comprising:

[0164] The computer program is stored on the memory and can be run on the processor, and when the computer program is executed by the processor, each process of the logic synthesis parameter optimization method embodiment of the circuit is realized, and the same technical effect is achieved. To avoid repetition, details are not described here.

[0165] The embodiment of the application further provides a computer readable storage medium, and a computer program is stored on the computer readable storage medium. When the computer program is executed by the processor, each process of the logic synthesis parameter optimization method embodiment of the circuit is realized, and the same technical effect is achieved. To avoid repetition, details are not described here.

[0166] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0167] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Accordingly, embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present application can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, and the like) embodying computer program instructions.

[0168] Embodiments of the present application are described herein with reference to the Figure 1 one or more functions specified in a flow or multiple flows and / or blocks. Figure 1 means for performing one or more functions specified in a flow or multiple flows and / or blocks.

[0169] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the Figure 1 one or more functions specified in a flow or multiple flows and / or blocks. Figure 1 means for performing one or more functions specified in a flow or multiple flows and / or blocks.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the Figure 1 one or more functions specified in a flow or multiple flows and / or blocks. Figure 1 means for performing one or more functions specified in a flow or multiple flows and / or blocks.

[0171] While preferred embodiments of the present application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description. Therefore, the appended claims are intended to encompass within their scope all such variations and modifications as are included within the scope of the present application.

[0172] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0173] The above describes in detail the circuit logic synthesis parameter optimization method, device, equipment and medium provided by the present application. The principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method of optimizing parameters of logic synthesis of a circuit, characterized by, The method comprises: obtaining an initial clock uncertainty parameter and an initial clock slew time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of a clock tree on the arrival time of a clock signal; and the clock slew time parameter is used to describe the conversion speed of the clock signal in the clock tree; determining an optimized clock uncertainty parameter and an optimized clock slew time parameter according to the initial clock uncertainty parameter, the initial clock slew time parameter and a preset optimization model; determining a timing score and an area score according to the optimized clock uncertainty parameter and the optimized clock slew time parameter; in a case where the timing score and the area score meet a preset score condition, determining a target clock uncertainty parameter and a target clock slew time parameter according to the optimized clock uncertainty parameter and the optimized clock slew time parameter; The method further comprises: determining at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock slew time parameter; the initial parameter group contains a clock uncertainty parameter and a clock slew time parameter; determining an optimized parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model, the preset optimization model being a particle swarm optimization model. determining a corresponding timing score and a corresponding area score for each of the optimized parameter groups; 2. The method of claim 1, wherein, in a case where the timing score corresponding to the optimized parameter group is greater than a preset timing threshold and the area score corresponding to the optimized parameter group is greater than a preset area threshold, determining a target parameter group according to the optimized parameter group; determining the target clock uncertainty parameter and the target clock slew time parameter according to the target parameter group. The method further comprises: in a case where the timing score corresponding to the optimized parameter group is less than the preset timing threshold or the area score corresponding to the optimized parameter group is less than the preset area threshold, returning to the step of determining the optimized parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model. in a case where the timing score corresponding to the optimized parameter group is less than the preset timing threshold or the area score corresponding to the optimized parameter group is less than the preset area threshold, returning to the step of determining the optimized parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model.

3. The method of claim 2, wherein, ​ ​ 4. The method of claim 3, wherein, ​ In a case where the timing score corresponding to the optimization parameter group is less than a preset timing threshold or the area score corresponding to the optimization parameter group is less than a preset area threshold, a first candidate parameter group is determined according to each of the at least one optimization parameter group and the initial parameter group corresponding thereto; A second candidate parameter group is determined according to the at least one optimization parameter group; The step of determining the optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model is returned.

5. The method of claim 4, wherein, The step of determining the optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model includes: The optimization parameter group corresponding to the at least one first candidate parameter group is determined according to the at least one first candidate parameter group, the second candidate parameter group and the preset optimization model. The step of determining the optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model is returned. The step of determining the optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and the preset optimization model is returned.

6. The method of claim 5, wherein, In a case where the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding to the optimization parameter group is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group. In a case where the timing score corresponding to the optimization parameter group is greater than a preset timing threshold and the area score corresponding to the optimization parameter group is greater than a preset area threshold, a target parameter group is determined according to the optimization parameter group and the second candidate parameter group.

7. The method of claim 1, wherein, The method further includes: In a case where the timing score and the area score do not satisfy a preset score condition, the step of determining the optimization clock uncertainty parameter and the optimization clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and the preset optimization model is returned.

8. A logic synthesis parameter optimization apparatus of a circuit, characterized by, The device includes: An initial parameter acquisition module is configured to acquire an initial clock uncertainty parameter and an initial clock conversion time parameter; the clock uncertainty parameter is used to describe the influence of the layout and routing of a clock tree on the arrival time of a clock signal; and the clock conversion time parameter is used to describe the conversion speed of a clock signal in the clock tree. An optimization parameter determination module is configured to determine an optimization clock uncertainty parameter and an optimization clock conversion time parameter according to the initial clock uncertainty parameter, the initial clock conversion time parameter and a preset optimization model. A comprehensive score determination module is configured to determine a timing score and an area score according to the optimization clock uncertainty parameter and the optimization clock conversion time parameter. A target parameter determination module is configured to determine a target clock uncertainty parameter and a target clock conversion time parameter according to the optimization clock uncertainty parameter and the optimization clock conversion time parameter in a case where the timing score and the area score satisfy a preset score condition. The device further includes: An initial parameter group obtaining submodule is configured to determine at least one initial parameter group according to the initial clock uncertainty parameter and the initial clock conversion time parameter; the initial parameter group contains a clock uncertainty parameter and a clock conversion time parameter; The optimization parameter determining module comprises: An optimization parameter group determining submodule is configured to determine an optimization parameter group corresponding to the at least one initial parameter group according to the at least one initial parameter group and a preset optimization model, and the preset optimization model is a particle swarm optimization model.

9. An electronic device, comprising: Comprise: A processor, a memory, and a computer program stored on the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the logic synthesis parameter optimization method of the circuit according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium, and when executed by the processor, implements the steps of the logic synthesis parameter optimization method of the circuit according to any one of claims 1-7.

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