Screening method and device of abnormal Flash chip, medium and equipment

Abstract

The invention provides an abnormal Flash chip screening method and device, a medium and equipment, and the method comprises the steps: carrying out a data abnormal voltage critical test on a to-be-tested chip, and determining a critical voltage value of the to-be-tested chip, the to-be-tested chip being a to-be-tested Flash chip; whether the critical voltage value is larger than a voltage threshold value or not is determined, and the voltage threshold value corresponds to a target gear of the negative bias voltage of the chip to be tested; and if yes, determining that the negative bias voltage of the to-be-tested chip is abnormal. Under the condition that the negative bias voltage cannot be directly measured, safety evaluation is carried out on the negative bias voltage of the to-be-measured chip from the side face through the critical voltage value of the to-be-measured chip, so that abnormal Flash chips are screened, and the accuracy of a screening result is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a method, device, medium and equipment for screening abnormal Flash chips. Background Art

[0002] NOR Flash (also known as NOR flash memory) and NAND Flash (also known as NAND flash memory) have several operations such as erase, write and read, and these operations are actually implemented by applying different bias voltages on the storage cells. Among them, the bias voltage is the voltage applied to make the circuit or electronic device work normally. This voltage is used to ensure that the device or circuit works in the appropriate working area to achieve the required performance.

[0003] Usually, this voltage is raised to a higher voltage through a charge pump and is higher than the maximum VCC supply voltage of the chip. Each memory cell can only withstand a limited number of programming / erasing cycles, so it is particularly important to measure this bias voltage. In order to prevent excessive voltage from damaging the memory device and reducing the reliability of the Flash chip, the bias voltage VPP / VNN needs to be measured to screen out chips with abnormal programming voltage. Summary of the invention

[0004] The object of the present invention is to provide a method, device, medium and equipment for screening abnormal Flash chips to improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a method for screening abnormal Flash chips, the method comprising:

[0007] Performing a data abnormal voltage critical test on a chip to be tested to determine a critical voltage value of the chip to be tested, wherein the chip to be tested is a Flash chip to be tested;

[0008] Determining whether the critical voltage value is greater than a voltage threshold, wherein the voltage threshold corresponds to a target level of a negative bias voltage of the chip to be tested;

[0009] If it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip to be tested is abnormal.

[0010] In a second aspect, an embodiment of the present invention provides a device for screening abnormal Flash chips, the device comprising:

[0011] The first processing unit performs a data abnormal voltage critical test on the chip to be tested to determine a critical voltage value of the chip to be tested, wherein the chip to be tested is a Flash chip to be tested;

[0012] The second processing unit is used to determine whether the critical voltage value is greater than a voltage threshold, wherein the voltage threshold corresponds to a target level of the negative bias voltage of the chip under test; if it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip under test is abnormal.

[0013] In a third aspect, an embodiment of the present invention provides a storage medium having a computer program stored thereon, and the computer program implements the above method when executed by a processor.

[0014] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store one or more programs; when the one or more programs are executed by the processor, the above method is implemented.

[0015] Compared with the prior art, the method, device, medium and equipment for screening abnormal Flash chips provided in the embodiments of the present invention perform a data abnormal voltage critical test on the chip to be tested to determine the critical voltage value of the chip to be tested, wherein the chip to be tested is the Flash chip to be tested; determine whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target gear of the negative bias voltage of the chip to be tested; if it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip to be tested is abnormal. In the method for screening abnormal Flash chips provided in the embodiments of the present invention, when the negative bias voltage cannot be directly measured, the negative bias voltage of the chip to be tested is safety evaluated from the side through the critical voltage value of the chip to be tested, thereby realizing the screening of abnormal Flash chips and ensuring the accuracy of the screening results.

[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A circuit reference schematic diagram provided for an embodiment of the present invention.

[0019] Figure 2 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0020] Figure 3One of the flow charts of the method for screening abnormal Flash chips provided by an embodiment of the present invention.

[0021] Figure 4 The second flowchart of the method for screening abnormal Flash chips provided by the embodiment of the present invention.

[0022] Figure 5 The third flowchart of the method for screening abnormal Flash chips provided by the embodiment of the present invention.

[0023] Figure 6 A fourth flowchart of the method for screening abnormal Flash chips provided in an embodiment of the present invention.

[0024] Figure 7 A schematic diagram of a unit of a device for screening abnormal Flash chips provided by an embodiment of the present invention.

[0025] In the figure: 10 - processor; 11 - memory; 12 - bus; 13 - communication interface; 501 - first processing unit; 502 - second processing unit. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0030] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0031] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] When the transmission gate channel from the negative bias voltage (VNN) of the Flash chip to the ground enters the high-voltage and high-voltage discharge stages during the erasing process, the transmission gate channel will have a momentary high resistance. If the clock interval read and erase state is at the same time as this situation, VNN will be coupled and suddenly changed, the electrostatic discharge (ESD) tube where the clock is located will be turned on / the parasitic transistor will also be turned on, and the high level of the clock will be pulled down by the large leakage, resulting in glitches and 100% erasing failure. In order to solve this problem, VNN needs to be disconnected from IO and grounded, but the derivative impact is that VNN cannot be tested, and the situation that VNN cannot be tested will seriously affect product reliability.

[0034] Please refer to Figure 1 , Figure 1 A circuit reference schematic diagram provided for an embodiment of the present invention. In the figure, CG represents ControlGate, SG represents Select Gate, BL represents Bit Line, Pwell represents P-type well region, VPP represents positive bias voltage, and VNN represents negative bias voltage.

[0035] Please refer to Table 1 and Table 2 below. Table 1 corresponds to the traditional design process, and Table 2 corresponds to the current design process. Among them, VNEG represents the negative power supply voltage, VPOS represents the positive power supply voltage, program represents write, Operation represents operation, and program-biasvoltage represents the bias voltage applied for write.

[0036] Table 1

[0037] Operation SG CG BL Pwell program VNEG VPOS VNEG VNEG program-bias voltage VNN VPP VNN VNN Traditional design technology Measurable Measurable Measurable Measurable

[0038] Table 2

[0039] Operation SG CG BL Pwell program VNEG VPOS VNEG VNEG program-bias voltage VNN VPP VNN VNN Current design process Unmeasurable Measurable Unmeasurable Unmeasurable

[0040] It should be understood that the principle of program is that electrons in the substrate are accumulated to the capture layer through tunneling under the action of an external electric field. There are electrons in the capture layer. If the channel surface is inverted, additional voltage is required. The implementation principle of the abnormal Flash chip screening method provided by the embodiment of the present invention is that FN tunneling occurs through the electric field action of the rated voltage between CG (VPP) and Pwell (VNN), changing the number of electrons stored in the capture layer. That is, when data needs to be stored, the positive voltage of CG makes it easier for electrons to move from the capture layer (Channel) to the floating gate to form a positive charge; on the contrary, when data needs to be erased, the negative voltage of Pwell drives electrons from the floating gate back to the capture layer to restore the original state.

[0041] An embodiment of the present invention provides an electronic device, which may be a test bench or a test server connected to the test bench in communication. Figure 2 , a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12, and the processor 10 is used to execute an executable module stored in the memory 11, such as a computer program.

[0042] The processor 10 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the abnormal Flash chip screening method can be completed by the hardware integrated logic circuit in the processor 10 or the instructions in the form of software. The above-mentioned processor 10 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0043] The memory 11 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0044] The bus 12 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Figure 2 Although only one bidirectional arrow is used in the figure, it does not mean that there is only one bus 12 or only one type of bus 12 .

[0045] The memory 11 is used to store programs, such as programs corresponding to the device for screening abnormal Flash chips. The device for screening abnormal Flash chips includes at least one software function module that can be stored in the memory 11 in the form of software or firmware or fixed in the operating system (OS) of the electronic device. After receiving the execution instruction, the processor 10 executes the program to implement the method for screening abnormal Flash chips.

[0046] Possibly, the electronic device provided by the embodiment of the present invention further includes a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0047] It should be understood that Figure 2The structure shown is only a schematic diagram of a portion of the electronic device. The electronic device may also include Figure 2 More or fewer components as shown, or with Figure 2 Different configurations are shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0048] The method for screening abnormal Flash chips provided by the embodiment of the present invention can be applied to, but not limited to, Figure 2 For detailed procedures, please refer to the electronic equipment shown in Figure 3 ,The screening method for abnormal Flash chips includes: S18, S19, S20 and S21, which are described in detail as follows.

[0049] S18, performing a data abnormality voltage critical test on the chip to be tested to determine the critical voltage value of the chip to be tested.

[0050] The chip to be tested is a Flash chip to be tested.

[0051] When the negative bias voltage VNN of the Flash chip cannot be directly measured due to process design conditions, the critical voltage value (VTP voltage) of the chip under test can be determined by performing a data abnormality voltage critical test on the chip under test. Then, S19 is executed to perform a safety assessment of the negative bias voltage of the chip under test from the side through the critical voltage value (VTP voltage) of the chip under test.

[0052] In an optional implementation, a data abnormality voltage critical test is performed on the chip under test, and the smallest storage unit in the chip under test, that is, the highest VT threshold of the storage unit (cell), is used as the critical voltage value of the chip under test.

[0053] S19, determining whether the critical voltage value is greater than the voltage threshold. If so, executing S20; if not, executing S21.

[0054] The voltage threshold corresponds to a target level of the negative bias voltage of the chip to be tested, and the voltage threshold may be set in advance.

[0055] S20, determining that the negative bias voltage of the chip to be tested is abnormal.

[0056] S21, determine whether the negative bias voltage of the chip under test is normal.

[0057] In the method for screening abnormal Flash chips provided in an embodiment of the present invention, when the negative bias voltage cannot be directly measured, the negative bias voltage of the chip to be tested is safety evaluated from the side through the critical voltage value of the chip to be tested, thereby achieving screening of abnormal Flash chips and ensuring the accuracy of the screening results.

[0058] On the basis of the above, regarding the content in S18, how to accurately obtain the critical voltage value of the chip to be tested to ensure the accuracy of the screening result of abnormal Flash chips, the embodiment of the present invention also provides an optional implementation method, please refer to the following. S18, the step of performing a data abnormal voltage critical test on the chip to be tested and determining the critical voltage value of the chip to be tested, includes: S181, S182, S183 and S184, which are specifically described as follows.

[0059] S181, applying a test voltage to the control gate terminal of the chip to be tested.

[0060] Optionally, a positive stress voltage is applied to the control gate terminal of the chip to be tested, wherein the initial test voltage is a preset fixed value.

[0061] S182, read the data of the target page in the chip to be tested, and determine whether the read result meets expectations. If it meets expectations, execute S183; if it does not meet expectations, execute S184.

[0062] It should be understood that if the read result is consistent with the pre-written result, it is considered to be in line with expectations. For example, if the pre-written data in the target page is 0, if the read result of the target page is also 0, it meets expectations.

[0063] S183, reducing the test voltage according to a preset amplitude.

[0064] After S183, S181 is repeatedly executed to apply a test voltage to the control gate terminal of the chip to be tested. The test voltage is gradually reduced to find a test voltage that does not meet expectations.

[0065] S184, taking the last test voltage as the critical voltage value of the chip to be tested.

[0066] Based on the above, how to determine the voltage threshold to ensure the accuracy of screening abnormal Flash chips, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 4 ,The screening method for abnormal Flash chips also includes S13, S15, S16 and S17, which are described in detail as follows.

[0067] S13, determining DAC output value distribution data of the sample chip according to the product identification of the chip to be tested.

[0068] The sample chip is a Flash chip with the same process as the chip to be tested and capable of directly measuring the negative bias voltage. The product identification of the chip to be tested can be, but is not limited to, the product ID or material number. DAC is an analog quantity. The negative bias voltage of each chip corresponds to an analog quantity level after trimming. There are several chips on the wafer. The same negative bias voltage target value of different chips will correspond to different analog quantity levels, thus presenting a distribution of analog quantity levels.

[0069] It should be understood that the chip to be tested and the Flash chip that can directly measure the negative bias voltage can be associated through product identification. When the product identifications of the two match, it means that the processes of the two are the same, and the Flash chip that can directly measure the negative bias voltage can be used as the sample chip corresponding to the chip to be tested. The sample chip with the same process as the chip to be tested can be directly measured to obtain its corresponding DAC output value. The number of sample chips is greater than the preset number, and the DAC output values ​​of multiple sample chips constitute the DAC output value distribution data of the sample chip.

[0070] It should be noted that the DAC output value distribution data of the sample chip can be obtained by querying the database, or can be directly entered by the staff.

[0071] S15, determining the initial gear position according to the DAC output value distribution data.

[0072] The initial gear is the gear corresponding to the absolute upper limit voltage of the DAC output value distribution data.

[0073] S16, based on the initial gear position, reducing the preset downshift amount to obtain the target gear position.

[0074] The downshift amount can be but is not limited to 4 DAC units.

[0075] S17, determining a voltage threshold according to a target level of the negative bias voltage of the chip to be tested.

[0076] Optionally, in combination with the mapping relationship between the target gear and the voltage threshold, the voltage threshold is determined according to the target gear of the negative bias voltage of the chip to be tested.

[0077] On the basis of the above, regarding how to set the downshift amount, so as to improve the accuracy of the screening result of abnormal Flash chips, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 5 , after determining the DAC output value distribution data of the sample chip according to the product identification of the chip to be tested in S13, the method for screening abnormal Flash chips also includes: S14, which is as follows.

[0078] S14, determining the downshift amount corresponding to the DAC output value distribution data according to the first condition and the second condition.

[0079] The distribution range corresponding to the DAC output value distribution data is the 6sigma distribution range.

[0080] The first condition indicates that the DAC output value distribution data is adjusted according to the downshift amount, and the maximum value in the adjusted DAC output value distribution data (within the positive distribution) does not exceed the maximum value in the DAC output value distribution data before the adjustment.

[0081] The second condition indicates that the DAC output value distribution data is adjusted according to the downshift amount, and the difference between the maximum value in the adjusted DAC output value distribution data and the target value in the DAC output value distribution data before the adjustment is less than a preset value. The target value may be the maximum value in the DAC output value distribution data before the adjustment.

[0082] It should be understood that for Flash chips that cannot directly measure negative bias voltage, the distribution of their DAC values ​​has the following characteristics: the data is normally distributed but relatively scattered, with a large sigma and abnormal outliers; for Flash chips that can directly measure negative bias voltage, the distribution of their DAC values ​​has the following characteristics: the data distribution is extremely convergent, with a small sigma, small positive and negative deviations, and all values ​​are within the expected distribution range.

[0083] In an optional implementation, for a Flash chip that cannot directly measure the negative bias voltage, there is still a voltage value corresponding to the DAC output value of the Die of -1.875v, which exceeds the main median -1.7v and the maximum target value of the Flash chip that can directly measure the negative bias voltage. Therefore, the bias voltage of the Die is abnormal.

[0084] After analyzing the Flash chips that can directly measure the negative bias voltage, it is found that each DAC unit corresponds to about 3% of the actual voltage change. For Flash chips that cannot directly measure the negative bias voltage, if the expected safety voltage is -1.72V, the voltage threshold may need to be set at the gear corresponding to -1.7V, but now it is necessary to downgrade and reduce the voltage threshold to the corresponding target gear, for example, to -1.6V (i.e. 1.72V-4×0.03V) to ensure safety. It should be noted that the reduction is the numerical value, which has nothing to do with positive or negative.

[0085] The embodiment of the present invention further provides an optional implementation manner, S16, based on the initial gear position, reducing the preset downshift amount to obtain the target gear position, the method for screening abnormal Flash chips also includes: S30, as follows.

[0086] S30 , increasing the bias voltage of the target test item according to the downshift amount, wherein the target test item is a test item whose bias voltage can be precisely trimmed.

[0087] It should be understood that the increase in the bias voltage of the target test item corresponds to the downshift amount.

[0088] For test items that can accurately trim the bias voltage, the bias voltage of the target test item is increased to offset the effect of the negative bias voltage reduction.

[0089] In order to improve the screening efficiency, the present invention also provides an optional implementation method, please refer to Figure 6 ,The screening method for abnormal Flash chips also includes: S11 and S12, which are specifically as follows.

[0090] S11, determining whether the chip to be tested can directly measure the negative bias voltage according to the product identification of the chip to be tested. If yes, execute S12; if no, execute S13.

[0091] Optionally, whether the chip to be tested can directly measure the negative bias voltage is determined by querying whether the product identification table that can directly measure the negative bias voltage includes the product identification of the chip to be tested.

[0092] S12, directly measuring the negative bias voltage of the chip to be tested, and determining whether the negative bias voltage of the chip to be tested is abnormal according to the negative bias voltage measurement result.

[0093] S13, determining DAC output value distribution data of the sample chip according to the product identification of the chip to be tested.

[0094] See also Figure 7 , Figure 7 An abnormal Flash chip screening device is provided in an embodiment of the present invention. Optionally, the abnormal Flash chip screening device is applied to the electronic device described above.

[0095] The device for screening abnormal Flash chips includes: a first processing unit 501 and a second processing unit 502 .

[0096] The first processing unit performs a data abnormal voltage critical test on the chip to be tested to determine a critical voltage value of the chip to be tested, wherein the chip to be tested is a Flash chip to be tested;

[0097] The second processing unit is used to determine whether the critical voltage value is greater than a voltage threshold, wherein the voltage threshold corresponds to a target level of the negative bias voltage of the chip under test; if it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip under test is abnormal.

[0098] Optionally, the second processing unit 502 may execute the above-mentioned S19, S20 and S21; the first processing unit 501 may execute the above-mentioned other steps.

[0099] It should be noted that the abnormal Flash chip screening device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effect. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding content in the above embodiment.

[0100] The embodiment of the present invention further provides a storage medium, which stores computer instructions and programs, and when the computer instructions and programs are read and run, the method for screening abnormal Flash chips in the above embodiment is executed. The storage medium may include a memory, a flash memory, a register, or a combination thereof.

[0101] The following provides an electronic device, which may be a test bench or a test server connected to the test bench in communication. Figure 2 As shown, the above-mentioned method for screening abnormal Flash chips can be implemented; specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 can be a CPU. The memory 11 is used to store one or more programs. When the one or more programs are executed by the processor 10, the above-mentioned method for screening abnormal Flash chips is executed.

[0102] In summary, the embodiments of the present invention provide a method, device, medium and equipment for screening abnormal Flash chips, which performs a data abnormal voltage critical test on the chip to be tested to determine the critical voltage value of the chip to be tested, wherein the chip to be tested is the Flash chip to be tested; determines whether the critical voltage value is greater than the voltage threshold, wherein the voltage threshold corresponds to the target gear of the negative bias voltage of the chip to be tested; if it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip to be tested is abnormal. In the method for screening abnormal Flash chips provided by the embodiments of the present invention, when the negative bias voltage cannot be directly measured, the negative bias voltage of the chip to be tested is safety evaluated from the side through the critical voltage value of the chip to be tested, thereby realizing the screening of abnormal Flash chips and ensuring the accuracy of the screening results.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0104] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for screening abnormal Flash chips, characterized in that: The method comprises: Performing a data abnormal voltage critical test on a chip to be tested to determine a critical voltage value of the chip to be tested, wherein the chip to be tested is a Flash chip to be tested; Determining whether the critical voltage value is greater than a voltage threshold, wherein the voltage threshold corresponds to a target level of a negative bias voltage of the chip to be tested; If it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip to be tested is abnormal.

2. The method for screening abnormal Flash chips according to claim 1, characterized in that: The step of performing a data abnormal voltage critical test on the chip to be tested to determine the critical voltage value of the chip to be tested includes: Apply a test voltage to the control gate terminal of the chip to be tested; Reading data of a target page in the chip to be tested to determine whether the reading result meets expectations; If it is as expected, the test voltage is reduced according to the preset amplitude, and the preset test voltage is repeatedly applied to the control gate terminal of the chip to be tested; If it does not meet expectations, the last test voltage will be used as the critical voltage value of the chip under test.

3. The method for screening abnormal Flash chips according to claim 1, characterized in that: The method further comprises: Determine the DAC output value distribution data of the sample chip according to the product identification of the chip to be tested; wherein the sample chip is a Flash chip with the same process as the chip to be tested and capable of directly measuring the negative bias voltage; Determine a preliminary gear position according to the DAC output value distribution data, wherein the preliminary gear position is a gear position corresponding to an absolute value upper limit voltage of the DAC output value distribution data; On the basis of the initial gear position, the preset downshift amount is reduced to obtain the target gear position.

4. The method for screening abnormal Flash chips according to claim 3, characterized in that: After determining the DAC output value distribution data of the sample chip according to the product identification of the chip to be tested, the method further includes: Determining the downshift amount corresponding to the DAC output value distribution data according to the first condition and the second condition; The first condition indicates that the DAC output value distribution data is adjusted according to the downshift amount, and the maximum value in the adjusted DAC output value distribution data does not exceed the maximum value in the DAC output value distribution data before the adjustment; The second condition indicates that the DAC output value distribution data is adjusted according to the downshift amount, and the difference between the maximum value in the adjusted DAC output value distribution data and the target value in the DAC output value distribution data before the adjustment is less than a preset value.

5. The method for screening abnormal Flash chips according to claim 3, characterized in that: After reducing the preset downshift amount based on the initial gear position to obtain the target gear position, the method further includes: The bias voltage of the target test item is increased according to the downshift amount, wherein the target test item is a test item of which the bias voltage can be accurately trimmed.

6. The method for screening abnormal Flash chips according to claim 3, characterized in that: After reducing the preset downshift amount based on the initial gear position to obtain the target gear position, the method further includes: The voltage threshold is determined according to a target level of the negative bias voltage of the chip to be tested.

7. The method for screening abnormal Flash chips according to claim 1, characterized in that: The method further comprises: Determining whether the chip to be tested can directly measure a negative bias voltage according to a product identification of the chip to be tested; If yes, directly measure the negative bias voltage of the chip to be tested, and determine whether the negative bias voltage of the chip to be tested is abnormal according to the negative bias voltage measurement result.

8. A device for screening abnormal Flash chips, characterized in that: The device comprises: The first processing unit performs a data abnormal voltage critical test on the chip to be tested to determine a critical voltage value of the chip to be tested, wherein the chip to be tested is a Flash chip to be tested; The second processing unit is used to determine whether the critical voltage value is greater than a voltage threshold, wherein the voltage threshold corresponds to a target level of the negative bias voltage of the chip under test; if it is greater than the voltage threshold, it is determined that the negative bias voltage of the chip under test is abnormal.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: A processor and a memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

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