Manufacturing method of interconnection structure and semiconductor device

Abstract

The invention discloses a manufacturing method of an interconnection structure and a semiconductor device, and the method comprises the steps: sequentially forming an etching stop layer and a second oxide layer on a first oxide layer, and enabling the first oxide layer to comprise a first connection structure; forming a first contact hole penetrating through the second oxide layer and the etching stop layer; detecting an error value between the bottom of the first contact hole and the top of the corresponding first connection structure; performing transverse etching on the bottom of the first contact hole, so that the surface of the corresponding first connection structure is exposed through the bottom of the second contact hole; and filling the second contact hole with a conductive material to form a second connection structure. According to the manufacturing method of the interconnection structure and the semiconductor device provided by the invention, the transverse size of the bottom surface of the second connection structure is increased, so that the second connection structure and the first connection structure which cannot be communicated originally are communicated, and the yield of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing an interconnection structure and a semiconductor device. Background Art

[0002] Semiconductor chips include multiple layers of overlapping circuits, each of which is formed by photolithography, which is the process of developing the pattern on the mask onto the mask layer and then transferring it from the mask layer to the wafer. In order to ensure the performance of semiconductor chips, it is necessary to ensure that each front layer and the back layer are aligned with the overlay, such as Figure 1 As shown, due to the influence of marking, measurement, etching, etc., semiconductor chips cannot be 100% aligned layer by layer.

[0003] In order to ensure that each front and back layer of the semiconductor chip has high overlay accuracy, after the development of the photolithography process is completed, a post-development inspection (After Develop Inspection, ADI) is required, and after the etching process is completed, a post-etching inspection (After etch Inspection, AEI) is required.

[0004] However, as the size of devices decreases, the alignment between the conductive structures of the back layer and the conductive structures of the front layer in semiconductor devices becomes increasingly challenging. Errors often occur during overlay alignment, which makes it impossible for the conductive structures of the back layer to be connected to the conductive structures of the front layer. Figure 2 and Figure 3 As shown, the yield loss of semiconductor devices is caused. Summary of the invention

[0005] In view of the above problems, the present application provides a method for manufacturing an interconnect structure and a semiconductor device, aiming to improve the yield of the semiconductor device by increasing the lateral size of the bottom surface of the second connection structure so that the second connection structure that was originally unable to connect can be connected to the first connection structure.

[0006] According to a first aspect of the present invention, a method for manufacturing an interconnect structure is provided, comprising: sequentially forming an etch stop layer and a second oxide layer on a first oxide layer, wherein the first oxide layer includes a first connection structure; forming a first contact hole penetrating the second oxide layer and the etch stop layer; detecting an error value between a bottom of the first contact hole and a top of the corresponding first connection structure; laterally etching the bottom of the first contact hole so that a surface of the corresponding first connection structure is exposed through the bottom of the second contact hole, and the second contact hole is formed after the bottom of the first contact hole is laterally etched; and filling the second contact hole with a conductive material to form a second connection structure, wherein a size of the laterally etched bottom of the first contact hole is not less than the error value.

[0007] Optionally, the step of laterally etching the bottom of the first contact hole includes: using an etching process to laterally expand the bottom of the first contact hole to form the second contact hole; detecting whether the bottom of the second contact hole exposes the upper surface of the first connection structure; if the bottom of the second contact hole does not expose the upper surface of the first connection structure, repeating the aforementioned steps of lateral expansion and detection; if the bottom of the second contact hole exposes the upper surface of the first connection structure, the lateral expansion of the bottom of the first contact hole is completed.

[0008] Optionally, after the bottom of the first contact hole is laterally etched, the lateral dimension of the first contact hole in the etch stop layer is enlarged, and the bottom radius of the second contact hole is increased by a third distance compared to the bottom radius of the first contact hole, and the third distance is not less than the error value.

[0009] Optionally, a cross section of the first contact hole is an inverted trapezoid that is wider at the top and narrower at the bottom.

[0010] Optionally, a bottom diameter of the second contact hole is smaller than or equal to a top diameter of the second contact hole.

[0011] Optionally, a bottom radius of the second contact hole is smaller than half of a distance between centers of two adjacent second contact holes.

[0012] Optionally, when etching the etch stop layer, a phosphoric acid solution or unbiased sulfur hexafluoride gas is used as an etchant.

[0013] Optionally, between the steps of forming a first contact hole penetrating the second oxide layer and the etch stop layer and detecting the error value between the bottom of the first contact hole and the corresponding top of the first connection structure, it also includes: detecting whether the bottom of the first contact hole exposes the upper surface of the first connection structure; if the bottom of the first contact hole does not expose the upper surface of the first connection structure, detecting the error value between the bottom of the first contact hole and the corresponding top of the first connection structure.

[0014] Optionally, before the step of sequentially forming an etch stop layer and a second oxide layer on the first oxide layer, the method further includes: forming a first oxide layer on the semiconductor structure; and forming a first connection structure in the first oxide layer, wherein the number of the first connection structure is at least one.

[0015] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first oxide layer; a first connecting structure located in the first oxide layer, the upper surface of the first oxide layer exposing the upper surface of the first connecting structure; an etch stop layer located on the first oxide layer; a second oxide layer located on the etch stop layer; a second connecting structure penetrating the second oxide layer and the etch stop layer, the bottom of the second connecting structure being connected to the upper surface of the first connecting structure; wherein the diameter of a portion of the second connecting structure located in the etch stop layer is greater than the bottom diameter of a portion of the second connecting structure located in the second oxide layer.

[0016] According to the manufacturing method of the interconnect structure and the semiconductor device of the embodiment of the present invention, a first connection structure is formed in a first oxide layer, and then an etching stop layer and a second oxide layer are formed on the first oxide layer. After forming a first contact hole penetrating the second oxide layer and the etching stop layer, a post-etching inspection method is used to determine whether the first contact hole exposes the upper surface of the corresponding first connection structure. If it is not exposed, the error value is detected. According to the detected error value, the bottom of the first contact hole located in the etching stop layer is transversely etched to increase the transverse dimension of the bottom of the first contact hole, so that the second contact hole with the enlarged transverse dimension of the bottom can expose part of the surface of the first connection structure, so that the conductive material subsequently deposited in the second contact hole can contact the first connection structure to realize the electrical connection between the first connection structure and the second connection structure. The method of enlarging the transverse dimension of the bottom of the first contact hole after forming the first contact hole enables the originally disconnected semiconductor device to realize the electrical connection, thereby improving the yield of the device.

[0017] Furthermore, in the manufacturing method of the interconnect structure and the semiconductor device of the embodiment of the present invention, anisotropic etching is used in the process of lateral etching of the bottom of the first contact hole, so that the etching process only occurs in the etch stop layer. For the entire contact hole, only the lateral size of the bottom of the contact hole changes, while the size of the contact hole in the second oxide layer does not change, thereby reducing the probability of unnecessary connection between adjacent second connection structures.

[0018] Furthermore, in the method for manufacturing the interconnect structure and the semiconductor device of the embodiment of the present invention, in the process of laterally etching the bottom of the contact hole by anisotropic etching, the etching distance is, for example, greater than the error value, but the bottom diameter of the second contact hole is less than or equal to the top diameter of the second contact hole, so that the connectivity problem between adjacent contact holes caused by the expansion of the bottom lateral dimension can be avoided. In another embodiment, the bottom radius of the second contact hole is less than half of the distance between the centers of two adjacent second contact holes, so as to avoid the connectivity problem between adjacent contact holes caused by the expansion of the bottom lateral dimension.

[0019] Furthermore, in the manufacturing method of the interconnect structure and the semiconductor device of the embodiment of the present invention, in the process of lateral etching of the bottom of the first contact hole, a step-by-step etching and detection method is adopted, and the contact hole is detected after each etching. On the one hand, it is confirmed whether the bottom of the second contact hole after etching exposes the upper surface of the first connection structure. On the other hand, the etching size can be well controlled to reduce the probability of connection between adjacent second contact holes and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which: Figure 1 A schematic diagram showing the interconnection structure of an ideal semiconductor device; Figure 2 A schematic diagram showing a structure in which an error occurs in the interconnection structure of a semiconductor device in the prior art; Figure 3 A schematic diagram of an electron microscope structure showing an error in the interconnection structure of a semiconductor device in the prior art is shown; Figure 4 A flow chart showing a method for manufacturing an interconnect structure according to an embodiment of the present invention; Figures 5 to 8 A cross-sectional view of a semiconductor device at various stages in a method for manufacturing an interconnect structure according to a first embodiment of the present invention is shown; Fig. 9 FIG. 4 is a schematic structural diagram of an interconnection structure according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when it is described that an element is "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.

[0025] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. The present application can be presented in various forms, some examples of which will be described below.

[0026] This application may be presented in a variety of forms, some examples of which are described below.

[0027] Figure 4 A flow chart showing a method for manufacturing an interconnect structure according to an embodiment of the present invention; Figures 5 to 8 1 and 2. Cross-sectional views of a semiconductor device at various stages in a method for manufacturing an interconnect structure according to a first embodiment of the present invention are shown.

[0028] The interconnection structure refers to the structure that connects different devices, circuits and functional modules together. These connections are usually realized through materials such as metal wires, multi-layer metal layers, and multi-layer insulation layers to achieve signal transmission and electrical connection between various parts inside the device. The interconnection structure plays a vital role in integrated circuits, which determines the performance, power consumption and reliability of the device. A well-designed interconnection structure can improve the performance and reliability of the device while reducing power consumption and cost.

[0029] In the present application, the interconnection structure refers to, for example, a connection structure between a conductive channel and other conductive channels, different devices, circuits, and functional modules, and of course, it can also be a connection between a conductive channel and other structures commonly used in the art. That is, the interconnection structure generally refers to a connection between two structures. In the present application, one of the two structures is, for example, a conductive channel, and the other structure is not limited, and can be any structure that needs to be electrically connected to other structures.

[0030] In this embodiment, the semiconductor device refers to an electronic device made of semiconductor materials, which is used to control the transmission of current, voltage and signal. Specifically, the semiconductor device includes a first connection structure and a second connection structure that need to be electrically connected. Specifically, the semiconductor device includes, for example, a diode, a transistor, a field effect transistor, an integrated circuit, etc.

[0031] refer to Figures 4 to 8 , the manufacturing method of the interconnect structure of the present application comprises the following steps: Step S201: forming a first oxide layer, and forming a first connection structure in the first oxide layer.

[0032] In this step, refer to Figure 5 , using a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., to deposit oxide on the semiconductor structure (not shown in the figure) to form a first oxide layer 110.

[0033] Then, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching, is used to etch the first oxide layer 110 through a mask to form a through hole in the first oxide layer 110 .

[0034] Furthermore, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to form a first connection structure 140 in the through hole of the first oxide layer 110 .

[0035] In this embodiment, the semiconductor structure may be a substrate or a semiconductor having a partial device structure formed thereon. If the semiconductor structure is a substrate, the first connection structure may be, for example, an active area (AA), a conductive channel, or the like.

[0036] In other embodiments, a substrate may be used to replace the first oxide layer 110. Figure 5 110 is a substrate, and 140 may be an active region or other device structures in the substrate.

[0037] Step S202: forming an etch stop layer and a second oxide layer in sequence on the first oxide layer.

[0038] In this step, refer to Figure 5, a deposition process such as physical vapor deposition, chemical vapor deposition, etc. is used to deposit nitride on the first oxide layer 110 to form an etch stop layer 120. Further, an oxide material is deposited on the etch stop layer 120 to form a second oxide layer 130 by a deposition process such as physical vapor deposition, chemical vapor deposition, etc.

[0039] In this embodiment, the material of the etch stop layer 120 is, for example, silicon nitride. The etch stop layer 120 can improve the selectivity of etching in subsequent steps, so that etching is only performed in the second oxide layer 130 on the etch stop layer, avoiding over-etching and protecting the first oxide layer 110 below the etch stop layer 120 from being damaged.

[0040] Step S203: forming a first contact hole penetrating the etch stop layer and the second oxide layer.

[0041] In this step, refer to Figure 5 , an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching, is used to etch the second oxide layer 130 and the etch stop layer 120 through a mask to form a first contact hole 101 in the second oxide layer 130 and the etch stop layer 120.

[0042] In this embodiment, the cross-sectional shape of the first contact hole 101 is, for example, an inverted trapezoid, which has a cross-sectional size that is wide at the top and narrow at the bottom. Specifically, the diameter of the first contact hole 101 at the upper surface of the second oxide layer 130 is a first distance D1, and the diameter at the upper surface of the first oxide layer 110 is a second distance D2, and the first distance D1 is greater than the second distance D2.

[0043] In a good device, the first contact hole 101 needs to correspond to the position of the first connection structure in the first oxide layer 110 , so that the bottom surface of the first contact hole 101 exposes the upper surface of the first connection structure 140 .

[0044] Step S204: detecting an error value between the bottom of the contact hole and the top of the corresponding first connection structure.

[0045] In this step, refer to Figure 6 The overlay offset between the first contact hole 101 and the first connection structure 140 is detected and measured by a post-etch inspection (AEI) method to obtain an error value D3.

[0046] After etch inspection (AEI) is a process that checks the critical dimensions of the product during the etching process to ensure the quality and accuracy of the etching process.

[0047] In this embodiment, when the bottom of the first contact hole 101 does not expose a portion of the upper surface of the corresponding first connection structure 140, it means that after the conductive material is filled in the first contact hole 101, the electrical connection between the conductive material and the first connection structure 140 cannot be achieved. Therefore, there is an error between the first contact hole 101 and the first connection structure.

[0048] In this embodiment, the error value D3 refers to, for example, the minimum distance between the bottom surface of the first contact hole 101 and the upper surface of the first connection structure 140, that is, the distance between the first connection structure 140 and the nearest edge of the first contact hole 101 in the upper surface of the first oxide layer 110, such as Figure 6 as shown in .

[0049] Step S205: performing transverse etching on the bottom of the first contact hole, so that the surface of the corresponding first connection structure is exposed through the bottom of the second contact hole.

[0050] In this step, refer to Figure 7 , a high selectivity anisotropic etching method is used to laterally etch the bottom of the first contact hole 101 in the etch stop layer 120, so that the lateral size of the first contact hole 101 in the etch stop layer 120 is enlarged. Specifically, the bottom radius of the first contact hole 101 increases by a third distance D4, and the third distance D4 is not less than the error value D3, that is, the lateral etched size of the bottom of the first contact hole 101 is not less than the error value D3. In order to facilitate the description of the contact hole before and after the bottom lateral etching, the contact hole after the lateral etching is referred to as the second contact hole 102, the portion of the second contact hole 102 located in the second oxide layer 130 is referred to as the upper portion of the second contact hole 102, and the portion of the second contact hole 102 located in the etch stop layer 120 is referred to as the lower portion of the second contact hole 102.

[0051] In this embodiment, the anisotropic etching is performed by wet etching, for example, and the wet etching solution is a phosphoric acid solution H 3 PO 4 , gas phase etching can also be used, and the reaction gas in the gas phase etching is, for example, sulfur hexafluoride SF6 gas without bias. This is because the phosphoric acid solution H 3 PO 4 The sulfur hexafluoride SF6 gas has a high selectivity for the etching stop layer of the silicon nitride SiN material. When the bottom surface of the contact hole is laterally expanded, the phosphoric acid solution H 3 PO 4 The sulfur hexafluoride SF6 gas does not easily react with the oxide layer, but easily reacts with the silicon nitride SiN material, so that the portion of the contact hole located in the second oxide layer 130 is little affected during the etching process to expand the bottom surface size of the contact hole.

[0052] The third distance D4 increased by the lower portion of the second contact hole 102 during the lateral etching process is greater than the error value D3 between the first contact hole 101 and the first connection structure 140 measured in the above step, so the bottom surface of the second contact hole 102 can expose the upper surface of the first connection structure. Figure 7 As shown in the dashed circle A in .

[0053] In the process of lateral etching to form the lower part of the second contact hole 102, a step-by-step etching method can be used to gradually expand the size of the lower part of the second contact hole 102 laterally, thereby avoiding excessive expansion of the size of the lower part of the second contact hole 102. In the step-by-step etching process, the lateral size of the lower part of the second contact hole 102 is first expanded by an etching process, and then it is detected whether the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102; if not, the lateral size of the lower part of the second contact hole 102 is secondarily expanded by an etching process, and then it is detected whether the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102; the steps of expansion and detection are repeated for many times until the upper surface of the first connection structure 140 is exposed through the lower part of the second contact hole 102, and the exposed size is not less than a preset value.

[0054] Among them, in the step-by-step etching process, the semiconductor structure after each etching is inspected using commonly used inspection techniques in semiconductor manufacturing processes, such as scanning electron microscopy (SEM) and post-etching inspection (AEI), to determine whether the lower portion of the second contact hole 102 exposes the upper surface of the first connection structure 140, and to detect whether there is any residue during the etching process.

[0055] By using the step-by-step etching and detection method to expand the lateral size of the lower portion of the second contact hole 102, the lateral size of the lower portion of the second contact hole 102 can be more accurately controlled, and the problem of connection between the lower portions of adjacent second contact holes 102 can be reduced. In addition, it is also possible to determine whether there is any etching residue through the monitoring step after each etching.

[0056] Furthermore, the diameter of the lower portion of the second contact hole 102 located on the upper surface of the first oxide layer 101 is the fourth distance (D2+2D4), and the diameter of the top surface of the second contact hole 102 located on the upper surface of the second oxide layer 130 is the same as the diameter of the top surface of the first contact hole 101, both being the first distance D1. In order to ensure that there is no short circuit between the lower portions of adjacent contact holes in the second oxide layer 130, in a preferred embodiment, the fourth distance (D2+2D4) of the bottom diameter of the second contact hole 102 is limited to be ≤ the first distance D1 of the top diameter of the second contact hole 102.

[0057] Step S206: filling the second contact hole with a conductive material.

[0058] In this step, refer to Figure 8 , a deposition process such as physical vapor deposition, chemical vapor deposition, etc. is used to fill the second contact hole 102 with a conductive material, and a surface planarization process is performed to form a second connection structure 250 in the second contact hole 102 .

[0059] The diameter of the portion of the second connection structure 250 located in the etch stop layer 120 is laterally enlarged, so that the first connection structure 140 and the second connection structure 250 that were originally unconnectable can be connected, that is, even if there is an error, it can be remedied, thereby improving the yield of the device.

[0060] Furthermore, between step S203 and step S204 of this embodiment, the following steps may be further included: Step S2031: Detect whether the bottom of the first contact hole exposes the upper surface of the first connection structure.

[0061] Although there is an offset during the etching process, the offset also varies in size. When there is no offset, the bottom of the first contact hole 101 exposes the upper surface of the first connection structure 140; when the offset is small, the bottom of the first contact hole 101, for example, exposes part of the upper surface of the first connection structure 140 and part of the upper surface of the first oxide layer 110; when the offset is large, the bottom of the first contact hole 101, for example, exposes the upper surface of the first oxide layer 110.

[0062] Therefore, in this step, whether to perform step S204 is determined by detecting whether the bottom of the first contact hole 101 exposes the upper surface of the first connection structure 140. Specifically, if the bottom of the first contact hole 101, for example, exposes the upper surface of the first oxide layer 110, that is, the upper surface of the first connection structure 140 is not exposed, step S204 is performed.

[0063] Fig. 9 FIG. 4 is a schematic structural diagram of an interconnection structure according to a second embodiment of the present invention.

[0064] refer to Fig. 9 In this embodiment, in order to increase the contact area between the second connection structure 250 and the first connection structure 140, the third distance D4 of the lateral etching of the etch stop layer 120 can be appropriately increased while determining the distance between adjacent first contact holes 101 between the upper surfaces of the second oxide layer 130.

[0065] Specifically, in one embodiment, the distance between adjacent first contact holes 101 on the upper surface of the second oxide layer 130 refers to, for example, the distance between the centers of the two adjacent contact holes, and the fifth distance D5 refers to, for example, half of the distance between the centers of the two adjacent contact holes. It can be considered that as long as the fourth distance (1 / 2D2+D4) of the bottom radius of the second contact hole 102 is limited to ≤ the fifth distance D5, there will be no short circuit problem between adjacent second connection structures. At this time, the fourth distance (1 / 2D2+D4) of the bottom radius of the second contact hole 102 is greater than the first distance D1 of the top radius of the second contact hole 102.

[0066] Of course, during the lateral etching of the contact hole located in the etch stop layer 120, the correspondence between the contact hole and the corresponding first connection structure 140 must be ensured to avoid the problem of a contact hole exposing the upper surface of the first connection structure 140 corresponding to the adjacent contact hole.

[0067] The present application also provides a semiconductor device, including an interconnect structure formed by the aforementioned method for manufacturing an interconnect structure. Specifically, the semiconductor device includes: a first oxide layer 110; a first connection structure 140, located in the first oxide layer 110, the upper surface of the first oxide layer 110 exposes the upper surface of the first connection structure 140; an etch stop layer 120, located on the first oxide layer 110; a second oxide layer 130, located on the etch stop layer 120; a second connection structure 250, penetrating the second oxide layer 130 and the etch stop layer 120, the bottom of the second connection structure 250 is connected to the upper surface of the first connection structure 140; wherein the diameter of the portion of the second connection structure 250 located in the etch stop layer 120 is greater than the bottom diameter of the portion of the second connection structure 250 located in the second oxide layer 130.

[0068] According to the manufacturing method of the interconnect structure and the semiconductor device of the embodiment of the present invention, a first connection structure is formed in a first oxide layer, and then an etching stop layer and a second oxide layer are formed on the first oxide layer. After forming a first contact hole penetrating the second oxide layer and the etching stop layer, a post-etching inspection method is used to determine whether the first contact hole exposes the upper surface of the corresponding first connection structure. If it is not exposed, the error value is detected. According to the detected error value, the bottom of the first contact hole located in the etching stop layer is transversely etched to increase the transverse dimension of the bottom of the first contact hole, so that the second contact hole with the enlarged transverse dimension of the bottom can expose part of the surface of the first connection structure, so that the conductive material subsequently deposited in the second contact hole can contact the first connection structure to realize the electrical connection between the first connection structure and the second connection structure. The method of enlarging the transverse dimension of the bottom of the first contact hole after forming the first contact hole enables the originally disconnected semiconductor device to realize the electrical connection, thereby improving the yield of the device.

[0069] Furthermore, in the manufacturing method of the interconnect structure and the semiconductor device of the embodiment of the present invention, anisotropic etching is used in the process of lateral etching of the bottom of the first contact hole, so that the etching process only occurs in the etch stop layer. For the entire contact hole, only the lateral size of the bottom of the contact hole changes, while the size of the contact hole in the second oxide layer does not change, thereby reducing the probability of unnecessary connection between adjacent second connection structures.

[0070] Furthermore, in the method for manufacturing the interconnect structure and the semiconductor device of the embodiment of the present invention, in the process of laterally etching the bottom of the contact hole by anisotropic etching, the etching distance is, for example, greater than the error value, but the bottom diameter of the second contact hole is less than or equal to the top diameter of the second contact hole, so that the connectivity problem between adjacent contact holes caused by the expansion of the bottom lateral dimension can be avoided. In another embodiment, the bottom radius of the second contact hole is less than half of the distance between the centers of two adjacent second contact holes, so as to avoid the connectivity problem between adjacent contact holes caused by the expansion of the bottom lateral dimension.

[0071] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing an interconnect structure, comprising: forming an etch stop layer and a second oxide layer in sequence on the first oxide layer, wherein the first oxide layer includes a first connection structure; forming a first contact hole penetrating the second oxide layer and the etch stop layer; Detecting an error value between a bottom of the first contact hole and a top of the corresponding first connection structure; Performing transverse etching on the bottom of the first contact hole so that the surface of the corresponding first connection structure is exposed through the bottom of the second contact hole, and the second contact hole is formed after the bottom of the first contact hole is transversely etched; filling the second contact hole with a conductive material to form a second connection structure, Wherein, a lateral etching dimension of the bottom of the first contact hole is not less than the error value.

2. The method for manufacturing an interconnect structure according to claim 1, wherein: The step of laterally etching the bottom of the first contact hole comprises: Using an etching process to laterally expand the bottom of the first contact hole to form the second contact hole; detecting whether the bottom of the second contact hole exposes the upper surface of the first connection structure; If the bottom of the second contact hole does not expose the upper surface of the first connection structure, repeating the aforementioned lateral expansion and detection steps; If the bottom of the second contact hole exposes the upper surface of the first connection structure, the lateral expansion of the bottom of the first contact hole is completed.

3. The method for manufacturing an interconnect structure according to claim 2, wherein: After the bottom of the first contact hole is laterally etched, the lateral dimension of the first contact hole in the etch stop layer is enlarged, and the bottom radius of the second contact hole is increased by a third distance compared to the bottom radius of the first contact hole, and the third distance is not less than the error value.

4. The method for manufacturing an interconnect structure according to claim 3, wherein: The cross section of the first contact hole is an inverted trapezoid that is wider at the top and narrower at the bottom.

5. The method for manufacturing an interconnect structure according to claim 4, wherein: A bottom diameter of the second contact hole is smaller than or equal to a top diameter of the second contact hole.

6. The method for manufacturing an interconnect structure according to claim 4, wherein: The bottom radius of the second contact hole is smaller than half of the distance between the centers of two adjacent second contact holes.

7. The method for manufacturing an interconnect structure according to claim 1, wherein: When etching the etch stop layer, the etchant is a phosphoric acid solution or a non-biased sulfur hexafluoride gas.

8. The method for manufacturing an interconnect structure according to claim 1, wherein: Between the steps of forming a first contact hole penetrating the second oxide layer and the etch stop layer and detecting an error value between a bottom of the first contact hole and a top of the corresponding first connection structure, the method further includes: detecting whether the bottom of the first contact hole exposes the upper surface of the first connection structure; If the bottom of the first contact hole does not expose the upper surface of the first connection structure, an error value between the bottom of the first contact hole and the corresponding top of the first connection structure is detected.

9. The method for manufacturing an interconnect structure according to claim 1, wherein: Before the step of sequentially forming an etch stop layer and a second oxide layer on the first oxide layer, the method further comprises: forming a first oxide layer on the semiconductor structure; forming a first connection structure in the first oxide layer, Wherein, the number of the first connection structure is at least one.

10. A semiconductor device comprising: First oxide layer; A first connection structure is located in the first oxide layer, and an upper surface of the first oxide layer exposes an upper surface of the first connection structure; An etch stop layer, located on the first oxide layer; a second oxide layer, located on the etch stop layer; a second connection structure, penetrating the second oxide layer and the etch stop layer, wherein the bottom of the second connection structure is connected to the upper surface of the first connection structure; The diameter of a portion of the second connection structure located in the etch stop layer is greater than the bottom diameter of a portion of the second connection structure located in the second oxide layer.

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