QFN packaged semiconductor device and method

Abstract

Disclosed herein is a QFN packaged semiconductor device having a first main surface, an opposing second main surface, and sidewalls therebetween, and comprising: a lead frame having a lead frame lower surface and comprising a central die pad region and a plurality of peripheral plateau regions; a semiconductor die having a top surface attached to the die pad; a plurality of bond wires providing an electrical connection between the semiconductor die and the plurality of peripheral plateau regions; and an encapsulation material encapsulating the semiconductor die and the bonding wire; wherein the encapsulation material forms a frame extending below the lower surface of the lead frame and defining the second major surface, the frame having an opening in a central region thereof below the semiconductor die, and wherein the sidewalls are spaced apart from the frame, therefore, the lower surface of the lead frame is exposed at the plurality of peripheral platform areas.

Description

Technical Field

[0001] The present disclosure relates to packaged semiconductor devices, and in particular, to so-called quad flat no-lead ("QFN") devices. Background Art

[0002] A QFN device is a packaged semiconductor device that does not include flying leads protruding from an encapsulation material that forms the base of the package. Figure 1 A cross-section of a conventional QFN device 100 is shown. The QFN device has a top or first major surface 102, defined by a molding compound or encapsulant 140, a bottom or second major surface 104, and sidewalls 106. A semiconductor die 120 is embedded in the device. In contrast to many other types of semiconductor packages, QFN packages do not have protruding leads for electrical contact. Instead, the electrical connections to the embedded semiconductor die 120 are formed as a separate component of the lead frame 110, which is within the typically cuboid enclosure of the package itself. Specifically, the substrate of the semiconductor die 120 is electrically connected to a die pad 112 that forms a central region of the lead frame. Contact pads on the upper surface of the semiconductor die are connected to other portions of the lead frame by means of wire bonds 130. The other portions are arranged around the periphery of the QFN device and are generally referred to as platform regions or platforms. In Figure 1 1. Two platform regions 114 are shown. The platform regions 114 are separated and electrically isolated from each other and from the central die pad 112 by an encapsulant 140. The platform regions 114 of the die pad 112 and the lower surface of the encapsulant 140, which separates the platform regions from each other and from the central die pad, together define the bottom or second major surface 104 of the device.

[0003] As the skilled person will be familiar with, the lead frame is usually provided or supplied in roll or sheet form along with several or many other lead frames as a whole or single component. The die pad and peripheral platform area are connected together and to each other by a rod or frame around the outside of the lead frame, which is removed during subsequent processing and particularly during singulation of the packaged semiconductor device. Removal of the frame electrically isolates the various component parts of the lead frame.

[0004] In order to ensure that the wire bonds 130 connecting the contact pads of the semiconductor die 120 to the peripheral platform area are not too long, the peripheral platform area must be relatively close to the die. However, this will pose a risk of electrical shorting when the QFN device is mounted on a circuit board or the like. Specifically, the solder attaching the peripheral platform area 114 may not be sufficiently separated from the solder attaching the die pad 112. In conventional QFN devices, this problem is solved by providing a partially thinned lead frame, for example by "half etching" to reduce its local thickness by about 50%. Specifically, the lower surface of the innermost portion of the peripheral platform area is recessed, such as Figure 1 As shown, to produce a thinner portion 116 of the lead frame. The recess may include an outer perimeter of the die pad, as shown at 118.

[0005] Providing the leadframe with recessed areas (eg, by etching or stamping) increases the cost of the leadframe. Furthermore, manufacturing tolerances of the thinning process introduce variability to the thickness of the thinner areas 116, which may adversely affect the reliability of the wire bonds. Summary of the invention

[0006] According to a first aspect of the present disclosure, a quad flat no-lead (QFN) packaged semiconductor device is provided, having a first major surface, an opposing second major surface, and a sidewall therebetween, and comprising: a lead frame having a lead frame lower surface and including a central die pad area and a plurality of peripheral platform areas; a semiconductor die, the top surface of which is attached to the die pad; a plurality of bonding wires providing electrical connections between the semiconductor die and the plurality of peripheral platform areas; and an encapsulating material encapsulating the semiconductor die and the bonding wires and defining the first major surface; wherein the encapsulating material forms a frame extending below the lead frame lower surface and defining the second major surface, the frame having an opening in its central area below the semiconductor die, and wherein the sidewalls are spaced apart from the frame, thereby exposing the lead frame lower surface at the plurality of peripheral platform areas. By providing a frame of encapsulating material extending below the lower surface of the lead frame, embodiments of the present disclosure can utilize a lead frame that does not require a partial thickness area. The reliability of wire bonding to the lead frame can be improved because all bonding sites are on a full-thickness lead frame.

[0007] In one or more embodiments, the lead frame has a uniform thickness. This can reduce the complexity of the lead frame itself, thereby simplifying and reducing costs.

[0008] In one or more embodiments, the peripheral platform regions are separated by an encapsulation. Conventional injection molding can be used to provide the encapsulation between the individual peripheral platform regions.

[0009] In one or more embodiments, the QFN semiconductor device package further includes solder material in the opening. Providing solder in the opening can protect the die pad and provide a more stable device. It can further simplify the integration of the device onto a printed circuit board or the like.

[0010] In one or more embodiments, the solder material in the opening forms part of the second major surface. This may simplify placement of the device on a PCB or the like.

[0011] In one or more embodiments, the QFN semiconductor device package further includes solder material attached to the peripheral platform. Providing solder material on the peripheral platform can facilitate protecting the platform itself and can facilitate attaching the device to a PCB or the like.

[0012] In one or more embodiments, the solder material attached to the peripheral platform region forms a portion of the second major surface.

[0013] In one or more embodiments, the weld material attached to the peripheral platform region extends to the sidewalls.

[0014] According to another aspect of the present disclosure, there is provided a lead frame having uniform thickness and comprising a central die pad region and a plurality of peripheral platform regions, the lead frame being configured to be integrated into a QFN packaged semiconductor die according to any one of the preceding claims. Providing a lead frame having uniform thickness, in particular a lead frame that does not require partial thickness regions, can simplify the design and manufacture of the lead frame, thereby reducing costs.

[0015] In one or more embodiments, the lead frame further includes a protective tape attached to the first major surface of the lead frame over at least a central portion of the central die pad region and an outer region of the peripheral platform region.

[0016] In one or more embodiments, an inner region of the peripheral platform region is not attached to the protective tape and is exposed.

[0017] According to another aspect of the present disclosure, a method for manufacturing a QFN packaged semiconductor die is provided, the method comprising: providing a lead frame having a lead frame lower surface and including a central die pad area and a plurality of peripheral platform areas; attaching a top surface of the semiconductor die to the die pad; providing electrical connection between the semiconductor die and the plurality of peripheral platform areas by means of a plurality of bonding wires; and encapsulating the semiconductor die and the bonding wires with an encapsulation material defining a first major surface; wherein the encapsulation material forms a frame extending below the lead frame lower surface and defining a second major surface, the frame having an opening in a central area thereof below the semiconductor die, and wherein a side wall is spaced apart from the frame, thereby exposing the lead frame lower surface at the plurality of peripheral platform areas.

[0018] In one or more embodiments, the lead frame has a uniform thickness. In one or more embodiments, the peripheral platform regions are separated by an encapsulant. In one or more embodiments, the method further includes providing a solder material in the opening.

[0019] In one or more embodiments, the welding material in the opening forms a portion of the second major surface. In one or more embodiments, the method further includes welding material attached to the peripheral platform. In one or more embodiments, the welding material attached to the peripheral platform area forms a portion of the second major surface. In one or more such embodiments, the welding material attached to the peripheral platform area extends to the sidewall. In one or more such embodiments, welding material in the opening is also included, and wherein the welding material in the opening forms a portion of the second major surface.

[0020] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which:

[0022] Figure 1 is a cross-sectional view of a conventional QFN packaged semiconductor device;

[0023] Figure 2 is a perspective view of the underside of a QFN packaged semiconductor device according to an embodiment of the present disclosure;

[0024] Figure 3a For along Figure 2 A--A' cross section;

[0025] Figure 3b For along Figure 2 B--B' cross section;

[0026] Figure 4 is a perspective view of the underside of a QFN packaged semiconductor device according to other embodiments of the present disclosure;

[0027] Figure 5 For along Figure 4 The cross section of C--C';

[0028] Figure 6 A lead frame assembly for use in one or more embodiments is shown;

[0029] Figure 7 The lead frame assembly 600 is shown covered with tape;

[0030] Figure 8showing an enlarged view of a single lead frame;

[0031] Figure 9a shows a cross section of a portion of a QFN packaged semiconductor device according to an embodiment of the present disclosure during a later stage of manufacturing;

[0032] Figure 9b shows a cross section of a portion of a QFN packaged semiconductor device according to an embodiment of the present disclosure still during a late stage of manufacturing;

[0033] Fig.9c shows a cross section after a portion of a QFN packaged semiconductor device according to an embodiment of the present disclosure has been removed from a mold tool;

[0034] Figure 9d shows a cross section of a portion of a QFN packaged semiconductor device according to an embodiment of the present disclosure after fabrication;

[0035] Fig.9e shows a cross section of a portion of a QFN packaged semiconductor device according to other embodiments of the present disclosure after fabrication;

[0036] Fig.10 Shown in the corresponding Figure 9b Schematic diagram of a processed QFN packaged semiconductor device at a stage of manufacture shown in but for a portion of other embodiments of the present disclosure;

[0037] Fig.11 A flowchart illustrating a method according to one or more embodiments of the present disclosure;

[0038] Fig.12 Schematically illustrates a partial cross section of a soldered peripheral platform region according to a conventional QFN device;

[0039] Fig.13a schematically illustrates a partial cross section of a soldered peripheral platform region of a QFN packaged semiconductor device according to an embodiment of the present disclosure; and

[0040] Fig.13b A side view of the same region is shown.

[0041] It should be noted that the drawings are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of the parts of these drawings have been shown by being enlarged or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0042] Figure 2A perspective view of the underside or lower surface of a QFN package 200 according to one or more embodiments of the present disclosure is shown. The QFN package semiconductor device has a top or first major surface 202 (which is not directly visible in the perspective view), an opposing second or bottom major surface 204 (which points upward in this underside view), and a sidewall 206 therebetween. The QFN package includes a lead frame having a lead frame lower surface, portions of which are visible in the figure. The lead frame includes a central die pad area 212, which may also be referred to as a pad or die pad, and a plurality of peripheral platform areas 214. Figure 2 , the QFN device includes a semiconductor die 220 attached to a die pad and a plurality of bond wires 230 that provide electrical connections between the semiconductor die, specifically contact pads on the top or active surface of the semiconductor die, and a plurality of peripheral platform regions. Additional bond wires 230 (also not shown) may be present. Figure 2 206 of the QFN device. The sidewalls 206 of the QFN device are formed almost entirely of encapsulating material, except for the edges of the peripheral platform area that are close to the second major surface and exposed to the sidewalls. It should be understood that in conventional QFN packages, the exposed edges of the platform area extend to the second major surface of the QFN device; however, as will become more apparent below, in embodiments of the present disclosure, the lead frame and therefore the exposed edges do not reach the second major surface of the device. That is, they do not reach the uppermost surface shown in the figure (which corresponds to the bottom or second major surface, because the device is actually typically oriented on a circuit board or the like).

[0043] If available Figure 2 As can be seen in FIG. 1 , the encapsulation material forms a frame 242 that extends below the lower surface of the lead frame (in the conventional orientation, corresponding to 'above' in the figure). This frame is smaller than the QFN, and therefore its outer periphery 244 is spaced apart from or recessed from the sidewalls 206 of the QFN package. The surface 216 of the peripheral platform area is therefore exposed around the periphery of the QFN device. The encapsulation material between the exposed surfaces 216 is also exposed, as shown at 218. The frame has an opening in its central area generally below the semiconductor die. In, for example Figure 2 In the embodiment depicted in , the opening in the frame exposes the die pad. The frame defines the second major surface of the QFN device, that is, the bottom surface of the QFN device in its normal orientation. Therefore, the opening in the frame that exposes the die pad can be considered as a recess or central recess from the second major surface. The exposed peripheral platform area with the encapsulant in between can similarly be considered as a recessed perimeter or recessed peripheral area from the second major surface.

[0044] Figure 3a Shown along Figure 2 The cross section of A-A', and Figure 3b A cross section along B--B' is shown. Figure 3a A semiconductor die 220 is shown electrically connected to a peripheral platform region 214 by means of a wire bond 230. In the illustrated embodiment, the wire bond also provides an electrical connection between a contact pad (not shown) on the semiconductor chip die and the die pad 212. The semiconductor die 220 and the wire bond 230 are encapsulated in an encapsulant 240 defining a first major surface 202. The encapsulant 240 also defines a sidewall 206 and forms the entire sidewall except for the edge of the peripheral platform region 214. The second major surface 204 of the QFN device is defined by a frame 242. It can be seen that the sidewall 206 does not reach the second major surface. Alternatively, there is a recess 208 between the lowermost portion of the sidewall 206 and the outermost portion of the frame 204. As can be seen in the figure, the lead frame 210 including the die pad 212 and the peripheral platform region 214 has a uniform or substantially uniform thickness as a whole.

[0045] Shown along Figure 2 B--B' cross section Figure 3b Similar to Figure 3a , except that since this cross section does not pass through the peripheral platform region, only the die pad 212 portion of the lead frame 210 is visible. The encapsulant 240 between the peripheral platform regions is visible and forms both the sidewalls and the upper surface of the recess 208 at this portion of the device. The skilled person will appreciate that due to the "fan-out" between the contacts on the active top surface of the semiconductor die and the peripheral platform region, some of the bond wires may be located at locations that are not parallel to the die pad 212 of the lead frame 210. Figure 3b The cross section 232 of FIG. 230 extends in the direction of the plane of the cross section, and thus the cross section may intersect the joining line. This is shown by the cross section 232 of the line 230 shown.

[0046] Figure 4 A perspective view of the underside or lower surface of a QFN package 200 is shown according to one or more other embodiments of the present disclosure. Figure 1 , except that it has a first major surface 202 (not visible) and a second major surface 204 at least partially defined by a frame of encapsulation material. The sidewalls 206 do not extend all the way to the second major surface 204, but are shallower than the QFN device itself. The recessed perimeter or peripheral region surrounds the frame at the surface level of the lead frame, and the peripheral platform region of the lead frame with the encapsulation 240 therebetween may be partially exposed in this peripheral region. Specifically, the outer edge of the peripheral platform region is visible on the sidewalls. However, unlike, for example, Figure 2 Compared with the embodiment shown in Figure 4The QFN device shown in 4 includes solder attached to the peripheral platform area and attached to the die pad. The solder 450 in the die pad may fill or substantially fill the opening in the frame and may have a surface substantially coplanar with the frame. In addition, the solder 460 attached to the peripheral platform area may also have a surface substantially coplanar with the frame. Of course, the skilled person will understand that, in particular, the solder attached to the platform area but to some extent in the central opening may not generally be completely flat, but may "ball up" due to surface tension.

[0047] Figure 5 Shown along Figure 4 The cross section of C--C'. Similar to Figure 3a , the semiconductor die 220 is electrically connected to the peripheral platform area 224 by means of wire bonds 230. As shown, the wire bonds may also provide an electrical connection between contact pads (not shown) on the semiconductor chip die and the die pad 212. The semiconductor die 220 and the wire bonds 230 are encapsulated in an encapsulant 240 that defines the first major surface 202. The encapsulant 240 also defines sidewalls 206. The sidewalls are primarily formed by the encapsulant, but also include exposed edges of the peripheral platform area 214. In this embodiment, the edges of the solder 460 also form part of the sidewalls, but the skilled person will appreciate that the solder may shrink to some extent due to surface tension. The embodiment according to this figure is also different from Figure 3a , because the solder 450 fills the opening or central recess in the frame 242. The frame 242 and the solder 450 are generally coplanar. Of course, the skilled artisan will appreciate that the figure may be idealized to a certain extent, because there are no bulges or bumps in the solder that may be caused by surface tension. Figure 5 In the embodiment shown in FIG. 1 , it is apparent that the lead frame may have a substantially uniform thickness t, which may be typically about 50 to 200 μm, and in a preferred embodiment may be in a range between 100 μm and 125 μm. The frame thickness f, which corresponds to the thickness of the solder 350 in the central opening and typically corresponds to the thickness of the solder 460 attached to the peripheral platform area 214 in this embodiment, may be typically about 50 to 200 μm, and in a preferred embodiment may be in a range between 100 μm and 125 μm, and is typically the same as f.

[0048] The QFN packaged semiconductor device according to the embodiment of the present disclosure can be made of conventional materials. In particular, the lead frame can be conveniently made of copper or electroplated copper. Figure 4 In the embodiment shown in , which includes solder that partially fills the recesses in and around the encapsulation frame, the solder may be a conventional solder used for semiconductor processing, such as Sn-Ag-Cu alloy - ("SAC" 305) or 95.4Sn / 3.1Ag.1.5Cu.

[0049] Figure 6 A lead frame assembly 600 is shown for use in one or more embodiments. Although a 2 by 3 array of lead frames 610 is shown, the skilled person will appreciate that arrays of other sizes may be used, or that the lead frames may be provided as a continuous solid number. The lead frames are connected together and to each other by rods or frames 620. During later singulation of the device, the rods or frames will typically be removed by cutting, which allows the device to be separated and the individual die pads 212 to be electrically isolated from the peripheral platform area 214.

[0050] Figure 7 Leadframe assembly 600 is shown covered with tape such as Kapton tape 710 or other high temperature resistant tape or film that can withstand at least 200°C and has degradation resistance, which has been patterned to expose at least a portion of peripheral platform area 730. The tape is typically a self-adhesive tape. Typically, the tape is placed across the array of leadframes and then patterned to align the gaps in the tape with the interior of the peripheral platform. The outer perimeter of the bare die pad 212 can also be exposed by removing the tape from this area.

[0051] Figure 8 An enlarged view of a single lead frame is shown, more clearly showing the tape 710 covering most of the die pad 212 at 712, and the outer portion of the peripheral platform area 214 at 714. The outer perimeter 812 of the die pad 212 is exposed, that is, it is not covered by the tape. It should be understood that, as described above, at this stage of the manufacturing process, the lead frame is integrated into a lead frame assembly.

[0052] Figure 9aA cross section of a portion of a QFN packaged semiconductor device 900 according to an embodiment of the present disclosure is shown at a later stage of manufacturing. The semiconductor die 220 is mounted on the die pad 212 of the lead frame by conventional means (typically with the aid of a conductive die attach epoxy not shown). The assembly is placed on a patterned support plate 970. The support plate 970 may also be referred to as a "heating block" because it typically includes a heating element that heats the lead frame for a wire bonding process, which, as the skilled person will appreciate, is conventionally performed using a combination of thermal and ultrasonic energy. The surface of the support plate 970 is generally flat, except for an annular or frame-shaped area 974, which protrudes from the surface by an amount corresponding to the thickness of the tape 712. Thus, both the wire bonds 230 to the die pad (i.e., the bonds shown at 232) and the wire bonds to the peripheral platform region (i.e., the bonds shown at 234) can be formed on a well-supported surface at a well-defined height because the lead frame has a well-defined thickness and its lower surface rests on the tape 710 or the raised portion 974 of the support plate 970, which also has a well-defined thickness. Thus, according to embodiments of the present disclosure, the reliability of the wire bonds can be improved relative to conventional QFNs, where the tolerances involved in etching the lead frame to half the thickness result in the height of the wire bonds being variable and somewhat undeterminable.

[0053] Figure 9b FIG. 9 is a cross-section of a portion of a QFN packaged semiconductor device 900 according to an embodiment of the present disclosure at a later stage of manufacturing. Specifically, Figure 9a The assembly is placed in the cavity of the mold frame 975, and the molding compound 140 is injected into the cavity. As can be seen in the figure, the molding compound or encapsulant 140 is squeezed into the gap in the tape below the lead frame. This produces a frame 242 of encapsulating material, which has a lower surface coplanar with the lower surface of the tape and has an outer perimeter 244 defined by the outermost edge of the gap in the tape.

[0054] Fig.9c A cross section is shown after a portion of a QFN packaged semiconductor device 900 according to an embodiment of the present disclosure has been removed from a mold tool.

[0055] Figure 9d A cross section of a portion of a QFN packaged semiconductor device 900 according to an embodiment of the present disclosure after fabrication is shown. This is the final QFN packaged semiconductor device 900 according to one or more embodiments. The tape has been removed so that the encapsulant frame 242 forms the lower major surface of the QFN packaged device, with a recess 208 around the perimeter of the device between the lowermost portion of the sidewall 206 and the outermost portion of the frame 204. The die pad 212 is exposed in a central opening within the frame 242.

[0056] Fig.9e 9 shows a cross section of a portion of a QFN packaged semiconductor device 900 according to an embodiment of the present disclosure after fabrication. Fig.9e , manufacturing can continue after the stage shown in FIG. 9D by providing solder 450 attached to the die pad in the central opening in the frame and solder 460 attached to the peripheral platform area around the periphery of the QFN package device. The skilled person will appreciate that, as mentioned above, Fig.9e The solder shown in may be idealized to some extent, since in actual applications the solder may tend to bulge under the influence of surface tension.

[0057] Now turn to Fig.10 , which is shown in the corresponding Figure 9b Schematic diagram of a processed QFN packaged semiconductor device at a manufacturing stage shown in FIG. 1 , but for a portion of other embodiments of the present disclosure. Fig.10 and Figure 9b , it can be seen that in Fig.10 In the embodiment shown in , there is no tape 710 on the bottom surface of the assembly. Instead of tape defining the boundaries of the epoxy frame 242 below the lead frame, the boundaries of the frame 242 are defined by the lower plate of the molding tool itself. In other words, the lower plate of the molding tool is not flat, but includes recesses in the locations that will correspond to the encapsulation frame. Of course, the skilled person will understand that, for example Fig.10 The embodiment shown in requires accurate placement of the lead frame assembly within the molding tool. This can be achieved, for example, using alignment features within the lead frame assembly. Figure 9b Compared with the method shown in Fig.10 The method of the embodiment shown in may include wire bonding of only devices mounted on a planar support plate, since the lead frame may be supported directly on the entire device due to its uniform thickness.

[0058] Fig.11A flow chart of a method according to one or more embodiments of the present disclosure is shown. After the previous processing steps schematically shown at 1110, the method continues at step 1115 by individually grinding the wafer from its original process thickness to its final thickness. The wafer is then mounted at step 1120, and the wafer is cut into individual dies at step 1125. The die is then bonded to the lead frame in step 1130, and the conductive epoxy is cured at step 1135 to drive off volatile compounds. The die assembly on the lead frame (with epoxy therebetween) is then plasma cleaned at step 1140. Wire bonding is then performed between the contact pads on the active surface of the die and the peripheral platform area of ​​the lead frame, and optionally between other contact pads on the active surface of the die and the die pads or pads at step 1145. At step 1150, the assembly is encapsulated in a conventional molding tool with an encapsulant molding compound. At step 1155, the tape defining the encapsulant mold at the bottom major surface is removed, typically by etching, although other methods such as mechanical removal may alternatively be used. A post-mold cure in which the package is heated to cure the encapsulant and reduce or limit stress is then applied to the assembly, as shown at step 1160. The assembly, which at this stage typically includes multiple dies each attached to a separate lead frame within a lead frame assembly, is then marked, for example, to indicate device-specific information, such as a part number or manufacturer identification, as shown at step 1165. The assembly is then singulated into individual QFN packaged semiconductor devices at step 1170.

[0059] Now turn to Fig.12 , which schematically shows a partial cross section of a soldered peripheral platform area according to a conventional QFN device. The platform area 1210 is embedded in an encapsulation 1220. The platform area 1210 is electrically connected to a printed circuit board or the like 1230 by means of solder 1240. It can be seen that the outermost portion of the platform area has a reduced thickness t1 (which is typically half of the full thickness t of the lead frame). The solder 1240 fills the recess left by the reduced thickness and helps to lock the QFN device in place and prevent movement or sliding of the device.

[0060] Fig.13a A partial cross-sectional view schematically shows a soldering peripheral platform area of ​​a QFN packaged semiconductor device according to an embodiment of the present disclosure, and Fig.13bA side view of the same area is shown. Since the lead frame 1310 has a uniform thickness, it does not include a reduced thickness portion. Alternatively, keying of the device to prevent movement or sliding is provided by an encapsulation frame that extends below the surface of the lead frame and specifically in the peripheral platform area. The outer peripheral edge 1345 of the frame of the encapsulation 1320 is locked with solder 1340. The peripheral platform area 1310 does not directly participate in the locking. Although not shown in the figure, the peripheral platform area may have a plated surface on it, or may be partially plated. This plated material may interact with the solder or form a solder barrier during the deposition of the solder or later during attachment to a PCB or the like by means of solder.

[0061] Other variations and modifications will be apparent to the skilled person from reading this disclosure.Such variations and modifications may involve equivalent and other features which are already known in the art of QFN devices and which may be used as substitutes or supplements for the features already described herein.

[0062] Although the attached claims are directed to specific feature combinations, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any combination of novel features or any generalization of the novel features disclosed explicitly or implicitly herein, regardless of whether the novel feature relates to the same invention as the present invention currently claimed in any claim or whether the novel feature alleviates any or all of the same technical problems as the technical problems alleviated by the present invention.

[0063] It should be noted that one or more of the embodiments above have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method claims, while other embodiments may have been described with reference to apparatus claims. However, one skilled in the art will appreciate from the foregoing that, unless otherwise indicated, any combination of features relating to different subject matters, in addition to any combination of features belonging to one type of subject matter, and in particular, any combination of features of method claims and features of apparatus claims, are also considered disclosed with this document.

[0064] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0065] For the sake of completeness, it is also provided that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfill the functions of several components recited in the claims [deleted if irrelevant], and the reference numerals in the claims should not be interpreted as limiting the scope of the claims. In addition, the word "may" is used in a permissive sense (i.e., meaning having the possibility of...) rather than a mandatory sense (i.e., meaning must). Similarly, the words "include, including and includes" mean including but not limited to.

Claims

1. A quad flat no-lead (QFN) package semiconductor device, characterized in that: The QFN packaged semiconductor device has a first main surface (102), an opposite second main surface (204), and a sidewall (206) therebetween, and includes: A lead frame (210) having a lead frame lower surface and including a central die pad region (212) and a plurality of peripheral platform regions (214); a semiconductor die (220) having a top surface attached to the die pad; a plurality of bond wires (230) providing electrical connections between the semiconductor die and the plurality of peripheral platform regions; and an encapsulation material (240) encapsulating the semiconductor die and bond wires and defining the first major surface; The encapsulation material forms a frame extending below the lower surface of the lead frame and defining the second major surface, the frame having an opening in a central area below the semiconductor die, and wherein the sidewalls are spaced apart from the frame, thereby exposing the lower surface of the lead frame at the plurality of peripheral platform areas.

2. The QFN packaged semiconductor device according to claim 1, wherein: The peripheral platform regions are separated by an encapsulation.

3. The QFN packaged semiconductor device according to claim 1, wherein: Also included is a solder material in the opening.

4. The QFN packaged semiconductor device according to claim 1, wherein: Also included is welding material attached to the peripheral platform.

5. A lead frame (210), characterized in that: The lead frame has a uniform thickness and includes a central die pad area (212) and a plurality of peripheral platform areas (214) configured to be integrated into the QFN packaged semiconductor die of claim 1.

6. The lead frame (110) according to claim 5, characterized in that: Also included is a protective tape attached to the first major surface of the lead frame over at least a central portion of the central die pad area (212) and an outer area of ​​the peripheral platform area (214).

7. A method for manufacturing a QFN packaged semiconductor die, characterized in that: The method comprises: providing a lead frame having a lead frame lower surface and including a central die pad region and a plurality of peripheral platform regions; attaching a top surface of a semiconductor die to the die pad; providing electrical connections between the semiconductor die and the plurality of peripheral platform regions by means of a plurality of bond wires; and encapsulating the semiconductor die and the bonding wires with an encapsulation material defining a first major surface; The encapsulation material forms a frame extending below the lower surface of the lead frame and defining a second major surface, the frame having an opening in a central region below the semiconductor die, and wherein sidewalls are spaced apart from the frame, thereby exposing the lower surface of the lead frame at the plurality of peripheral platform regions.

8. The method according to claim 7, characterized in that The solder material in the opening forms a portion of the second major surface.

9. The method according to claim 7, characterized in that: Also included is welding material attached to the peripheral platform.

10. The method according to claim 7, characterized in that Also included is a solder material in the opening, and wherein the solder material in the opening forms a portion of the second major surface.

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