Semiconductor device with three-dimensional structure

Abstract

The present disclosure provides a semiconductor device having a three-dimensional structure, the semiconductor device including: a first wafer including a first bonding pad on one surface thereof; a second wafer including a second bonding pad bonded to the first bonding pad on one surface thereof bonded to the one surface of the first wafer; a plurality of anti-warping grooves, which are formed in the one surface of the first wafer, and are arranged in a strip shape; and a plurality of anti-warpage ribs on the one surface of the second wafer, the plurality of anti-warpage ribs being coupled to the plurality of anti-warpage grooves, respectively, and being arranged in a strip shape.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110366848.6 (application date: April 6, 2021, invention name: semiconductor device with three-dimensional structure). Technical Field

[0002] Various embodiments relate generally to a semiconductor technology, and more particularly, to a semiconductor device having a three-dimensional structure using a wafer bonding technology. Background Art

[0003] In semiconductor devices, for the purpose of high capacity and miniaturization, it is necessary to increase the integration. Proposals for increasing the integration include a structure in which components included in the semiconductor device are not manufactured on a single wafer but are separately manufactured on at least two wafers, and then the wafers are bonded to electrically connect the components.

[0004] The material layers used in the semiconductor manufacturing process have intrinsic stress, and warpage may occur in the wafer due to the stress caused by the material layer deposition process and the heat treatment process. When warpage occurs in the wafer, bonding failure may occur, in which the adhesion between the wafers is reduced and the electrical connection between the wafers is cut off. Summary of the invention

[0005] Various embodiments are directed to proposing measures capable of suppressing or reducing wafer warpage.

[0006] In one embodiment, a semiconductor device having a three-dimensional structure may include: a first wafer, the first wafer including a first bonding pad on one surface thereof; a second wafer, the second wafer including a second bonding pad bonded to the first bonding pad on one surface thereof bonded to the one surface of the first wafer; a plurality of anti-warping grooves, the plurality of anti-warping grooves are on the one surface of the first wafer and are arranged in a strip shape; and a plurality of anti-warping ribs, the plurality of anti-warping ribs are on the one surface of the second wafer, the plurality of anti-warping ribs are respectively connected to the plurality of anti-warping grooves, and are arranged in a strip shape.

[0007] In one embodiment, a semiconductor device having a three-dimensional structure may include: a first wafer, the first wafer including a first bonding pad on one surface thereof; a second wafer, the second wafer including a second bonding pad bonded to the first bonding pad on one surface thereof bonded to the one surface of the first wafer; a plurality of first anti-warping pads, the plurality of first anti-warping pads are on the one surface of the first wafer and are arranged in a strip shape; and a plurality of second anti-warping pads, the plurality of second anti-warping pads are on the one surface of the second wafer and are respectively bonded to the plurality of first anti-warping pads, and the plurality of second anti-warping pads are arranged in a strip shape.

[0008] In one embodiment, a semiconductor device having a three-dimensional structure may include: a first wafer, the first wafer including a first bonding pad on one surface thereof; a second wafer, the second wafer including a second bonding pad bonded to the first bonding pad on one surface thereof bonded to the one surface of the first wafer; and a plurality of anti-warping metal ribs, the plurality of anti-warping metal ribs being defined in the first wafer and arranged in a strip shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to an embodiment of the present disclosure.

[0010] Figure 2 is a top view showing the arrangement of the warpage preventing grooves.

[0011] FIG. 3A to FIG. 3C It is a top view showing a method of arranging unit areas.

[0012] Figure 4A is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to another embodiment of the present disclosure.

[0013] Figure 4B It is shown Figure 4A A top view of the extension direction of the anti-warping groove and the first anti-warping pad.

[0014] Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to other embodiments of the present disclosure.

[0015] Figure 5B , Figure 6B , Figure 7B and Figure 8B It is shown Figure 5A , Fig. 6A , Fig. 7A and Fig. 8AA top view of the extension direction of the anti-warping groove and the reinforcing support member shown in FIG.

[0016] Figures 9 to 13 is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to other embodiments of the present disclosure.

[0017] Fig.14 is a top view showing the disposition of a first warpage prevention pad according to an embodiment of the present disclosure on a chip level structure.

[0018] Fig.15A is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to still another embodiment of the present disclosure.

[0019] Fig. 15B It is shown Fig.15A A view showing the extension direction of the anti-warping metal ribs.

[0020] Fig.16 is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The advantages and features of the present disclosure and methods for achieving them will become apparent from the description of the following exemplary embodiments, and will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0022] Because the numerical values, dimensions, ratios, angles, and number of elements describing the embodiments of the present disclosure given in the drawings are merely illustrative, the present disclosure is not limited to the contents shown. Throughout the specification, the same reference numerals represent the same components. When describing the present disclosure, when it is determined that the detailed description of the related art may obscure the main points or clarity of the present invention, its detailed description will be omitted. It should be understood that, unless otherwise specifically stated, the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the means listed thereafter. When an indefinite article or a definite article (e.g., "one", "an" or "the") is used when referring to a singular noun, unless otherwise specifically stated, the article may include the plural number of the noun.

[0023] When interpreting the elements in the embodiments of the present disclosure, they should be interpreted as including an error range even in the case where there is no explicit statement.

[0024] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a) and (b) may be used. These terms are only used for the purpose of distinguishing one component from another component, and do not limit the essence, order, sequence or quantity of the components. In addition, the components in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, as used herein, a first component may be a second component within the technical spirit of the present disclosure.

[0025] If a component is described as being “connected,” “coupled,” or “linked” to another component, this may mean that the component is not only directly “connected,” “coupled,” or “linked,” but also indirectly “connected,” “coupled,” or “linked” via a third component. When describing a positional relationship, such as “element A on element B,” “element A above element B,” “element A below element B,” and “element A next to element B,” one or more other elements may be disposed between element A and element B unless the term “directly” or “immediately adjacent” is explicitly used.

[0026] The features of the various exemplary embodiments of the present disclosure may be partially or completely connected, combined or separated. Various interactions and operations are technically possible. The various exemplary embodiments may be practiced individually or in combination.

[0027] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to an embodiment of the present disclosure.

[0029] Reference Figure 1 According to an embodiment of the present disclosure, a semiconductor device having a three-dimensional structure may include a first wafer W1 and a second wafer W2 bonded to each other. In order to facilitate understanding of the embodiments of the present disclosure, the cross-sectional views used for reference in this specification show that the first wafer W1 and the second wafer W2 are separated. However, it should be understood that the first wafer W1 and the second wafer W2 are actually bonded to each other.

[0030] The first wafer W1 may include a first substrate 10, a memory cell array MCA defined below the first substrate 10, and a dielectric layer 30 defined below the first substrate 10 to cover the memory cell array MCA. The memory cell array MCA may have a structure in which a plurality of memory cells are three-dimensionally stacked. For example, the memory cell array MCA may include a plurality of electrode layers 22 and a plurality of interlayer dielectric layers 24 alternately stacked below the source plate 11, and a vertical channel CH passing through the plurality of electrode layers 22 and the plurality of interlayer dielectric layers 24.

[0031] The electrode layer 22 may include at least one source selection line, at least one drain selection line, and a plurality of word lines. The vertical channel CH may be connected to the bit line BL. At least one source selection transistor, a plurality of memory cells, and at least one drain selection transistor may be arranged along a vertical channel CH in a vertical direction VD to form a cell string. The vertical direction VD represents a direction protruding vertically from the top surface of the first substrate 10. Each memory cell may be accessed through a bit line BL and a word line. Although the present embodiment discloses a three-dimensional stacked memory cell as an example, it should be noted that the scope of the present disclosure is not limited thereto.

[0032] The second wafer W2 may include a second substrate 40, a logic circuit LOGIC defined on the second substrate 40, and a dielectric layer 50 defined on the second substrate 40 to cover the logic circuit LOGIC. The logic circuit LOGIC may be used to control the memory cell array MCA.

[0033] The first wafer W1 may include a plurality of first bonding pads PAD1 electrically connected to the memory cell array MCA on one surface S1 thereof. The second wafer W2 may include a plurality of second bonding pads PAD2 electrically connected to the logic circuit LOGIC on one surface S2 thereof. When the first bonding pads PAD1 and the second bonding pads PAD2 are bonded to each other, the memory cell array MCA of the first wafer W1 and the logic circuit LOGIC of the second wafer W2 may be electrically connected.

[0034] When the dielectric layer 30 is etched from the one surface S1 to a predetermined depth, a plurality of anti-warpage grooves RG may be formed. The plurality of anti-warpage grooves RG may be used to disperse or relieve stress, thereby suppressing warpage of the first wafer W1.

[0035] The surface portion 30A of the dielectric layer 30 in which the plurality of warpage prevention grooves RG are formed may be made of a dielectric material having a higher hardness than the inner portion 30B of the dielectric layer 30. Although not shown, the dielectric layer 30 may include an etch stop layer used as an etch stop during an etching process for forming the warpage prevention grooves RG, and the depth of the warpage prevention grooves RG may be adjusted by changing the vertical position of the etch stop layer.

[0036] The dielectric layer 50 may include a protrusion protruding from the one surface S2 of the second wafer W2 to a predetermined height in the vertical direction VD to form a plurality of anti-warpage ribs RR corresponding to the plurality of anti-warpage grooves RG of the first wafer W1. The plurality of anti-warpage ribs RR may be used to increase the rigidity of the second wafer W2, thereby suppressing the warpage of the second wafer W2.

[0037] The surface portion 50A of the dielectric layer 50 from which the plurality of warpage prevention ribs RR are formed may be made of a dielectric material having a higher hardness than the inner portion 50B of the dielectric layer 50. Although not shown, the plurality of warpage prevention ribs RR may be formed by patterning the dielectric layer 50 through an etching process. Although not shown, the dielectric layer 50 may include an etch stop layer serving as an etch stop during the etching process for forming the warpage prevention ribs RR, and the height of the warpage prevention ribs RR may be adjusted by changing the vertical position of the etch stop layer.

[0038] Although Figure 1 It is shown that the first wafer W1 is a cell wafer including a memory cell array MCA, and the second wafer W2 is a logic wafer including a logic circuit LOGIC for controlling the memory cell array MCA, but it should be noted that the technical spirit of the present disclosure is not limited thereto.

[0039] Hereinafter, and in the drawings, two directions parallel to the top surface of the first substrate 10 and intersecting each other are defined as a first direction FD and a second direction SD, respectively. For example, the first direction FD may correspond to an extension direction of a word line, and the second direction SD may correspond to an extension direction of a bit line. The first direction FD and the second direction SD may substantially intersect each other perpendicularly. In the drawings, a direction indicated by an arrow and a direction opposite thereto represent the same direction.

[0040] Figure 2 is a top view showing the arrangement of the warpage preventing grooves.

[0041] Reference Figure 2 The first wafer W1 may include a plurality of unit areas UA arranged in the first direction FD and the second direction SD. The unit area UA may include a plurality of first unit areas UA1 and a plurality of second unit areas UA2 alternately arranged in the first direction FD and the second direction SD, for example, in a checkerboard pattern.

[0042] A plurality of warpage preventing grooves RG having a linear or stripe shape may be laid out in each of the first and second unit areas UA1 and UA2 .

[0043] The extension direction of the warpage prevention groove RG in the first unit area UA1 and the extension direction of the warpage prevention groove RG in the second unit area UA2 may be different from each other. For example, the warpage prevention groove RG extending in the first direction FD may be arranged in the first unit area UA1, and the warpage prevention groove RG extending in the second direction SD may be arranged in the second unit area UA2. Because the warpage prevention groove RG extends in different directions, it is possible to avoid and prevent the inherent stress caused in the first direction FD and the second direction SD in the manufacturing process from being concentrated in any one direction.

[0044] In one embodiment, the number of first unit areas UA1 included in the first wafer W1 and the number of second unit areas UA2 included in the first wafer W1 may be the same, and the sum of the areas of the first unit areas UA1 included in the first wafer W1 and the sum of the areas of the second unit areas UA2 included in the first wafer W1 may be substantially the same.

[0045] The second wafer W2 (see Figure 1 ) of the anti-warping rib RR (see Figure 1 ) has substantially the same layout structure as the warpage preventing groove RG. Therefore, the layout structure of the warpage preventing rib RR will not be described separately below.

[0046] FIG. 3A to FIG. 3C It is a top view showing a method of arranging unit areas.

[0047] Reference Figure 3A The first wafer W1 may include a plurality of chip regions CHIP disposed to be separated from each other, and scribe lanes SL extending in the first direction FD and the second direction SD are interposed between the plurality of chip regions CHIP. The scribe lanes SL may be used as separation lines for separating the chip regions CHIP from each other during a segmentation process. Figure 3A The unit area UA configured in units of the chip area CHIP is shown.

[0048] In a three-dimensional memory, the asymmetry between the lengths of the chip area CHIP in the first direction FD and the second direction SD may increase due to a design change that increases the number of stacked memory cells. This increase in asymmetry may reduce the stress dispersion effect provided by the anti-warpage groove RG, resulting in an imbalance between the stress in the first direction FD and the stress in the second direction SD. Therefore, it is necessary to reduce the difference in the length of the unit area UA in the first direction FD and the second direction SD. Preferably, the lengths of the unit area UA in the first direction FD and the second direction SD should be the same. That is, the unit area UA should have a square or substantially square structure.

[0049] like Figure 3B As shown, in order to reduce the difference between the lengths of the unit area UA in the first direction FD and the second direction SD, each chip area CHIP may be divided to form a plurality of unit areas UA. For example, in the case where the length L1 has a size approximately twice that of the length L2, each chip area CHIP may be divided into two in the first direction FD to form two unit areas UA in each chip area CHIP.

[0050] like Figure 3CAs shown, a plurality of adjacent chip regions CHIP may be grouped to form one unit region UA. For example, in the case where the length L1 has a size approximately three times that of the length L2, three chip regions CHIP continuously arranged in the second direction SD may be grouped to form one unit region UA.

[0051] Figure 4A is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to another embodiment of the present disclosure, and Figure 4B It is shown Figure 4A A top view of the extension direction of the anti-warpage groove and the first anti-warpage pad.

[0052] Reference Figure 4A , the first warpage preventing pads DPAD1 may be defined on one surface S1 of the first wafer W1. The first warpage preventing pads DPAD1 may be used to suppress warpage of the first wafer W1.

[0053] The first warpage preventing pad DPAD1 is a dummy pattern that does not exert any influence on the operations of the memory cell array MCA and the logic circuit LOGIC. The first warpage preventing pad DPAD1 may be electrically isolated from the memory cell array MCA and the logic circuit LOGIC.

[0054] The second warpage preventing pads DPAD2 bonded to the first warpage preventing pads DPAD1 may be defined on one surface S2 of the second wafer W2. The second warpage preventing pads DPAD2 may serve to suppress warpage of the second wafer W2.

[0055] The second warpage preventing pad DPAD2 is a dummy pattern that does not exert any influence on the operations of the memory cell array MCA and the logic circuit LOGIC. The second warpage preventing pad DPAD2 may be electrically isolated from the memory cell array MCA and the logic circuit LOGIC.

[0056] The first anti-warpage pad DPAD1 and the second anti-warpage pad DPAD2 may be made of a conductive material having a higher hardness than the first bonding pad PAD1 and the second bonding pad PAD2. For example, the first bonding pad PAD1 and the second bonding pad PAD2 may be made of copper (Cu), and the first anti-warpage pad DPAD1 and the second anti-warpage pad DPAD2 may be made of tungsten (W).

[0057] To simplify the diagram, Figure 4A Only one first anti-warpage pad DPAD1 and one second anti-warpage pad DPAD2 are shown in FIG. However, it should be understood that a plurality of first anti-warpage pads DPAD1 and a plurality of second anti-warpage pads DPAD2 are provided in the embodiments contemplated by the present disclosure.

[0058] Reference Figure 4B , a plurality of first warpage preventing pads DPAD1 may be arranged in each of the first unit area UA1 and the second unit area UA2 of the first wafer W1.

[0059] Each first anti-warpage pad DPAD1 may have a strip or line shape extending in a specific direction. The extension direction of the first anti-warpage pad DPAD1 arranged in the first unit area UA1 and the extension direction of the first anti-warpage pad DPAD1 arranged in the second unit area UA2 may be different from each other. For example, the first anti-warpage pad DPAD1 extending in the first direction FD may be arranged in the first unit area UA1, and the first anti-warpage pad DPAD1 extending in the second direction SD may be arranged in the second unit area UA2. This layout disperses the stress caused in the first direction FD and the stress caused in the second direction SD, and suppresses or reduces the stress from being concentrated in any one direction.

[0060] In each unit area UA, the extension direction of the first anti-warpage pad DPAD1 may be the same as the extension direction of the anti-warpage groove RG. For example, in the first unit area UA1, the extension direction of the anti-warpage groove RG and the extension direction of the first anti-warpage pad DPAD1 may be the same (e.g., the first direction FD). In the second unit area UA2, the extension direction of the anti-warpage groove RG and the extension direction of the first anti-warpage pad DPAD1 may be the same (e.g., the second direction SD).

[0061] Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to other embodiments of the present disclosure, and Figure 5B , Figure 6B , Figure 7B and Figure 8B It is shown FIG. 5A to FIG. 8A A top view of the extension direction of the anti-warping groove and the reinforcing support shown in FIG.

[0062] Reference Figure 5A , the first substrate 10 may have a front surface disposed to face the memory cell array MCA and a rear surface facing away from the front surface. A plurality of grooves R may be formed on the rear surface of the first substrate 10, and a reinforcing support member SP1 may be filled in the plurality of grooves R. The reinforcing support member SP1 is used to suppress warping of the first wafer W1, and may be made of a material having a higher hardness than the first substrate 10.

[0063] Reference Figure 5B, a plurality of reinforcement supports SP1 may be arranged in each of the first unit area UA1 and the second unit area UA2. Each reinforcement support SP1 may have a bar or line shape extending in a specific direction.

[0064] The extension direction of the reinforcing support member SP1 arranged in the first unit area UA1 and the extension direction of the reinforcing support member SP1 arranged in the second unit area UA2 may be different from each other. For example, the reinforcing support member SP1 extending in the first direction FD may be arranged in the first unit area UA1, and the reinforcing support member SP1 extending in the second direction SD may be arranged in the second unit area UA2.

[0065] In each unit area UA, the extension direction of the reinforcing support member SP1 may be the same as the extension direction of the anti-warping groove RG. For example, in the first unit area UA1, the extension direction of the anti-warping groove RG and the extension direction of the reinforcing support member SP1 may be the same (e.g., the first direction FD). In the second unit area UA2, the extension direction of the anti-warping groove RG and the extension direction of the reinforcing support member SP1 may be the same (e.g., the second direction SD).

[0066] Reference Fig. 6A and Figure 6B In each unit area UA, the extension direction of the reinforcing support member SP1' may be different from the extension direction of the warpage prevention groove RG. For example, in the first unit area UA1, the extension direction of the warpage prevention groove RG may be the first direction FD, and the extension direction of the reinforcing support member SP1' may be the second direction SD. In the second unit area UA2, the extension direction of the warpage prevention groove RG may be the second direction SD, and the extension direction of the reinforcing support member SP1' may be the first direction FD.

[0067] Reference Fig. 7A A plurality of grooves R' may be formed on the front surface of the first substrate 10, and the reinforcing support member SP2 may be filled in the plurality of grooves R'. The reinforcing support member SP2 is used to suppress warping of the first wafer W1, and may be made of a material having a higher hardness than the first substrate 10.

[0068] Reference Figure 7B , a plurality of reinforcing supports SP2 may be arranged in each of the first unit area UA1 and the second unit area UA2. Figure 5A Similar to the reinforcing support member SP1 in FIG. 1 , the reinforcing support member SP2 may also have a strip or line shape extending in a specific direction.

[0069] The extension direction of the reinforcing support member SP2 arranged in the first unit area UA1 and the extension direction of the reinforcing support member SP2 arranged in the second unit area UA2 may be different from each other. For example, the extension direction of the reinforcing support member SP2 arranged in the first unit area UA1 may be the first direction FD, and the extension direction of the reinforcing support member SP2 arranged in the second unit area UA2 may be the second direction SD.

[0070] In each unit area UA, the extension direction of the reinforcing support member SP2 may be the same as the extension direction of the anti-warping groove RG. For example, in the first unit area UA1, the extension direction of the anti-warping groove RG and the extension direction of the reinforcing support member SP2 may be the same (e.g., the first direction FD). In the second unit area UA2, the extension direction of the anti-warping groove RG and the extension direction of the reinforcing support member SP2 may be the same (e.g., the second direction SD).

[0071] Reference Fig. 8A and Figure 8B , in each unit area UA, the extension direction of the reinforcing support member SP2' may be different from the extension direction of the anti-warping groove RG. For example, in the first unit area UA1, the extension direction of the anti-warping groove RG may be the first direction FD, and the extension direction of the reinforcing support member SP2' may be the second direction SD. In the second unit area UA2, the extension direction of the anti-warping groove RG may be the second direction SD, and the extension direction of the reinforcing support member SP2' may be the first direction FD.

[0072] Figures 9 to 13 is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to other embodiments of the present disclosure.

[0073] Reference Fig. 9 , the first warpage prevention pad DPAD1 may be defined on one surface S1 of the first wafer W1, and the second warpage prevention pad DPAD2 may be defined on one surface S2 of the second wafer W2. Figure 4A and Figure 4B When compared with the above-described embodiments, Fig. 9 The embodiment shown has the anti-warping groove omitted ( Figure 4A RG) and anti-warping ribs ( Figure 4A The structure of RR).

[0074] Reference Fig.10 , the first wafer W1 may further include a conductive reinforcement pattern CS1 surrounding the side and bottom surfaces of the first bonding pads PAD1. The conductive reinforcement pattern CS1 may be made of a conductive material having a higher hardness than the first bonding pads PAD1.

[0075] The conductive enhancement pattern CS1 can be formed in the same process step as the first anti-warpage pad DPAD1. For example, a first groove and a second groove having an opening width larger than the opening width of the first groove can be formed on a surface S1 of the first wafer W1, and a conductive material can be formed in the first groove and the second groove. Due to the difference in opening width between the first groove and the second groove, when the first groove with a smaller opening width is completely filled with a conductive material, the conductive material can be formed linearly only on the sidewall and bottom surface of the second groove with a larger opening width, or formed as a layer. The conductive material filled in the first groove can constitute the first anti-warpage pad DPAD1, and the conductive material layer formed on the sidewall and bottom surface of the second groove can constitute the conductive enhancement pattern CS1. After the conductive enhancement pattern CS1 is formed, the first bonding pad PAD1 is formed in the second groove.

[0076] Reference Fig.11 , the first wafer W1 may further include a conductive reinforcement pattern CS2 covering a bottom surface of the first bonding pads PAD1. The conductive reinforcement pattern CS2 may be made of a conductive material having a higher hardness than that of the first bonding pads PAD1.

[0077] The conductive reinforcement pattern CS2 may be formed in the same process step as the first warpage prevention pad DPAD1. Fig.10 After forming the conductive reinforcing pattern CS1 in the second trench, the conductive reinforcing pattern CS2 may be formed by removing the conductive reinforcing pattern CS1 formed on the sidewall of the second trench. As a result, the conductive reinforcing pattern CS2 is a portion of the conductive reinforcing pattern CS1 remaining on the bottom surface of the second trench.

[0078] Reference Fig.12 In order to increase the warpage suppression effect of the first warpage prevention pad DPAD1 in the first wafer W1, the first warpage prevention pad DPAD1 may be formed to have a thickness greater than that of the first bonding pad PAD1. For example, if the thickness of the first bonding pad PAD1 is T1, the thickness of the first warpage prevention pad DPAD1 may be T2 greater than T1.

[0079] In addition, if Fig.13 As shown, the first anti-warpage pad DPAD1 may have different thicknesses depending on the position. For example, the first anti-warpage pad DPAD1 overlapping the bit line BL in the vertical direction VD may have a thickness T2a, and the first anti-warpage pad DPAD1 not overlapping the bit line BL in the vertical direction VD may have a thickness T2b greater than T2a.

[0080] Fig.14is a top view showing the disposition of a first warpage prevention pad according to an embodiment of the present disclosure on a chip level structure.

[0081] Reference Fig.14 , the chip region CHIP of the first wafer W1 may include a first coupling region OFC and a second coupling region SR. A first bonding pad PAD1 coupled to a bit line may be arranged in the first coupling region OFC, and a first bonding pad PAD1 coupled to a word line may be arranged in the second coupling region SR.

[0082] The area outside the first coupling region OFC and the second coupling region SR may be defined as an open area. The first warpage prevention pad DPAD1 may be disposed in the open area. The length of the first warpage prevention pad DPAD1 may be determined in consideration of a pad alignment margin during wafer bonding.

[0083] Fig.15A is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to still another embodiment of the present disclosure, and Fig. 15B It is shown Fig.15A A top view of the extension direction of the anti-warping metal rib shown in FIG.

[0084] Reference Fig.15A The first wafer W1 may include a plurality of warpage prevention metal ribs MR. The warpage prevention metal ribs MR are used to prevent warpage of the first wafer W1, and may be disposed in the dielectric layer 30 and may be electrically isolated from the memory cell array MCA.

[0085] Reference Fig. 15B , a plurality of anti-warping metal ribs MR may be arranged in each of the first unit area UA1 and the second unit area UA2. Each anti-warping metal rib MR may have a strip or linear shape extending in a specific direction. The extension direction of the anti-warping metal ribs MR arranged in the first unit area UA1 and the extension direction of the anti-warping metal ribs MR arranged in the second unit area UA2 may be different from each other. For example, the extension direction of the anti-warping metal ribs MR arranged in the first unit area UA1 may be a first direction FD, and the extension direction of the anti-warping metal ribs MR arranged in the second unit area UA2 may be a second direction SD.

[0086] Return to reference Fig.15A , the warpage preventing metal ribs MR may be electrically connected to each other through the connection wirings IW.

[0087] The warpage preventing metal ribs MR may be electrically coupled to first warpage preventing pads DPAD1 defined on one surface S1 of the first wafer W1 .

[0088] The second wafer W2 may include a second anti-warpage pad DPAD2 bonded to the first anti-warpage pad DPAD1 on one surface S2 thereof. Although not shown, the second anti-warpage pad DPAD2 may be electrically connected to the logic circuit LOGIC and may be provided with a shield voltage from the logic circuit LOGIC. The shield voltage provided to the second anti-warpage pad DPAD2 may be transmitted to the anti-warpage metal rib MR and the connection wiring IW through the first anti-warpage pad DPAD1. The anti-warpage metal rib MR and the connection wiring IW may be used to suppress interference between the memory cell array MCA of the first wafer W1 and the logic circuit LOGIC of the second wafer W2.

[0089] Fig.16 is a cross-sectional view showing a semiconductor device having a three-dimensional structure according to another embodiment of the present disclosure.

[0090] Reference Fig.16 , an air gap AIR may be defined between adjacent warpage preventing metal ribs MR in the dielectric layer 30. The air gap AIR may have a stripe or line shape extending in the same direction as the extending direction of the warpage preventing metal ribs MR. The air gap AIR may be used to disperse or relieve stress, thereby suppressing warpage of the first wafer W1.

[0091] The dielectric constant of the air gap AIR is ε0 (=1) which is smaller than the dielectric constant (ε>1) of the dielectric layer 30. Therefore, when compared with a case where there is no air gap AIR, in a case where the air gap AIR is formed in the dielectric layer 30, the value of the coupling capacitance between the memory cell array MCA and the logic circuit LOGIC is reduced, and therefore, interference between the memory cell array MCA and the logic circuit LOGIC due to the coupling capacitance is reduced.

[0092] The above-mentioned exemplary embodiments of the present disclosure can be implemented not only by devices and methods, but also by programs that implement functions corresponding to the configurations of the exemplary embodiments of the present disclosure or by recording media on which the programs are recorded, and can be easily implemented by ordinary technicians in the field based on the description of the aforementioned exemplary embodiments.

[0093] Although exemplary embodiments of the present disclosure are described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered to be merely descriptive and not intended to limit the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted in conjunction with the appended claims, and include all equivalents that fall within the scope of the appended claims.

[0094] CROSS-REFERENCE TO RELATED APPLICATIONS

[0095] This application claims the priority of Korean Patent Application No. 10-2020-0111624 filed on September 2, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device having a three-dimensional structure, the semiconductor device comprising: a first wafer including a first bonding pad on a surface of the first wafer; a second wafer, the second wafer comprising a second bonding pad on one surface of the second wafer bonded to the one surface of the first wafer, the second bonding pad being bonded to the first bonding pad; as well as A plurality of warpage preventing metal ribs are defined in the first wafer and arranged in a stripe shape.

2. The semiconductor device according to claim 1, further comprising: a connection wiring connecting adjacent warping preventing metal ribs among the plurality of warping preventing metal ribs, Wherein, a shielding voltage is applied to the plurality of warping prevention metal ribs and the connection wiring.

3. The semiconductor device according to claim 1, wherein The first wafer comprises: a dielectric layer surrounding the plurality of anti-warping metal ribs; and An air gap is defined between the plurality of warpage preventing metal ribs in the dielectric layer.

4. The semiconductor device according to claim 1, wherein The first wafer includes a plurality of first unit regions and a plurality of second unit regions alternately arranged in a first direction and a second direction, The first direction and the second direction are parallel to the one surface of the first wafer and intersect each other, and An extending direction of the warpage preventing metal ribs provided in the plurality of first unit regions and an extending direction of the warpage preventing metal ribs provided in the plurality of second unit regions are different from each other.

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