Semiconductor device structure having liner with tapered sidewall

Abstract

The invention provides a semiconductor element structure. The semiconductor element structure comprises a first dielectric layer arranged on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a third dielectric layer disposed on the second dielectric layer; the conductive structure is arranged in the third dielectric layer, penetrates through the second dielectric layer and extends into the first dielectric layer; a liner surrounding the conductive structure, wherein the liner has a tapered sidewall in direct contact with the first dielectric layer; a spacer structure disposed between the liner and the second dielectric layer, wherein the spacer structure is in direct contact with a top surface of the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner; and a higher plug disposed over the inner silicide portion and the outer silicide portion.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2024100894084, filed on January 22, 2024, with the invention name of “Semiconductor element structure with a liner having tapered sidewalls and its preparation method”. Application No. 2024100894084 claims priority and benefits of U.S. formal application No. 18 / 381,907 filed on October 19, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device structure and a manufacturing method thereof, and more particularly to a semiconductor device structure with a liner having a tapered sidewall and a manufacturing method thereof. Background Art

[0003] Semiconductor components are essential to many modern applications. As electronic technology advances, semiconductor components are becoming smaller in size while providing more functionality and including a larger number of integrated circuits. As semiconductor components are miniaturized, various types and sizes of semiconductor components providing different functionality are integrated and packaged into a single module. In addition, multiple manufacturing operations are performed to integrate various types of semiconductor components together.

[0004] However, the manufacturing and integration of semiconductor devices involve many complex steps and operations. The integration in semiconductor devices is becoming more and more complex. The increasing complexity of semiconductor devices in manufacturing and integration may cause defects, such as insufficient step coverage and / or voids. Therefore, continuous improvement of the manufacturing process of semiconductor devices is needed to solve these problems.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] One aspect of the present disclosure provides a semiconductor element, including a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a third dielectric layer disposed on the second dielectric layer; a conductive structure disposed in the third dielectric layer, which passes through the second dielectric layer and extends into the first dielectric layer; a liner surrounding the conductive structure, wherein the liner has a tapered sidewall directly in contact with the first dielectric layer; a spacer structure disposed between the liner and the second dielectric layer, wherein the spacer structure is in direct contact with a top surface of the first dielectric layer; an inner silicide portion disposed on the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner; and a higher plug disposed on the inner silicide portion and the outer silicide portion.

[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor element, comprising forming a first dielectric layer on a semiconductor substrate; forming a second dielectric layer on the first dielectric layer; performing a first etching process to form an opening structure, wherein the opening structure has a tapered profile, and wherein the opening structure has a lower opening located in the first dielectric layer and a higher opening located in the second dielectric layer; performing a second etching process to laterally extend the higher opening of the opening structure so that an enlarged higher opening exposes a top surface of the first dielectric layer; forming a spacer structure on the top surface of the first dielectric layer; forming a liner covering the spacer structure; forming a conductive structure located on the liner and surrounded by the liner; recessing a top surface of the second dielectric layer; forming an inner silicide portion located on the conductive structure and an outer silicide portion surrounding the inner silicide portion and located on the conductive structure and the liner; and forming a higher plug on the inner silicide portion and the outer silicide portion.

[0008] Due to the design of the semiconductor device structure disclosed in the present invention, the liner includes a tapered sidewall that is in direct contact with the first dielectric layer, which helps to improve the step coverage of the liner and the overlying conductive structure. In addition, sufficient step coverage of the conductive structure can reduce electromigration (EM). As a result, the performance and reliability of the semiconductor device structure can be improved. In addition, the inner silicide portion and the outer silicide portion constitute a composite landing pad, which has an increased landing area for the higher plug to land. Therefore, the contact resistance can be reduced, and the problem of misalignment between the lower conductive structure and the higher plug can be avoided or reduced. In this way, the overall device performance can be improved, and the yield of the semiconductor device structure can be increased.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The various aspects of the present disclosure can be read in conjunction with the following drawings and detailed descriptions for easy understanding. It is emphasized that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced for the sake of clarity of discussion.

[0011] Figures 1 to 3 A cross-sectional view of a semiconductor device structure is shown according to some embodiments.

[0012] Figure 4 A flow chart of a method for preparing a semiconductor device structure is shown according to one embodiment.

[0013] Figures 5 to 21 A cross-sectional view showing a process of manufacturing a semiconductor device structure according to an embodiment.

[0014] Fig. 22 According to another embodiment, a flow chart of a method for preparing a semiconductor device structure is shown.

[0015] Fig.23 and Fig.24 A cross-sectional view showing a process of manufacturing a semiconductor device structure according to another embodiment.

[0016] Figure 25 to Figure 28 A cross-sectional view showing a process of manufacturing a semiconductor device structure according to another embodiment.

[0017] The reference numerals are described as follows:

[0018] 1A: Semiconductor device structure

[0019] 1B: Semiconductor device structure

[0020] 1C: Semiconductor device structure

[0021] 1D: Semiconductor device structure

[0022] 10: Methods

[0023] 40: Methods

[0024] 101: Semiconductor substrate

[0025] 103: First dielectric layer

[0026] 105: Second dielectric layer

[0027] 107: Patterned Mask

[0028] 110: Opening

[0029] 112: Open structure

[0030] 112a: Lower opening

[0031] 112b: Higher opening

[0032] 115: Patterned Mask

[0033] 118: Opening

[0034] 120: Enlarged higher opening

[0035] 123: Gasket material

[0036] 123': L-shaped pad

[0037] 125: Porous low dielectric constant dielectric layer

[0038] 127: Interval structure

[0039] 133: Lining

[0040] 135: Barrier layer

[0041] 137: Metal layer

[0042] 139: Metal filling part

[0043] 139TS: Top surface

[0044] 141: Conductive structure

[0045] 155: Energy Removable Layer

[0046] 157: Interval structure

[0047] 159: Energy Removable Layer

[0048] 159A: Air Gap

[0049] 159L: Padding

[0050] 160: Air Gap

[0051] 167: Interval structure

[0052] 171: The third dielectric layer

[0053] 171TS: Top surface

[0054] 173: Fourth dielectric layer

[0055] 310: Groove

[0056] 311: Patterned Mask

[0057] 313: Silicon layer

[0058] 315: Internal silicide part

[0059] 315TS: Top surface

[0060] 317: External silicide part

[0061] 317TS: Top surface

[0062] 319: Higher plug

[0063] B1: Bottom surface

[0064] B2: Bottom surface

[0065] S1: Sidewall

[0066] S2: Sidewall

[0067] S3: Sidewall

[0068] S4: Sidewall

[0069] S5: Sidewall

[0070] S6: Sidewall

[0071] S7: Sidewall

[0072] S8: Sidewall

[0073] S11: Steps

[0074] S13: Steps

[0075] S15: Steps

[0076] S17: Steps

[0077] S19: Steps

[0078] S21: Steps

[0079] S23: Steps

[0080] S25: Steps

[0081] S27: Steps

[0082] S29: Steps

[0083] S31: Steps

[0084] S33: Steps

[0085] S41: Steps

[0086] S43: Steps

[0087] S45: Steps

[0088] S47: Steps

[0089] S49: Steps

[0090] S51: Steps

[0091] S53: Steps

[0092] S55: Steps

[0093] S57: Steps

[0094] S59: Steps

[0095] S61: Steps

[0096] S63: Steps

[0097] S65: Steps

[0098] T1: Top surface

[0099] T2: Top surface

[0100] T3: Top surface

[0101] W1: Top width

[0102] W2: bottom width

[0103] W3: Width

[0104] θ1: Angle

[0105] θ2: Angle DETAILED DESCRIPTION

[0106] The following disclosure provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes specific examples of components and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not be used to limit the scope of the embodiments of the present disclosure. For example, when the description mentions that a first component is formed "on" or "on" a second component, it may include an embodiment in which the first component is in direct contact with the second component, and it may also include an embodiment in which there are other components formed between the two without direct contact. In addition, the present disclosure may repeat reference symbols and / or marks in different embodiments. These repetitions are for the purpose of simplicity and clarity, and are not used to limit the relationship between the different embodiments and / or structures discussed.

[0107] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used herein to facilitate describing the relationship between one element or component as shown in the drawings and another element or component. These spatially relative terms are intended to encompass different orientations of the element in use or operation other than the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative adjectives used therein may be interpreted similarly.

[0108] Figure 1 A cross-sectional view of a semiconductor device structure 1A is shown according to some embodiments. Figure 1 As shown, according to some embodiments, the semiconductor device structure 1A includes a semiconductor substrate 101, a first dielectric layer 103 disposed on the semiconductor substrate 101, a second dielectric layer 105 disposed on the first dielectric layer 103, a third dielectric layer 171 disposed on the second dielectric layer 105, and a fourth dielectric layer 173 disposed on the third dielectric layer 171.

[0109] In some embodiments, the semiconductor device structure 1A also includes a spacer structure 127 disposed in the second dielectric layer 105. In some embodiments, the spacer structure 127 is disposed on the top surface T1 of the first dielectric layer 103 and is in direct contact with the top surface T1 of the first dielectric layer 103. In some embodiments, the spacer structure 127 includes an L-shaped pad 123' and a porous low-k dielectric layer 125 disposed on the L-shaped pad 123'. In some embodiments, the top of the L-shaped pad 123' protrudes from the top surface T2 of the second dielectric layer 105.

[0110] In some embodiments, the semiconductor device structure 1A further includes a liner 133 covering the spacer structure 127. In some embodiments, the liner 133 is disposed in the third dielectric layer 171 and extends into the second dielectric layer 105 and the first dielectric layer 103. In some embodiments, the vertical sidewalls S7 and S8 of the liner 133 are in direct contact with the third dielectric layer 171. In addition, according to some embodiments, the liner 133 is in direct contact with the spacer structure 127 and the first dielectric layer 103. Figure 1 As shown, according to some embodiments, a bottom surface B2 of the liner 133 is lower than a top surface T1 of the first dielectric layer 103 and higher than a bottom surface B1 of the first dielectric layer 103 .

[0111] Furthermore, according to some embodiments, the liner 133 has tapered sidewalls S1 and S2 that are in direct contact with the first dielectric layer 103. Figure 1As shown, the liner 133 has an angle θ1 between the sidewall S1 and the bottom surface B2, and another angle θ2 between the sidewall S2 and the bottom surface B2. In some embodiments, each of the angles θ1 and θ2 is greater than 90 degrees. In some embodiments, the porous low-k dielectric layer 125 is enclosed by the liner 133 and the L-shaped liner 123' of the spacing structure 127.

[0112] In some embodiments, the semiconductor device structure 1A includes a conductive structure 141 disposed on and surrounded by the liner 133. In some embodiments, the conductive structure 141 includes a barrier layer 135 conformally disposed on and surrounded by the liner 133, a metal layer 137 disposed on and surrounded by the barrier layer 135, and a metal filling portion 139 disposed on and surrounded by the metal layer 137. In some embodiments, the conductive structure 141 is surrounded by the spacer structure 127.

[0113] Still refer to Figure 1 According to some embodiments, the metal-filled portion 139 of the conductive structure 141 has a tapered profile, wherein a bottom portion of the metal-filled portion 139 is narrower than a corresponding top portion of the metal-filled portion 139. For example, the metal-filled portion 139 has a top width W1 and a bottom width W2, and the top width W1 is greater than the bottom width W2. In some embodiments, the conductive structure 141 has a tapered profile, wherein a bottom portion of the conductive structure 141 is narrower than a corresponding top portion of the conductive structure 141.

[0114] Furthermore, in some embodiments, the conductive structure 141 passes through the third dielectric layer 171 and the second dielectric layer 105 and extends to a higher portion of the first dielectric layer 103. In some embodiments, the conductive structure 141 is separated from the first dielectric layer 103, the second dielectric layer 105, and the spacer structure 127 by the liner 133. In some embodiments, the metal layer 137 of the conductive structure 141 includes a copper-manganese (Cu-Mn) alloy, and the metal filling portion 139 of the metal conductive structure 141 includes copper (Cu).

[0115] Still refer to Figure 1, the semiconductor device structure 1A includes an inner silicide portion 315 and an outer silicide portion 317 disposed in the third dielectric layer 171. In some embodiments, the inner silicide portion 315 is disposed on the metal filling portion 139. In some embodiments, the outer silicide portion 317 is disposed on the metal layer 137, the barrier layer 135, the liner 133, and the L-shaped pad 123'. In some embodiments, the outer silicide portion 317 is disposed on the metal layer 137, the barrier layer 135, and the liner 133. It should be noted that according to some embodiments, the top surface 317TS of the outer silicide portion 317 is higher than the top surface 315TS of the inner silicide portion 315. In some embodiments, the top surface 317TS of the outer silicide portion 317 is the topmost surface of the outer silicide portion 317, and the top surface 315TS of the inner silicide portion 315 is the topmost surface of the inner silicide portion 315. In some embodiments, a top surface 317TS of the outer silicide portion 317 and a top surface T3 of the third dielectric layer 171 are substantially coplanar.

[0116] Still refer to Figure 1 , the semiconductor device structure 1A includes a higher plug 319 disposed in the fourth dielectric layer 173 and extending to the third dielectric layer 171. The higher plug 319 is disposed above the inner silicide portion 315 and the outer silicide portion 317. The higher portion of the higher plug 319 is disposed in the fourth dielectric layer 173, and the lower portion of the higher plug 319 is disposed in the third dielectric layer 171. In some embodiments, the width W3 of the higher plug 319 is greater than the top width W1 of the metal filling portion 139.

[0117] Figure 2 A cross-sectional view of a semiconductor device structure 1B is shown according to some other embodiments. The semiconductor device structure 1B is similar to the semiconductor device structure 1A. However, according to some embodiments, in the semiconductor device structure 1B, the porous low-k dielectric layer 125 is replaced by an energy-removable layer 155, and a spacer structure 157 including an L-shaped pad 123' and the energy-removable layer 155 is obtained.

[0118] In some embodiments, the energy removable layer 155 of the spacing structure 157 is surrounded by the liner 133 and the L-shaped pad 123' of the spacing structure 157. Details similar to those of the previous embodiments will not be repeated here.

[0119] Figure 3 A cross-sectional view of a semiconductor device structure 1C is shown according to some other embodiments. The semiconductor device structure 1C is similar to the semiconductor device structure 1B. However, according to some embodiments, in the semiconductor device structure 1C, the energy removable layer 155 is replaced by an air gap 160, and a spacer structure 167 including an L-shaped pad 123' and the air gap 160 is obtained.

[0120] In some embodiments, the semiconductor device structure 1C is formed by performing a heat treatment process on the semiconductor device structure 1B, and the energy removable layer 155 is transformed into the air gap 160 during the heat treatment process. In some embodiments, the air gap 160 of the spacer structure 167 is surrounded by the liner 133 and the L-shaped pad 123' of the spacer structure 167. The details of this embodiment similar to the above-mentioned embodiment will not be repeated here.

[0121] Figure 4 A flow chart of a method 10 for preparing a semiconductor device structure 1A is shown according to some embodiments, and the method 10 includes steps S11 , S13 , S15 , S17 , S19 , S21 , S23 , S25 , S27 , S29 , S31 , and S33 . Figure 4 Steps S11 to S33 will be described in conjunction with the following diagrams, for example Figure 1 and Figures 5 to 21 .

[0122] Figures 5 to 21 A cross-sectional view showing an intermediate stage of forming a semiconductor device structure 1A according to some embodiments. Figure 5 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

[0123] Alternatively or additionally, the semiconductor substrate 101 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0124] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be formed using separation by implantation oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0125] According to some embodiments, a first dielectric layer 103 is formed on the semiconductor substrate 101, such as Figure 5 The corresponding steps are Figure 4 The method 10 is shown as step S11. In some embodiments, the first dielectric layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or another suitable material. The manufacturing technology of the first dielectric layer 103 can include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or another suitable method.

[0126] Next, according to some embodiments, a second dielectric layer 105 is formed on the first dielectric layer 103, such as Figure 5 Some materials and processes used to form the second dielectric layer 105 are similar or identical to those used to form the first dielectric layer 103, and their details are not repeated here. Figure 4 This is shown as step S11 in the method 10 shown.

[0127] Still refer to Figure 5 According to some embodiments, a patterned mask 107 having an opening 110 is formed on the second dielectric layer 105. In some embodiments, the opening 110 partially exposes the second dielectric layer 105. In some embodiments, the second dielectric layer 105 and the patterned mask 107 include different materials so that the etching selectivity in a subsequent etching process can be different.

[0128] Then, according to some embodiments, an etching process (also referred to as a first etching process) is performed using the patterned mask 107 as a mask, thereby forming an opening structure 112 in the first dielectric layer 103 and the second dielectric layer 105. Figure 6 In some embodiments, the opening structure 112 includes a lower opening 112a in the first dielectric layer 103 and a higher opening 112b in the second dielectric layer 105. The corresponding steps are as follows: Figure 4 This is shown as step S13 in the method 10. In some embodiments, the first etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0129] In some embodiments, the opening structure 112 passes through the second dielectric layer 105 and extends to a higher portion of the first dielectric layer 103. In other words, the opening structure 112 stops at an intermediate level of the first dielectric layer 103. For example, according to some embodiments, the bottom surface B2 of the opening structure 112 is located between the top surface T1 and the bottom surface B1 of the first dielectric layer 103, such as Figure 6 shown.

[0130] In addition, according to some embodiments, the opening structure 112 has a tapered profile, wherein the bottom portion of the opening structure 112 is narrower than the corresponding top portion of the opening structure 112. In some embodiments, the opening structure 112 has tapered sidewalls, such as sidewalls S1 and S2 in the first dielectric layer 103, and sidewalls S3 and S4 in the second dielectric layer 105. In some embodiments, the sidewall S1 is aligned with the sidewall S3, and the angle θ1 between the sidewall S1 and the bottom surface B2 of the opening structure 112 is greater than 90 degrees. In some embodiments, the sidewall S2 is aligned with the sidewall S4, and the angle θ2 between the sidewall S2 and the bottom surface B2 of the opening structure 112 is greater than 90 degrees. After the opening structure 112 is formed, the patterned mask 107 is removed. In some embodiments, the patterned mask 107 is removed by a stripping process, an ashing process, an etching process, or another suitable process. After the patterned mask 107 is removed, the top surface T2 (not shown) of the second dielectric layer 105 is exposed.

[0131] Next, according to some embodiments, a patterned mask 115 having an opening 118 is formed on the second dielectric layer 105, such as Figure 7 In some embodiments, the opening 118 of the patterned mask 115 exposes a portion of the top surface T2 of the second dielectric layer 105 close to the opening structure 112. In some embodiments, the second dielectric layer 105 and the patterned mask 115 include different materials, so that the etching selectivity in the subsequent etching process can be different.

[0132] Then, according to some embodiments, an etching process (also referred to as a second etching process) is performed using the patterned mask 115 as a mask, thereby forming an enlarged higher opening 120 in the second dielectric layer 105, such as Figure 8 In some embodiments, the higher opening 112b of the opening structure 112 (see Figure 7 ) is laterally extended by the second etching process. As a result, the sidewalls S5 and S6 of the enlarged higher opening 120 are obtained, and the enlarged higher opening 120 partially exposes the top surface T1 of the first dielectric layer 103. The corresponding steps are Figure 4 This is shown as step S15 in the method 10 shown.

[0133] In some embodiments, the lower opening 112a of the original opening structure 112 remains substantially intact during the second etching process. In the context of the present disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, further preferably 98%, and most preferably 99%. In some embodiments, after the second etching process, the angle θ1 and the angle θ2 are both greater than 90 degrees. After the enlarged upper opening 120 is formed, the patterned mask 115 can be removed.

[0134] Then, according to some embodiments, a liner material 123 is formed to line the lower opening 112a and the enlarged upper opening 120, such as Fig. 9 The corresponding steps are Figure 4 In the method 10 shown in FIG. 1 , it is shown as step S17. In some embodiments, after removing the patterned mask 115, the liner material 123 is conformally formed on the Figure 8 on the structure.

[0135] In some embodiments, a liner material 123 is formed to line the bottom surface B2 and sidewalls S1, S2 of the lower opening 112a, and to line the sidewalls S5, S6 of the enlarged upper opening 120. In some embodiments, the portion of the top surface T1 of the first dielectric layer 103 exposed by the enlarged upper opening 120 is covered by and in direct contact with the liner material 123. In some embodiments, the liner material 123 further extends to cover the top surface T2 of the second dielectric layer 105.

[0136] In addition, in some embodiments, the liner material 123 includes a dielectric material, such as silicon nitride, a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN), or another suitable dielectric material. In some embodiments, the manufacturing technology of the liner material 123 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or another suitable method.

[0137] Next, according to some embodiments, a porous low-k dielectric layer 125 is formed on the liner material 123, such as Fig.10 The corresponding steps are Figure 4 In the method 10 shown in FIG. 1 , the porous low-k dielectric layer 125 is conformally formed on the Fig. 9 on the structure.

[0138] In some embodiments, the porous low-k dielectric layer 125 comprises silicon oxide, silicon nitride, silicon oxynitride, or another suitable low-k material. For example, the dielectric constant (k value) of the low-k material may be less than about 3.0. In some embodiments, the fabrication technique of the porous low-k dielectric layer 125 comprises a deposition process, such as a CVD process, a PVD process, an ALD process, or another suitable method.

[0139] Subsequently, according to some embodiments, an etching process (also referred to as a third etching process) is performed to partially remove the liner material 123 and the porous low-k dielectric layer 125, thereby obtaining a spacer structure 127 including the remaining portion of the liner material 123 and the porous low-k dielectric layer 125, as shown in FIG. Fig.11 The corresponding steps are Figure 4 This is shown as step S21 in the illustrated method 10. In some embodiments, the remaining portion of the gasket material 123 has an "L" shape, which is referred to as an L-shaped gasket 123'.

[0140] In some embodiments, after performing the third etching process, the spacer structure 127 partially exposes the sidewalls S5 and S6 of the enlarged upper opening 120, and exposes the sidewalls S1, S2 and the bottom surface B2 of the lower opening 112a. In some embodiments, the exposed portions of the sidewalls S5 and S6 are located above the spacer structure 127. In some embodiments, after forming the spacer structure 127, the top surface T2 of the second dielectric layer 105 is exposed.

[0141] In some embodiments, the liner material 123 and the porous low-k dielectric layer 125 are etched by an anisotropic etching process that vertically removes equal amounts of the liner material 123 and the porous low-k dielectric layer 125 at all locations, leaving the spacer structure 127 on the lower portion of the sidewalls S5 and S6 of the second dielectric layer 105. In some embodiments, the third etching process is a dry etching process, such as plasma etching, reactive-ion etching (RIE), neutral beam etching (NBE), or the like.

[0142] Then, according to some embodiments, a liner 133 is conformally formed on Fig.11The liner 133 covers the spacing structure 127, such as Fig.12 The corresponding steps are Figure 4 This is shown as step S23 in the illustrated method 10. In some embodiments, the liner 133 is formed to line the bottom surface B2 and the sidewalls S1 and S2 of the lower opening 112a.

[0143] In some embodiments, the liner 133 is formed to cover the spacer structure 127 and the portions of the sidewalls S5 and S6 exposed by the spacer structure 127. In some embodiments, the liner 133 further extends to cover the top surface T2 of the second dielectric layer 105. In some embodiments, the porous low-k dielectric layer 125 of the spacer structure 127 is enclosed by the L-shaped liner 123' and the liner 133.

[0144] In some embodiments, the liner 133 includes a dielectric material, such as silicon nitride, a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN), or another suitable dielectric material. In some embodiments, the manufacturing technique of the liner 133 includes a deposition process, such as a CVD process, a PVD process, an ALD process, or another suitable method. After the liner 133 is formed, the sidewalls S1 and S2 of the lower opening 112a are also referred to as the tapered sidewalls of the liner 133, and the bottom surface B2 of the lower opening 112a is also referred to as the bottom surface of the liner 133.

[0145] Next, according to some embodiments, a barrier layer 135 is conformally formed on the liner 133, such as Fig.13 As shown. In some embodiments, the barrier layer 135 further extends above the top surface T2 of the second dielectric layer 105. In some embodiments, the barrier layer 135 comprises tantalum (Ta), tantalum nitride (TaN), titanium (Ti), nitride (TiN), cobalt tungsten (CoW), another suitable material, or a combination thereof. In addition, the manufacturing technology of the barrier layer 135 may include a deposition process, such as a CVD process, a PVD process, an ALD process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, or another suitable process.

[0146] Then, according to some embodiments, a metal layer 137 is conformally formed on the barrier layer 135, such as Fig.14As shown. In some embodiments, the metal layer 137 further extends above the top surface T2 of the second dielectric layer 105. In some embodiments, the metal layer 137 includes a copper-containing alloy, such as a copper-manganese (Cu-Mn) alloy. However, any other suitable material may be used, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag). Some processes for forming the metal layer 137 are similar or identical to the processes for forming the barrier layer 135, and the details thereof will not be repeated here.

[0147] Then, according to some embodiments, the remaining portion of the enlarged upper opening 120 and the remaining portion of the lower opening 112a (if any) are filled with a metal filling portion 139, such as Fig.15 As shown. In some embodiments, the metal filling portion 139 further extends above the top surface T2 of the second dielectric layer 105. In some embodiments, the metal filling portion 139 includes copper (Cu). However, any other suitable material may be used, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag). Some processes for forming the metal filling portion 139 are similar or identical to the processes for forming the barrier layer 135, and the details thereof will not be repeated here.

[0148] Next, according to some embodiments, a planarization process is performed on the metal filling portion 139, the metal layer 137, and the barrier layer 135 until the liner 133 is exposed, such as Fig.16 After the planarization process, the metal filling portion 139 , the metal layer 137 , and the remaining portion of the barrier layer 135 together form a conductive structure 141 .

[0149] In some embodiments, the conductive structure 141 is surrounded by the liner 133 and the spacer structure 127. In some embodiments, the conductive structure 141 is separated from the second dielectric layer 105, the spacer structure 127, and the first dielectric layer 103 by the liner 133. The planarization process may include a chemical mechanical polishing (CMP) process. Figure 4 This is shown as step S25 in the method 10 shown.

[0150] In some embodiments, the liner 133 of the semiconductor device structure 1A has tapered sidewalls S1 and S2 that are in direct contact with the first dielectric layer 103, which helps to improve the step coverage of the liner 133 and the conductive structure 141 located above the liner 133. In addition, sufficient step coverage of the conductive structure 141 can reduce electromigration. In addition, the porous low-k dielectric layer 125 of the spacer structure 127 can reduce the resistive-capacitive (RC) delay in signal propagation. As a result, the performance and reliability of the semiconductor device structure can be improved.

[0151] Next, according to some embodiments, a patterned mask 311 is formed to cover the conductive structure 141. In some embodiments, the patterned mask 311 and the liner 133 include different materials, so that the etching selectivity in the subsequent etching process can be different. In some embodiments, the patterned mask 311 and the second dielectric layer 105 include different materials, so that the etching selectivity in the subsequent etching process can be different.

[0152] Then, according to some embodiments, an etching process (also referred to as a fourth etching process) is performed using the patterned mask 311 as a mask to remove a portion of the liner 133 and the second dielectric layer 105. Fig.18 As shown. The top surface T2 of the second dielectric layer 105 is recessed. The exposed sidewalls of the liner 133 are referred to as sidewalls S7 and S8. In some embodiments, the top surface T2 is lower than the top surface 139TS of the metal filling portion 139. In some embodiments, the top surface T2 of the second dielectric layer 105 is recessed to partially expose the L-shaped liner 123'. In some embodiments, after the second dielectric layer 105 is recessed, the L-shaped liner 123' is still covered by the second dielectric layer 105. The corresponding steps are as follows. Figure 4 This is shown as step S27 in the method 10. In some embodiments, the fourth etching process includes a dry etching process, such as an anisotropic dry etching process. After the top surface T2 of the second dielectric layer 105 is recessed, the patterned mask 311 is removed.

[0153] Next, according to some embodiments, a silicon layer 313 is conformally deposited on and in direct contact with the second dielectric layer 105, the conductive structure 141, the liner 133, and the L-shaped pad 123', such as Fig.19 The corresponding steps are Figure 4 This is shown as step S29 in the method 10. In some embodiments, the silicon layer 313 covers the top surface T2 of the second dielectric layer 105, the sidewalls S7 and S8 of the liner 133, the higher portion of the L-shaped pad 123', and the top surface of the conductive structure 141. In some embodiments, the manufacturing technology of the silicon layer 313 includes a CVD process, a PVD process, an ALD process, a spin coating process, or another applicable process.

[0154] According to some embodiments, after the silicon layer 313 is deposited, a self-aligned silicide process is performed to form an inner silicide portion 315 on the metal filling portion 139 and an outer silicide portion 317 on the metal layer 137, the barrier layer 135, the liner 133, and the L-shaped pad 123', as shown in FIG. Fig. 20 The corresponding steps are Figure 4 This is shown as step S31 in the method 10 shown.

[0155] In this embodiment, a self-aligned silicidation process is performed to grow silicide on the exposed surface. More specifically, in the illustrated embodiment, the inner silicide portion 315 and the outer silicide portion 317 are formed by reacting the conductive structure 141, the liner 133, and the L-shaped pad 123' with the silicon layer 313, and the unreacted portion of the silicon layer 313 is removed by annealing and etching. Fig. 20 According to some embodiments, the inner silicide portion 315 is grown on the top surface 139TS of the metal filling portion 139, and the outer silicide portion 317 is grown to cover the metal layer 137, the barrier layer 135, the top surface of the liner 133, the sidewalls S7 and S8 of the liner 133, and the higher portion of the L-shaped pad 123'.

[0156] Furthermore, in some embodiments, the material of the metal filling portion 139 is selected so that the metal layer 137, the barrier layer 135, and the liner layer 133 exhibit a greater silicidation rate than the metal filling portion 139. Therefore, the outer silicide portion 317 grows faster than the inner silicide portion 315. In some embodiments, after the self-aligned silicidation process, the top surface 317TS of the outer silicide portion 317 is greater than the top surface 315TS of the inner silicide portion 315. In some embodiments, the metal layer 137 and the barrier layer 135 include a titanium-containing material, and the outer silicide portion 317 includes a titanium-containing silicide.

[0157] In some embodiments, the inner silicide portion 315 is surrounded by the outer silicide portion 317, and a groove 310 is formed on the inner silicide portion 315 and surrounded by the outer silicide portion 317. In addition, according to some embodiments, the outer silicide portion 317 is in direct contact with the top surface T2 of the second dielectric layer 105. Since the manufacturing technology of the inner silicide portion 315 and the outer silicide portion 317 includes a self-aligned silicide process, the related cost can be reduced.

[0158] Next, according to some embodiments, a third dielectric layer 171 is deposited on the second dielectric layer 105, and the third dielectric layer 171 covers the inner silicide portion 315 and the outer silicide portion 317, such as Fig.21 As shown. A planarization process is performed until the top surface 317TS of the outer silicide portion 317 is exposed to provide a substantially flat surface for subsequent processes. Some materials and processes used to form the third dielectric layer 171 are similar or identical to the materials and processes used to form the first dielectric layer 103, and their details are not repeated here. In some embodiments, the top surface 171TS of the third dielectric layer 171 and the top surface 317TS of the outer silicide portion 317 are substantially coplanar.

[0159] Next, a fourth dielectric layer 173 may be formed on the third dielectric layer 171. Some materials and processes used to form the fourth dielectric layer 173 are similar or identical to those used to form the first dielectric layer 103, and the details thereof are not repeated here. Figure 5 and Figure 6 The etching process shown is used to form an opening (not shown). The opening exposes the inner silicide portion 315 and a portion of the outer silicide portion 317 adjacent to the inner silicide portion 315.

[0160] Next, according to some embodiments, a tall plug 319 is formed in the opening to directly contact the inner silicide portion 315 and the outer silicide portion 317, such as Figure 1 As shown. In some embodiments, the upper plug 319 includes tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), a combination of the foregoing, or another applicable metal material. The formation of the upper plug 319 may include a deposition process and a planarization process. The deposition process may be a CVD process, a PVD process, an ALD process, an MOCVD process, a sputtering process, an electroplating process, or another applicable process. The planarization process may include a CMP process. The corresponding steps are as follows. Figure 4 This is shown as step S33 in the method 10 shown.

[0161] Fig. 22 A flow chart of a method 40 for preparing semiconductor device structures 1B and 1C is shown according to some embodiments, and the method 40 includes steps S41 , S43 , S45 , S47 , S49 , S51 , S53 , S55 , S57 , S59 , S61 , S63 , and S65 . Fig. 22 Steps S41 to S65 will be described in conjunction with the following diagrams, for example Fig.23 and Fig.24 The heat treatment process in step S65 is optional. In the embodiment for forming the semiconductor device structure 1B, after step S63, the following is obtained: Figure 2The semiconductor device structure 1B shown in FIG. 1B can be omitted, and step S65 can be omitted. In the embodiment for forming the semiconductor device structure 1C, after step S65, the following is obtained: Figure 3 The semiconductor device structure 1C is shown.

[0162] Fig.23 and Fig.24 The cross-sectional view shows the intermediate stages of forming semiconductor device structures 1B and 1C according to one embodiment. Fig.23 The operations for forming the semiconductor device structures 1B and 1C before the structure shown in FIG. 1 can be similar to those for forming the semiconductor device structures 1B and 1C. Figures 5 to 9 The operation of the semiconductor device structure 1A shown is substantially the same ( Fig. 22 Steps S41 to S47 in the method 40 shown in FIG. Figure 4 The steps S11 to S17 in the method 10 shown are the same), and the relevant detailed description can be referred to the aforementioned paragraphs and will not be discussed here.

[0163] According to some embodiments, after forming the liner material 123 lining the lower opening 112a and the enlarged upper opening 120, an energy removable layer 155 is formed on the liner material 123, such as Fig.23 The corresponding steps are Fig. 22 In the method 40 shown in FIG. 40 , the energy removable layer 155 is formed conformally. Fig. 9 In some embodiments, the energy removable layer 155 extends above the top surface T2 of the second dielectric layer 105 .

[0164] In some embodiments, the energy removable layer 155 includes a thermally decomposable material. In some other embodiments, the energy removable layer 155 includes a photon decomposable material, an electron beam decomposable material, or another suitable energy decomposable material. In some embodiments, the energy removable material includes a substrate and a decomposable porogen material that is substantially removed upon exposure to an energy source (e.g., heat). In this case, the substrate may include hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon dioxide (SiO2), and the decomposable porogen material may include a porogen organic compound that can provide porosity to the space initially occupied by the energy removable layer 155 in a subsequent process. In addition, the deposition of the energy removable layer 155 may include a CVD process, a PVD process, an ALD process, a spin coating process, or another suitable process.

[0165] Subsequently, according to some embodiments, an etching process (also referred to as a fifth etching process) is performed to partially remove the liner material 123 and the energy-removable layer 155, thereby obtaining a spacer structure 157 including the remaining portion of the liner material 123 and the energy-removable layer 155, as shown in FIG. Fig.24 The corresponding steps are Fig. 22 This is shown as step S51 in the illustrated method 40. In some embodiments, the remaining portion of the gasket material 123 has an "L" shape, which is referred to as an L-shaped gasket 123'.

[0166] In some embodiments, after performing the fifth etching process, the spacer structure 157 partially exposes the sidewalls S5 and S6 of the enlarged upper opening 120, and exposes the sidewalls S1, S2 and the bottom surface B2 of the lower opening 112a. In some embodiments, the exposed portions of the sidewalls S5 and S6 are located above the spacer structure 157. In some embodiments, after forming the spacer structure 157, the top surface T2 of the second dielectric layer 105 is exposed.

[0167] In some embodiments, the liner material 123 and the energy removable layer 155 are etched by an anisotropic etching process that vertically removes equal amounts of the liner material 123 and the energy removable layer 155 at all locations, leaving the spacer structure 157 on the lower portion of the sidewalls S5 and S6 of the second dielectric layer 105. In some embodiments, the third etching process is a dry etching process, such as plasma etching, RIE, NBE, or the like.

[0168] Then, using something like Figures 12 to 21 The steps shown in FIG. 1 are used to form the liner 133, the inner silicide portion 315, the outer silicide portion 317, the third dielectric layer 171, the fourth dielectric layer 173, and the upper plug 319, and the description thereof will not be repeated here. After forming the upper plug 319, the Figure 2 The semiconductor device structure 1B shown. In the semiconductor device structure 1B, the energy removable layer 155 of the spacer structure 157 is enclosed by the L-shaped liner 123 ′ and the liner 133 .

[0169] According to some embodiments, after obtaining the semiconductor device structure 1B, a thermal treatment process may be performed to transform the energy removable layer 155 of the spacer structure 157 into the air gap 160, such as Figure 3 The corresponding steps are Fig. 22 This is shown as step S65 in the illustrated method 40. It should be noted that step S65 is optional.

[0170] In some embodiments, the temperature used in the heat treatment process can be high enough to effectively burn away the energy removable layer 155, thereby leaving the air gap 160 in the spacer structure 167. After forming the air gap 160 of the spacer structure 167, the semiconductor device structure 1C is obtained. In the semiconductor device structure 1C, the air gap 160 of the spacer structure 167 is closed by the L-shaped liner 123' and the liner 133.

[0171] In the embodiments of the semiconductor device structures 1B and 1C, the liner 133 has tapered sidewalls S1 and S2 that are in direct contact with the first dielectric layer 103, which helps to improve the step coverage of the liner 133 and the conductive structure 141 located above the liner 133. In addition, sufficient step coverage of the conductive structure 141 can reduce electromigration. In addition, the energy removable layer 155 of the spacer structure 157 and the air gap 160 of the spacer structure 167 can reduce RC delay in signal propagation. As a result, the performance and reliability of the semiconductor device structure can be improved.

[0172] The present disclosure provides embodiments of semiconductor device structures and methods for making the same. In some embodiments, the semiconductor device structure includes a first dielectric layer (e.g., first dielectric layer 103) and a second dielectric layer (e.g., second dielectric layer 105) disposed on the first dielectric layer, and a conductive structure (e.g., conductive structure 141 including barrier layer 135, metal layer 137, and metal filling portion 139) passing through the second dielectric layer and extending into the first dielectric layer. In some embodiments, the conductive structure is separated from the first dielectric layer by a liner (e.g., liner 133), and the liner has a tapered sidewall (e.g., sidewalls S1 and S2) that is in direct contact with the first dielectric.

[0173] Since the opening in the first dielectric layer (e.g., the lower opening 112a) has a tapered sidewall for the liner to be arranged thereon, the conformality (i.e., step coverage) of the liner can be improved, and the step coverage of the conductive structure disposed on the liner can also be improved. Sufficient step coverage of the conductive structure can reduce electromigration. As a result, the performance and reliability of the semiconductor device structure can be improved.

[0174] In addition, the inner silicide portion 315 and the outer silicide portion 317 form a composite landing pad having an increased landing area for the upper plug 319 to land on. Therefore, the contact resistance can be reduced, and the misalignment problem between the lower conductive structure 141 and the upper plug 319 can be avoided or reduced. In this way, the overall device performance can be improved, and the yield of the semiconductor device structure can be increased.

[0175] Figure 25 to Figure 28 A cross-sectional view of a semiconductor device structure 1D is shown according to some embodiments.

[0176] like Fig.25 As shown, we can use similar Figures 5 to 11 The intermediate semiconductor element is prepared by the steps shown in the figure, and its description is not repeated here. Fig.25 As shown, an energy removable layer 159 is formed in the second dielectric layer 105 and between two adjacent intermediate structures. An opening (not shown) is formed in Fig.25 Between the two adjacent intermediate structures shown. Fig.23 The steps shown are to deposit the energy removable layer 159 to fill the openings, and a description thereof will not be repeated here. The enlarged higher openings 120 may be masked during the formation of the energy removable layer 159.

[0177] like Fig.26 As shown, a liner 133 may be formed to cover the energy removable layer 159. Figures 12 to 15 The liner layer 133, the porous low-k dielectric layer 125, the metal layer 137, and the metal filling portion 139 are formed by the steps shown, and a description thereof will not be repeated here.

[0178] like Fig. 27 As shown, using similar Figures 16 to 21 The steps shown form the conductive structure 141 , the inner silicide portion 315 , the outer silicide portion 317 , the third dielectric layer 171 , the fourth dielectric layer 173 , and the upper plug 319 , and a description thereof will not be repeated herein.

[0179] Reference Fig.28 , and Fig. 22 The heat treatment process is similar to the heat treatment process shown in step S65 of the method 40 shown in FIG. 40, and its description is not repeated here. In some embodiments, during the heat treatment process, the remaining energy can be removed and transformed into an air gap structure including an air gap 159A enclosed by a liner 159L. After forming the air gap 159A, a semiconductor device structure 1D is obtained. By using the air gap 159A between adjacent conductive components (e.g., the conductive structure 141 and the higher plug 319), the parasitic capacitance between the conductive components can be reduced. As a result, the performance and reliability of the semiconductor device structure can be improved.

[0180] One aspect of the present disclosure provides a semiconductor element, comprising a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a third dielectric layer disposed on the second dielectric layer; a spacing structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, which passes through the second dielectric layer and extends into the first dielectric layer, wherein the conductive structure is surrounded by the spacing structure; a liner separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacing structure, wherein the liner has a tapered sidewall directly in contact with the first dielectric layer; an inner silicide portion disposed on the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner; and a higher plug disposed on the inner silicide portion and the outer silicide portion.

[0181] One aspect of the present disclosure provides a semiconductor element, including a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a third dielectric layer disposed on the second dielectric layer; a conductive structure disposed in the third dielectric layer, which passes through the second dielectric layer and extends into the first dielectric layer; a liner surrounding the conductive structure, wherein the liner has a tapered sidewall directly in contact with the first dielectric layer; a spacer structure disposed between the liner and the second dielectric layer, wherein the spacer structure is in direct contact with a top surface of the first dielectric layer; an inner silicide portion disposed on the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner; and a higher plug disposed on the inner silicide portion and the outer silicide portion.

[0182] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including forming a first dielectric layer on a semiconductor substrate; forming a second dielectric layer on the first dielectric layer; performing a first etching process to form an opening structure, wherein the opening structure has a tapered profile, and wherein the opening structure has a lower opening located in the first dielectric layer and a higher opening located in the second dielectric layer; performing a second etching process to laterally extend the higher opening of the opening structure so that a top surface of the first dielectric layer is exposed by an enlarged higher opening; forming a spacing structure on the top surface of the first dielectric layer; forming a liner covering the spacing structure; forming a conductive structure located on the liner and surrounded by the liner; recessing a top surface of the second dielectric layer; forming an inner silicide portion located on the conductive structure and an outer silicide portion surrounding the inner silicide portion and located on the conductive structure and the liner; and forming a higher plug on the inner silicide portion and the outer silicide portion.

[0183] Due to the design of the semiconductor device structure disclosed in the present invention, the liner 133 includes tapered sidewalls S1 and S2 that are in direct contact with the first dielectric layer 103, which helps to improve the step coverage of the liner 133 and the overlying conductive structure 141. In addition, sufficient step coverage of the conductive structure 141 can reduce electromigration (EM). As a result, the performance and reliability of the semiconductor device structure 1A can be improved. In addition, the inner silicide portion 315 and the outer silicide portion 317 constitute a composite landing pad, which has an increased landing area for the higher plug 319 to land. Therefore, the contact resistance can be reduced, and the problem of misalignment between the lower conductive structure 141 and the higher plug 319 can be avoided or reduced. In this way, the overall device performance can be improved, and the yield of the semiconductor device structure 1A can be increased.

[0184] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0185] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: A first dielectric layer is disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a third dielectric layer disposed on the second dielectric layer; a conductive structure disposed in the third dielectric layer, passing through the second dielectric layer, and extending into the first dielectric layer; a liner layer surrounding the conductive structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; a spacing structure disposed between the liner and the second dielectric layer, wherein the spacing structure is in direct contact with a top surface of the first dielectric layer; an inner silicide portion disposed on the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner; as well as A higher plug is disposed above the inner silicide portion and the outer silicide portion. 2 . The semiconductor device structure as claimed in claim 1 , wherein the liner is in direct contact with the third dielectric layer, the second dielectric layer, the spacer structure, the conductive structure and the outer silicide portion. 3 . The semiconductor device structure as claimed in claim 1 , wherein a bottom surface of the liner is higher than a bottom surface of the first dielectric layer, and an angle between the tapered sidewall and the bottom surface of the liner is greater than 90 degrees.

4. The semiconductor device structure as claimed in claim 1, wherein the conductive structure further comprises: a metal filling portion; a metal layer surrounding the metal filling portion; as well as A barrier layer surrounds the metal layer. 5 . The semiconductor device structure as claimed in claim 4 , wherein a top width of the metal filling portion is greater than a bottom width of the metal filling portion. 6 . The semiconductor device structure as claimed in claim 4 , wherein the metal filling portion comprises copper (Cu), and the metal layer comprises a copper-manganese (Cu—Mn) alloy.

7. The semiconductor device structure as claimed in claim 5, wherein the spacer structure further comprises: an L-shaped pad; as well as A porous low-k dielectric layer surrounds the L-shaped pad and the liner.

8. The semiconductor device structure as claimed in claim 1, wherein the spacer structure further comprises: an L-shaped pad; as well as An energy removable layer surrounds the L-shaped pad and the liner.

9. The semiconductor device structure as claimed in claim 1, wherein the spacer structure further comprises: an L-shaped pad; as well as An air gap is enclosed by the L-shaped gasket and the lining.

10. A method for preparing a semiconductor element, comprising: forming a first dielectric layer on a semiconductor substrate; forming a second dielectric layer on the first dielectric layer; Performing a first etching process to form an opening structure, wherein the opening structure has a tapered profile, and wherein the opening structure has a lower opening located in the first dielectric layer and a higher opening located in the second dielectric layer; Performing a second etching process to laterally extend the upper opening of the opening structure so that an enlarged upper opening exposes a top surface of the first dielectric layer; forming a spacer structure on the top surface of the first dielectric layer; forming a lining layer covering the spacer structure; forming a conductive structure located on the liner and surrounded by the liner; recessing a top surface of the second dielectric layer; forming an inner silicide portion located on the conductive structure and an outer silicide portion surrounding the inner silicide portion and located on the conductive structure and the liner; as well as A higher plug is formed over the inner silicide portion and the outer silicide portion. 11 . The method of claim 10 , wherein a top surface of the outer silicide portion is higher than a top surface of the inner silicide portion.

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