Semiconductor device

Abstract

A semiconductor device includes: a capacitor structure including: a bottom electrode; the first dielectric layer is positioned on the bottom electrode; the second dielectric layer is positioned on the first dielectric layer; the third dielectric layer is positioned on the second dielectric layer; and a top electrode on the third dielectric layer, where each of the first dielectric layer and the third dielectric layer includes zirconium oxide, the second dielectric layer includes hafnium zirconium oxide, and the top electrode includes hafnium zirconium oxide. And each of the first dielectric layer, the second dielectric layer, and the third dielectric layer includes a first crystal phase and a second crystal phase.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a capacitor structure. Background Art

[0002] Semiconductor devices are considered important elements in the electronics industry due to their small size, multifunctionality and / or low cost characteristics. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both memory and logic elements.

[0003] As the integration density of semiconductor devices increases, it is necessary to realize capacitors with sufficiently high capacitance in a limited area. The capacitance of a capacitor varies in proportion to the surface area of ​​the electrode and the dielectric constant of the dielectric layer, and varies inversely with the equivalent oxide thickness of the dielectric layer. Summary of the invention

[0004] One or more example embodiments provide a semiconductor device having improved capacitance characteristics.

[0005] One or more example embodiments provide a semiconductor device having reduced leakage current.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0007] According to one aspect of example embodiments, a semiconductor device may include: a capacitor structure, the capacitor structure including: a bottom electrode; a first dielectric layer, the first dielectric layer being located on the bottom electrode; a second dielectric layer, the second dielectric layer being located on the first dielectric layer; a third dielectric layer, the third dielectric layer being located on the second dielectric layer; and a top electrode, the top electrode being located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer includes zirconium oxide, the second dielectric layer includes hafnium zirconium oxide, and each of the first dielectric layer, the second dielectric layer, and the third dielectric layer includes a first crystalline phase and a second crystalline phase.

[0008] According to one aspect of example embodiments, a semiconductor device may include a capacitor structure including a bottom electrode, a first dielectric layer located on the bottom electrode, a second dielectric layer located on the first dielectric layer, a third dielectric layer located on the second dielectric layer, and a top electrode located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer includes zirconium oxide, the second dielectric layer includes hafnium zirconium oxide, and the capacitor structure is configured to reach a maximum capacitance when a voltage applied to the capacitor structure is in a range of -0.9V to 0.9V.

[0009] According to one aspect of an example embodiment, a semiconductor device may include: a capacitor structure, the capacitor structure including: a bottom electrode; a first dielectric layer, the first dielectric layer being located on the bottom electrode; a second dielectric layer, the second dielectric layer being located on the first dielectric layer; a third dielectric layer, the third dielectric layer being located on the second dielectric layer; and a top electrode, the top electrode being located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer includes zirconium oxide, the second dielectric layer includes hafnium zirconium oxide, and each of the first dielectric layer, the second dielectric layer, and the third dielectric layer includes an antiferroelectric region and a ferroelectric region.

[0010] According to one aspect of example embodiments, a semiconductor device may include: a substrate; a first conductive contact and a second conductive contact, the first conductive contact and the second conductive contact being located on the substrate; a first bottom electrode and a second bottom electrode, the first bottom electrode being located on the first conductive contact and the second bottom electrode being located on the second conductive contact; and a first stacked dielectric layer, the first stacked dielectric layer being located on the first bottom electrode and the second bottom electrode and including a first dielectric layer located on each of the first bottom electrode and the second bottom electrode, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer; and a top electrode, the top electrode being located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer of the first stacked dielectric layer includes zirconium oxide, the second dielectric layer of the first stacked dielectric layer includes hafnium zirconium oxide, and each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stacked dielectric layer includes a first crystalline phase and a second crystalline phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view illustrating a capacitor structure of a semiconductor device according to one or more example embodiments;

[0013] Figure 2 is a top view illustrating a capacitor structure of a semiconductor device according to one or more example embodiments;

[0014] Figure 3 is a graph illustrating a change in capacitance of a capacitor as a function of an applied voltage according to one or more example embodiments;

[0015] Figure 4 is a top view illustrating a semiconductor device at an intermediate formation stage according to one or more example embodiments;

[0016] Figure 5 is a method for forming a plurality of components of a semiconductor device and a semiconductor device according to one or more exemplary embodiments after an intermediate forming stage. Figure 4 A cross-sectional view corresponding to the line AA';

[0017] Figure 6 and Figure 7 is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments;

[0018] Figures 8 to 10 According to one or more example embodiments Figure 5 An enlarged cross-sectional view corresponding to parts P1, P2 and P3;

[0019] Fig.11 is a top view illustrating a semiconductor device according to one or more example embodiments;

[0020] Fig. 12A and Fig. 12B According to one or more example embodiments, Fig.11 A cross-sectional view corresponding to the lines BB' and CC';

[0021] Fig.13 is a top view illustrating a semiconductor device according to one or more example embodiments;

[0022] Fig.14 is a perspective view illustrating a semiconductor device according to one or more example embodiments;

[0023] Fig.15A and Fig. 15B According to one or more example embodiments, Fig.13 The cross-sectional view corresponding to the lines D-D' and EE';

[0024] Fig.16 is a top view illustrating a semiconductor device according to one or more example embodiments; and

[0025] Fig.17 is a perspective view illustrating a semiconductor device according to one or more example embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the accompanying drawings, and their redundant descriptions will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0027] As used herein, expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements, rather than the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0028] It should be understood that when an element or layer is referred to as being “over,” “on,” “on,” “under,” “under,” “connected to,” or “coupled to” another element or layer, it can be directly over, directly over, directly over, directly under, directly under, directly under, directly connected to, or directly coupled to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly over,” “directly on,” “directly under,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0029] Figure 1 is a cross-sectional view illustrating a capacitor structure of a semiconductor device according to one or more example embodiments.

[0030] refer to Figure 1, the semiconductor device may include a capacitor structure CAP. In some embodiments, the capacitor structure CAP may be used as a data storage element, and in this case, the semiconductor device according to some embodiments may be used as a semiconductor memory device. The capacitor structure CAP may include a bottom electrode BE, a stacked dielectric layer DL, and a top electrode TE sequentially arranged along a vertical direction VD. The vertical direction VD may be a direction orthogonal to an interface between the bottom electrode BE and the top electrode TE. The stacked dielectric layer DL may be between the bottom electrode BE and the top electrode TE.

[0031] The bottom electrode BE and the top electrode TE may be formed of or include at least one conductive material (e.g., doped silicon, doped silicon germanium, metal material, metal nitride material, conductive oxide material, and metal silicide material). In some embodiments, the bottom electrode BE and the top electrode TE may be formed of VN, TiN, NbN, MoN, TaN, Ru, RuO 2 、Pt、Ir、SrRuO 3 , W and WN or includes VN, TiN, NbN, MoN, TaN, Ru, RuO 2 、Pt、Ir、SrRuO 3 At least one of W, W, and WN. The bottom electrode BE and the top electrode TE may each be a single layer made of a single material, or a composite layer including two or more materials.

[0032] The stacked dielectric layer DL may include a first dielectric layer DL1, a second dielectric layer DL2, and a third dielectric layer DL3 that may be sequentially disposed on the bottom electrode BE. The first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may be sequentially disposed along a vertical direction VD. In some embodiments, the first dielectric layer DL1 and the third dielectric layer DL3 may contact the bottom electrode BE and the top electrode TE, respectively, but example embodiments are not limited thereto. As an example, an additional layer may be further disposed between the first dielectric layer DL1 and the bottom electrode BE or between the third dielectric layer DL3 and the top electrode TE. The second dielectric layer DL2 may be interposed between the first dielectric layer DL1 and the third dielectric layer DL3.

[0033] The first dielectric layer DL1 and the third dielectric layer DL3 may include the same material. In some embodiments, the first dielectric layer DL1 and the third dielectric layer DL3 may be made of zirconium oxide (eg, ZrO 2 ) is formed of or includes zirconium oxide (e.g., ZrO 2 ).

[0034] As an example, at least one of the first dielectric layer DL1 and the third dielectric layer DL3 may include aluminum-doped zirconium oxide. In the case of using aluminum-doped zirconium oxide, the leakage current of the capacitor structure CAP may be reduced. The concentration of aluminum in the aluminum-doped zirconium oxide may be greater than 0 at% and may be less than or equal to 20 at%, and when the aluminum concentration is within this range, the leakage current may be reduced to the maximum.

[0035] As another example, the first dielectric layer DL1 and the third dielectric layer DL3 may each include aluminum-free zirconium oxide.

[0036] In some embodiments, the first dielectric layer DL1 and the third dielectric layer DL3 may each include at least one element of V, Ti, Nb, Mo, Ta, Ru, Pt, Sr, Ru, W, Si, B, Ge, Nb, Sc, Y, Fe, Os, Co, Rh, and Sn. The element may exist in the first dielectric layer DL1 and the third dielectric layer DL3 as a result of diffusion from an external structure (e.g., the bottom electrode BE or the top electrode BE) into the stacked dielectric layers DL, but example embodiments are not limited thereto.

[0037] The second dielectric layer DL2 may include a material different from the first and third dielectric layers DL1 and DL3. For example, if the first and third dielectric layers DL1 and DL3 include zirconium oxide, the second dielectric layer DL2 may be formed of or include hafnium zirconium oxide.

[0038] Hafnium zirconium oxide can be represented as Hf 1-x Zr x O 2 Here, the value of x may be in the range of 0.1 to 0.7. The capacitance of the capacitor structure CAP may vary depending on the voltage applied to the bottom electrode BE and the top electrode TE and the value of x. When the value of x is within the above range, the capacitance of the capacitor structure CAP may have a maximum value (e.g., maximum capacitance) in a low voltage range (e.g., between -0.9V and 0.9V). Therefore, the capacitor structure CAP of the semiconductor device may operate at a low voltage.

[0039] Each of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may have two or more crystal phases. Each of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may include a first crystal phase and a second crystal phase that are different from each other. The first crystal phase may be a crystal phase having antiferroelectric properties, and the second crystal phase may be a crystal phase having ferroelectric properties. For example, the first crystal phase may be a tetragonal crystal phase having antiferroelectric properties, and the second crystal phase may be an orthorhombic crystal phase having ferroelectric properties. Therefore, each of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may include an antiferroelectric region and a ferroelectric region.

[0040] The first crystalline phase and the second crystalline phase may be disposed in each of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 in various ways. As an example, a portion of the first crystalline phase and a portion of the second crystalline phase may be stacked on each other. As another example, another portion of the first crystalline phase and another portion of the second crystalline phase may be located at a similar height, and in this case, they may be observed on a single plane. However, example embodiments are not limited thereto, and the structure or configuration of the first crystalline phase and the second crystalline phase may be changed differently.

[0041] The polarization (P) of the stacked dielectric layers DL may vary due to the change of the electric field (E) generated by the bottom electrode BE and the top electrode TE, and such a change may be represented as a PE hysteresis loop.

[0042] In the comparative example, the dielectric layer is composed of a ferroelectric region without an antiferroelectric region, and in this case, when the electric field is zero (i.e., E=0), the dielectric layer may have a non-gradient polarization state (i.e., P≠0). Therefore, in order to change the polarization direction of the dielectric layer or eliminate the residual polarization, an electric field in the opposite direction should be applied to the dielectric layer. In the case where the dielectric layer exhibits such properties, the capacitor structure may not be suitable for use as a data storage element in a volatile memory device.

[0043] In another comparative example, the dielectric layer is composed of an antiferroelectric region without a ferroelectric region, and in this case, there may be no polarization when the electric field is weak, and the dielectric layer may have a low permittivity. In the case of using a dielectric layer having these properties in a capacitor structure, the capacitor structure may not have a sufficiently large capacitance.

[0044] According to some embodiments, a first crystalline phase having an antiferroelectric region and a second crystalline phase having a ferroelectric region may be arranged in a mixed manner in the stacked dielectric layer DL. Since the first crystalline phase and the second crystalline phase are mixed in the stacked dielectric layer DL, the capacitor structure CAP may have a large capacitance and may be used as a data storage element in a volatile memory device. Each of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may include a first crystalline phase and a second crystalline phase. In the case where each of the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 is formed to have a plurality of crystalline phases, the manufacturing process may be simplified compared to the case where the dielectric layers are formed to have single crystalline phases different from each other. That is, according to some embodiments, semiconductor devices may be manufactured more easily.

[0045] When measured in the vertical direction VD, the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may have a first thickness TK1, a second thickness TK2, and a third thickness TK3, respectively. Each of the first thickness TK1 and the third thickness TK3 may be to In the range of the first thickness TK1 and the third thickness TK3 less than In the case of the first thickness TK1 and the third thickness TK3 being greater than In the case of, the capacitance of the capacitor structure CAP may be reduced. The second thickness TK2 may be to In the second thickness TK2 is less than In the case of the second thickness TK2 being greater than , the difficulty of the manufacturing process and the amount of leakage current may increase. In this case, the capacitance of the capacitor structure CAP may decrease.

[0046] Figure 2 is a top view illustrating a capacitor structure of a semiconductor device according to one or more example embodiments.

[0047] refer to Figure 2, in a top view, the bottom electrode BE may be circular. The first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may be configured to sequentially encapsulate the circular bottom electrode BE. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may be configured to conformally encapsulate the bottom electrode BE. The top electrode TE may encapsulate the third dielectric layer DL3. That is, the first dielectric layer DL1 may conformally encapsulate the bottom electrode BE, the second dielectric layer DL2 may conformally encapsulate the first dielectric layer DL1, and the third dielectric layer DL3 may conformally encapsulate the second dielectric layer DL2, and the top electrode TE may encapsulate (or conformally encapsulate) the third dielectric layer DL3.

[0048] When viewed in a top view, the bottom electrode BE may include a seam formed therein, or may be in a hollow donut shape. In the case where the bottom electrode BE is arranged in a donut shape, the top electrode TE may also include a portion extending into the bottom electrode BE, and the stacked dielectric layer DL may be interposed between the bottom electrode BE and the top electrode TE.

[0049] Figure 3 is a graph illustrating a variation in capacitance of a capacitor with applied voltage according to one or more example embodiments.

[0050] refer to Figure 3 , the capacitance of the capacitor structure CAP may vary due to the voltage applied to the bottom electrode BE and the top electrode TE. Figure 3 The voltage on the horizontal axis represents the potential difference between the bottom electrode BE and the top electrode TE. Figure 3 In FIG. 5 , curves L1 and L2 show the capacitance characteristics of the capacitor structure CAP, and the curves L1 and L2 are respectively measured when two dielectric layers DL with different chemical structures are used.

[0051] Curve L1 shows that the first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 each include ZrO 2 , Hf 1-x Zr x O 2 and ZrO 2 Here, the value of x is in the range of 0.1 to 0.7. Curve L2 shows that the first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 each include ZrO 2 , Hf 1-x Zr x O 2 and ZrO 2 And the value of x is less than 0.1 or greater than 0.7 of the capacitance of the capacitor structure CAP.

[0052] Under the same voltage condition, the capacitance of the capacitor structure CAP in the curve L1 may be larger than that in the curve L2. In addition, the capacitance of the capacitor structure CAP in the curve L1 may have a maximum value (e.g., a highest value) in the voltage range of -0.9V to 0.9V. This indicates that when Hf 1-x Zr x O 2 When the value of x in is in the range of 0.1 to 0.7, the capacitor structure CAP can have the highest (eg, maximum) capacitance in a relatively low voltage range (eg, -0.9 V to 0.9 V). As a result, the capacitor structure CAP can operate at a low voltage and the electrical characteristics of the semiconductor device can be improved.

[0053] Figure 4 is a top view illustrating a semiconductor device at an intermediate formation stage according to one or more example embodiments. Figure 5 is a method for forming a plurality of components of a semiconductor device and a semiconductor device according to one or more exemplary embodiments after an intermediate forming stage. Figure 4 A cross-sectional view corresponding to the line AA'.

[0054] refer to Figure 4 and Figure 5 , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0055] An interlayer insulating layer 162 may be disposed on the substrate 100. The interlayer insulating layer 162 may cover at least a portion of the top surface of the substrate 100. In some embodiments, the interlayer insulating layer 162 may be formed of or include at least one of silicon nitride, silicon oxide, and silicon oxynitride. In some embodiments, the interlayer insulating layer 162 may include an empty region (e.g., an air gap).

[0056] Conductive contacts 160 may be provided in the interlayer insulating layer 162. In some embodiments, a plurality of conductive contacts 160 may be provided to be spaced apart from each other in a first direction D1 and a second direction D2, the first direction D1 and the second direction D2 being parallel to the bottom surface of the substrate 100 and not parallel to each other (e.g., orthogonal to each other). The conductive contacts 160 may be made of at least one of a doped semiconductor material (e.g., polysilicon), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), a metal nitride material (e.g., a nitride material of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), and a metal silicide material (e.g., a silicide material of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). A conductive contact 160 may be formed of or include at least one of a doped semiconductor material (e.g., polysilicon), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), a metal nitride material (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), and a metal silicide material (e.g., silicide materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). The conductive contact 160 may be electrically connected to an impurity region (e.g., a source / drain region) formed in the substrate 100.

[0057] An etch stop layer ES may be disposed on the conductive contact 160. The etch stop layer ES may be disposed on the interlayer insulating layer 162. The etch stop layer ES may be disposed to cover the interlayer insulating layer 162 and expose the conductive contact 160. The etch stop layer ES may include at least one of silicon oxide, SiCN, and SiBN. The capacitor structure CAP may correspond to Figure 1 The capacitor structure CAP may be disposed on the etch stop layer ES and the conductive contact 160 and may include a bottom electrode BE, a stacked dielectric layer DL, and a top electrode TE.

[0058] The bottom electrode BE may be disposed on the conductive contact 160. The bottom electrode BE may penetrate the etch barrier layer ES and be electrically connected to the conductive contact 160. A lower portion of the bottom electrode BE may be encapsulated by the etch stop layer ES.

[0059] A plurality of bottom electrodes BE may be arranged to be spaced apart from each other in the first direction D1 and the second direction D2. For example, in a top view, the bottom electrodes BE may be arranged in a honeycomb shape. Each bottom electrode BE may be placed at the center of a hexagon defined by the other six bottom electrodes BE.

[0060] Figure 6 and Figure 7is a cross-sectional view illustrating a semiconductor device according to one or more example embodiments.

[0061] refer to Figures 5 to 7 The bottom electrode BE can be in various shapes. For example, the bottom electrode BE can be in a column shape, such as Figure 5 The bottom electrode BE may be in the shape of a column with an inner seam SM, as shown in FIG. Figure 6 The bottom electrode BE may be in the shape of a hollow cylinder (eg, a cup shape) with one closed end, as shown in FIG. Figure 7 However, the shape of the bottom electrode BE is not limited to these examples.

[0062] Return to reference Figure 4 and Figure 5 , a support layer SS may be disposed on the substrate 100. The support layer SS may be disposed between the bottom electrodes BE adjacent to each other. The support layer SS may contact the side surface of the bottom electrode BE and may encapsulate the side surface of the bottom electrode BE. Therefore, the support layer SS may mechanically support the bottom electrode BE.

[0063] A plurality of support layers SS may be disposed to be spaced apart from each other in a third direction D3 perpendicular to the bottom surface of the substrate 100. The support layer SS may have at least two different thicknesses when measured in the third direction D3. The top surface of the uppermost support layer SS among the support layers SS may be located at a height different from or the same as the top surface of the bottom electrode BE. In some embodiments, the support layer SS may be formed of or include at least one of silicon nitride, SiBN, and SiCN.

[0064] The penetration holes PH may be provided between the bottom electrodes BE adjacent to each other. For example, each of the penetration holes PH may be provided between three adjacent bottom electrodes BE among the bottom electrodes BE to have a circular shape and expose a portion of the side surface of each of the three bottom electrodes BE. However, example embodiments are not limited thereto, and the penetration holes PH may have various shapes between the bottom electrodes BE. The penetration holes PH may be provided to penetrate the support layer SS. The penetration holes PH may expose the etching stop layer ES. In some embodiments, a plurality of penetration holes PH may be provided to be spaced apart from each other in the first direction D1 and the second direction D2.

[0065] The top electrode TE may be disposed on the bottom electrode BE. The top electrode TE may cover the bottom electrode BE and the supporting layer SS. The top electrode TE may be disposed to fill the penetration hole PH, and the space between the bottom electrodes BE, the space between the supporting layers SS, and the space between the lowermost supporting layer SS of the supporting layers SS and the etching stop layer ES.

[0066] The stacked dielectric layer DL may be interposed between each bottom electrode BE and the top electrode TE. The stacked dielectric layer DL may extend into a region between the support layer SS and the top electrode TE and between the etch stop layer ES and the top electrode TE. The stacked dielectric layer DL may conformally cover the support layer SS, the bottom electrode BE, and the etch stop layer ES. The stacked dielectric layer DL may fill the through hole PH together with the top electrode TE.

[0067] Figures 8 to 10 According to one or more example embodiments Figure 5 An enlarged cross-sectional view corresponding to parts P1, P2 and P3.

[0068] refer to Figures 8 to 10 The stacked dielectric layer DL may include a first dielectric layer DL1, a second dielectric layer DL2, and a third dielectric layer DL3. The first dielectric layer DL1, the second dielectric layer DL2, and the third dielectric layer DL3 may correspond to Figure 1 As an example, the first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 may be interposed between the bottom electrode BE and the top electrode TE. Figure 8 shown, and can have Figure 1 The first dielectric layer DL1 , the second dielectric layer DL2 , and the third dielectric layer DL3 have similar structures and material properties.

[0069] The first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 may also be interposed between the support layer SS and the top electrode TE, such as Fig. 9 In addition to providing a support layer SS instead of the bottom electrode BE, the first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 located between the support layer SS and the top electrode TE may have the same Figure 1 The first dielectric layer DL1 , the second dielectric layer DL2 , and the third dielectric layer DL3 have similar structures and material properties.

[0070] The first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 may also be interposed between the etching stop layer ES and the top electrode TE. Fig.10 In addition to providing an etch stop layer ES instead of the bottom electrode BE, the first dielectric layer DL1, the second dielectric layer DL2 and the third dielectric layer DL3 located between the etch stop layer ES and the top electrode TE may have the same Figure 1 The first dielectric layer DL1 , the second dielectric layer DL2 , and the third dielectric layer DL3 have similar structures and material properties.

[0071] Fig.11is a top view illustrating a semiconductor device according to one or more example embodiments. Fig. 12A and Fig. 12B According to one or more example embodiments, Fig.11 Cross-sectional views corresponding to lines BB' and CC'.

[0072] refer to Fig.11 , Fig. 12A and Fig. 12B , a substrate 100 may be provided. The substrate 100 may correspond to Figure 5 substrate 100.

[0073] A device isolation pattern STI may be provided on the substrate 100. The device isolation pattern STI may define an active pattern ACT on the substrate 100. Each active pattern ACT may be in a shape protruding along the third direction D3. As an example, the device isolation pattern STI may be provided in the substrate 100, and the active pattern ACT may be a portion of the substrate 100 enclosed by the device isolation pattern STI. For ease of description, unless otherwise stated, the term "substrate 100" may be used to refer to the rest of the substrate 100 excluding the active pattern ACT.

[0074] The active patterns ACT may be spaced apart from each other in the first direction D1 and the second direction D2. The active patterns ACT may be isolated stripe patterns spaced apart from each other and elongated in the fourth direction D4. The fourth direction D4 may be parallel to the bottom surface of the substrate 100 and may not be parallel to the first direction D1 and the second direction D2.

[0075] Each active pattern ACT may include a central portion CA and a pair of edge portions EA. The pair of edge portions EA may be two opposite ends of the active pattern ACT in the fourth direction D4. The central portion CA may be a portion of the active pattern ACT between the pair of edge portions EA or between a pair of word lines WL to be described below. Each or at least one of the edge portion EA and the central portion CA may include an impurity region doped with impurities (e.g., n-type or p-type impurities).

[0076] The device isolation pattern STI may include an insulating material. As an example, the device isolation pattern STI may be formed of or include at least one of silicon oxide or silicon nitride. The device isolation pattern STI may be a single layer made of one of the above materials, or a composite layer made of at least two of the above materials.

[0077] The word line WL may be arranged to cross the active pattern ACT. As an example, the word line WL may cross the active pattern ACT and the device isolation pattern STI in the first direction D1. In some embodiments, a plurality of word lines WL may be arranged. The word lines WL may be spaced apart from each other in the second direction D2. In some embodiments, a pair of word lines WL adjacent to each other in the second direction D2 may be arranged to cross the active pattern ACT.

[0078] As an example, each word line WL may include a gate electrode GE, a gate insulation pattern GI, and a gate capping pattern GC. The gate electrode GE may be disposed to cross the active pattern ACT and the device isolation pattern STI in the first direction D1. The gate insulation pattern GI may be interposed between the gate electrode GE and the active pattern ACT. The gate capping pattern GC may cover the top surface of the gate electrode GE.

[0079] A buffer pattern BP may be provided on the substrate 100. The buffer pattern BP may cover the active pattern ACT, the device isolation pattern STI, and the word line WL. In some embodiments, the buffer pattern BP may be formed of or include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buffer pattern BP may be a single layer made of a single material, or a composite layer including two or more materials.

[0080] A bit line node contact DC may be provided on each active pattern ACT, and in some embodiments, a plurality of bit line node contacts DC may be provided. Each bit line node contact DC may be connected to a corresponding one of the central portions CA of the active pattern ACT. The bit line node contacts DC may be spaced apart from each other in the first direction D1 and the second direction D2. The bit line node contacts DC may be between the active pattern ACT and the bit lines BL to be described below. Each bit line node contact DC may connect a corresponding bit line BL of the bit lines BL to a central portion CA of the corresponding active pattern ACT of the active pattern ACT. In some embodiments, the bit line node contact DC may be formed of doped polysilicon or include doped polysilicon.

[0081] The bit line node contacts DC may be disposed in the first recess regions RS1, respectively. The first recess regions RS1 may be disposed at an upper portion of the active pattern ACT and an upper portion of the device isolation pattern STI adjacent thereto. The first recess regions RS1 may be spaced apart from each other in the first direction D1 and the second direction D2.

[0082] A gap filling insulating pattern BI may be provided to fill each first recessed region RS1. The gap filling insulating pattern BI may fill the inner space of the first recessed region RS1. In some embodiments, the gap filling insulating pattern BI may cover the inner surface of the first recessed region RS1 and at least a portion of the side surface of the bit line node contact DC (e.g., in the first recessed region RS1). The gap filling insulating pattern BI may be formed of or include at least one of silicon oxide, silicon nitride, or a combination thereof. The gap filling insulating pattern BI may be a single layer made of a single material, or a composite layer including two or more materials.

[0083] The bit line BL may be disposed on the bit line node contact DC. The bit line BL may be disposed on the bit line node contact DC arranged in a straight line along the second direction D2. In some embodiments, a plurality of bit lines BL may be provided. The bit lines BL may be spaced apart from each other in the first direction D1. The bit line BL may include a metal material. For example, the bit line BL may be formed of at least one metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag) or include at least one metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0084] The polysilicon pattern PP may be interposed between the bit line BL and the buffer pattern BP. A top surface of the polysilicon pattern PP is located at substantially the same height as a top surface of the bit line node contact DC. The polysilicon pattern PP may include doped polysilicon.

[0085] The ohmic pattern OP may be interposed between the bit line BL and the bit line node contact DC and between the bit line BL and the polysilicon pattern PP. The ohmic pattern OP may be formed of or include at least one metal silicide material (e.g., silicide materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag). In some embodiments, a barrier layer pattern may be further interposed between the bit line BL and the bit line node contact DC and between the bit line BL and the polysilicon pattern PP. The blocking layer pattern may be formed of or include at least one conductive metal nitride material (e.g., nitride materials of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0086] A bit line cover pattern BCP may be provided on the bit line BL. In some embodiments, the bit line cover patterns BCP may be provided on the top surfaces of the bit lines BL, respectively. The bit line cover patterns BCP may extend along the bit line BL or along the second direction D2, and may be spaced apart from each other in the first direction D1. Each bit line cover pattern BCP may be vertically located above a corresponding bit line BL in the bit line BL. The bit line cover pattern BCP may consist of a single layer or a plurality of layers. As an example, the bit line cover pattern BCP may include a first cover pattern, a second cover pattern, and a third cover pattern stacked sequentially. In some embodiments, the first to third cover patterns may each include silicon nitride. As another example, the bit line cover pattern BCP may also include additional cover patterns (e.g., a fourth cover pattern and a fifth cover pattern).

[0087] A bit line spacer SPC may be disposed on a side surface of the bit line BL and a side surface of the bit line capping pattern BCP. The bit line spacer SPC may cover a side surface of the bit line BL and a side surface of the bit line capping pattern BCP. The bit line spacer SPC may be disposed on a side surface of the bit line BL and may extend along the second direction D2.

[0088] Each bit line spacer SPC may include a plurality of sub-spacers. In some embodiments, each bit line spacer SPC may include three or more sub-spacers sequentially disposed on the side surface of the bit line BL. Each sub-spacer may independently include at least one of silicon nitride, silicon oxide, or silicon oxynitride. As another example, at least one sub-spacer may include an air gap that separates the other sub-spacers from each other.

[0089] A storage node contact BC may be provided between adjacent bit lines BL. In some embodiments, a plurality of storage node contacts BC may be provided to be spaced apart from each other in the first direction D1 and the second direction D2. The storage node contact BC may fill a second recessed region RS2 formed on an edge portion EA of the active pattern ACT. The storage node contact BC may be electrically connected to the edge portion EA. The storage node contact BC may include a conductive material. As an example, the storage node contact BC may be formed of at least one of doped polysilicon and a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag) or include at least one of doped polysilicon and a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0090] On the word line WL, the fence pattern FN may separate the storage node contacts BC from each other in the second direction D2. In some embodiments, the fence patterns FN may be spaced apart from each other in the second direction D2, and the storage node contacts BC are interposed between the fence patterns FN. In some embodiments, the fence pattern FN may be formed of or include silicon nitride.

[0091] The diffusion barrier layer DP may conformally cover the storage node contact BC and the bit line spacer SPC. The diffusion barrier layer DP may be formed of or include a conductive metal nitride material (e.g., including at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, or Ag). A metal silicide layer may be further interposed between the diffusion barrier layer DP and the storage node contact BC.

[0092] A landing pad LP may be provided on the storage node contact BC. In some embodiments, a plurality of landing pads LP may be provided, and the plurality of landing pads LP may be spaced apart from each other in the first direction D1 and the second direction D2. Each landing pad LP may be connected to a corresponding storage node contact BC in the storage node contact BC. The landing pad LP may cover the top surface of the bit line cover pattern BCP. In some embodiments, the lower portion of the landing pad LP may be vertically located above the storage node contact BC, and the upper portion of the landing pad LP may be offset from the lower portion in the second direction D2 or in the opposite direction thereof. The landing pad LP may be formed of or include at least one metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag).

[0093] A filling pattern FI may be provided to enclose the landing pad LP. The filling pattern FI may be between the landing pads LP adjacent to each other. In a top view, the filling pattern FI may be provided in a mesh shape with holes, and in this case, the landing pad LP may be provided in the hole to penetrate the filling pattern FI. The filling pattern FI may be formed of or include at least one of silicon nitride, silicon oxide, and silicon oxynitride. Alternatively, the filling pattern FI may include an empty space (e.g., an air gap) having an air layer.

[0094] The capacitor structure CAP, the etch stop layer ES, and the support layer SS may be disposed on the conductive contact 160. The capacitor structure CAP, the etch stop layer ES, and the support layer SS may correspond to Figures 4 to 10The capacitor structure CAP, the etching stop layer ES and the support layer SS. Fig.11 , Fig. 12A and Fig. 12B The capacitor structure CAP, the etching stop layer ES and the support layer SS may have Figures 4 to 10 The capacitor structure CAP, the etch stop layer ES and the support layer SS have substantially the same or similar features.

[0095] Fig.13 is a top view illustrating a semiconductor device according to one or more example embodiments. Fig.14 According to one or more example embodiments Fig.13 A three-dimensional diagram of a semiconductor device. Fig.15A and Fig. 15B According to one or more example embodiments, Fig.13 The cross-sectional views corresponding to the lines D-D' and EE'.

[0096] refer to Figures 13 to 15B , the semiconductor device 200 may include a substrate 210, a plurality of first conductive lines 220, a channel layer 230, a gate electrode 240, a gate insulating layer 250, and a capacitor structure CAP. The semiconductor device 200 may be a memory device including a vertical channel transistor (VCT). The VCT may refer to a transistor structure in which the channel layer 230 extends from the substrate 210 in a vertical direction or defines a channel length in a vertical direction.

[0097] A lower insulating layer 212 may be disposed on the substrate 210, and first conductive lines 220 spaced apart from each other in the first direction D1 and extending in the second direction D2 may be disposed on the lower insulating layer 212. A plurality of first insulating patterns 222 may be disposed on the lower insulating layer 212 to fill empty spaces between the first conductive lines 220. The first insulating patterns 222 may extend in the second direction D2, and the first insulating patterns 222 may have top surfaces located at the same height as top surfaces of the first conductive lines 220. The first conductive lines 220 may serve as bit lines of the semiconductor device 200.

[0098] In some embodiments, the first conductive line 220 may be formed of or include at least one of doped polysilicon, a metal material, a conductive metal nitride material, a conductive metal silicide material, a conductive metal oxide material, and a combination thereof. For example, the first conductive line 220 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and combinations thereof or comprising doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x And combinations thereof, but example embodiments are not limited thereto. The first conductive line 220 may include one or more layers, each of which is formed of at least one of the aforementioned materials. In some embodiments, the first conductive line 220 may be formed of at least one of a two-dimensional semiconductor material (e.g., graphene, carbon nanotubes, and combinations thereof) or include at least one of a two-dimensional semiconductor material (e.g., graphene, carbon nanotubes, and combinations thereof).

[0099] The channel layer 230 may be placed on the first conductive line 220 to be spaced apart from each other in the first direction D1 and the second direction D2 and to form a matrix arrangement. The channel layer 230 may have a first width in the first direction D1 and a first height in the third direction D3, and the first height may be greater than the first width. For example, the first height may be approximately 2 to 10 times the first width, but example implementations are not limited thereto. The bottom of the channel layer 230 may be used as a first source / drain region, the upper portion of the channel layer 230 may be used as a second source / drain region, and the portion of the channel layer 230 between the first source / drain region and the second source / drain region may be used as a channel region.

[0100] In some embodiments, the channel layer 230 may be made of at least one oxide semiconductor material (eg, In x Ga y Zn z O、In x Ga y Si z O、In x Sny Zinc z O,In x Zinc y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zinc y Sn z O, Sn x O, Hf x In y Zinc z O, Ga x Zinc y Sn z O, Al x Zinc y Sn z O, Yb x Ga y Zinc z O,In x Ga y (For example, In x Ga y Zinc z O,In x Ga y S z O,In x Sn y Zinc z O,In x Zinc y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zinc y Sn z O, Sn x O, Hf x In y Zinc z O, Ga x Zinc y Sn z O, Al x Zinc y Sn z O, Yb x Ga y Zinc z O,In x Ga yO and combinations thereof). The channel layer 230 may have a single layer or multilayer structure of an oxide semiconductor material. In some embodiments, the band gap energy of the channel layer 230 may be greater than the band gap energy of silicon. For example, the band gap energy of the channel layer 230 may be approximately 1.5 eV to 5.6 eV. In some embodiments, when the band gap energy of the channel layer 230 is approximately 2.0 eV to 4.0 eV, the channel layer 230 may exhibit optimized channel performance. In some embodiments, the channel layer 230 may have a polycrystalline or amorphous structure, but example embodiments are not limited thereto. In some embodiments, the channel layer 230 may include a two-dimensional semiconductor material (e.g., graphene, carbon nanotubes, or combinations thereof).

[0101] The gate electrode 240 may extend in the first direction D1 on the opposite side surface of the channel layer 230. For example, the gate electrode 240 may include a first sub-gate electrode 240P1 disposed to face the first side surface of the channel layer 230 and a second sub-gate electrode 240P2 disposed to face the second side surface of the channel layer 230 opposite to the first side surface. Since one channel layer 230 is disposed between the first sub-gate electrode 240P1 and the second sub-gate electrode 240P2, the semiconductor device 200 may have a dual-gate transistor structure. However, example embodiments are not limited thereto, and the semiconductor device 200 may have a single-gate transistor structure having the first sub-gate electrode 240P1 facing the first side surface of the channel layer 230 without the second sub-gate electrode 240P2.

[0102] The gate electrode 240 may be formed of or include at least one of doped polysilicon, a metal material, a conductive metal nitride material, a conductive metal silicide material, a conductive metal oxide material, and a combination thereof. For example, the gate electrode 240 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and combinations thereof to form or include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO xand at least one of a combination thereof, but example embodiments are not limited thereto.

[0103] The gate insulating layer 250 may be interposed between the channel layer 230 and the gate electrode 240 and may encapsulate the side surface of the channel layer 230. Fig.13 As shown, the entire side surface of the channel layer 230 may be encapsulated by the gate insulating layer 250, and a portion of the side surface of the gate electrode 240 may contact the gate insulating layer 250. In some embodiments, the gate insulating layer 250 may extend in an extension direction (i.e., the first direction D1) of the gate electrode 240, and two opposite side surfaces of the channel layer 230 facing the gate electrode 240 may contact the gate insulating layer 250.

[0104] In some embodiments, the gate insulating layer 250 may be formed of or include at least one of silicon oxide, silicon oxynitride, a high-k dielectric material having a higher dielectric constant than silicon oxide, and combinations thereof. The high-k dielectric material may include a metal oxide material or a metal oxynitride material. For example, the high-k dielectric material for the gate insulating layer 250 may include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al2O 3 and combinations thereof, but example embodiments are not limited thereto.

[0105] A plurality of second insulating patterns 232 may be disposed on the first insulating patterns 222 to extend in the second direction D2, and the channel layer 230 may be disposed between two adjacent second insulating patterns 232 among the second insulating patterns 232. In some embodiments, a first filling layer 234 and a second filling layer 236 may be disposed in a space between two adjacent channel layers 230 among the channel layers 230. The first filling layer 234 may be disposed at the bottom of the space between two adjacent channel layers 230 among the channel layers 230, and the second filling layer 236 may be disposed on the first filling layer 234 to fill the rest of the space between two adjacent channel layers 230 among the channel layers 230. A top surface of the second filling layer 236 may be placed at the same height as a top surface of the channel layer 230, and the second filling layer 236 may cover a top surface of the gate electrode 240. Alternatively, the second insulation pattern 232 and the first insulation pattern 222 may be formed as a continuous structure having no observable interface between the second insulation pattern 232 and the first insulation pattern 222, or the second filling layer 236 and the first filling layer 234 may be formed as a continuous structure having no observable interface between the second filling layer 236 and the first filling layer 234.

[0106] The capacitor contact 260 may be disposed on the channel layer 230. In some embodiments, the capacitor contacts 260 may be vertically located above the channel layer 230 and may be spaced apart from each other in the first direction D1 and the second direction D2 to form a matrix arrangement. The capacitor contacts 260 may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and combinations thereof to form or include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x and at least one of a combination thereof, but example embodiments are not limited thereto. An upper insulating layer 262 may be disposed on the second insulating pattern 232 and the second filling layer 236 to encapsulate side surfaces of the capacitor contact 260 .

[0107] The etch stop layer ES may be disposed on the upper insulating layer 262, and the capacitor structure CAP may be disposed on the etch stop layer ES. The capacitor structure CAP may correspond to Figure 1 For example, the capacitor structure CAP may include a bottom electrode BE, stacked dielectric layers DL, and a top electrode TE, and the stacked dielectric layers DL may include a first dielectric layer DL1, a second dielectric layer DL2, and a third dielectric layer DL3.

[0108] The bottom electrode BE may be disposed to penetrate the etch stop layer ES and may be electrically connected to the top surface of the capacitor contact 260. The bottom electrode BE may have a columnar structure extending in the third direction D3, but example embodiments are not limited thereto. In some embodiments, the bottom electrode BE may be disposed to be vertically located above the capacitor contact 260 and may be spaced apart from each other in the first direction D1 and the second direction D2 to form a matrix arrangement. Alternatively, a landing pad may be further disposed between the capacitor contact 260 and the bottom electrode BE, and the bottom electrode BE may be arranged in a hexagonal shape.

[0109] Fig.16 is a top view illustrating a semiconductor device according to one or more example embodiments. Fig.17 is a diagram illustrating a method according to one or more example embodiments Fig.16 A three-dimensional diagram of a semiconductor device.

[0110] refer to Fig.16 and Fig.17 , the semiconductor device 200A may include a substrate 210A, a plurality of first conductive lines 220A, a channel structure 230A, a contact gate electrode 240A, a plurality of second conductive lines 242A, and a capacitor structure CAP. In some embodiments, the semiconductor device 200A may be a memory device including a VCT.

[0111] A plurality of active regions AC may be defined in the substrate 210A by the first device isolation layer 212A and the second device isolation layer 214A. A channel structure 230A may be formed in each active region AC, and may include a first active pillar 230A1 and a second active pillar 230A2 extending in a vertical direction and a connection portion 230L connected to the bottom of the first active pillar 230A1 and the bottom of the second active pillar 230A2. A first source / drain region SD1 may be disposed in the connection portion 230L, and a second source / drain region SD2 may be disposed at an upper portion of each of the first active pillar 230A1 and the second active pillar 230A2. The first active pillar 230A1 and the second active pillar 230A2 may be used as a part of an independent unit memory cell, respectively.

[0112] Each of the first conductive lines 220A may extend in, for example, the second direction D2 to cross the active region AC. One of the first conductive lines 220A may be disposed on the connection portion 230L and between the first active pillar 230A1 and the second active pillar 230A2, and in particular, on the first source / drain region SD1. Another of the first conductive lines 220A adjacent to one of the first conductive lines 220A may be disposed between the two channel structures 230A. One of the first conductive lines 220A may be used as a common bit line, which is shared by two unit memory cells, which are composed of the first active pillar 230A1 and the second active pillar 230A2 placed on both sides of the common bit line.

[0113] One contact gate electrode 240A may be disposed between two channel structures 230A adjacent to each other along the second direction D2. For example, the contact gate electrode 240A may be disposed between a first active pillar 230A1 and a second active pillar 230A2, the first active pillar 230A1 being included in one channel structure 230A, the second active pillar 230A2 being included in another channel structure 230A adjacent to the channel structure 230A, and one of the contact gate electrodes 240A may be shared by the first active pillar 230A1 and the second active pillar 230A2 disposed on both sides thereof. The gate insulating layer 250A may be disposed between the contact gate electrode 240A and the first active pillar 230A1, and between the contact gate electrode 240A and the second active pillar 230A2. The second conductive line 242A may be disposed on the top surface of the contact gate electrode 240A and may extend in the first direction D1. The second conductive line 242A may function as a word line in the semiconductor device 200A.

[0114] The capacitor contact 260A may be disposed on the channel structure 230A. The capacitor contact 260A may be disposed on the second source / drain region SD2, and the capacitor structure CAP may be disposed on the capacitor contact 260A. The capacitor structure CAP may correspond to Figure 1 For example, the capacitor structure CAP may include a bottom electrode BE, a stacked dielectric layer DL, and a top electrode TE, and here, the stacked dielectric layer DL may include a first dielectric layer DL1, a second dielectric layer DL2, and a third dielectric layer DL3.

[0115] According to some embodiments, a first crystalline phase having an antiferroelectric region and a second crystalline phase having a ferroelectric region may be provided in a mixed manner in a dielectric layer to improve the capacitance characteristics of a capacitor structure. In addition, the dielectric layer may be doped with aluminum to reduce leakage current. Therefore, the electrical characteristics of a semiconductor device may be improved.

[0116] Furthermore, the dielectric layer may be a stacked dielectric layer consisting of a plurality of dielectric layers, each of which has a first crystal phase and a second crystal phase, and this may simplify a process of manufacturing a semiconductor device.

[0117] Each embodiment provided in the above description is not exclusive of being associated with one or more features of another example or another embodiment that is also provided herein or that is not provided herein but is consistent with the present disclosure.

[0118] While the present disclosure has been shown and described with particular reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising a capacitor structure, wherein the capacitor structure comprises: bottom electrode; a first dielectric layer, the first dielectric layer being located on the bottom electrode; a second dielectric layer, the second dielectric layer being located on the first dielectric layer; a third dielectric layer, the third dielectric layer being located on the second dielectric layer; as well as a top electrode, the top electrode being located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium zirconium oxide, and Each of the first dielectric layer, the second dielectric layer and the third dielectric layer includes a first crystal phase and a second crystal phase.

2. The semiconductor device according to claim 1, wherein The first crystalline phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer has antiferroelectric properties, and wherein the second crystalline phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer has ferroelectric properties.

3. The semiconductor device according to claim 1, wherein The first crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer is a tetragonal crystal phase, and wherein the second crystal phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer is an orthorhombic crystal phase.

4. The semiconductor device according to claim 1, wherein: The hafnium zirconium oxide in the second dielectric layer is Hf 1- x Zr x O2, and wherein x is in the range of 0.1 to 0.

7.

5. The semiconductor device according to claim 1, wherein At least one of the first dielectric layer, the second dielectric layer, and the third dielectric layer includes zirconium oxide doped with aluminum.

6. The semiconductor device according to claim 5, wherein: The aluminum concentration in the aluminum-doped zirconium oxide is greater than 0 at % and less than or equal to 20 at %.

7. The semiconductor device according to claim 1, wherein The capacitor structure is configured to achieve a maximum capacitance when a voltage applied to the capacitor structure is in the range of -0.9V to 0.9V.

8. The semiconductor device according to claim 1, wherein The thickness of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer is about to within the range.

9. The semiconductor device according to claim 1, wherein: The thickness of the second dielectric layer is to within the range.

10. The semiconductor device according to claim 1, wherein The first dielectric layer contacts the bottom electrode, and wherein the third dielectric layer contacts the top electrode.

11. The semiconductor device according to claim 1, wherein In a top view of the semiconductor device, the first dielectric layer, the second dielectric layer, and the third dielectric layer sequentially encapsulate the bottom electrode.

12. The semiconductor device according to claim 1, wherein The bottom electrode is in a column or cylindrical shape.

13. A semiconductor device, comprising a capacitor structure, wherein the capacitor structure comprises: bottom electrode; a first dielectric layer, the first dielectric layer being located on the bottom electrode; a second dielectric layer, the second dielectric layer being located on the first dielectric layer; a third dielectric layer, the third dielectric layer being located on the second dielectric layer; as well as a top electrode, the top electrode being located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer comprises zirconium oxide, wherein the second dielectric layer comprises hafnium zirconium oxide, and The capacitor structure is configured to achieve a maximum capacitance when a voltage applied to the capacitor structure is in a range of -0.9V to 0.9V.

14. The semiconductor device according to claim 13, wherein: Each of the first dielectric layer, the second dielectric layer, and the third dielectric layer includes an antiferroelectric region and a ferroelectric region.

15. A semiconductor device, comprising: substrate; a first conductive contact and a second conductive contact, the first conductive contact and the second conductive contact being located on the substrate; a first bottom electrode and a second bottom electrode, the first bottom electrode being located on the first conductive contact, and the second bottom electrode being located on the second conductive contact; as well as a first dielectric layer stack located on the first bottom electrode and the second bottom electrode and including a first dielectric layer located on each of the first bottom electrode and the second bottom electrode, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer; as well as a top electrode, the top electrode being located on the third dielectric layer, wherein each of the first dielectric layer and the third dielectric layer of the first stack of dielectric layers comprises zirconium oxide, wherein the second dielectric layer of the first stack of dielectric layers comprises hafnium zirconium oxide, and Wherein, each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stacked dielectric layer includes a first crystalline phase and a second crystalline phase.

16. The semiconductor device according to claim 15, further comprising a supporting layer located between the first bottom electrode and the second bottom electrode, in, The first dielectric layer of the first stack of dielectric layers is located on the support layer.

17. The semiconductor device according to claim 15, further comprising: an etch stop layer, the etch stop layer being located between the substrate and the top electrode; as well as a second dielectric layer stack located on the etch stop layer and comprising a first dielectric layer located on the etch stop layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer; wherein each of the first dielectric layer and the third dielectric layer of the second stack of dielectric layers comprises zirconium oxide, wherein the second dielectric layer of the second stack of dielectric layers comprises hafnium zirconium oxide, and Each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the second stacked dielectric layer includes the first crystal phase and the second crystal phase.

18. The semiconductor device according to claim 15, wherein: Each of the first bottom electrode and the second bottom electrode has a pillar shape or a cylindrical shape.

19. The semiconductor device according to claim 15, wherein: The first crystalline phase of each of the first dielectric layer, the second dielectric layer and the third dielectric layer of the first stacked dielectric layer has antiferroelectric properties, and wherein the second crystalline phase of each of the first dielectric layer, the second dielectric layer and the third dielectric layer of the first stacked dielectric layer has ferroelectric properties.

20. The semiconductor device according to claim 15, wherein The first crystalline phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stacked dielectric layers is a tetragonal crystalline phase, and wherein the second crystalline phase of each of the first dielectric layer, the second dielectric layer, and the third dielectric layer of the first stacked dielectric layers is an orthorhombic crystalline phase.

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