Trans-impedance amplifier with adjustable input range

Abstract

The invention relates to a transimpedance amplifier with an adjustable input range. A multi-stage transimpedance amplifier (TIA) with an adjustable input linearity range is disclosed. The TIA comprises: a first stage configured to convert a single-ended current signal from an optical sensor of a receiver signal chain into a single-ended voltage signal; and a second stage configured to convert the single-end voltage signal provided by the first stage into a differential signal. In such a TIA, a clamp may be used to adjust the input linear range, which may be programmed with an output offset current to prevent overload of the second stage of the TIA and maintain the linear transfer function without compression.

Description

[0001] This application is a divisional application of the Chinese invention patent application filed on September 25, 2020, with application number 202011023489.6 and invention name “Transimpedance Amplifier with Adjustable Input Range”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application is related to U.S. patent application No. 62 / 905,772, filed on September 25, 2019, entitled “TRANSIMPEDANCE AMPLIFIER WITH ADJUSTABLE INPUT RANGE,” the disclosure of which is hereby incorporated herein by reference in its entirety. Technical Field

[0004] The present disclosure relates generally to electronics and, more particularly, to transimpedance amplifiers. Background Art

[0005] Light detection and ranging (LIDAR) refers to a measurement method that measures the distance to a target object by illuminating the object with light (e.g., with pulses of light (e.g., pulses of laser light)) and measuring the reflected light with an optical sensor (such as an avalanche photodiode (APD)). The difference in laser return time and wavelength can then be used to determine the distance to the object and / or make a digital three-dimensional representation of the object. LIDAR systems are used in a variety of situations. For example, LIDAR systems can be used with aircraft, cars, binoculars or monoculars, etc.

[0006] A conventional receiver chain for a LIDAR system may include an optical sensor that receives / detects light pulses and converts them into a current, a transimpedance amplifier (TIA) that converts the current signal from the optical sensor into a voltage signal, and an analog-to-digital converter (ADC) that converts the voltage signal from the TIA into a digital signal for further processing. Some ADCs operate better when the input signal provided to them is a differential signal. However, optical sensors typically generate current in only one direction, and therefore, the optical sensor output is typically single-ended. Therefore, a LIDAR system may include a circuit that is configured to convert a single-ended voltage output from the TIA into a differential signal, which may then be provided as an input to the ADC. Such a circuit may be part of an ADC driver, which is an electronic component configured to perform signal conditioning on the ADC. Such a circuit may also be considered the second stage of the TIA (i.e., the first stage converts the current signal from the optical sensor into a single-ended voltage signal, and the second stage converts the single-ended voltage signal into a differential signal).

[0007] The ADC driver can be a critical factor in enabling the ADC to achieve the desired performance. First, the ADC driver (which typically operates at a higher supply voltage than the ADC) should ensure that the maximum output of the driver never exceeds the supply of the ADC to protect the ADC from permanent damage. Second, the ADC driver should regulate its output so as not to overload the ADC. The ADC may be overloaded when the output from the ADC driver exceeds the minimum and maximum voltages within the full-scale range of the ADC. High-speed ADCs (e.g., those used as modern pipeline converters) may also be overloaded if the common-mode voltage of the input signal provided to the ADC is not maintained in a narrow band around the input common-mode voltage of the ADC (e.g., less than 100 millivolts (mV)).

[0008] In addition to the danger of overloading the ADC, the TIA and single-ended to differential conversion circuits in the signal path to the ADC may also be overloaded when their inputs exceed certain limits. An overload condition in any of these components of the receiver chain is highly undesirable because it may take several microseconds or even milliseconds before the receiver recovers from the overload, during which time the receiver may not be able to process the input signal, i.e., the receiver is effectively temporarily disabled. In applications such as LIDAR systems, temporarily disabling the receiver may be absolutely critical because it means that the LIDAR system has no knowledge of its surroundings until the receiver recovers from the overload. Summary of the invention

[0009] According to one aspect of the present disclosure, a system is disclosed, which is configured to convert a single-ended current input into a differential voltage output, the system comprising: a first amplifier circuit having an output for providing a first amplifier output generated by the first amplifier circuit based on the single-ended current input; an output offset current generating circuit configured to generate an output offset current; a second amplifier circuit having a differential input including a first input and a second input, and configured to generate the differential voltage output based on the following operations: receiving a signal based on the first amplifier output at the first input, and receiving a signal based on the output offset current at the second input; and a clamp circuit coupled to the output of the first amplifier circuit and further coupled to a control signal, the control signal being configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output based on the output offset current.

[0010] According to another aspect of the present disclosure, a system is disclosed, which is configured to convert a single-ended current input into a differential voltage output, the system comprising: a first stage, configured to receive the single-ended current input and generate a single-ended output based on the single-ended current input; a clamping circuit, configured to generate a clamped single-ended output by clamping the single-ended output when one of the following is true: when the single-ended output exceeds a maximum voltage value, wherein the maximum voltage value is based on an output offset current, or when the single-ended output drops below a minimum voltage value, wherein the minimum voltage value is based on the output offset current; and a second stage, configured to: receive a signal based on the clamped single-ended output as a first input of a differential input of the second stage, receive a signal based on the output offset current as a second input of the differential input of the second stage, and generate the differential voltage output based on the differential input.

[0011] According to another aspect of the present disclosure, a system is disclosed, which is configured to convert a single-ended signal into a differential signal, the system comprising: an amplifier; and a clamping circuit, wherein: the amplifier has a differential input and a differential output, a first input of the differential input of the amplifier is configured to receive a signal based on the single-ended signal that has been clamped by the clamping circuit based on a clamping control signal, wherein the clamping control signal is based on an output offset current, a second input of the differential input of the amplifier is configured to receive a signal based on the output offset current, and the amplifier is configured to generate the differential signal based on the signal received at the differential input of the amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, and wherein:

[0013] Figure 1 is a circuit diagram showing a LIDAR receiver.

[0014] Figure 2 is a circuit diagram illustrating an exemplary implementation of a reference voltage source for a LIDAR receiver.

[0015] Figure 3 A diagram of an exemplary input waveform to amplifier A2 and a diagram of an exemplary output waveform of amplifier A2 with I0 set to zero are provided.

[0016] Figure 4 An illustration of an exemplary input waveform for amplifier A2 is provided with I0 set to 0.5*I LR FIG. 1 is a diagram of an exemplary output waveform of amplifier A2.

[0017] Figure 5 is a circuit diagram illustrating a LIDAR receiver with a multi-stage TIA with an adjustable input range according to some embodiments of the present disclosure.

[0018] Figure 6 It is to show that according to some embodiments of the present disclosure, Figure 5 2 is a circuit diagram of an exemplary single-ended TIA used within a multi-stage TIA.

[0019] Fig. 7A and Figure 7B yes Figure 6 , showing example operating points for minimum and maximum output swing, respectively.

[0020] Figure 8 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with an adjustable input range implemented by a voltage-controlled high-side clamp circuit according to some embodiments of the present disclosure.

[0021] Fig. 9 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with an adjustable input range implemented by a voltage-controlled low-side clamp circuit according to some embodiments of the present disclosure.

[0022] Fig.10 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with an adjustable input range implemented by a current-controlled high-side clamp circuit according to some embodiments of the present disclosure.

[0023] Fig.11 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with an adjustable input range implemented by a current-controlled low-side clamp circuit according to some embodiments of the present disclosure.

[0024] Fig.12 is a block diagram of an exemplary LIDAR system in which a multi-level TIA with an adjustable input range may be implemented according to some embodiments of the present disclosure.

[0025] Fig.13 A block diagram is provided illustrating an exemplary data processing system that may be configured to implement or control at least a portion of processing a received signal using a multi-stage TIA with an adjustable input range according to some embodiments of the present disclosure.

[0026] Fig.14 is an exemplary illustration of a LIDAR system integrated with a car according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] Overview

[0028] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0029] Some aspects of the present disclosure relate to a multi-stage TIA with an adjustable input linear range. An exemplary TIA includes a first stage and a second stage. The first stage is configured to convert a single-ended current input signal into a single-ended output voltage signal. In some embodiments, the single-ended current input signal may be, but is not limited to, a current signal received from an optical sensor of a receiver signal chain of a LIDAR system. The second stage is configured to convert a single-ended output voltage signal generated by the first stage into a differential voltage output signal. To this end, the second stage is configured to receive a differential input via the following two inputs: a first input (e.g., a negative input, represented herein as "IN-") and a second input (e.g., a positive input, represented herein as "IN+"). The first differential input of the second stage is configured to receive a signal based on the single-ended voltage signal generated by the first stage. The second differential input of the second stage is configured to receive a signal based on an output offset current of the second stage. The second stage is further configured to provide a differential output via the following two outputs: a first output (e.g., a negative output, represented herein as "OUT-") and a second output (e.g., a positive output, represented herein as "OUT+"). In such a TIA, the input linear range of the second stage can be adjusted by using a clamp circuit at / in (or associated with) the output of the first stage to keep the second stage of the TIA and the subsequent ADC from overloading and to help ensure that the second stage has a linear transfer function with essentially no compression.

[0030] In various embodiments, the clamp circuit may be a high-side clamp circuit or a low-side clamp circuit. As known in the art and used herein, "high-side clamping" of a signal refers to ensuring that the magnitude of the signal does not exceed a maximum value set by a circuit referred to as a "high-side clamp circuit" or simply a "high-side clamp". Similarly, as known in the art and used herein, "low-side clamping" of a signal refers to ensuring that the magnitude of the signal does not drop below a minimum value set by a circuit referred to as a "low-side clamp circuit" or simply a "low-side clamp". When triggered, the clamp circuit of any of the multi-stage TIAs described herein can ensure that the voltage of the signal at the first differential input is consistent with the clamp value, that is, if the clamp circuit is a high-side clamp circuit, the voltage does not exceed a maximum voltage value, or if the clamp circuit is a low-side clamp circuit, the voltage does not drop below a minimum voltage value.

[0031] In some embodiments, the clamp circuit can be programmed using the output offset current, which means that the clamp value applied by the clamp circuit can be based on the output offset current of the second stage (e.g., can depend on the output offset current or can be calculated by the output offset current). Therefore, when the clamp circuit of the multi-stage TIA described herein is a high-side clamp, the maximum value set / applied by the clamp circuit to the single-ended output voltage signal from the first stage can be based on the output offset current of the second stage. On the other hand, when the clamp circuit is a low-side clamp, the minimum value set / applied by the clamp circuit to the single-ended output voltage signal from the first stage can be based on the output offset current of the second stage. Regardless of whether the clamp circuit is a high-side clamp or a low-side clamp, because the second input of the differential input of the second stage receives a signal based on the output offset current, and because the first input of the differential input of the second stage receives a clamped version of the single-ended output voltage signal from the first stage (where the clamp is also based on the output offset current), the multi-stage TIA can advantageously ensure that the differential input of the second stage and the subsequent ADC are not overloaded.

[0032] In some implementations, the second stage of the multi-stage TIA disclosed herein can be considered as part of the ADC driver.

[0033] Figures 5 to 14 Some exemplary implementations of a multi-level TIA with an adjustable input range are shown. However, any implementation of a multi-level TIA with an adjustable input range is within the scope of the present disclosure based on the description provided herein.

[0034] Other aspects of the present disclosure provide systems (e.g., LIDAR systems (particularly, LIDAR receivers)) and methods of operating such systems and methods of using such systems to determine the distance to at least one object, which systems may include one or more multi-stage TIAs with adjustable input ranges implemented using programmable clamp circuits as described herein. Although some embodiments of the present disclosure refer to LIDAR as an exemplary system in which a multi-stage TIA with an adjustable input range as described herein may be implemented, in other embodiments, a multi-stage TIA as described herein may be implemented in systems other than LIDAR, all of which are within the scope of the present disclosure. In addition, although some embodiments of the present disclosure describe a multi-stage TIA with an adjustable input range receiving a single-ended current input from an optical sensor, all multi-stage TIAs described herein may be used in systems in which the single-ended current input is provided by any other source or electronic component. Similarly, although some embodiments of the present disclosure describe a multi-stage TIA with an adjustable input range that provides a differential voltage output to an ADC, all multi-stage TIAs described herein may be used in systems in which a differential voltage output is provided from the multi-stage TIA to any other electronic component other than the ADC. Still further, as described herein, arrangements for converting a single-ended signal to a differential signal using an output offset current and clamping the single-ended signal based on the value of the output offset current may be used in systems other than LIDAR systems, ADC drivers, and TIAs, all of which are within the scope of the present disclosure.

[0035] The precise design of the multi-stage TIA with adjustable input range described herein can be achieved in many different ways, all of which are within the scope of the present disclosure. In one example of design variations according to various embodiments of the present disclosure, for each of the transistors of the multi-stage TIA with adjustable input range, a bipolar transistor (e.g., where the various transistors can be NPN or PNP transistors), a field effect transistor (FET) (e.g., a metal oxide semiconductor (MOS) technology transistor (e.g., where the various transistors can be N-type MOS (NMOS) or P-type MOS (PMOS) transistors)), or a combination of one or more FETs and one or more bipolar transistors can be selected. In view of this, in the following description, they are sometimes described with reference to the first terminal, the second terminal, and the third terminal of the transistor. The term "first terminal" of a transistor is used to refer to the emitter terminal in the case where the transistor is a bipolar transistor, or the source terminal in the case where the transistor is a FET; the term "second terminal" of a transistor is used to refer to the collector terminal in the case where the transistor is a bipolar transistor, or the drain terminal in the case where the transistor is a FET; and the term "third terminal" of a transistor is used to refer to the base terminal in the case where the transistor is a bipolar transistor, or the gate terminal in the case where the transistor is a FET. These terms remain the same regardless of whether the transistor of a given technology is an N-type transistor (e.g., an NPN transistor in the case where the transistor is a bipolar transistor or an NMOS transistor in the case where the transistor is a FET) or a P-type transistor (e.g., a PNP transistor in the case where the transistor is a bipolar transistor or a PMOS transistor in the case where the transistor is a FET). In another example, in various embodiments, for each of the transistors of the multi-stage TIA with an adjustable input range, which transistors are implemented as N-type transistors (e.g., NMOS transistors where the transistors are implemented as FETs, or NPN transistors where the transistors are implemented as bipolar transistors) and which transistors are implemented as P-type transistors (e.g., PMOS transistors where the transistors are implemented as FETs, or PNP transistors where the transistors are implemented as bipolar transistors) can be selected, respectively. In still other examples, in various embodiments, it can be selected which type of transistor architecture to employ. For example, any of the transistors implemented as FETs of the multi-stage TIA with an adjustable input range as described herein can be planar transistors or can be non-planar transistors (some examples of the latter include FinFETs, nanowire transistors, or nanoribbon transistors).

[0036] As will be appreciated by those skilled in the art, various aspects of the present disclosure (particularly various aspects of a multi-level TIA with an adjustable input range as proposed herein) can be implemented in various ways (e.g., as a method, system, computer program product, or computer-readable storage medium). Therefore, various aspects of the present disclosure can take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software aspects and hardware aspects (generally referred to herein as "circuit", "module" or "system"). The functions described in the present disclosure can be implemented as an algorithm executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and parts of steps of each of the methods described herein can be performed by different processing units. In addition, various aspects of the present disclosure can take the form of a computer program product implemented in one or more computer-readable media, which are preferably non-transitory and contain (e.g., store) computer-readable program code. In various embodiments, such a computer program may, for example, be downloaded (updated) to existing devices and systems (eg, to existing receivers, LIDAR systems, and / or their controllers, etc.) or stored when these devices and systems are manufactured.

[0037] The following detailed description presents various descriptions of certain embodiments. However, the innovation described herein can be implemented in a variety of different ways (e.g., as defined and covered by the selected examples). In the following description, reference is made to the accompanying drawings, in which the same reference numerals can indicate the same or functionally similar elements. It should be understood that the elements shown in the accompanying drawings are not necessarily drawn to scale. In addition, it should be understood that some embodiments may include more elements than shown in the accompanying drawings and / or a subset of the elements shown in the accompanying drawings. Further, some embodiments may combine any suitable combination of features from two or more accompanying drawings.

[0038] The description may use the phrase "in one embodiment" or "in multiple embodiments", which may each refer to one or more of the same or different embodiments. Unless otherwise indicated, the use of ordinal adjectives "first", "second" and "third" etc. to describe a common object only indicates that different instances of the same object are referenced, and is not intended to imply that the object described in this manner must be in a given sequence in time, space, rank or in any other manner. In addition, for purposes of this disclosure, phrase "A and / or B" or symbol "A / B" refers to (A), (B) or (A and B), and phrase "A, B and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). As used herein, symbol "A / B / C" refers to (A, B and / or C). When it comes to measurement range, the term "between..." includes the end of the measurement range.

[0039] Various aspects of the exemplary embodiments are described using terms commonly employed by those skilled in the art to convey the substance of their work to other technicians in the art. For example, the term "connect" refers to a direct electrical connection between the things being connected without any intermediate devices / components, while the term "coupled" refers to a direct electrical connection between the things being connected, or an indirect electrical connection through one or more passive or active intermediate devices / components. In another example, the term "circuit" refers to one or more passive and / or active components that are arranged to cooperate with each other to provide the desired functionality. Sometimes, in this description, the term "circuit" may be omitted (e.g., a clamp circuit may be simply referred to as a "clamp", etc.). If used, based on the context of a specific value as described herein or known in the art, the terms "substantially", "approximately", "approximately", etc. may be used to generally refer to within + / -20% of a target value, such as within + / -10% of a target value.

[0040] The Basics of Multi-Level TIA

[0041] In order to explain the multi-level TIA with adjustable input range implemented using programmable clamp circuits proposed in this article, it may be useful to first understand the settings in which the multi-level TIA can be used and the phenomena that may occur when such TIA is used. The following basic information can be considered as the basis for properly explaining the present disclosure. Such information is provided only for the purpose of explanation, and therefore, should not be interpreted in any way to limit the broad scope of the present disclosure and its potential applications.

[0042] As mentioned above, a multi-level TIA may be used in a LIDAR system. Figure 11 is a schematic diagram of a LIDAR receiver 100. The LIDAR receiver generally includes an optical sensor (eg, APD) 102, a TIA 104, and an ADC 106. The optical sensor 102 may be configured to receive pulses of light reflected from an object and convert the pulses of light into current pulses. Figure 1 As shown, in some embodiments, the optical sensor 102 can connect its cathode to the input port of the TIA 104 (the input port of the TIA 104 is at Figure 1 104). Thus, the optical sensor 102 may be negatively biased and may sink current from the TIA 104. Although not specifically shown in this figure, in other embodiments, the optical sensor 102 may have its anode connected to the input port of the TIA 104; thus, the optical sensor 102 will be positively biased and may provide current to the TIA 104.

[0043] TIA 104 may be configured to amplify current pulses from optical sensor 102 and provide voltage pulses. TIA 104 may be a multi-stage TIA having a first stage and a second stage. The first stage may include amplifier circuit 105 (at Figure 1 105 and may also be referred to interchangeably herein as "amplifier A0") and a feedback resistor (RT) 107 electrically coupled between the input of amplifier circuit 105 and the output of amplifier circuit 105. The first stage may be configured to convert a single-ended input current signal IIN (e.g., the current from optical sensor 102) into a single-ended output voltage signal that is provided at the output of amplifier circuit 105. The output of amplifier circuit 105 may be electrically connected to the input of a second stage, which may be considered to be part of an ADC driver. The second stage may include amplifier circuit 109 (at Figure 1 The second stage may be configured to perform a single-ended to differential conversion to generate a differential drive signal for ADC 106. To this end, amplifier circuit 109 has a differential input, such as Figure 1 It is shown having two input terminals: a first input terminal, shown as "IN-" (eg, negative input); and a second input terminal, shown as "IN+" (eg, positive input). Figure 1 It is further shown that the amplifier circuit 109 has a differential output, such as Figure 1The ADC 106 is shown as having the following two output terminals: a first output terminal, shown as "OUT-" (e.g., negative output); and a second output terminal, shown as "OUT+" (e.g., positive output). The ADC 106 can convert the received differential analog signal (which is based on the differential output from the amplification circuit 109) (e.g., a differential analog voltage pulse signal) into a digital signal. The digital signal can be provided to a digital signal processor ( Figure 1 not shown).

[0044] Typically, the two amplifiers A0 and A2 are designed to be optimized according to different parameters. Amplifier A0 can be optimized for maximum dynamic range (e.g., maximum input linear range and minimum input current noise), while amplifier A2 can be optimized for maximum output swing as an output stage that can also include or be included in an ADC driver that can scale the signal and center the differential output around the input common-mode voltage of the ADC.

[0045] like Figure 1 As shown, the negative input terminal of amplifier A2 (i.e., Figure 1 The positive input terminal of amplifier A2 (i.e., the positive input terminal of amplifier A2, which is labeled “IN-” in FIG. 1 ) can be coupled to the single-ended output of amplifier A0. Figure 1 The input terminal of A2 (labeled “IN+” in FIG. 1 ) may be coupled to a reference voltage source 110 configured to output a reference voltage VREF. The reference voltage provided by the reference voltage source VREF may be adjustable, for example, to best utilize a dynamic range provided by electronic components configured to receive a differential output from the second stage of the TIA 104, for example, to best utilize a dynamic range provided by the ADC 106.

[0046] In some embodiments, Figure 1 The reference voltage source 110 can be Figure 2 As shown, the reference voltage circuit 210 is used to implement (otherwise, Figure 2 Shown with Figure 1 The LIDAR receiver 100 shown is substantially identical to the LIDAR receiver 200 ). Figure 2 As shown, in some embodiments, the circuit 210 may include an amplifier circuit 205 (in Figure 2, and may also be referred to interchangeably herein as "amplifier A1") and a feedback resistor (RT) 207 electrically coupled between the input of the amplifier circuit 205 and the output of the amplifier circuit 205. The output of the amplifier circuit 205 may be electrically coupled to the input of the second stage, for example, to the positive input terminal of amplifier A2. In some embodiments, amplifier A1 may be substantially an exact copy or scaled copy of amplifier A0 (which may save area and power). Amplifier A0 may be referred to as a "signal TIA" or "master TIA" (since this is the circuit that performs the current-to-voltage conversion), while amplifier A1 may be referred to as a "reference TIA" or "replica TIA". The reference voltage VREF provided by amplifier A1 at the positive input of amplifier A2 may be adjusted in a power efficient manner using a current source that provides a current I0 to the input of the replica TIA A1. The output voltage of the replica amplifier A1, where I0=0, may be configured to track the output voltage of the master amplifier A0, where IIN=0, over process, voltage, and temperature (PVT) variations. Current I0 is often referred to as the "output offset current" of / for the first stage of TIA 104. The output offset current may be used to modify the output of the multi-stage TIA 104 (a process sometimes referred to as "tilting") to better utilize the input signal range of subsequent electronic components (e.g., ADC 106) configured to receive the output of the TIA 104.

[0047] Prior art solutions typically focus on mitigating overloads of amplifier A0 (e.g., in response to the output current of the optical sensor 102 exceeding the linear input range of amplifier A0) to prevent permanent damage and ensure fast recovery times. A TIA optimized for low noise and large output swings in high-speed LIDAR receivers may have a linear range of 100 microamperes. At very large currents from the optical sensor 102 (e.g., on the order of hundreds of milliamperes), external mechanisms such as protection diodes may be necessary to prevent permanent damage to amplifier A0. At more modest currents from the optical sensor 102 (e.g., on the order of a few milliamperes), amplifier A0 may include internal mechanisms to keep the transistors out of the saturation region, which facilitates fast recovery after the overload condition is removed.

[0048] The inventors of the present disclosure recognized that each amplifier stage of a multi-stage TIA needs to recover quickly for optimal response. While existing solutions may rely on internal mechanisms within each amplifier to handle overload conditions, embodiments of the present disclosure provide a simple adjustable circuit that relies on limiting the maximum swing in the previous amplifier stage.

[0049] Input and output waveforms at amplifier A2 of the multi-stage TIA

[0050] Figure 3A diagram 310 of an exemplary input waveform of amplifier A2 and a diagram 320 of an exemplary output waveform of amplifier A2 with I0=0 are provided. A solid line 312 of the diagram 310 indicates a signal provided to the negative input IN- of amplifier A2 when I0=0. A dashed line 314 of the diagram 310 indicates a signal provided to the positive input IN+ of amplifier A2 when I0=0. A solid line 322 of the diagram 320 indicates a signal provided at the negative output OUT- of amplifier A2 when I0=0. A dashed line 324 of the diagram 320 indicates a signal provided at the positive output OUT+ of amplifier A2 when I0=0.

[0051] Line 312 of graph 310 shows an exemplary response of the output of amplifier A0 relative to the input current IIN of amplifier A0. For IIN=0, the output of amplifier A0 may have a minimum value V min,A0 , which is marked at the bottom of the graph 310. The output of the replica amplifier A1 with zero output offset current (ie, I0=0) is also V min,A0 When IIN = 0 and I0 = 0, amplifiers A0 and A1 can be considered matched in all respects and their outputs are identical. As the input current IIN increases, the output of amplifier A0 can reach its maximum value V max,A0 , which is also marked in the diagram 310. Therefore, when I0=0, the minimum differential input of amplifier A2 can be 0, which is the output (V min,A0 ) and the output of amplifier A1 (also V min,A0 ). On the other hand, the maximum differential input of amplifier A2 can be V max,A0 and V min,A0 The difference between the output of amplifier A0 when IIN is maximum (i.e., V max,A0 ) and the output of amplifier A1 when I0 = 0 (i.e. V min,A0 ) Figure 3 Graph 320 of FIG. 328 shows a vertical dot-dash line 328. The portion of graph 320 shown to the left of line 328 shows the negative and positive outputs of amplifier A2 when IIN=0. The portion of graph 320 shown to the right of line 328 shows the negative and positive outputs of amplifier A2 as IIN gradually increases, showing the deviation between the negative and positive outputs of amplifier A2.

[0052] In pulsed LIDAR systems (where output linearity is often not important), the maximum output swing of amplifier A0, referenced to its input, corresponds to its linear input range of current (I LR , where "LR" stands for "linear range"), that is:

[0053]

[0054] Where RT is the feedback resistor 107 between the input and output of amplifier A0. In this case, Figure 3 As shown in the diagram 320 of FIG. 3 , the differential output response of amplifier A2 can be a symmetrical output around the common mode voltage Vcm (at Figure 3 320 is shown by dotted line 326), where the minimum value at the negative output terminal OUT- of amplifier A2 is V min,A2 , and the maximum value at the positive output terminal OUT+ of amplifier A2 is V max,A2 In some embodiments, the common mode voltage Vcm of amplifier A2 may be set to match the input common mode voltage of ADC 106. In various embodiments, TIA 104 may have additional passive and / or active components (not shown in this figure) to set or adjust the output to a desired common mode output voltage to match the input common mode of ADC 106.

[0055] To maximize the differential output swing of amplifier A2, the optimal reference voltage VREF at the positive input IN+ of amplifier A2 can be opt Set to V min,A0 and V max,A0 The average value of:

[0056]

[0057] This will limit the maximum voltage at the differential input of amplifier A2 to:

[0058]

[0059] That is, the linear range of the amplifier is + / -dV, which is half of the maximum swing of amplifier A0.

[0060] The optimum output offset current in this case is The optimal output offset current is equal to the linear input range I of the first stage amplifier A0. LR Half (i.e., I0 opt =0.5*I LR ). Figure 4 A diagram 410 of an exemplary input waveform of amplifier A2 and a diagram 420 of an exemplary output waveform of amplifier A2 are provided, wherein the output offset current I0 is equal to the linear input range I of amplifier A2. LR Half (i.e., I0 = I0 opt =0.5*I LR ). The solid line 412 of the graph 410 indicates that when I0=I0 opt =0.5*I LRThe dashed line 414 of the diagram 410 indicates that when I0=I0 opt =0.5*I LR The solid line 422 of the graph 420 indicates that when I0=I0 opt =0.5*I LR The dashed line 424 of the graph 420 indicates that when I0=I0 opt =0.5*I LR The signal provided at the positive output OUT+ of amplifier A2 is .

[0061] like Figure 4 As shown, with the optimum reference voltage at the positive input IN+ of amplifier A2, Figure 4 The differential output swing of amplifier A2 in diagram 420 may be Figure 3 The differential output swing of 320 is twice as large as shown in the figure. Figure 3 and Figure 4 The diagram shows that when IIN=0 and output offset current I0=0, then amplifiers A0 and A1 are matched in all respects and their outputs are essentially the same, and by varying I0, a differential voltage can be produced at the input of A2, which can advantageously achieve what is commonly referred to as "tilt" - that is, separation between the negative and positive outputs of amplifier A2 when IIN=0, which allows the full range of amplifier A2 to be used. Figure 4 Diagram 420 further shows line 426 representing common mode voltage Vcm and vertical dot-dash line 428. The portion of diagram 420 shown to the left of line 428 shows the negative and positive outputs of amplifier A2 when IIN is minimum (e.g., when IIN=0, which is minimum for a unipolar input current at the input of amplifier A0). The portion of diagram 420 shown to the right of line 428 shows the negative and positive outputs of amplifier A2 as IIN gradually increases. Both the left and right portions of line 428 show the deviation between the negative and positive outputs of amplifier A2, which is the "tilt" of amplifier A2 by appropriately selecting the output offset current I0. This is consistent with Figure 3 The opposite of the diagram, where the output offset current I0 is equal to zero, and therefore, when IIN = 0, Figure 3 The left portion of line 328 in graph 320 of FIG. 3 has no deviation between the negative and positive outputs of amplifier A2.

[0062] Multi-stage TIA based on output offset current clamping

[0063] As described above, the output offset current I0 can be provided to the replica amplifier A1 to produce a voltage at the positive input of the differential amplifier A2 that allows better utilization of the input linear range of the amplifier A2. As described above, the optimal output offset current I0 opt can be equal to half the linear range of the output of amplifier A0, i.e., half the linear range current defined by equation (1) above, which yields an optimum voltage VREF at the positive input of amplifier A2 opt , according to equation (2) above, the optimal voltage is V min,A0 and V max,A0 In various embodiments, the arrangement of the TIA 104 with amplifiers A0, A1, and A2 as described herein may be used with different ADCs (or different other electronic components that receive the differential output from amplifier A2 as input), where the different ADCs may have different input ranges, and therefore, the second stage of the multi-stage TIA 104 may have a different input range. Additionally, if the input range of the differential ADC is smaller than the input range of the TIA, the input range of the TIA should be limited so that the output of the TIA does not exceed the input range of the ADC. Therefore, the optimal output offset current I0 opt The value of may vary depending on the implementation of the multi-stage TIA 104. Thus, the multi-stage TIA may be configured such that the output offset current I0 may be controlled by an external signal, such as an external voltage signal. Such a voltage signal may be provided as the output of a digital-to-analog converter (DAC), or by any other circuit suitable for generating such a control signal. A voltage-to-current converter may then be used to convert the external voltage signal into the output offset current I0.

[0064] The inventors of the present disclosure have recognized that even with an output offset current that can be controlled by an external signal as described above, it may not always work as expected to prevent overloading of various components of a multi-stage TIA, such as multi-stage TIA 104. In particular, the inventors of the present disclosure have recognized that even if it is possible to use an external control signal to attempt to generate an output offset current that is equal to the optimal I0 opt The actual output offset current I0 received by the replica amplifier A1 act It may also deviate from the optimal I0 opt Some reasons why the value of the actual output offset current may deviate from the optimal value include PVT variations and the fact that the external control signal and the voltage-to-current converter circuit that can be used to generate the output offset current based on the control voltage may vary. act Deviation from the optimal output offset current I0 opt This may cause problems such as overloading amplifier A2. For example, if the actual output offset current I0 actLess than I0 opt , the maximum differential input of amplifier A2 may exceed dV and overload amplifier A2. Similarly, based on the actual output offset current deviation from the optimal current I0 opt Allowing the voltage at the positive input of amplifier A2 to drop below some minimum value may cause problems.

[0065] The embodiments of the present disclosure are based on the recognition that the actual output offset current I0 can be compensated by providing a clamp circuit. act With the optimum output offset current I0 opt The clamp circuit is coupled to the negative input of amplifier A2 and is configured to define an actual output offset current I0 based on the voltage at the positive input of amplifier A2. act To clamp the maximum or minimum voltage at the negative input of amplifier A2. In this way, the actual output offset current I0 act may happen to deviate from the optimum output offset current I0 opt , which causes the actual voltage at the positive input of amplifier A2 to deviate from the optimal value VREF opt , but is configured to correspondingly clamp the voltage at the negative input of amplifier A2 to a value based on the actual output offset current I0 act A clamping circuit with a value of can compensate for said deviation at the positive input to ensure that, for example, amplifier A2 is not overloaded.

[0066] Figure 5 is a circuit diagram illustrating a LIDAR receiver 500 with a multi-stage TIA 504 having an adjustable input range according to some embodiments of the present disclosure. Figure 5 As shown, the LIDAR receiver 500 may include the optical sensor 102 and the ADC 106, as described above. In addition, the TIA 504 may include a first stage having an amplifier A0 and a resistor RT, as described above, the amplifier A0 being configured to receive the input current signal IIN, and may further include a second stage having an amplifier A2, also as described above. In addition, the TIA 504 may further include a circuit such as a replica amplifier A1, which is configured to use the output offset current I0 to set the voltage at the positive input of the amplifier A2, also as described above. Therefore, the TIA 504 may be substantially similar to Figure 21. The difference of TIA 504 is that it further includes a clamp circuit 520, which is coupled to the output of amplifier A0 (or, equivalently, coupled to one of the differential inputs of amplifier A2, i.e., coupled to the negative input of amplifier A2) and is configured to clamp the voltage of the signal at the output of amplifier A0 (or, equivalently, the voltage of the signal at the negative input of amplifier A2) to a clamp value, wherein the clamp value is based on the output offset current I0 provided to replica amplifier A1.

[0067] Consider first the case where the clamp circuit 520 is a high-side clamp circuit.

[0068] To avoid overloading amplifier A2, the maximum voltage at the output of amplifier A0 may need to be limited to less than V max,A0 .to this end, Figure 5 The illustrated clamp circuit 520 (C0) may be a high-side clamp 520 coupled to the output of amplifier A0. Clamp C0 may be coupled directly or indirectly to the output of amplifier A0 for the purpose of limiting the maximum output voltage of amplifier A0. In particular, clamp C0 may be programmed with a value of output offset current I0 that is the same as the value of the output offset current used by replica amplifier A1 to generate a reference voltage at the positive input of amplifier A2, such that the output voltage of amplifier A0 may be clamped to a maximum value V defined based on output offset current I0. CLHI For example, the maximum output voltage of amplifier A0 can be clamped to not exceed the output voltage of amplifier A1 by the linear input range dV of amplifier A2, that is:

[0069] V CLHI =V out,A1 +dV, (4)

[0070] The term V CLHI The abbreviation "CLHI" indicates the voltage V CLHI is the high (HI) clamp (CL) voltage. Equation (4) can be rewritten as:

[0071]

[0072] It should be noted that Figure 5The TIA 504 shown in shows a current source that generates the output offset current I0 twice (once to provide an input to amplifier A1 and once to provide an input to clamp 520). In some embodiments, this may mean that the same current source is used to generate the output offset current I0 in both cases (i.e., a single current source is used to provide the output offset current I0 as the input to amplifier A1 and as the input to clamp 520). For example, in some such embodiments, a single current mirror with multiple outputs may be used to generate a current having the same value. In other embodiments, the current sources that generate the current I0 as the input to amplifier A1 and as the input to clamp 520 may be different current sources, both of which are set to the same value, e.g., both are programmed using an external voltage, as described above. In . Figure 5 In some embodiments, amplifier A1 may be a scaled (e.g., smaller) version of amplifier A0 (e.g., to save silicon area and / or quiescent current drawn from a power supply). For example, scaling may be implemented by using a feedback resistor with a resistance of N*RT, where the scaling factor N may be a number greater than 1 (where Figure 5 The feedback resistors of amplifier A1 are shown with N=1). In such an embodiment, the current source at the input of amplifier A1 will be scaled down by the same factor to I0 / N.

[0073] When the input is involved, the maximum voltage at the output of amplifier A0 is clamped to the clamping voltage V using such a clamping circuit 520. CLHI corresponds to (or results in) effectively adjusting the linear input range of amplifier A0 (i.e., the first stage of TIA 504) based on the output offset current (thus, TIA 504 may be referred to as a "multi-stage TIA with an adjustable input range"). In particular, equation (1) can now be rewritten as max,A0 Replace with V CLHI ,as follows:

[0074]

[0075] Substitute V in equation (6) CLHI Substituting into the right side of equation (5), enter the linear range I LR The correlation with the output offset current I0 becomes clear:

[0076]

[0077] The proposed high-side clamp 520 can not only reduce or eliminate the possibility of overloading amplifier A2, but also adjust the input linear range of amplifier A0 to maintain a linear transfer function between the single-ended input IIN and the differential outputs OUT+ and OUT- of amplifier A2. Equation (7) shows that the input linear range is now a function of the output offset current I0, where the maximum value is (V max,A0 ±V min,A0 ) / RT=VREF opt / RT. The maximum input linear range is the input linear range before the high-side clamp is introduced.

[0078] Figure 6 is a circuit diagram showing a first stage 600 of an exemplary TIA according to some embodiments of the present disclosure. The first stage 600 may be used to implement Figure 5 The first stage of TIA 504 shown in FIG. 5 is used to implement Figure 5 Amplifier A0 with resistor RT is shown. In particular, Figure 5 An example of a wide bandwidth high dynamic range amplifier 105 (A0) is shown in FIG. Figure 6 As shown in FIG. 6A and 6B (enclosed in a dashed outline), Figure 6 As shown, amplifier 605 may include transistors Q1 and Q2 (both shown as NPN transistors), a load element 610 (eg, a load resistor) R1 , and a current source I2 . Figure 6 Further shown is a circuit connected between the input terminal IIN of the amplifier A0 and the output terminal of the amplifier A0 (in Figure 6 A feedback resistor 107 (RT) is connected between the input and output terminals of the transistor and the output terminals of the transistor (labeled as out, A0). Figure 6 Also shown are Vee (ie, the negative power supply for the circuit, which may be ground) and Vcc (ie, the positive power supply for the circuit).

[0079] Fig. 7A and Figure 7B yes Figure 6 , showing example operating points for minimum and maximum output swing, respectively.

[0080] Fig. 7A The default operating point with no input current is shown under the following conditions: positive power supply Vcc = 3.3V, negative power supply Vee = 0.0V, and zero input current. Fig. 7A For each of the transistors shown in FIG. , it is assumed that the base-emitter voltage (V BE ) is 0.8V, and the base current is assumed to be negligible. The input terminal IIN at the base of Q1 is Vee + V BE = 0.8V, and the same is true for the output terminal out, A0. Therefore, the minimum voltage output swing may be V min,A0 =0.8V.

[0081] Figure 7B exhibits maximum output swing. When I C,Q1 When the collector current of Q1 approaches zero, the base voltage of Q2 approaches the positive power supply of 3.3V, and therefore the maximum output voltage on the output terminal out, A0, will be 0.8V lower than the positive power supply, i.e., V max,A0 =2.5V(V max,A0 =Vcc-V BE =2.5V). At maximum output swing, for feedback resistor RT = 17 kilo-ohms, the input current (which is also equal to the input linear range under this condition) will be 100 microamps. According to equation (2) above, applying an output offset current of 50 microamps at the input amplifier A1 will produce the optimal reference voltage VREF opt =1.65V.

[0082] Figure 8 is a circuit diagram illustrating an example of a first stage 800 of a multi-stage TIA 504 with an adjustable input range implemented by a clamp circuit 520 that is a voltage-controlled high-side clamp circuit, according to some embodiments of the present disclosure.

[0083] Figure 8 Provides similar Figure 6 The diagram of the first stage 600 shown in FIG. 1 further shows transistor Q3, which is used to implement the clamp circuit 520 into a high-side clamp circuit 820 ( Figure 8 820). Figure 8 As shown, transistor Q3 can be controlled by control voltage 825 (e.g., by coupling its base terminal to control voltage 825), which can be set to V as described above. CLHI , i.e., where control voltage 825 is a function of output offset current I0. Transistor Q3 is indirectly coupled to the output (out, A0) of amplifier A0 by coupling to transistor Q2, as shown in FIG. Figure 8 As shown, the maximum output swing of amplifier A0 can be limited. Figure 8 As shown, in some embodiments, transistor Q3 can be implemented as a PNP transistor, wherein the base of transistor Q3 can be coupled to a control voltage (high clamping voltage) V CLHI , the collector of transistor Q3 can be coupled to the negative power supply Vee, and the emitter of transistor Q3 can be coupled to the base of load transistor R1 and transistor Q2 implemented as amplifier A0 of circuit 605, as described above. In this arrangement, if the output offset current is set to zero, and further assuming that V BE,Q2 =|V BE,Q3 |, V CLHISetting it equal to 1.65V (according to equation (5) above) limits the input linear range to 50 microamps (according to equation (7) above).

[0084] In other embodiments, the clamp circuit 520 may be implemented as a voltage controlled low side clamp. According to some embodiments of the present disclosure, an example of such an implementation is Fig. 9 , a circuit diagram showing an example of a first stage 900 of a multi-stage TIA with an adjustable input range implemented by a voltage-controlled low-side clamp circuit 920 is provided. In addition to the following, Fig. 9 The circuit diagram shown in is similar to Figure 8 : all PNP transistors have been replaced by NPN transistors and vice versa, the supply voltages Vcc and Vee have been swapped, and the reference numbers given to various components begin with "9" instead of "8", "6" or "1". In the first stage 900, the term V CLLO The abbreviation "CLLO" in the control signal 925 indicates that the control signal 925 is a low (LO) clamp (CL) voltage V CLLO . Similar to the high clamping voltage V CLHI , low clamping voltage V CLLO is the voltage applied by clamp circuit 520 to the output of amplifier A0 to ensure that the output does not drop below a certain minimum value, which is V CLLO . Also similar to the above high clamping voltage V CLHI , low clamping voltage V CLLO In particular, the clamp can be programmed by a value of the output offset current I0 that is the same as the value of the output offset current used by the replica amplifier A1 to generate a reference voltage at the positive input of the amplifier A2, so that the output voltage of the amplifier A0 can be clamped to a minimum value V defined based on the output offset current I0. CLLO For example, the minimum output voltage of amplifier A1 can be clamped to not drop below the output voltage of amplifier A1 by the linear input range dV of amplifier A2, that is:

[0085] V CLLO =V out,A1 -dV. (8)

[0086] Equation (8) can be rewritten as:

[0087]

[0088] One may notice the symmetry between the high-side clamp equations (4), (5) and the low-side clamp equations (8), (9): the power and current directions have been reversed, so +dV in equation (4) becomes -dV in equation (8), +I0*RT in equation (5) becomes -I0*RT in equation (9), and V in equation (5) is min,A0 =Vee+V BE becomes V in equation (9) max,A0 =(Vcc-|V BE |).

[0089] When the input is involved, the minimum voltage at the output of amplifier A0 is clamped to a clamp voltage V using clamp circuit 520 as a low-side clamp. CLLO This corresponds to (or results in) adjusting the linear input range of the second stage of TIA 504 according to equation (9).

[0090] Figure 8 and Fig. 9 The embodiment shown in FIG. 1 shows a voltage controlled clamp circuit configured to clamp the voltage at the negative input of amplifier A2 to ensure that the voltage at the negative input of amplifier A2 does not exceed the voltage V depending on the output offset current. CLHI The maximum value set (for Figure 8 ), and the voltage at the negative input of amplifier A2 does not drop below V which is determined by the output offset current CLLO The minimum value set (for Fig. 9 However, in other embodiments, the voltage controlled clamp circuit may be implemented differently. Figure 8 and Fig. 9 The circuits 820 or 920 shown in FIG. 1 and / or the first stage of the TIA 504 may use a circuit different from Figure 8 and Fig. 9 805 or 905 as shown in FIG. 1 , as long as such other circuits allow for implementation of V as described herein. CLHI and V CLLO In addition, in some other embodiments, the clamp circuit 520 can be implemented as a current control clamp circuit, that is, instead of the voltage V CLHI or V CLLO , the control signal depending on the output offset current is the high-side current I CLHI Or low side current I CLLO .

[0091] Fig.10is a circuit diagram showing an example of a first stage 1000 of a multi-stage TIA 504 with an adjustable input range implemented by a clamp circuit 520 as a current-controlled high-side clamp circuit according to some embodiments of the present disclosure. In addition to the following, Fig.10 Provides similar Figure 8 An illustration of the first stage 800 is shown in: Figure 8 The high clamping voltage control circuit 820 shown in FIG. 8 is now Fig.10 The high clamping current control circuit 1020 (ie, circuit 1020 ( Fig.10 The approximate outline of the clamp circuit shown in FIG. 1 with a dashed outline labeled with reference number 1020) is replaced. Fig.10 As shown, the clamp circuit 1020 may include a transistor Q3 coupled to the first stage of the amplifier, as shown in FIG. Figure 8 As stated above. Figure 8 In contrast to the illustration of FIG. 1 , the base terminal of transistor Q3 of clamp circuit 1020 is coupled to a further device, such as transistors Q3 and Q4 and resistor R4, which may include, for example Fig.10 The further device may couple the base terminal of transistor Q3 of clamp circuit 1020 to a control current 1025 which may be set to I as a function of output offset current I0. CLHI , for example, such as:

[0092]

[0093] The equation can be rewritten as:

[0094]

[0095] In some embodiments, R4 can be set to RT. The voltage V in these equations BE is the base-emitter voltage across transistor Q2.

[0096] Since the transistor Q3 of the clamp circuit 1020 is indirectly coupled to the output (out, A0) of the amplifier A0 by being coupled to the transistor Q2, as shown in FIG. Fig.10 As shown, the control current I coupled to the clamp circuit 520 CLHI The transistor Q3 of the clamp circuit 1020 can limit the maximum output swing of the amplifier A0 (by limiting the output voltage of the amplifier A0 to V CLHI ).

[0097] In other embodiments, the clamp circuit 520 may be implemented as a current controlled low side clamp. According to some embodiments of the present disclosure, an example of such an implementation is Fig.11As shown in FIG. 1 , a circuit diagram showing an example of a first stage 1100 of a multi-stage TIA 504 with an adjustable input range implemented by a clamp circuit 520 as a current-controlled low-side clamp circuit is provided. In addition to the following, Fig.11 The circuit diagram shown in is similar to Fig.10 : all PNP transistors have been replaced by NPN transistors and vice versa, the supply voltages Vcc and Vee have been swapped, and the reference numbers given to the various components begin with "11" instead of "10". In the first stage 1100, the term I CLLO The abbreviation "CLLO" in the figure indicates that the control signal 1125 is a low (LO) clamp (CL) current I CLLO . Similar to the above high clamping current I CLHI , low clamping current I CLLO The clamp circuit 520 is allowed to apply a voltage V to the output of amplifier A0. CLLO to ensure that the output does not drop below a certain minimum voltage value, which is V CLLO . Also similar to the above high clamping current I CLHI , low clamping current I CLLO Depends on the actual output offset current I0, for example, such as:

[0098]

[0099] The equation can be rewritten as:

[0100]

[0101] Assume Vee = 0. In some embodiments, R4 can be set to RT. The voltage V in these equations BE is the base-emitter voltage across transistor Q2 (negative for a PNP transistor).

[0102] When the input is involved, the clamp circuit 520 used as a low-side clamp is based on the clamp current I CLLO Clamping the minimum voltage at the output of amplifier A0 corresponds to (or results in) adjusting the linear input range of the second stage of TIA 504 according to equation (12).

[0103] Fig.10 and Fig.11 The embodiment shown in FIG. 1 shows a current control clamp circuit configured to clamp the voltage at the negative input of amplifier A2 to ensure that the voltage at the negative input of amplifier A2 does not exceed the voltage determined by I depending on the output offset current. CLHI The maximum value set (for Fig.10), and the voltage at the negative input of amplifier A2 does not drop below the voltage determined by the output offset current I CLLO The minimum value set (for Fig.11 However, in other embodiments, the current control clamp circuit may be implemented differently. Fig.10 and Fig.11 The circuits 1020 or 1120 shown in FIG. 1 and / or the first stage of TIA 504 may use a circuit different from Fig.10 and Fig.11 1005 or 1105 as shown in the embodiment of the present invention, as long as such other circuits allow the implementation of V as described herein. CLHI and V CLLO That's it.

[0104] Figures 5 to 11 Some specific exemplary implementations of a multi-stage TIA with a programmable clamp of the first stage according to some embodiments of the present disclosure are shown. Some variations of these arrangements according to other embodiments of the present disclosure have been described above. Other variations / embodiments are also possible and within the scope of the present disclosure, i.e., various other programmable clamps (high side or low side and voltage controlled or current controlled clamps), as long as the clamp depends on the output offset current I0 as described herein. Some of these further variations / embodiments are described below.

[0105] In some embodiments, a multi-stage TIA with a clamp programmable using an output offset current as described herein may have additional passive and / or active components to set or adjust a desired common-mode output voltage, for example, to match the input common mode of an ADC or any other electronic component configured to receive a differential input from the multi-stage TIA.

[0106] In addition, despite Figures 6 to 11 The illustrations are provided for circuits using bipolar transistors, but the descriptions can be readily applied to circuits using FETs or a combination of bipolar transistors and FETs. For example, in a further embodiment of a multi-stage TIA 504 with an adjustable input range as described herein, Figures 6 to 11 Any NPN transistors shown in can be replaced with NMOS transistors, and / or Figures 6 to 11Any PNP transistors shown in can be replaced with PMOS transistors. In such embodiments, references to the base terminal of the above-described bipolar transistors can be replaced with "gate terminal" for transistors implemented as FETs, references to the emitter terminal of the above-described bipolar transistors can be replaced with "source terminal" for transistors implemented as FETs, and references to the collector terminal of the above-described bipolar transistors can be replaced with "drain terminal" for transistors implemented as FETs. Moreover, as is known in the art, the positive power supply Vcc of the bipolar transistor will be the positive power supply VDD of the FET, and the negative power supply Vee of the bipolar transistor will be the negative power supply VSS of the FET.

[0107] Exemplary Systems

[0108] A multi-level TIA with an adjustable input range as described herein can be used in any type of system. An example of such a system is Fig.12 , a block diagram of an exemplary laser ranging (eg, LIDAR) system 1200 is provided according to some embodiments of the present disclosure. Fig.12 As shown, system 1200 may include a transmitter signal chain 1210, a receiver signal chain 1230, a processor 1250, and a controller 1260. In some cases, the receiver signal chain 1230 may be implemented separately from the transmitter signal chain 1210. Fig.12 As shown, the transmitter signal chain 1210 may include a digital-to-analog converter (DAC) 1212, a low-pass filter (LPF) 1214, a programmable gain amplifier (PGA) 1216, a laser driver 1218, and a laser 1220. The receiver chain 1230 may include an optical sensor (e.g., a photodiode (PD) 1232), a transimpedance amplifier (TIA) 1234, an LPF 1236, an analog-to-digital converter (ADC) driver 1238, and an ADC 1240. In some cases, the receiver chain may include a PGA coupled between the TIA 1234 and the LPF 1236. Such a PGA may be implemented in place of the ADC driver 1238 or in addition to the ADC driver.

[0109] Processor 1250 may be configured to generate a digital signal indicating that a laser pulse is to be emitted by laser 1220. The digital signal from processor 1250 may then be converted to an analog signal by DAC 1212, further processed by optional LPF 1214, amplified by PGA 1216, and provided to laser driver 1218. In some embodiments, laser 1220 may be a laser diode, such as an inductively resonant laser diode.

[0110] The light emitted by the laser 1220 can reach an object or target, and the reflected light can be received by the optical sensor 1232 of the receiver signal chain 1230. Therefore, the reflected light can be detected at the optical sensor 1232. For example, the optical sensor 1232 can be an avalanche photodiode (APD). The optical sensor 1232 can generate a current pulse indicating the received reflected light, and the current pulse can be converted into a voltage pulse by the TIA 1234 and, optionally, further processed by the LPF 1236. In some embodiments, the LPF 1236 can be a tunable filter. As shown, the LPF 1236 can be coupled in the signal path between the TIA 1234 and the ADC driver 1238. In some other embodiments, the LPF 1236 can be coupled in the signal path between the ADC driver 1238 and the ADC 1240. The ADC driver 1238 can generate a drive signal based on the output of the TIA 1234 to drive the ADC 1240. ADC 1240 may convert the received drive signal into a digital signal for further processing by processor 1250. TIA 1234 and / or ADC 1238 may include any embodiment of a multi-stage TIA with programmable clamps as described herein, such as with reference to Figures 5 to 11 Any embodiment of the multi-level TIA with programmable clamping.

[0111] In some embodiments, the processor 1250 may be a hardware processor. In some embodiments, the processor 1250 may be a baseband digital signal processor. In some embodiments, the processor 1250 may determine the distance between the object and the laser ranging system 1200. In some embodiments, the processor 1250 may output a signal indicating the determined distance. In some embodiments, the processor 1250 may identify the object from which the pulse of light reflected from the object comes based at least in part on the width of the pulse generated by the TIA 1234. In some embodiments, the processor 1250 may output data identifying the object. In some embodiments, one instance of the processor 1250 may be associated with the receiver signal chain 1230 and another instance of the processor 1250 may be associated with the transmitter signal chain 1210.

[0112] The controller 1260 may be used to control various aspects of the system 1200, and in particular, aspects of the present disclosure relate to the multi-stage TIA with programmable clamps described herein. For example, the controller 1260 may generate control signals that control the operation of various elements of the multi-stage TIA with programmable clamps as described herein. In some embodiments, the controller 1260 may be implemented as Fig.13 The data processing system shown in .

[0113] Fig.13A block diagram is provided showing an exemplary data processing system 1300 according to some embodiments of the present disclosure that can be configured to implement or control at least a portion of an implementation of a multi-stage TIA with an adjustable input range implemented using programmable clamps. For example, in some embodiments, the data processing system 1300 can be configured to control the function of the control voltage VCLHI, as described herein. In some embodiments, the controller 1260 can be implemented as the data processing system 1300.

[0114] like Fig.13 As shown, data processing system 1300 may include at least one processor 1302 (e.g., hardware processor 1302), which is coupled to memory element 1304 via system bus 1306. In this way, the data processing system can store program code in memory element 1304. Further, processor 1302 can execute program code accessed from memory element 1304 via system bus 1306. In one aspect, the data processing system can be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that data processing system 1300 can be implemented in the form of any system including a processor and a memory that can perform the functions described in the present disclosure.

[0115] In some embodiments, the processor 1302 may execute software or algorithms to perform the activities discussed in this specification, particularly activities related to a multi-level TIA with programmable clamps as described herein. The processor 1302 may include any combination of hardware, software, or firmware that provides programmable logic, including as non-limiting examples a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application specific integrated circuit (IC) (ASIC), or a virtual machine processor. The processor 1302 may be communicatively coupled to a memory element 1304 (e.g., in a direct memory access (DMA) configuration) such that the processor 1302 may read from or write to the memory element 1304.

[0116] In general, memory element 1304 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual storage area, magnetic or tape storage, or any other suitable technology. Unless otherwise specified, any memory element discussed herein should be interpreted as being included in the broad term "memory". Information measured, processed, tracked, or sent to or from any component of data processing system 1300 can be provided in any database, register, control list, cache, or storage structure, all of which can be referenced in any suitable time frame. Any such storage option can be included in the broad term "memory" as used herein. Similarly, any potential processing element, module, and machine described herein should be interpreted as being included in the broad term "processor". Each of the elements shown in this figure (e.g., Figures 5 to 12 Any circuits / components shown in ) may also include appropriate interfaces for receiving, sending and / or otherwise transmitting data or information in a network environment so that they can communicate with, for example, the data processing system 1300 of another of these elements.

[0117] In certain exemplary embodiments, the mechanisms associated with a multi-level TIA with programmable clamps as outlined herein may be implemented by logic encoded in one or more tangible media (which may include non-transitory media) (e.g., embedded logic provided in an ASIC), logic in DSP instructions, software to be executed by a processor (which may include object code and source code), or other similar machine, etc. In some of these examples, a memory element (such as, for example, a memory element) may be implemented by a processor. Fig.13 The memory element 1304 shown in FIG. 1304 may store data or information used for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. The processor may execute any type of instructions associated with the data or information to implement the operations detailed herein. In one example, a processor (such as, for example, Fig.13The processor 1302 shown in the figure can transform an element or item (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPRPM), electrically erasable programmable read-only memory (EEPROM)), or ASIC including digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0118] Memory element 1304 can include one or more physical memory devices, such as, for example, local memory 1308 and one or more mass storage devices 1310. Local memory can refer to RAM or other non-permanent memory devices that are generally used during the actual execution of program code. Mass storage devices can be implemented as hard disk drives or other persistent data storage devices. Processing system 1300 can also include one or more cache memories (not shown), which provide temporary storage of at least some program codes to reduce the number of times that program codes must be retrieved from mass storage devices 1310 during execution.

[0119] like Fig.13 As shown, memory element 1304 may store application 1318. In various embodiments, application 1318 may be stored in local memory 1308, one or more mass storage devices 1310, or separate from local memory and mass storage devices. It should be understood that data processing system 1300 may further execute an operating system (OS) that may facilitate the execution of application 1318. Fig.13 13). Application 1318 implemented in the form of executable program code may be executed by data processing system 1300, for example, by processor 1302. In response to executing the application, data processing system 1300 may be configured to perform one or more operations or method steps described herein.

[0120] Input / output (I / O) devices, depicted as input devices 1312 and output devices 1314, may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, and the like. Examples of output devices may include, but are not limited to, a monitor or display, a speaker, and the like. In some embodiments, the output device 1314 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator (such as a dial, a barometer, or an LED). In some embodiments, the system may include a driver (not shown) for the output device 1314. The input and / or output devices 1312, 1314 may be coupled to the data processing system directly or through an intervening I / O controller.

[0121] In one embodiment, the input and output devices may be implemented as a combined input / output device (in Fig.13 1312 and output device 1314). An example of such a combined device is a touch-sensitive display, sometimes referred to as a "touch screen display" or simply a "touch screen." In such an embodiment, input to the device can be provided by movement of a physical object (such as, for example, a stylus or finger of a user) on or near the touch screen display.

[0122] Optionally, network adapter 1316 may also be coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and / or remote storage devices through an intermediate private or public network. The network adapter may include a data receiver for receiving data sent by the system, device, and / or network to the data processing system 1300, and a data transmitter for sending data from the data processing system 1300 to the system, device, and / or network. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with data processing system 1300.

[0123] Fig.14 An illustration 1400 of a LIDAR system integrated with an automobile according to some embodiments of the present disclosure is provided. This is an exemplary application in which any of the multi-stage TIAs with adjustable input ranges implemented using programmable clamps as described herein may be implemented. Fig.14Two LIDAR systems 1402 and 1404 are shown integrated with a car 1406. The first LIDAR system 1402 can be positioned near the right headlight of the car 1406, while the second LIDAR system 1404 can be positioned near the left headlight of the car 1406. As described herein, the LIDAR systems 1402 and / or 1404 can implement any suitable principles of a multi-level TIA with programmable clamps. The LIDAR systems 1402 and / or 1404 can detect the distance between the car 1406 and the object 1408.

[0124] As shown, a transmitter of LIDAR system 1402 may emit pulses of light 1410 at angle 1412. At least some of the pulses of light 1410 may be emitted by a laser diode (e.g., Fig.12 1402). Transmitted light 1410 may travel through the air and reach object 1408. Object 1408 may reflect pulses of light 1414 back to a receiver of LIDAR system 1402. The embodiments discussed herein may generate information for identifying object 1408. Pulses of light 1410 may be emitted three-dimensionally to obtain three-dimensional information of the surrounding environment.

[0125] One or more additional LIDAR systems can be integrated with the car 1406 to cover a larger detection area and / or obtain additional information about a selected area. In some embodiments, the data collected by each LIDAR system can be combined to analyze information from a larger area and / or provide additional information about a selected area. In some embodiments, the angle 1412 can be adjusted and can be within any suitable range.

[0126] Figures 5 to 11 The illustrations of FIG. 5 provide only some non-limiting examples in which various embodiments of a multi-stage TIA with an adjustable input range as described herein, such as TIA 504, may be used. In other embodiments, TIA 504 may be used in addition to Figure 5The invention can be implemented in systems other than the LIDAR system shown (i.e., the input current IIN provided to the TIA 504 can be any input current provided from any other source and not necessarily from the optical sensor 102). The various teachings related to the multi-level TIA with an adjustable input range as described herein are applicable to a variety of other systems. In some cases, the various embodiments of the multi-level TIA with an adjustable input range as described herein can be used for automotive systems, safety-critical industrial applications, medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instruments (which can be highly accurate), and various digital processing-based systems. In other cases, the various embodiments of the multi-level TIA with an adjustable input range as described herein can be used in industrial markets including process control systems that help improve productivity, energy efficiency, and reliability. In further cases, the various embodiments of the multi-level TIA with an adjustable input range can be used for consumer applications.

[0127] Select Example

[0128] The following paragraphs provide examples of various of the embodiments disclosed herein.

[0129] Example A1 provides a multi-stage TIA including a high-side clamp associated with a first stage.

[0130] Example A2 provides a multi-level TIA according to Example A1, wherein the TIA includes Figure 5 The coupling between components is shown.

[0131] Example A3 provides a multi-level TIA according to Example A1, wherein the TIA includes Figure 8 The coupling between components is shown.

[0132] Example A4 provides an electronic component including a multi-level TIA according to any of the preceding Examples A.

[0133] Example A5 provides the electronic component according to Example A4, wherein the electronic component is a TIA or an ADC driver.

[0134] Example A6 provides an electronic component according to Example A4, wherein the electronic component is a LIDAR receiver.

[0135] Example B1 provides a system (such as a TIA) configured to convert a single-ended current input into a differential voltage output. The system includes: a first amplifier circuit (e.g., amplifier A0 described herein) having an output for providing a first amplifier output generated by the first amplifier circuit based on the single-ended current input; an output offset current generating circuit (e.g., amplifier A1 described herein) configured to generate an output offset current; a second amplifier circuit (e.g., amplifier A2 described herein) having a differential input including a first input and a second input, and configured to generate a differential voltage output based on the following operations: receiving a signal based on the first amplifier output at a first input of the differential input of the second amplifier circuit (e.g., at a negative input IN-), and receiving a signal based on the output offset current at a second input of the differential input of the second amplifier circuit (e.g., at a positive input IN+). The system further includes: a clamp circuit coupled to the output of the first amplifier circuit and further coupled to a control signal configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output based on the output offset current generated by the output offset current generating circuit.

[0136] In such a system, the clamp circuit is configured to clamp the first amplifier output based on a control signal provided to the clamp circuit to ensure that the first amplifier output does not drop below a minimum voltage or exceed a maximum voltage set by the control signal. The clamped version of the first amplifier output is then provided to a first input of a differential input of a second amplifier circuit. Because the second input of the differential input of the second amplifier circuit receives a signal based on the output offset current, and because the first input of the differential input of the second amplifier circuit receives a clamped version of the first amplifier output in which the clamping depends on a control signal that is also based on the output offset current, the system can advantageously ensure that the differential input of the second amplifier circuit is not overloaded.

[0137] Example B2 provides a system according to Example B1, wherein the first amplifier circuit includes a first transistor (e.g., Figure 8 or Fig. 9 ) and a second transistor (eg, Figure 8 or Fig. 9 The transistor Q2 shown in FIG. 1 ) and the clamping circuit includes a third transistor (eg, Figure 8 or Fig. 9In a further example of the system according to example B2, each of the first transistor, the second transistor, and the third transistor includes a first terminal, a second terminal, and a third terminal, wherein the first terminal of the third transistor is coupled to the third terminal of the second transistor, the first terminal of the second transistor is coupled to the output of the first amplifier circuit, the first amplifier circuit is configured to receive a single-ended current input at the third terminal of the first transistor, and the second terminal of the first transistor is coupled to the third terminal of the second transistor.

[0138] Example B3 provides a system according to Example B2, wherein the control voltage signal sets a maximum voltage value, each of the first transistor and the second transistor is an N-type transistor, and the third transistor is a P-type transistor. In a further example of the system according to Example B3, the second terminal of the third transistor and the first terminal of the first transistor can be coupled to a negative power supply (e.g., Vee for a bipolar transistor implementation, or VSS for a FET implementation), and the second terminal of the second transistor can be coupled to a positive power supply (e.g., Vcc for a bipolar transistor implementation, or VDD for a FET implementation).

[0139] Example B4 provides a system according to Example B3, wherein the control signal is based on a positive supply voltage (eg, voltage Vcc for a bipolar transistor implementation or voltage VDD for a FET implementation) of the first amplifier circuit and the clamp circuit.

[0140] Example B5 provides a system according to Example B2, wherein the control voltage signal sets a minimum voltage value, each of the first transistor and the second transistor is a P-type transistor, and the third transistor is an N-type transistor. In a further example of the system according to Example B5, the second terminal of the third transistor and the first terminal of the first transistor can be coupled to a positive power supply (e.g., Vcc for a bipolar transistor implementation, or VDD for a FET implementation), and the second terminal of the second transistor can be coupled to a negative power supply (e.g., Vee for a bipolar transistor implementation, or VSS for a FET implementation).

[0141] Example B6 provides a system according to Example B5, wherein the control signal is based on a negative supply voltage (eg, voltage Vee for a bipolar transistor implementation or voltage VSS for a FET implementation) of the first amplifier circuit and the clamp circuit.

[0142] Example B7 provides a system according to any of Examples B2 to B6, wherein the control signal is configured to be further based on a voltage difference between the first terminal and the third terminal of the first transistor (e.g., in the case where Q1 is a bipolar transistor, based on the voltage V BE,Q1) to set one of the minimum voltage value or the maximum voltage value of the first amplifier output. In other example B, the control signal is configured to be further based on V depending on Vee min,A0 To set one of the minimum voltage value or the maximum voltage value output by the first amplifier.

[0143] Example B8 provides a system according to any of Examples B2 to B7, wherein the control signal is configured to be further based on a voltage difference between the first terminal and the third terminal of the second transistor (e.g., in the case where Q2 is a bipolar transistor, based on the voltage V BE,Q2 ) to set one of the minimum voltage value or the maximum voltage value of the first amplifier output. In other example B, the control signal is configured to be further based on V depending on Vcc max,A0 To set one of the minimum voltage value or the maximum voltage value output by the first amplifier.

[0144] Example B9 provides a system according to any one of Examples B2 to B8, wherein the control signal is configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output further based on a resistance of a feedback component (e.g., resistance RT across amplifier A0), the feedback component having a first terminal coupled to a third terminal of the first transistor (i.e., coupled to an input of the first amplifier circuit) and having a second terminal coupled to a third terminal of the second transistor (i.e., coupled to an output of the first amplifier circuit).

[0145] Example B10 provides a system according to any one of Examples B2 to B9, wherein for any of the first transistor, the second transistor, and the third transistor that are bipolar transistors, the first terminal is an emitter terminal, the second terminal is a collector terminal, and the third terminal is a base terminal.

[0146] Example B11 provides a system according to any one of Examples B2 to B10, wherein for any of the first transistor, the second transistor, and the third transistor that are field effect transistors (FETs), the first terminal is a source terminal, the second terminal is a drain terminal, and the third terminal is a gate terminal.

[0147] Example B12 provides the system according to any of Examples B1 to B11, wherein the control signal is a control voltage signal.

[0148] Example B13 provides the system according to any of Examples B1 to B11, wherein the control signal is a control current signal.

[0149] Example B14 provides a system according to any of the preceding Examples B, wherein the system is a driver for an analog-to-digital converter.

[0150] In further example B, the system according to any of the preceding examples B may be a LIDAR system.

[0151] Example B15 provides a system (such as a TIA) configured to convert a single-ended current input into a differential voltage output, the system comprising: a first stage configured to receive a single-ended current input and to generate a single-ended output based on the single-ended current input; a clamping circuit configured to generate a clamped single-ended output by clamping the single-ended output when one of the following is true: 1) if / when the single-ended output exceeds a maximum voltage value (if the single-ended output does not exceed the maximum voltage value, the clamped single-ended output is the same as the single-ended output generated by the first stage), wherein the maximum voltage value is based on an output offset current, or 2) if / when the single-ended output drops below a minimum voltage value (if the single-ended output does not drop below the minimum voltage value, the clamped single-ended output is the same as the single-ended output generated by the first stage), wherein the minimum voltage value is based on the output offset current. The system further includes a second stage configured to receive a signal based on the clamped single-ended output as a first input of a differential input of the second stage, receive a signal based on the output offset current as a second input of the differential input of the second stage, and generate a differential voltage output based on the differential input.

[0152] Example B16 provides the system according to Example B15, wherein each of the single-ended output, the clamped single-ended output, and the signal based on the output offset current is a voltage signal.

[0153] Example B17 provides a system according to Example B15 or B16, wherein the first stage includes: an amplifier having an input for receiving a single-ended current input and having an output for providing a single-ended output; and a feedback resistor having a first terminal coupled to the input of the amplifier and having a second terminal coupled to the output of the amplifier.

[0154] Example B18 provides the system according to any of Examples B15 to B17, further including a circuit configured to generate an output offset current.

[0155] Example B19 provides a system according to Example B18, wherein the circuit is coupled to a control voltage, and the circuit is a voltage-to-current converter configured to generate an output offset current based on the control voltage.

[0156] Example B20 provides a system configured to convert a single-ended signal into a differential signal, the system including an amplifier and a clamp circuit, wherein the amplifier has a differential input and a differential output, a first input of the differential input of the amplifier is configured to receive a signal based on a single-ended signal that has been clamped by the clamp circuit based on a clamp control signal, wherein the clamp control signal is based on an output offset current, a second input of the differential input of the amplifier is configured to receive a signal based on the output offset current, and the amplifier is configured to generate a differential signal based on the signal received at the differential input of the amplifier.

[0157] Example B21 provides a system according to example B20, wherein the system further includes features according to one or more of examples B1 to B19.

[0158] Example B22 provides a system according to Example B20 or B21, wherein the system is a driver for an ADC or LIDAR system.

[0159] Example B23 provides a method comprising steps performed by a system or device according to any of the preceding examples.

[0160] Example B24 provides a method comprising the steps of causing the system to operate according to any of the preceding examples.

[0161] Example B25 provides a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform at least a portion of a method according to any of Examples B23 and B24.

[0162] Example B26 provides a computer program product comprising instructions that, when executed by a processor, cause the processor to perform at least a portion of a method according to any of Examples B23 and B24.

[0163] Other Embodiments, Modifications and Applications

[0164] The principles and advantages discussed herein can be used in any device where it is necessary to limit the output of the TIA. For example, various aspects of the present disclosure can be implemented in various ranging systems. For example, various aspects of the present disclosure can be implemented in any suitable LIDAR system (such as, for example, automotive LIDAR, industrial LIDAR, space LIDAR, military LIDAR, etc.). The LIDAR system may include a receiver or a transmitter and a receiver. The LIDAR system may be integrated with a vehicle such as a car, an unmanned aircraft such as an unmanned aerial vehicle, an autonomous robot, or a space vehicle. The LIDAR system may emit and / or receive lasers. The LIDAR system may be used for three-dimensional sensing applications. The LIDAR system may be used with augmented reality technology. In addition, various aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, electronic products, components of electronic products (such as integrated circuits), vehicle electronic devices (such as automotive electronic devices), etc. Further, the electronic device may include an unfinished product.

[0165] Although certain embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the present disclosure. For example, although some embodiments relate to an APD coupled to an input port of a TIA, these embodiments are equally applicable to any other device that can generate current pulses to provide an input to a TIA (e.g., to any other type of PD). In another example, although some embodiments may relate to a PD that absorbs current from a TIA, these embodiments may be modified to a PD that provides current to a TIA in a manner that is obvious to a person of ordinary skill in the art, and therefore, all of these embodiments are within the scope of the present disclosure. In fact, the novel methods, devices, and systems described herein related to a multi-level TIA with programmable clamps may be implemented in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the methods, devices, and systems described herein without departing from the spirit of the present disclosure. For example, the circuit blocks and / or circuit elements described herein may be deleted, moved, added, subdivided, combined, and / or modified. Each of these circuit blocks and / or circuit elements may be implemented in various different ways. The accompanying claims and their equivalents are intended to cover any such forms or modifications as would fall within the scope and spirit of the disclosure.

[0166] Any principles and advantages discussed herein may be applied to other systems, devices, integrated circuits, electronic devices, methods, and not just to the above-described embodiments. The elements and operations of the various embodiments described above may be combined to provide further embodiments. The principles and advantages of the embodiments may be used in conjunction with any other system, device, integrated circuit, equipment, or method that may benefit from any teaching herein.

[0167] It should be understood that not all objects or advantages may be achieved according to any particular embodiment described herein. Thus, for example, those skilled in the art will recognize that certain embodiments may be configured to operate in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as taught or suggested herein.

[0168] In an exemplary embodiment, any number of circuits in the figure can be implemented on the board of the associated electronic device. The board can be a general circuit board that can accommodate various components of the internal electronic system of the electronic device, and further provide connectors for other peripheral devices. More specifically, the board can provide an electrical connection through which other components of the system can communicate electrically. Any suitable processor (including a digital signal processor, a microprocessor, a support chipset, etc.), a computer-readable non-transient memory element, etc. can be appropriately coupled to the board based on specific configuration needs, processing requirements, computer design, etc. Other components (such as external storage bodies, controllers for configuring any components, and peripheral devices) can be attached to the board via a cable as a plug-in card, or integrated into the board itself. In various embodiments, the functions described herein can be implemented in the form of simulation into software or firmware running in one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. The software or firmware providing simulation can be provided on a non-transient computer-readable storage medium containing instructions that allow the processor to perform those functions.

[0169] In another exemplary embodiment, the circuits described herein may be implemented as stand-alone modules (e.g., devices having associated components and circuit systems configured to perform specific applications or functions), or as plug-in modules into dedicated hardware for electronic devices. Note that specific embodiments of the present disclosure may be easily included in part or in whole in a system-on-chip (SOC) package. SOC represents an IC that integrates the components of a computer or other electronic system into a single chip. It may contain digital functions, analog functions, mixed signal functions, and typically radio frequency functions: all of which can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package. In various other embodiments, the circuits described herein may be implemented in one or more silicon cores in an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and other semiconductor chips.

[0170] It must also be noted that all specifications, dimensions, and relationships (e.g., number of processors, logical operations, etc.) outlined herein are provided for purposes of example and instruction only. Such information may vary considerably without departing from the spirit of the present disclosure or the scope of the appended claims. The description applies only to one non-limiting example, and therefore, they should be interpreted as such. In the foregoing description, exemplary embodiments have been described with reference to a specific arrangement of components. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. Therefore, the description and drawings are to be considered illustrative, rather than restrictive.

[0171] Note that in the numerous examples provided herein, two, three, four or more electronic components may be used to describe the interaction. However, this is done only for the purpose of clarity and example. It should be understood that the system can be integrated in any suitable manner. Along similar design alternatives, any components, modules and elements shown in the figures can be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given set of processes by only referencing a limited number of electrical components. It should be understood that the circuits in the figures and their teachings are easily expandable and can accommodate a large number of components, as well as more complex / complex arrangements and configurations. Therefore, the examples provided should not limit the scope or inhibit the broad teachings of the circuits, as they may be applied to countless other architectures.

[0172] Note that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “exemplary embodiment,” “an embodiment,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to mean that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0173] Numerous other changes, substitutions, variations, alterations, and modifications may be determined by those skilled in the art, and it is intended that the present disclosure encompasses all such changes, substitutions, variations, alterations, and modifications that fall within the scope of the appended selected examples. Note that all optional features of the above-described apparatus may also be implemented with respect to the methods or processes described herein, and that the details in the examples may be used anywhere in one or more embodiments.

Claims

1. A method of operating a system, the system comprising a first amplifier circuit, a second amplifier circuit, a third amplifier circuit and a clamp circuit, the method comprising: operating a first amplifier circuit to generate a first amplifier output based on a single-ended current input; providing a signal based on the output offset current to each of an input of the second amplifier circuit and an input of the clamp circuit; operating the second amplifier circuit to produce a second amplifier output based on the output offset current; operating a clamp circuit coupled to an output of the first amplifier circuit and to a control signal to set one of a minimum voltage value or a maximum voltage value of the first amplifier output based on a signal provided to an input of the clamp circuit; as well as The third amplifier circuit is operated to generate a differential output based on a signal based on the second amplifier output and a signal based on the first amplifier output, the first amplifier output following the minimum voltage value or the maximum voltage value set by the clamp circuit for the first amplifier output.

2. The method according to claim 1, wherein: The first amplifier circuit includes a first transistor and a second transistor, The clamping circuit includes a third transistor, Each of the first transistor, the second transistor, and the third transistor includes a first terminal, a second terminal, and a third terminal, the first terminal of the third transistor being coupled to the third terminal of the second transistor, the first terminal of the second transistor being coupled to the output of the first amplifier circuit, The first amplifier circuit is configured to receive the single-ended current input at the third terminal of the first transistor, and The second terminal of the first transistor is coupled to the third terminal of the second transistor.

3. The method according to claim 1, wherein The first amplifier circuit includes a first transistor and a second transistor, The clamping circuit includes a third transistor, The control signal is used to set the maximum voltage value, Each of the first transistor and the second transistor is an N-type transistor, and The third transistor is a P-type transistor.

4. The method of claim 3, wherein the control signal is based on a positive supply voltage of the first amplifier circuit and the clamp circuit.

5. The method according to claim 1, wherein The first amplifier circuit includes a first transistor and a second transistor, The clamping circuit includes a third transistor, The control signal is used to set the minimum voltage value, Each of the first transistor and the second transistor is a P-type transistor, and The third transistor is an N-type transistor.

6. The method of claim 5, wherein the control signal is based on a negative supply voltage of the first amplifier circuit and the clamp circuit.

7. The method according to claim 1, wherein The first amplifier circuit includes a transistor, and The control signal is used to set one of a minimum voltage value or a maximum voltage value output by the first amplifier further based on: When the transistor is a bipolar junction transistor, the voltage difference between the emitter terminal and the base terminal of the transistor, or When the transistor is a field effect transistor, the voltage difference between the source terminal and the gate terminal of the transistor.

8. The method according to claim 2, wherein The system further includes a feedback component having a first terminal coupled to the third terminal of the first transistor and having a second terminal coupled to the first terminal of the second transistor, and The control signal is used to set one of the minimum voltage value or the maximum voltage value output by the first amplifier further based on the resistance of the feedback component.

9. A system for generating a differential output based on a signal input, comprising: a first amplifier circuit that generates an output based on a signal input; a clamping circuit that clamps the output of the first amplifier circuit based on the magnitude of the output of the first amplifier circuit and further based on an offset current; a second amplifier circuit that generates an output based on the offset current, the second amplifier circuit being a replica of the first amplifier circuit; as well as A third amplifier circuit generates the differential output based on: receiving at a first input of the third amplifier circuit a signal based on an output produced by the first amplifier circuit and clamped by the clamp circuit, and A signal based on an output produced by the second amplifier circuit is received at a second input of the third amplifier circuit.

10. The system of claim 9, wherein The first amplifier circuit includes a first transistor and a second transistor, The clamping circuit includes a third transistor coupled to a control signal to clamp the output of the first amplifier circuit to a minimum voltage value or a maximum voltage value, When the control signal is used to clamp the output of the first amplifier circuit to the maximum voltage value, each of the first transistor and the second transistor is an N-type transistor, and the third transistor is a P-type transistor, and When the control signal is used to clamp the output of the first amplifier circuit to the minimum voltage value, each of the first transistor and the second transistor is a P-type transistor, and the third transistor is an N-type transistor.

11. The system of claim 9, wherein the system is a driver for an analog-to-digital converter.

12. The system of claim 9, wherein the system is a Light Detection and Ranging (LIDAR) system.

Images