Data generation circuit for high-speed transmitter

Abstract

The invention relates to the technical field of integrated circuits, and discloses a data generation circuit for a high-speed transmitter. The circuit adopts a two-stage structural design, a first-stage circuit unit generates a narrow pulse signal through cooperation of an input tube, a pre-discharge control tube, a reset control tube and a pre-charge control tube, and a second-stage circuit unit converts a non-full-swing pulse signal into a full-swing signal through a pull-down tube and a plurality of pull-up tubes and outputs the full-swing signal. According to the invention, stable and reliable signal generation and shaping in an ultra-high-speed scene with a unit time interval less than or equal to 10 picoseconds are realized, and the device is suitable for a high-speed transmitter with a 1 / 4 rate or a 1 / 8 rate, and has the characteristics of simple structure and accurate time sequence.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a data generating circuit for an ultra-high-speed transmitter. Background Art

[0002] With the rapid development of communication technology, data transmission rates are constantly increasing, and modern high-speed communication systems have put forward higher and higher requirements for signal quality and transmission reliability. In ultra-high-speed transmitters, 1 / 4 or 1 / 8 rate structures are widely used. The core idea is to use multi-phase clock signals to synthesize multiple low-speed data into full-rate data for transmission. Although this architecture reduces the transmission rate requirements for single-channel data, it still faces severe technical challenges in the data synthesis link.

[0003] Especially with the trend of increasing data transmission rates, the unit time interval (1-UI) has been shortened to the order of 10 picoseconds. In such a short period of time, it is difficult for traditional data generation circuits to achieve complete charging and discharging of MOS tubes, which directly affects the signal quality and system reliability. The data generation circuit in the prior art usually adopts a simple charging and discharging structure, which is prone to problems such as insufficient signal amplitude, blunt edges, and inaccurate timing in ultra-high-speed scenarios. In addition, due to the lack of an effective pre-charge and discharge mechanism, the response speed of the circuit is difficult to meet the requirements of ultra-high-speed transmission.

[0004] Another prominent issue is the signal swing control. In ultra-high-speed scenarios, due to the extremely limited charging and discharging time, the generated signal often cannot reach the ideal full swing (0 to VDD), which not only reduces the noise margin of the signal, but also increases the difficulty of judgment at the receiving end. The existing signal shaping circuit has a complex structure and cumbersome control logic, making it difficult to complete effective signal shaping in an ultra-short time.

[0005] At the same time, in high-speed transmitters driven by multi-phase clocks, precise timing control between various signals is also a key issue. Traditional circuit structures make it difficult to ensure accurate synchronization between narrow pulse signals and control signals, which can easily lead to signal distortion and data transmission errors. Especially in the coordination process of multiple links such as pre-charging, pre-discharging and signal shaping, how to ensure precise control of each timing node has always been a problem that has plagued the industry.

[0006] Therefore, there is an urgent need for a new type of data generation circuit that can achieve reliable signal generation and shaping in an ultra-short unit time interval, and has the characteristics of simple structure, precise timing, and easy implementation. This circuit should be able to solve the charging and discharging efficiency problem in ultra-high-speed scenarios, ensure the full swing characteristics of the output signal, and ensure accurate signal transmission through a reasonable timing control mechanism, so as to meet the increasingly improved performance requirements of modern high-speed communication systems. Summary of the invention

[0007] The purpose of the present application is to provide a data generating circuit for a high-speed transmitter to solve the problems raised in the above background technology.

[0008] The present application discloses a data generating circuit for a high-speed transmitter, comprising a first-stage circuit unit and a second-stage circuit unit, wherein:

[0009] The first-stage circuit unit is used to generate a narrow pulse signal, including:

[0010] Input tube (M1), the gate is used to receive input data signals;

[0011] A pre-discharge control tube (M2), whose source is connected to the drain of the input tube (M1) to form a first intermediate node, and whose gate is used to receive an A-phase clock signal;

[0012] A reset control tube (M3), a drain of which is connected to the drain of the pre-discharge control tube (M2) to form an output node, and a gate of which is used to receive the A-phase clock signal;

[0013] A pre-charge control tube (M4), the drain of which is connected to the output node, the source of which is used to receive the power supply voltage, and the gate of which is used to receive the B-phase clock signal; wherein the B-phase clock signal has a predetermined time delay compared with the A-phase clock signal; the pre-discharge control tube (M2) and the pre-charge control tube (M4) respond to the A-phase clock signal and the B-phase clock signal to sequentially complete pre-charging and pre-discharging of the output node to generate a pulse signal;

[0014] The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including:

[0015] A pull-down tube (M5) is connected between the final output node and the lowest potential, and its control terminal is used to receive a reset signal;

[0016] A plurality of pull-up tubes (M6, M7) have drains and sources respectively connected between the final output node and the power supply voltage, and a control end is used to receive a pulse signal output by the first-stage circuit unit; the pull-down tube (M5) cooperates with the pull-up tubes (M6, M7) to convert a non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

[0017] In a preferred example, the time width of the narrow pulse signal is 1-UI, wherein UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

[0018] In a preferred example, the A-phase clock signal and the B-phase clock signal are two phases in the same group of multi-phase clock signals, wherein the multi-phase clock signal includes at least 4-phase clock signals, and the time interval between the rising edges of each adjacent two-phase clock signal is 1-UI; wherein the B-phase clock signal is 3-UI ahead of the A-phase clock signal.

[0019] In a preferred example, the gate of the input tube (M1) is connected to the input end to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control tube (M2) to form a first intermediate node (Data_int).

[0020] In a preferred example, the working process of the first-stage circuit unit includes: (1) before the rising edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on to pre-charge the output node (Dout_int) to the power supply voltage; before the rising edge of the A-phase clock signal arrives and after the falling edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned on, and the output node (Dout_int) is pre-charged and maintained at the power supply voltage; (2) when the rising edge of the A-phase clock signal arrives, the pre-discharge control tube (M2) is turned on to discharge the output node to a preset level; (3) when the rising edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned off, and the output node is further discharged to the lowest potential; (4) when the falling edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on, the pre-discharge control tube (M2) is turned off, and the output node is reset and charged to the power supply voltage.

[0021] In a preferred example, it also includes at least one group of reset signal generating circuits, which are used to generate a reset signal synchronized with the pulse signal according to the multi-phase clock signal, and the reset signal generating circuit includes: a first AND gate, whose input ends are respectively connected to the second clock signal and the fourth clock signal, and are used to perform an AND operation on the two; a second AND gate, whose input ends are respectively connected to the sixth clock signal and the eighth clock signal, and are used to perform an AND operation on the two; an OR-NON gate, whose input ends are respectively connected to the output ends of the first AND gate and the second AND gate, and are used to perform an OR-NON operation on the output signals of the two, and whose output end is used to output the reset signal.

[0022] In a preferred example, the reset signal generating circuit receives an 8-phase clock signal as an input signal, and the time interval between rising edges of every two adjacent clock signals is 1-UI.

[0023] In a preferred embodiment, the working process of the second-stage circuit unit includes:

[0024] When the reset signal is at a high level and the pulse signal output by the first-stage circuit unit is at a high level, the pull-down tube (M5) is turned on to discharge the final output node to the zero potential;

[0025] When the reset signal is at a low level and the pulse signal output by the first-stage circuit unit is at a low level, the plurality of pull-up tubes (M6, M7) are alternately turned on to charge the final output node to the power supply voltage.

[0026] In a preferred example, the data generating circuit is used for a high-speed transmitter with a 1 / 4 rate or a 1 / 8 rate.

[0027] The implementation methods of this application have the following technical effects:

[0028] The data generation circuit proposed in this application adopts a two-stage structural design, which successfully solves the key problems of signal generation and shaping in ultra-high-speed scenarios. The first-stage circuit realizes the efficient generation of narrow pulse signals through the ingenious cooperation of the input tube (M1), the pre-discharge control tube (M2), the reset control tube (M3) and the pre-charge control tube (M4). Especially in the extremely short 1-UI with a time interval of less than or equal to 10 picoseconds, the reliable generation of the signal is ensured through multiple precisely controlled stages such as pre-charge and pre-discharge. The second-stage circuit converts the non-full-swing pulse signal into a full-swing signal through the coordinated work of the pull-down tube (M5) and multiple pull-up tubes (M6, M7), significantly improving the signal quality.

[0029] In terms of timing control, the present application utilizes the delay relationship between the A-phase clock signal and the B-phase clock signal, and cooperates with the synchronous RST signal output by the reset signal generating circuit to achieve precise timing coordination. Among them, for the 1 / 8 rate structure, the A-phase and B-phase clock signals differ by 3-UI; for the 1 / 4 rate structure, the A-phase and B-phase clock signals differ by 1-UI. Specifically, in the first-stage circuit, the pre-charge control tube and the pre-discharge control tube work alternately to complete the signal pre-charge, pre-discharge, full discharge and reset charge process. This carefully designed timing arrangement ensures that all necessary signal processing steps are completed in an ultra-short time.

[0030] It is worth noting that the reset signal generating circuit of the present application generates a reset signal synchronized with the 1-UI pulse by using a specific phase combination in a multi-phase clock signal through a simple combination of two AND gates and one NOR gate. It should be pointed out that the specific number of groups and clock combinations of the reset signal generating circuit will vary depending on the rate adopted by the transmitter.

[0031] Taking the 1 / 8 rate transmitter as an example, since an 8-phase clock (CK1 / CK2 / … / CK7 / CK8) is used, four sets of reset signals are required. In addition to the CK2 / CK4 / CK6 / CK8 set mentioned above, the generation logic of the other three sets of reset signals are:

[0032] The second group: CK2 and CK8 are ANDed, CK4 and CK6 are ANDed, and then the two ANDed results are ORed.

[0033] The third group: perform AND operation on CK3 and CK5, perform AND operation on CK1 and CK7, and then perform NOR operation on the two AND operation results.

[0034] The fourth group: CK5 and CK7 are ANDed, CK1 and CK3 are ANDed, and then the two ANDed results are ORed.

[0035] Each reset signal group consists of two AND gates and one NOR gate, but the input clock combination is different. The four reset signals are staggered 1-UI in time and synchronized with the corresponding 1-UI data pulses, thus achieving precise timing control.

[0036] For a 1 / 4 rate transmitter, since a 4-phase clock is used, only two sets of reset signals are needed. Their generation logic can refer to the 1 / 8 rate case and select the appropriate clock combination.

[0037] The introduction of multiple sets of reset signals is an important innovation of the present application in timing control. By using different clock combinations, the phases of the reset signals of each group are cleverly staggered to avoid signal conflicts, while ensuring that each 1-UI data pulse can be reset synchronously. This design not only simplifies the circuit structure, but also greatly improves the reliability of the system. In ultra-high-speed scenarios, this solution of multiple sets of reset signals undoubtedly provides greater flexibility and adaptability for the implementation of data generation circuits.

[0038] In summary, the above reset signal generation scheme fully demonstrates the innovative ideas of this application in timing optimization. By designing multiple sets of reset signals according to local conditions, the key timing problems in ultra-high-speed data transmission are effectively solved. This design, together with the 1-UI pulse generation circuit and the full-swing conversion circuit, constitutes a complete technical solution of this application, which has strong feasibility and practical value.

[0039] This design not only simplifies the circuit structure, but also ensures the accuracy of signal shaping. Especially in the second-stage circuit, the RST signal cooperates with the pulse signal to control the conduction state of the pull-down tube and the pull-up tube, achieving a stable full-swing signal output.

[0040] In general, this application is applicable to high-speed transmitters at 1 / 4 rate or 1 / 8 rate, and realizes complex signal processing functions through a simple circuit structure. The working processes of all MOS tubes in the circuit are closely coordinated and echo each other, which ensures the signal quality while also ensuring the reliable operation of the circuit. This design not only solves the signal processing problem in ultra-high-speed scenarios, but also has strong engineering practicality, providing important technical support for the development of high-speed communication systems.

[0041] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a timing diagram of the generation of 1-UI data and RST signal according to an embodiment of the present application.

[0043] Figure 2 1-UI data generation circuit diagram according to an embodiment of the present application, wherein: Figure 2 (a) is a schematic diagram of the structure of a 1-UI data circuit, as an example of a plurality of 1-UI data generating circuits (a 1 / 8 rate transmitter requires 8 such 1-UI data generating circuits, and a 1 / 4 rate transmitter requires 4 such 1-UI data generating circuits); Figure 2 (b) is a schematic diagram of the voltage waveform of the key node; Figure 2 (c) Node voltage timing diagram, showing the detailed change process of the Dout_int node voltage under the control of the clock signals CK1 and CK6 and the corresponding relationship between the two.

[0044] Figure 3 1-UI data full swing circuit diagram according to an embodiment of the present application, wherein: Figure 3 (a) is a schematic diagram of the structure of the full-swing conversion circuit; Figure 3 (b) is a schematic diagram of the structure of the RST signal generating circuit, which is an example of one of the multiple reset signal generating circuits; Figure 3 (c) is a schematic diagram of the voltage waveform of the key node. DETAILED DESCRIPTION

[0045] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0046] Description of some concepts:

[0047] Unit Interval (UI) represents the time length of a data bit in digital communication systems. 1-UI in this application refers to the minimum time unit required for the transmission of a single data bit, which can be as small as 10 picoseconds in ultra-high-speed scenarios. This basic time unit plays a key role in signal generation and processing.

[0048] A full swing signal is a signal whose voltage swings completely between the power supply voltage (VDD) and the ground (0V). Compared with a non-full swing signal, a full swing signal has a larger noise margin and better signal integrity, which is critical to ensuring the reliability of data transmission.

[0049] Pre-charge is the process of pre-charging the output node to the power supply voltage VDD before formal data transmission. In this application, this process is achieved by turning on the M4 tube to make necessary preparations for subsequent signal generation. The introduction of pre-charge significantly improves the response speed of the circuit.

[0050] Pre-discharge is the process of pre-discharging the node voltage to a specific level (Vout_precharge) before full discharge. This process is controlled by the M2 tube and is one of the key steps in realizing high-speed signal generation in this application, laying the foundation for obtaining an ideal signal waveform.

[0051] 1 / 4 rate and 1 / 8 rate are working modes in which the maximum clock frequency of the transmitter is 1 / 4 or 1 / 8 of the full rate respectively. This structure is widely used in high-speed transmitters. It combines multiple low-speed data into full-rate data through multi-phase clocks, effectively reducing the transmission rate requirements of single-channel data.

[0052] Multi-phase clock refers to a group of clock signals with a fixed phase difference. This application uses 8 phase clocks (CK1-CK8), where the phase difference between adjacent clock signals is 1-UI. The precise coordination of this group of clock signals is the basis for achieving high-speed data transmission.

[0053] Multi-phase clock refers to a group of clock signals with a fixed phase difference. This application uses different numbers of phase clocks according to the rate requirements of the transmitter: for a 1 / 8 rate transmitter, 8 phase clocks (CK1-CK8) are used; for a 1 / 4 rate transmitter, 4 phase clocks (CK1-CK4) are used. In both cases, the phase difference between adjacent clock signals is 1-UI. The precise coordination of these clock signals is the basis for achieving high-speed data transmission.

[0054] The RST signal (Reset Signal) is a reset control signal used to control signal shaping. It is synchronized with the 1-UI pulse and controls the key working timing in the full-swing conversion circuit to ensure the accuracy of signal shaping.

[0055] Reset Charge is the process of restoring the output node voltage to the initial level. This process is achieved by turning on the M3 tube, making full preparations for the signal generation of the next cycle and ensuring the continuous and stable operation of the circuit.

[0056] Pull-up / Pull-down Transistors are MOS transistors used to pull the node voltage up to VDD or down to ground. In the full-swing conversion circuit of the present application, M5 is used as a pull-down transistor and M6 / M7 is used as a pull-up transistor. Their coordinated work realizes the full-swing conversion of the signal.

[0057] A non-full swing pulse is a pulse signal whose voltage swing does not reach 0 to VDD. This signal is an original signal that needs to be shaped, and can be converted into an ideal full swing signal after being processed by the present application, thereby improving the reliability of the system.

[0058] The following is a brief description of some of the innovative features of this application:

[0059] In general, the present application relates to a 1-UI data generation circuit for an ultra-high-speed transmitter. In the field of ultra-high-speed data transmission, since the unit time interval (1-UI) has been shortened to about 10ps, it has become a major technical challenge to achieve complete charging and discharging of MOS tubes in such a short time. Therefore, as one of the most critical modules in an ultra-high-speed transmitter, the performance of the 1-UI data generation circuit directly affects the reliability of the entire system.

[0060] In response to this technical difficulty, the present application proposes an innovative circuit solution, which realizes the reliable generation of 1-UI data through the exquisite coordination of 4 MOS tubes. The basic working process of the circuit is: first, the input tube M1 is used to control the input data. When the input data is at a high level, M1 is turned on to ensure that the data is ready; before the rising edge of the B-phase clock signal (such as CK1) arrives, the output node is precharged through the M4 tube to reach the VDD level; when the rising edge of the A-phase clock signal (such as CK6) arrives, the M2 tube is turned on and the output node starts to pre-discharge until it reaches the preset Vout_precharge level; then when the rising edge of the B-phase clock signal (CK1) arrives, the M4 tube is turned off, and the circuit enters the full discharge stage; finally, after the falling edge of the A-phase clock signal (CK6) arrives, the M2 tube is turned off and the M3 tube is turned on, and the output node is reset and charged to VDD to prepare for the next cycle. Through the continuous cycle of these steps, a 1-UI pulse signal can be reliably generated. In order to further improve the signal quality, this application also introduces a shaping amplifier circuit composed of an RST control signal and three MOS tubes at the output stage to convert the non-full-swing pulse signal into a full-swing signal from 0 to VDD. The innovation of this design is mainly reflected in three aspects: first, through the precise coordination of four MOS tubes and multi-phase clocks, a complete pre-charge, pre-discharge, full discharge and reset charging process is achieved in a very short 1-UI time; second, the RST signal and the shaping amplifier circuit of the three MOS tubes are used to ensure the full-swing characteristics of the output signal; finally, the overall circuit structure is simple and does not require complex control logic, which is very suitable for applications in ultra-high-speed scenarios.

[0061] This application successfully realizes the generation and shaping of ultra-short 1-UI pulses by cleverly utilizing the on-off timing of MOS tubes and the coordination of multi-phase clocks, significantly improving the response speed of the circuit. This design not only solves the signal generation problem in ultra-high-speed scenarios, but also has the advantages of simple structure and high reliability, representing a feasible ultra-high-speed signal processing solution.

[0062] Figure 1 It is a timing diagram of the 1-UI data generation circuit of the present application, which focuses on showing how to use a multi-phase clock to accurately control the generation of a 1-UI pulse signal and the synchronization of a reset signal in an ultra-high-speed data transmission scenario.

[0063] As shown in the figure, the present application uses an 8-phase clock signal (CK1 to CK8), where the time interval between the rising edges of two adjacent clocks is 1 unit interval (UI). The 8-phase clock is used as the timing control signal of the circuit of the present application and the reference clock for data splicing.

[0064] It should be noted that in the description of the present application, the above-mentioned 8-phase clock signal is represented by symbols such as CK1 and CK2, where the numbers represent the serial numbers of the clock phases. It should be noted that the multi-phase clock signal used in the present application is not limited to 8 phases, and it can be flexibly set according to the rate requirements of the transmitter in actual applications (such as 1 / 4 rate or 1 / 8 rate). For example, in an application scenario with a 1 / 4 rate, a total of 4-phase clock signals from CK1 to CK4 can be used; and in an application scenario with a 1 / 8 rate, a total of 8-phase clock signals from CK1 to CK8 can be used. For ease of description, the present application takes a 1 / 8 rate and an 8-phase clock signal as an example for explanation, but the embodiments are not limited to this.

[0065] When an 8-phase clock signal is used, the definitions of each clock signal are as follows:

[0066] CK1 represents the first clock signal

[0067] CK2 represents the second clock signal

[0068] CK3 represents the third clock signal

[0069] CK4 represents the fourth clock signal

[0070] CK5 represents the fifth clock signal

[0071] CK6 represents the sixth clock signal

[0072] CK7 represents the seventh clock signal

[0073] CK8 represents the eighth clock signal

[0074] In the subsequent description, the above symbols will be used uniformly to refer to the corresponding clock signals to maintain consistency and simplicity of description. This unified description method helps to understand the key technical points of the present application such as using multi-phase clocks to accurately control signal timing and realize data splicing.

[0075] Taking D1_LOW as an example, after the low-speed data signal is processed by the 1-UI data generation circuit of the present application, a narrow pulse signal D1_UI with a width of only 1-UI is generated under the cooperation of the rising edge of CK6 and the rising edge of CK1. Using a similar method, other low-speed data signals can also generate corresponding 1-UI pulse signals.

[0076] In order to further improve the quality of the 1-UI pulse signal, the present application also introduces the RST reset signal. Taking RST1 as an example, the reset signal is generated by the combinational logic of CK2 to CK8, and remains at a low level during the D1_UI pulse, and is at a high level at other times. RST1 is strictly synchronized with D1_UI in time, and is used to control the post-stage shaping circuit to shape the 1-UI pulse into a full-swing signal.

[0077] Finally, all 1-UI pulse signals (ie, D1_UI, D2_UI, ..., D8_UI) are alternately spliced ​​in sequence in a time-division multiplexing manner to form a complete high-speed data output signal DOUT_HIGH. It can be seen that each data bit in DOUT_HIGH corresponds to a 1-UI pulse.

[0078] In summary, the present application ingeniously utilizes the time interval characteristics of multi-phase clocks and the precise coordination between different clocks to reliably generate and shape 1-UI pulse signals, thereby realizing serial transmission of ultra-high-speed data. Figure 1 It vividly demonstrates the timing control relationship of this application and intuitively reveals its core innovative ideas.

[0079] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0080] The first embodiment of the present application relates to a data generation circuit for a high-speed transmitter, such as Figure 2 and Figure 3 As shown, it includes a first-level circuit unit and a second-level circuit unit.

[0081] The first-stage circuit unit is used to generate a narrow pulse signal, including:

[0082] Input tube (M1), the gate is used to receive input data signals;

[0083] A pre-discharge control tube (M2), whose source is connected to the drain of the input tube (M1) to form a first intermediate node, and whose gate is used to receive an A-phase clock signal;

[0084] A reset control tube (M3), a drain of which is connected to the drain of the pre-discharge control tube (M2) to form an output node, and a gate of which is used to receive the A-phase clock signal;

[0085] A pre-charge control tube (M4), the drain of which is connected to the output node, the source of which is used to receive the power supply voltage, and the gate of which is used to receive the B-phase clock signal; wherein the B-phase clock signal has a predetermined time interval compared with the A-phase clock signal; the pre-discharge control tube (M2) and the pre-charge control tube (M4) respond to the A-phase clock signal and the B-phase clock signal to sequentially complete pre-charging and pre-discharging of the output node to generate a pulse signal;

[0086] The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including:

[0087] A pull-down tube (M5) is connected between the final output node and the lowest potential, and its control terminal is used to receive a reset signal;

[0088] A plurality of pull-up tubes (M6, M7) have source and drain electrodes respectively connected between the final output node and the power supply voltage, and a control end is used to receive a pulse signal output by the first-stage circuit unit; the pull-down tube (M5) cooperates with the pull-up tubes (M6, M7) to convert a non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

[0089] Optionally, the time width of the narrow pulse signal is 1-UI, where UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

[0090] Optionally, the A-phase clock signal and the B-phase clock signal are two phases in the same group of multi-phase clock signals, wherein the multi-phase clock signal includes at least 4-phase clock signals, and the time interval between the rising edges of each adjacent two-phase clock signal is 1-UI; wherein the B-phase clock signal is 3-UI ahead of the A-phase clock signal.

[0091] Optionally, the gate of the input tube (M1) is connected to the input end to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control tube (M2) to form a first intermediate node (Data_int).

[0092] Optionally, the working process of the first-stage circuit unit includes: (1) before the rising edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on to pre-charge the output node (Dout_int) to the power supply voltage; in the time period before the rising edge of the A-phase clock signal arrives and after the falling edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned on, and the output node (Dout_int) is pre-charged and maintained at the power supply voltage; (2) when the rising edge of the A-phase clock signal arrives, the pre-discharge control tube (M2) is turned on to discharge the output node to a preset level; (3) when the rising edge of the B-phase clock signal arrives, the pre-charge control tube (M4) is turned off, and the output node is further discharged to the lowest potential; (4) when the falling edge of the A-phase clock signal arrives, the reset control tube (M3) is turned on, the pre-discharge tube (M2) is turned off, and the output node is reset and charged to the power supply voltage.

[0093] Optionally, the circuit also includes at least one group of reset signal generating circuits, which is used to generate a reset signal synchronized with the pulse signal according to the multi-phase clock signal. For ease of understanding, the structure of one group of reset signal generating circuits is described below as an example. The reset signal generating circuit includes: a first AND gate, whose input ends are respectively connected to the second clock signal and the fourth clock signal, and is used to perform an AND operation on the two; a second AND gate, whose input ends are respectively connected to the sixth clock signal and the eighth clock signal, and is used to perform an AND operation on the two; an OR gate, whose input ends are respectively connected to the output ends of the first AND gate and the second AND gate, and is used to perform an OR operation on the output signals of the two, and its output end is used to output the reset signal. The structures of the other groups of reset signal generating circuits are the same, and the only difference is that the selected clock signal combination is different.

[0094] Optionally, the reset signal generating circuit receives an 8-phase clock signal as an input signal, and the time interval between rising edges of every two adjacent clock signals is 1-UI.

[0095] Optionally, the working process of the second-level circuit unit includes:

[0096] When the reset signal is at a high level and the pulse signal output by the first-stage circuit unit is at a high level, the pull-down tube (M5) is turned on to discharge the final output node to the zero potential;

[0097] When the reset signal is at a low level and the pulse signal output by the first-stage circuit unit is at a low level, the plurality of pull-up tubes (M6, M7) are alternately turned on to charge the final output node to the power supply voltage.

[0098] Optionally, the data generating circuit is used for a high-speed transmitter with a 1 / 4 rate or a 1 / 8 rate.

[0099] The following further Figure 2 and Figure 3 Provide explanation.

[0100] Figure 2 This is a specific implementation diagram of the 1-UI data generation circuit. When the input data is high, M1 is turned on, and the voltage of the node Data_int is pulled down to 0, preparing for the subsequent discharge process; when the input data is low, M1 is turned off. At this time, even if the CK6 and CK1 clock signals work normally, the Dout_int node will always remain at the pre-charged high level VDD, and no 1-UI pulse will be generated. Figure 2 a and Figure 2 b. Its working principle is as follows:

[0101] (1) In the pre-charge stage, the input data signal needs to be considered. When the input data is at a high level, M1 is turned on and the node Data_int is pulled down to a low level. At this time, if CK1 is at a high level and CK6 is at a low level, M3 is turned on, M2 is turned off, and the output node Dout_int is charged to the VDD level; after CK1 becomes a low level and before the rising edge of CK6 arrives, M4 is turned on and the output node Dout_int is maintained at the VDD level. It should be noted that the premise of the above pre-charge process is that the input data signal is at a high level. When the input data is at a low level, M1 is turned off and the node Data_int always remains at a high level. At this time, no matter what the levels of CK1 and CK6 are, since the M2 source has no low-level drive, the Dout_int node cannot be discharged and will always remain at the VDD level.

[0102] (2) When the rising edge of CK6 arrives (CK1 is at a high level at this time), M2 and M4 are turned on (M3 is turned off). Under the joint action of M2 and M4, Dout_int begins to pre-discharge, and the voltage drops to a certain value Vout_precharge. This process is the pre-discharge achieved by M2 and M4.

[0103] (3) When the rising edge of CK1 arrives (CK6 is still at a high level at this time), M3 / M4 are turned off. With M2 continuously turned on, Dout_int enters the full discharge stage, and the voltage further drops to close to VSS. At this time, a 1-UI pulse is generated.

[0104] (4) When the falling edge of CK6 arrives, M2 is turned off, M3 is turned on, and Dout_int is reset and charged back to VDD, preparing for the next cycle.

[0105] (5) Input data Data is controlled by M1 and is ready at the Data_int node. M1 is equivalent to an input switch, and its working conditions can be divided into two types:

[0106] When the input data Data is at a high level, M1 is turned on and the node Data_int is pulled down to a low level. This low level signal is transmitted to the source of M2, and under the cooperation of CK6 and CK1 clocks, the Dout_int node will generate a narrow pulse signal with a width of 1-UI.

[0107] When the input data Data is low, M1 is turned off, and the node Data_int is in a high impedance state. Its voltage is determined by the parasitic capacitance and is usually near VDD. At this time, even if the CK6 and CK1 clocks work normally, since the M2 source has no low-level drive, the Dout_int node cannot be discharged and always maintains a pre-charged high-level state. In other words, the output node will not generate a 1-UI pulse, and the circuit is in a silent state.

[0108] In summary, the conduction of M1 tube directly affects the operation of the subsequent circuit. Only in the period when the input data Data is at a high level, the Dout_int node will generate a 1-UI pulse with the rhythm of the clock signal; when the input data is at a low level, the output node remains static. This design ensures accurate control of the output pulse by the input data.

[0109] (6) During the entire process, M1, M2, M3, and M4 cooperate with the timing of CK1 and CK6 to reliably generate a pulse signal within the 1-UI time.

[0110] (7) Figure b shows a schematic diagram of the voltage waveforms of each key node, intuitively showing the working process of the circuit within 1-UI.

[0111] In summary, this circuit uses the on and off of four MOS tubes and the timing coordination of the two-phase clock to efficiently complete the generation of 1-UI pulses. Its key innovation lies in the clever embedding of multiple stages such as pre-charge, pre-discharge, full discharge, and reset charge into the 8UI time, making full use of limited time resources.

[0112] Furthermore, Figure 2(c) is a schematic diagram of the voltage waveform timing of the key node Dout_int in the data generation circuit of the present invention, which further shows the details of the change of the node voltage under the control of the clock signals CK1 and CK6. As shown in the figure, the voltage of Dout_int goes through three main stages: reset, pre-discharge, and generation of 1-UI pulses. Specifically, it can be seen in the figure that when the falling edge of CK6 arrives (at this time, the rising edge of CK1 has changed to a high level 1UI in advance), the Dout_int node will be reset (also called pre-charge) to the VDD level, and the reset time lasts for 4UI, which is sufficient time to ensure complete reset. Subsequently, when the rising edge of CK6 arrives (at this time CK1 is a low level), Dout_int starts pre-discharge (pre-discharge), and the 3UI time between the rising edge of CK6 and the falling edge of CK1 is used to realize the decrease of the node voltage. When the rising edge of CK1 arrives, Dout_int further pulls down for 1UI time to form a narrow pulse signal with a width of 1-UI. Finally, the arrival of the next falling edge of CK6 (at this time CK1 has been restored to a high level) starts the reset of Dout_int again, and the circuit repeats the above waveform change cycle. Figure 2 The precise correspondence between the voltage of the Dout_int node and the clock signals CK1 and CK6 in (c) intuitively reflects the innovative idea of ​​the circuit of the present invention to reliably generate a 1-UI pulse signal through carefully designed timing control within limited time resources.

[0113] Figure 3 (a) is a schematic diagram of a 1-UI data full swing circuit, which is used to Figure 2 The 1-UI pulse signal generated in the circuit is shaped into a signal with a full swing (i.e., 0 to VDD).

[0114] Its main circuit structure and working principle are as follows:

[0115] 1. Introduce an RST control signal and three MOS tubes (M5, M6, M7) to realize the shaping and amplification of the 1-UI pulse signal.

[0116] 2. When the falling edge of the 1-UI pulse signal (Dout_int1 or Dout_int2) arrives, the RST signal is at a low level, at which time M5 is turned off, and M6 or M7 is turned on, charging the final output node Dout to the VDD level.

[0117] 3. When the rising edge of the 1-UI pulse signal (Dout_int1 or Dout_int2) arrives, the RST signal is at a high level. At this time, both M6 and M7 are turned off, and M5 is turned on, discharging the final output node Dout to 0 (VSS).

[0118] 4. By coordinating the timing of the RST signal and the 1-UI pulse signal through M5, M6, and M7, the non-full-swing 1-UI pulse can be reliably converted into a rail-to-rail full-swing signal output.

[0119] so Figure 3 The circuit in (a) is Figure 2 The latter stage of the circuit further improves the swing and quality of the output signal and is an important component of the 1-UI data generation circuit. The RST signal is generated by a multi-phase clock combination to ensure synchronization with the 1-UI pulse.

[0120] Figure 3 (b) is a schematic diagram of the RST signal generation circuit. Its function is to generate an RST control signal synchronized with the 1-UI pulse based on a multi-phase clock signal. Figure 3 The shaping circuit in (a) provides appropriate control timing.

[0121] The specific circuit structure is as follows:

[0122] 1. Two AND gates, respectively performing AND operations on CK2 and CK4, and CK6 and CK8.

[0123] 2. A NOR gate, which performs a NOR operation on the output results of the two AND gates to obtain the final RST signal.

[0124] Its working principle is:

[0125] 1. Assume that the input is an 8-phase clock signal (CK1 to CK8), and the interval between the rising edges of each two adjacent clocks is 1-UI.

[0126] 2. The first AND gate performs AND operation on CK2 and CK4. When and only when CK2 and CK4 are both high, its output is high and the corresponding RST signal should be low.

[0127] 3. Similarly, the second AND gate performs AND operation on CK6 and CK8. When and only when CK6 and CK8 are both high, its output is high and the corresponding RST signal should be low.

[0128] 4. The last NOR gate performs a NOR operation on the outputs of the two AND gates. The RST signal is high only when the outputs of the two AND gates are low, otherwise it is low.

[0129] 5. This generates an RST control signal synchronized with the 1-UI pulse, which is low when CK2 / CK4 are simultaneously high or CK6 / CK8 are simultaneously high, and high at other times.

[0130] so Figure 3 (b) The circuit uses the combinational logic of multi-phase clocks to cleverly generate the required RST control signal. Figure 3 The shaping circuit of (a) provides precise control timing, thereby reliably realizing the shaping and amplification of the 1-UI pulse signal.

[0131] Figure 3 (c) shows the voltage waveforms of the key nodes of the 1-UI data full swing circuit, which clearly reflects the complete working process of the circuit within the 1-UI time. Figure 3 (a) The shaping effect of M5-M7 tubes on the input pulse signal, and the control timing of the RST signal.

[0132] First, from the waveform (red) of the Dout_int node, this is caused by Figure 2 The initial 1-UI pulse signal generated by the circuit. This waveform shows the complete charging and discharging process: starting from the VDD level, it drops to the Vout_precharge voltage after the pre-discharge stage, and then enters the full discharge stage until it is close to the ground level, forming a characteristic narrow pulse shape. This process reflects the precise timing control of the previous stage circuit.

[0133] Secondly, the waveform of the RST signal (green) shows the timing characteristics of the reset control. Figure 3 (b) The control signal generated by the circuit remains at a low level during the 1-UI pulse. The falling edge arrives 1UI ahead of the falling edge of the 1-UI pulse, and the rising edge is strictly synchronized with the rising edge of the 1-UI pulse. The RST signal achieves precise timing control of the output node by controlling the conduction state of the M5 tube: when RST is high, M5 is turned on to pull down the output, and when RST is low, M5 is turned off to allow pull-up.

[0134] Finally, the shaped Dout output waveform (red) clearly shows the full-swing characteristic.

[0135] The working process can be divided into three stages:

[0136] 1. When RST is at a low-high level (the 1-UI pulse has not arrived yet), M6 and M7 are turned off, and M5 is turned on, discharging Dout to the ground level.

[0137] 2. When 1UI time passes before the falling edge of the 1-UI pulse, RST becomes low, M5 is turned off, and Dout is maintained at the ground level; after the falling edge of the 1-UI pulse, M6 or M7 is turned on, and Dout is charged to VDD.

[0138] 3.1-When the UI pulse ends (rising edge arrives), the RST rising edge also arrives synchronously, M6 / M7 is turned off, M5 is turned on, and Dout is discharged to a low level under the action of M5.

[0139] It is worth noting that due to the strong pull-down capability of M5, the falling edge of Dout shows good steep characteristics. The rising edge shows relatively gentle characteristics due to the alternating conduction of M6 and M7 and the parasitic RC effect. Despite this, the final output Dout signal still achieves a stable 0-VDD full swing, significantly improving the signal quality.

[0140] This set of waveforms fully records the shaping process of the 1-UI pulse signal, reflecting the precise timing control and reliable operation characteristics of the circuit. The coordinated changes in the voltages of the three key nodes intuitively demonstrate the innovative design concept of this application in ultra-high-speed signal processing.

[0141] Working principle:

[0142] The working process of the above embodiment can be divided into two core parts: the first stage circuit realizes the generation of 1-UI pulse, and the second stage circuit completes the full swing conversion of the signal. Among them, the first stage circuit works under the control of the multi-phase clock through the precise coordination of 4 MOS tubes; the second stage circuit uses 3 MOS tubes and RST signal to realize signal shaping.

[0143] First, the working process of the first-stage circuit is as follows Figure 2 As shown. Due to the 1 / 8 rate structure, the input data signal is relatively slow, which can ensure that the input tube M1 is fully turned on and the level of the node Data_int is stable. The operation of the circuit can be divided into two cases:

[0144] When the input data is at a high level, M1 is turned on and Data_int is pulled down to a low level. In the pre-charge stage, the clock CK1 is at a low level, the pre-charge control tube M4 is turned on, and the output node Dout_int is charged to the VDD level. When the rising edge of CK6 arrives, the pre-discharge control tube M2 is turned on and the reset control tube M3 is turned off, Dout_int begins the pre-discharge process, and the voltage drops to the preset Vout_precharge level. Then the rising edge of CK1 arrives, the pre-charge control tube M4 is turned off, the circuit enters the full discharge stage, and the Dout_int voltage drops further. Finally, when the falling edge of CK6 arrives, M2 is turned off and M3 is turned on, Dout_int is reset and charged to VDD, ready for the next cycle. Through this precise timing control, a narrow pulse signal can be reliably generated within the 1-UI time.

[0145] When the input data is low, M1 is turned off and the Data_int node is always kept at a high level. At this time, no matter how the CK6 and CK1 clocks change, since there is no low-level drive at the M2 source, the Dout_int node cannot be discharged and is always maintained at the VDD level. In other words, during the period when the input is low, the output node will not generate a 1-UI pulse and the circuit is in a silent state.

[0146] In summary, only when the input data is at a high level, the first-stage circuit will start a series of actions such as pre-charging and pre-discharging, generating narrow pulses within the 1-UI time. In the period when the input data is at a low level, the circuit remains static. The high and low levels of the input data directly control the generation of the output pulse.

[0147] Secondly, the working process of the second stage circuit is as follows Figure 3 As shown. The RST signal is Figure 3 (b) is generated by the combinational logic circuit shown in Figure 1, which is obtained by performing logic operations on the four even-phase clock signals CK2 / CK4 / CK6 / CK8. When RST is low and Dout_int1 or Dout_int2 is low, the pull-up tube M6 or M7 is turned on, and the pull-down tube M5 is turned off. At this time, the output node Dout is charged to VDD; when RST is high (Dout_int1 or Dout_int2 also becomes high synchronously), M5 is turned on and M6 / M7 is turned off, and Dout is pulled down to the ground level. In this way, the non-full-swing Dout_int signal is converted into a full-swing signal from 0 to VDD.

[0148] The RST signal generation circuit adopts a simple combinational logic structure, such as Figure 3 (b) As shown in Figure 2, two AND gates perform AND operations on CK2 / CK4 and CK6 / CK8 respectively, and then obtain the final RST signal through the NOR gate. This design ensures the precise synchronization of the RST signal and the 1-UI pulse, thereby ensuring the accuracy of signal shaping.

[0149] The working waveform of the whole circuit is as follows: Figure 3 As shown in (c), it can be clearly seen that after the non-full-swing pulse of Dout_int is processed by the second-stage circuit, a good full-swing square wave signal is obtained at the output node Dout. This signal has a larger noise tolerance and better signal integrity, which is very suitable for transmission in ultra-high-speed systems.

[0150] The above embodiments successfully achieve signal generation and shaping in an ultra-short time through ingenious circuit design and precise timing control, and provide a reliable technical solution for ultra-high-speed data transmission.

[0151] Furthermore, the above embodiment proposes an innovative two-stage ultra-high-speed data generation circuit. The first-stage circuit realizes reliable narrow pulse signal generation in an extremely short time of less than 10 picoseconds by precisely coordinating the input tube, pre-discharge control tube, reset control tube and pre-charge control tube, and utilizing the phase difference of the two-phase clock signals CK1 and CK6; the second-stage circuit innovatively introduces multiple sets of RST reset signal mechanisms, and further reshapes the non-full-swing signal into an ideal full-swing signal through the precise driving of the pull-down tube and the pull-up tube. The collaborative innovation of the two-stage circuit not only breaks through the key bottleneck of ultra-high-speed data transmission, but also can flexibly adapt to different application scenarios such as 1 / 4 rate and 1 / 8 rate, and has broad application prospects in the fields of optical fiber communication, chip interconnection, etc.

[0152] Technical effects:

[0153] The data generation circuit proposed in the above embodiment adopts a two-stage structure design, which successfully solves the key problems of signal generation and shaping in ultra-high-speed scenarios. The first-stage circuit realizes the efficient generation of narrow pulse signals through the ingenious cooperation of the input tube (M1), the pre-discharge control tube (M2), the reset control tube (M3) and the pre-charge control tube (M4). Especially in the extremely short 1-UI with a time interval of less than or equal to 10 picoseconds, the reliable generation of the signal is ensured through multiple precisely controlled stages such as pre-charge and pre-discharge. The second-stage circuit converts the non-full-swing pulse signal into a full-swing signal through the coordinated work of the pull-down tube (M5) and multiple pull-up tubes (M6, M7), which significantly improves the signal quality.

[0154] In terms of timing control, the present application utilizes the delay relationship between the A-phase clock signal and the B-phase clock signal, and cooperates with the synchronous RST signal output by the reset signal generating circuit to achieve precise timing coordination. Among them, for the 1 / 8 rate structure, the A-phase and B-phase clock signals differ by 3-UI; for the 1 / 4 rate structure, the A-phase and B-phase clock signals differ by 1-UI. Specifically, in the first-stage circuit, the pre-charge control tube and the pre-discharge control tube work alternately to complete the signal pre-charge, pre-discharge, full discharge and reset charge process. This carefully designed timing arrangement ensures that all necessary signal processing steps are completed in an ultra-short time.

[0155] Those skilled in the art can understand that the technical solution of the present application is applicable to high-speed transmitters of 1 / 4 rate and 1 / 8 rate at the same time. For the convenience of description and understanding, the detailed description of the circuit structure, working process and timing relationship in the specification is based on the 1 / 8 rate transmitter as an example. In the 1 / 8 rate structure, an 8-phase clock signal (CK1 to CK8) is used, and the A-phase and B-phase clock signals differ by 3-UI, requiring 4 sets of reset signal generating circuits. In the 1 / 4 rate structure, only a 4-phase clock signal is used, and the A-phase and B-phase clock signals differ by 1-UI, and only 2 sets of reset signal generating circuits are required accordingly. Although the specific number of clock phases and the timing relationship are different, the core circuit structure, pre-charge and discharge mechanism and signal shaping principle remain unchanged. In other words, the two-stage circuit structure proposed in the present application (including the 1-UI pulse generating circuit of the first stage and the full swing conversion circuit of the second stage) can flexibly adapt to the application requirements of different rates by adjusting the clock phase configuration and the number of reset signal groups. This design not only ensures the versatility of the technical solution, but also provides sufficient flexibility for practical applications.

[0156] It is worth noting that the above embodiment shows a method for implementing a group of reset signal generating circuits. Taking this group as an example, through a simple combination of two AND gates and one NOR gate, a reset signal synchronized with the corresponding 1-UI pulse is generated using CK2, CK4, CK6, and CK8 in the 8-phase clock signal. Several other groups of similar reset signal generating circuits are also required in the 1 / 8 rate transmitter. They use different clock phase combinations but all adopt the same circuit structure. This design not only simplifies the circuit structure, but also ensures the accuracy of signal shaping. In particular, in the second-stage circuit, the RST signal cooperates with the pulse signal to control the conduction state of the pull-down tube and the pull-up tube, thereby achieving a stable full-swing signal output.

[0157] In general, the above embodiment is applicable to high-speed transmitters at 1 / 4 rate or 1 / 8 rate, and realizes complex signal processing functions through a simple circuit structure. The working processes of all MOS tubes in the circuit are closely coordinated and echo each other, which ensures the signal quality while also ensuring the reliable operation of the circuit. This design not only solves the signal processing problem in ultra-high-speed scenarios, but also has strong engineering practicality, providing important technical support for the development of high-speed communication systems.

[0158] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0159] This example proposes a 1-UI full-swing data generation circuit, which integrates pre-charge and discharge functions, greatly improves the circuit response speed, and is suitable for use in ultra-high-speed transmitters.

[0160] Specifically, this example proposes a design such as Figure 2 As shown, 4 MOS tubes are used to realize the function of 1-UI data generation ( Figure 2 a). If we take 1 / 8 rate as an example ( Figure 2 b), the rising edge of clock CK6 leads the rising edge of CK1 by 3-UI time; since the input data is a relatively low-rate signal, it can be considered that the input Data is fully prepared, the M1 tube is fully turned on, and the voltage of the node Data_int is 0; in the pre-charge stage (pre-charge), CK6 is low level, the M3 tube is turned on, and the node Dout_int is charged to VDD. After the falling edge of CK1, M4 is turned on, and Dout_int is maintained at VDD; after the rising edge of CK6 arrives, the M2 tube is turned on (the M3 tube is turned off), and Dout_int begins to pre-discharge; when discharged to vout_prechage, the rising edge of CK1 arrives, the M4 tube is turned off, and enters the full discharge stage; after the falling edge of CK6 arrives, the M2 tube is turned off, the M3 tube is turned on, and Dout_int is reset and charged to VDD, and then the above process is continuously cycled. It should be noted that the above analysis is based on the case where the input data signal is high level. When the input data is low level, the M1 tube is in the off state, and the node Data_int always remains at the VDD level. At this time, no matter how CK1 and CK6 change, the Dout_int node will not discharge, but will always maintain the VDD level. In other words, when the input data is low, the output node will not generate narrow pulses, and the circuit is in a silent state. In this case, since there is no large current charging and discharging, there is no problem of charging and discharging speed. The timing of the circuit is completely determined by the high level period of the input data.

[0161] In the above circuit, the Dout_int signal cannot reach the full swing (0→VDD); combined with Figure 3 The circuit shown in the figure can achieve full swing of the output signal Dout, where the RST signal comes from the combinational logic implementation of the last clock signal (CK2 / CK4 / CK6 / CK8). The circuit diagram is shown in Figure 3 b; the signal timing is as follows Figure 1 shown.

[0162] like Figure 3As shown in c, when the falling edge of the Dout_int1 or Dout_int2 pulse signal comes, the RST signal is low, the M5 tube is turned off, and the M6 ​​or M7 tube charges the output node Dout to VDD; when the rising edge of the Dout_int1 or Dout_int2 pulse signal comes, the RST signal is high, the M6 / M7 tubes are all turned off, and the M5 tube discharges the output node Dout to zero; after this processing, the Dout_int1 or Dout_int2 pulse signal is shaped to a full-swing signal.

[0163] In summary, this application achieves ultra-high-speed, low-power, and high-precision pulse signal generation through system optimization in pre-charge and pre-discharge control, MOS tube size ratio, and second-stage shaping circuit, greatly broadening the application space of ultra-high-speed serial communication. This technical solution is simple to operate and easy to integrate, and can be widely used in high-speed optical fiber communication, chip interconnection, radar and other fields, with significant technical advantages and commercial value.

[0164] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0165] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A data generation circuit for a high-speed transmitter, characterized in that: It includes a first-level circuit unit and a second-level circuit unit, wherein: The first-stage circuit unit is used to generate a narrow pulse signal, including: Input tube M1, the gate is used to receive input data signals; A pre-discharge control tube M2, whose source is connected to the drain of the input tube M1 to form a first intermediate node, and whose gate is used to receive the A-phase clock signal; A reset control tube M3, whose drain is connected to the drain of the pre-discharge control tube M2 to form an output node, and whose gate is used to receive the A-phase clock signal; A pre-charge control tube M4, whose drain is connected to the output node, whose source is used to receive the power supply voltage, and whose gate is used to receive the B-phase clock signal; wherein the B-phase clock signal has a predetermined time delay compared with the A-phase clock signal; the pre-discharge control tube M2 and the pre-charge control tube M4 respond to the A-phase clock signal and the B-phase clock signal to sequentially pre-charge and pre-discharge the output node to generate a pulse signal; The second-stage circuit unit is used to shape the pulse signal into a full-swing signal, including: The pull-down tube M5 is connected between the final output node and the lowest potential, and its control terminal is used to receive a reset signal; A plurality of pull-up tubes M6 and M7 have drains and sources respectively connected between the final output node and the power supply voltage, and a control end is used to receive the pulse signal output by the first-stage circuit unit; the pull-down tube M5 cooperates with the pull-up tubes M6 and M7 to convert the non-full-swing pulse signal into a full-swing signal output in response to the reset signal and the pulse signal.

2. The data generating circuit according to claim 1, wherein: The time width of the narrow pulse signal is 1-UI, wherein UI is a unit time interval, and the unit time interval UI is less than or equal to 10 picoseconds.

3. The data generating circuit according to claim 2, characterized in that: The A-phase clock signal and the B-phase clock signal are two phases in the same group of multi-phase clock signals, wherein the multi-phase clock signal includes at least 4-phase clock signals, and the time interval between the rising edges of each adjacent two-phase clock signal is 1-UI; wherein the B-phase clock signal leads the A-phase clock signal by 3-UI.

4. The data generating circuit according to claim 3, characterized in that: The gate of the input tube M1 is connected to the input end to receive the input data signal, the source is grounded, and the drain is connected to the source of the pre-discharge control tube M2 to form a first intermediate node.

5. The data generating circuit according to claim 4, characterized in that: The working process of the first-stage circuit unit includes: before the rising edge of the A-phase clock signal arrives, the pre-charge control tube M4 is turned on to pre-charge the output node to the power supply voltage; when the rising edge of the A-phase clock signal arrives, the pre-discharge control tube M2 is turned on to discharge the output node to a preset level; when the rising edge of the B-phase clock signal arrives, the pre-charge control tube M4 is turned off, and the output node is further discharged to the lowest potential; when the falling edge of the A-phase clock signal arrives, the reset control tube M3 is turned on, the pre-discharge control tube M2 is turned off, and the output node is reset and charged to the power supply voltage.

6. The data generating circuit according to claim 3, characterized in that: It also includes at least one group of reset signal generating circuits, which are used to generate a reset signal synchronized with the pulse signal according to the multi-phase clock signal, and the reset signal generating circuit includes: a first AND gate, whose input ends are respectively connected to the second clock signal and the fourth clock signal, and are used to perform an AND operation on the two; a second AND gate, whose input ends are respectively connected to the sixth clock signal and the eighth clock signal, and are used to perform an AND operation on the two; an OR-not gate, whose input ends are respectively connected to the output ends of the first AND gate and the second AND gate, and are used to perform an OR-not operation on the output signals of the two, and whose output end is used to output the reset signal.

7. The data generating circuit according to claim 6, wherein: The reset signal generating circuit receives an 8-phase clock signal as an input signal, and the time interval between rising edges of every two adjacent clock signals is 1-UI.

8. The data generating circuit according to claim 7, characterized in that: The working process of the second-level circuit unit includes: When the reset signal is at a high level and the pulse signal output by the first-stage circuit unit is at a high level, the pull-down tube M5 is turned on to discharge the final output node to zero potential; When the reset signal is at a low level and the pulse signal output by the first-stage circuit unit is at a low level, the plurality of pull-up tubes M6 and M7 are alternately turned on to charge the final output node to the power supply voltage.

9. The data generating circuit according to claim 8, characterized in that: The data generating circuit is used for a high-speed transmitter with a 1 / 4 rate or a 1 / 8 rate.

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