Analog switch circuit with overvoltage protection and chip

Abstract

The application discloses an analog switch circuit and a chip with overvoltage protection. The analog switch circuit comprises a switch unit, a substrate selection unit and an overvoltage detection unit; wherein the output end of the substrate selection unit is connected with the switch unit and the overvoltage detection unit, and the output end of the overvoltage detection unit is connected with the control end of the switch unit. The overvoltage detection unit is used for generating and outputting a second control signal and a third control signal according to a first control signal, an input analog signal and a power supply voltage, and controlling the on-off state of the switch unit. When overvoltage occurs at the input end of the analog switch circuit in the off or on state, the analog switch circuit can keep or turn to the off state, thereby avoiding problems such as the analog switch being unable to be turned off, the device being damaged and the performance being poor due to the input overvoltage.

Description

Technical Field

[0001] This invention relates to an analog switch circuit with overvoltage protection, and also to an integrated circuit chip including the analog switch circuit, belonging to the field of analog integrated circuit technology. Background Technology

[0002] Analog switches are used to open and close the transmission paths of various analog or power signals to control their transmission. They are characterized by low on-resistance and fast transmission time. In some System-on-Chips (SoC) chips, such as Microcontroller Unit (MCU) chips, to save on the number of I / O (Input / Output) ports, internal analog switches are often used to multiplex digital I / O ports into analog GPIO (General Purpose Input / Output) ports. These ports serve as input ports for internal analog circuits such as ADCs (Analog-to-Digital Converters). These multiplexed ports typically need to interface with other peripheral chips on the PCB (Printed Circuit Board) for data transmission and device control.

[0003] In existing technologies, such as Figure 1 As shown, the multiplexed port PAD_IN is connected to the input of the internal analog circuit via an analog switch. This analog switch consists of a PMOS transistor M1 and an NMOS transistor M2. Assume the chip's operating voltage VDD is 3.3V. When the control voltage ENB of M1 is 0V and the control voltage EN of M2 is 3.3V, the analog switch is closed. In this case, if a 5V voltage is applied to the PAD_IN port from an external chip, this voltage exceeds the normal operating voltage of the internal analog circuit (3.3V), causing damage to the components in the internal analog circuit. When the control voltage ENB of M1 is 3.3V and the control voltage EN of M2 is 0V, the analog switch is off. In this case, if a 5V voltage is applied to the PAD_IN port, firstly, the gate-source voltage Vgs of PMOS transistor M1 is -1.7V, causing M1 to conduct, which will also damage the components in the internal analog circuit; secondly, the gate-source voltage Vgs of NMOS transistor M2 is 5V, which also exceeds the normal operating voltage of 3.3V, so M2 will also experience overvoltage. Furthermore, when a 5V voltage is applied to the PAD_IN port, this voltage exceeds the body voltage (VDD) of the PMOS transistor M1, disrupting the reverse bias voltage of the PMOS substrate and causing a body effect. This leads to problems such as increased threshold voltage, leakage current, and degraded PMOS performance. Therefore, it is necessary to address the technical issues caused by the mismatch between the overvoltage introduced at the PAD_IN port and the operating voltage of the SOC chip, resulting in the analog switch failing to turn off, device damage, and performance degradation.

[0004] Chinese patent application No. 202210055351.7 discloses an analog switch circuit with bidirectional overvoltage protection. This analog switch circuit includes a switch control circuit, an overvoltage current limiting protection circuit, and a switch circuit. The switch control circuit is connected to the switch circuit and is used to control the switch circuit. The overvoltage current limiting protection circuit is connected to the switch circuit and is used to protect the switch circuit in the event of bidirectional overvoltage at both the analog input port and the analog output port. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide an analog switch circuit with overvoltage protection.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the above-described analog switching circuit.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] According to a first aspect of the present invention, an analog switching circuit with overvoltage protection is provided, comprising a switching unit, a substrate selection unit, and an overvoltage detection unit; wherein,

[0009] The output terminal of the substrate selection unit is connected to the switching unit and the overvoltage detection unit, and the output terminal of the overvoltage detection unit is connected to the control terminal of the switching unit.

[0010] The substrate selection unit is used to provide a body bias voltage for the PMOS transistors in the switching unit and the overvoltage detection unit.

[0011] The overvoltage detection unit is used to generate and output a second control signal and a third control signal based on the first control signal, the input analog signal and the power supply voltage, and provide them to the switching unit.

[0012] The switching unit connects or disconnects the transmission path of the input analog signal according to the first control signal, the second control signal and the third control signal;

[0013] When an overvoltage occurs at the input terminal of the analog switch circuit in the off state, the analog switch circuit remains off. When an overvoltage occurs at the input terminal of the analog switch circuit in the on state, the analog switch circuit switches to the off state, thereby achieving overvoltage protection for the analog switch circuit and subsequent analog circuits.

[0014] Preferably, the switching unit includes a fifth PMOS transistor, a sixth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; wherein,

[0015] The drain of the fifth PMOS transistor is connected in series with the source of the sixth PMOS transistor, and the drain of the sixth NMOS transistor is connected in series with the source of the seventh NMOS transistor.

[0016] The source terminal of the fifth PMOS transistor and the source terminal of the sixth NMOS transistor are connected in parallel to each other and serve as the input terminal of the switching unit.

[0017] The drain of the sixth PMOS transistor and the drain of the seventh NMOS transistor are connected in parallel to each other and serve as the output terminal of the switching unit.

[0018] The gate terminal of the fifth PMOS transistor is connected to the second output terminal of the overvoltage detection unit, and the gate terminal of the sixth PMOS transistor is connected to the first output terminal of the overvoltage detection unit.

[0019] The gate of the sixth NMOS transistor is connected to the power supply voltage terminal, and the gate of the seventh NMOS transistor is connected to the first control signal terminal.

[0020] Preferably, the overvoltage detection unit includes a second control signal subunit and a third control signal subunit, wherein,

[0021] The output terminal of the second control signal subunit is connected to the input terminal of the third control signal subunit;

[0022] The second control signal subunit is used to generate and output the second control signal based on the first control signal, the input analog signal, and the power supply voltage;

[0023] The third control signal subunit is used to generate and output the third control signal based on the first control signal, the input analog signal, the power supply voltage, and the second control signal.

[0024] Preferably, the two control signal subunits include a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first inverter, and a first OR gate; wherein,

[0025] The third PMOS transistor, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected in series to form a series branch, providing an input signal to the first input terminal of the first OR gate; the first NMOS transistor is a native NMOS transistor.

[0026] Preferably, the source terminal of the third PMOS transistor is connected to the input terminal of the input analog signal, the gate terminal is connected to the power supply voltage terminal, and the drain terminal is connected to the drain terminal of the first NMOS transistor.

[0027] The gate terminal of the first NMOS transistor is connected to the power supply voltage terminal, and the source terminal is connected to the drain terminal of the second NMOS transistor and the first input terminal of the first OR gate.

[0028] The gate terminal of the second NMOS transistor is connected to the bias voltage terminal, and the source terminal is connected to the drain terminal of the third NMOS transistor.

[0029] The gate terminal of the third NMOS transistor is connected to the first control signal terminal, and the source terminal is connected to the ground potential terminal;

[0030] The input terminal of the first inverter is connected to the first control signal terminal, and the output terminal is connected to the second input terminal of the first OR gate.

[0031] The output of the first OR gate is connected to the switching unit as the first output of the overvoltage detection unit, and also to the third control signal subunit.

[0032] Preferably, the third control signal subunit includes a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; wherein...

[0033] The source terminal of the fourth NMOS transistor is connected to the output terminal of the second control signal subunit, the gate terminal of the fourth NMOS transistor is connected to the first control signal terminal, and the drain terminal is connected to the source terminal of the fifth NMOS transistor.

[0034] The gate of the fifth NMOS transistor is connected to the power supply voltage terminal, and its drain is connected to the second output terminal of the overvoltage detection unit and the switching unit on one hand, and to the drain of the fourth PMOS transistor on the other hand.

[0035] The gate terminal of the fourth PMOS transistor is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal.

[0036] Preferably, when an overvoltage occurs at the input terminal of the analog switch circuit in the open state, the second control signal output by the overvoltage detection unit is at a high level; the third control signal is at a high level, and the voltage of the third control signal is equal to the voltage of the input analog signal.

[0037] Preferably, when an overvoltage occurs at the input terminal of the analog switch circuit in the ON state, the second control signal output by the overvoltage detection unit is in a high-level state; the third control signal is in a high-level state, and the voltage of the third control signal is equal to the voltage of the input analog signal.

[0038] Preferably, the substrate selection unit includes a first PMOS transistor and a second PMOS transistor; wherein...

[0039] The body and drain terminals of the first PMOS transistor are short-circuited, the gate terminal is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal.

[0040] The body and drain terminals of the second PMOS transistor are shorted together, the gate terminal is connected to the input terminal of the input analog signal, and the source terminal is connected to the power supply voltage terminal.

[0041] The drain terminals of the first PMOS transistor and the second PMOS transistor are connected to each other and serve as the output terminal of the substrate selection unit.

[0042] According to a second aspect of the present invention, an integrated circuit chip is provided, including the analog switch circuit with overvoltage protection described above.

[0043] Compared with existing technologies, the analog switch circuit with overvoltage protection provided by this invention employs a substrate selection unit to provide a bias voltage to the PMOS transistor body, and an overvoltage detection unit to generate second and third control signals to provide to the switching unit. This control scheme ensures that when an overvoltage occurs at the input terminal of the analog switch circuit in either the open or closed state, the analog switch circuit can maintain or switch to the open state. This avoids problems such as the analog switch failing to turn off, device damage, and performance degradation caused by input overvoltage, thus achieving overvoltage protection for the analog switch circuit and subsequent analog circuits. Therefore, the analog switch circuit with overvoltage protection provided by this invention has the advantages of ingenious and reasonable structural design, low design cost, high reliability, and excellent circuit performance. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a typical analog switching circuit in the prior art;

[0045] Figure 2 A structural block diagram of an analog switch circuit with overvoltage protection provided by the present invention;

[0046] Figure 3 This is a circuit schematic diagram of the substrate selection unit in an embodiment of the present invention;

[0047] Figure 4 This is a circuit diagram of the overvoltage detection unit in an embodiment of the present invention;

[0048] Figure 5 This is a circuit diagram of the switching unit in an embodiment of the present invention. Detailed Implementation

[0049] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0050] like Figure 2As shown, an embodiment of the present invention provides an analog switch circuit with overvoltage protection, comprising a switch unit, a substrate selection unit, and an overvoltage detection unit. The output terminal of the substrate selection unit is connected to the switch unit and the overvoltage detection unit, and the output terminal of the overvoltage detection unit is connected to the control terminal of the switch unit. The input terminal of the switch unit is connected to the PAD_IN port, and the output terminal OUT of the switch unit is connected to the input terminal of the application circuit. The PAD_IN port is the input port of the external analog signal VIN. In application scenarios where digital I / O ports are multiplexed as analog GPIO ports, the PAD_IN port is the multiplexed I / O port.

[0051] The switching unit connects or disconnects the transmission path of the input analog signal VIN according to the first control signal SWC, the second control signal SWCX_OR, and the third control signal SWCX_H. The first control signal SWC is the switch on / off control signal provided by the application system; typically, its high-level voltage is the same as the power supply voltage VDD. The power supply voltage VDD is the operating power supply voltage for the analog switching circuit and the application circuit connected to its output.

[0052] The substrate selection unit is used to provide the body bias voltage for the PMOS transistors in the switching unit and the overvoltage detection unit. When the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≤VDD-Vth), and when the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN≥VDD+Vth), the substrate selection unit selects the larger voltage value between the input analog signal and the power supply voltage and outputs it to the switching unit and the overvoltage detection unit as the body bias voltage of the PMOS transistor.

[0053] The overvoltage detection unit is used to generate and output the second control signal SWCX_OR and the third control signal SWCX_H based on the first control signal SWC, the input analog signal VIN and the power supply voltage VDD, and provide them to the switching unit.

[0054] When an overvoltage occurs at the input terminal of the analog switch circuit in the open state, the analog switch circuit remains in the open state. When an overvoltage occurs at the input terminal of the analog switch circuit in the closed state, the analog switch circuit switches to the open state, thereby achieving overvoltage protection for the analog switch circuit and subsequent analog circuits.

[0055] In one embodiment of the present invention, such as Figure 3As shown, the substrate selection unit includes a first PMOS transistor P0 and a second PMOS transistor P1. The body and drain terminals of the first PMOS transistor P0 are shorted together, its gate terminal is connected to the power supply voltage VDD, and its source terminal is connected to the PAD_IN port. The body and drain terminals of the second PMOS transistor P1 are shorted together, its gate terminal is connected to the PAD_IN port, and its source terminal is connected to the power supply voltage VDD. The drain terminals of the first PMOS transistor P0 and the second PMOS transistor P1 are interconnected and serve as the output terminal of the substrate selection unit.

[0056] When the input analog signal voltage VIN at the PAD_IN port is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≤ VDD - Vth), the first PMOS transistor P0 is turned off, and the second PMOS transistor P1 is turned on. Therefore, the output voltage BULK_HV is equal to the power supply voltage VDD. When the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth), the first PMOS transistor P0 is turned on, and the second PMOS transistor P1 is turned off. Therefore, the output voltage BULK_HV is equal to the input analog signal voltage VIN. Furthermore, when the input analog signal voltage VIN is near the power supply voltage VDD, i.e., VDD+Vth>VIN>VDD-Vth, the first PMOS transistor P0 and / or the second PMOS transistor P1 are in a weak conduction state (i.e., subthreshold state), and the output voltage BULK_HV is between the power supply voltage VDD and the input analog signal voltage VIN. At this time, since the input analog signal voltage VIN is very close to the power supply voltage VDD, the analog switching circuit operates in normal working condition.

[0057] The above analysis shows that when the magnitude of the input analog signal voltage VIN deviates significantly from the power supply voltage VDD, the substrate selection unit uses the larger of the input analog signal voltage VIN and the power supply voltage VDD as the output voltage BULK_HV, which is provided to the switching unit and the overvoltage detection unit as the body bias voltage of the PMOS transistor in the unit. This ensures that the body of the PMOS transistor is always at the highest potential, and keeps the parasitic diode inside the PMOS transistor in a reverse bias state, thereby avoiding leakage current and performance degradation caused by overvoltage of the input analog signal VIN.

[0058] In one embodiment of the present invention, such as Figure 4As shown, the overvoltage detection unit includes a second control signal subunit and a third control signal subunit, wherein the output terminal of the second control signal subunit is connected to the input terminal of the third control signal subunit. The second control signal subunit is used to generate and output a second control signal SWCX_OR based on the first control signal SWC, the input analog signal VIN, and the power supply voltage VDD; the third control signal subunit is used to generate and output a third control signal SWCX_H based on the first control signal SWC, the input analog signal VIN, the power supply voltage VDD, and the second control signal SWCX_OR.

[0059] The second control signal subunit includes a third PMOS transistor P2, a first NMOS transistor N0, a second NMOS transistor N1, a third NMOS transistor N2, a first inverter INV1, and a first OR gate OR1. The first NMOS transistor N0 is a native NMOS transistor, which has a near-zero threshold voltage characteristic. The third PMOS transistor P2, the first NMOS transistor N0, the second NMOS transistor N1, and the third NMOS transistor N2 are connected in series to form a series branch. This series branch functions as a source-input comparator, comparing the source voltage and the gate voltage, and outputting the signal PAD_DET to the first input of the first OR gate OR1.

[0060] In the two control signal subunits, the source of the third PMOS transistor P2 is connected to the PAD_IN port, its gate is connected to the power supply voltage VDD, and its drain is connected to the drain of the first NMOS transistor N0. The gate of the first NMOS transistor N0 is connected to the power supply voltage VDD, and its source is connected to the drain of the second NMOS transistor N1 and the first input of the first OR gate OR1. The gate of the second NMOS transistor N1 is connected to the bias voltage VBIAS, and its source is connected to the drain of the third NMOS transistor N2. The gate of the third NMOS transistor N2 is connected to the first control signal SWC, and its source is connected to ground. The input of the first inverter INV1 is connected to the first control signal SWC, and its output is connected to the second input of the first OR gate OR1. The output of the first OR gate OR1 serves as the first output of the overvoltage detection unit (i.e., the output of the second control signal SWCX_OR) connected to the switching unit, and also connects to the third control signal subunit.

[0061] The third control signal subunit includes a fourth PMOS transistor P3, a fourth NMOS transistor N3, and a fifth NMOS transistor N4. The source of the fourth NMOS transistor N3 is connected to the output of the first OR gate OR1 in the second control signal subunit; the gate of the fourth NMOS transistor N3 is connected to the first control signal SWC terminal, and its drain is connected to the source of the fifth NMOS transistor N4; the gate of the fifth NMOS transistor N4 is connected to the power supply voltage VDD terminal, and its drain serves as both the second output of the overvoltage detection unit (i.e., the output of the third control signal SWCX_H) connected to the switching unit, and also connects to the drain of the fourth PMOS transistor P3; the gate of the fourth PMOS transistor P3 is connected to the power supply voltage VDD terminal, and its source is connected to the PAD_IN port.

[0062] In the overvoltage detection unit, the body terminals of all PMOS transistors are connected to the output terminal of the substrate select unit; typically, the body terminals of NMOS transistors are connected to ground.

[0063] The following describes the working principle of the overvoltage detection unit and the state changes of its output second control signal SWCX_OR and third control signal SWCX_H, respectively, through the working scenarios of the first control signal SWC and the input analog signal VIN under different states.

[0064] In the first operating scenario, when the first control signal SWC is low, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≤ VDD - Vth), the third PMOS transistor P2 and the third NMOS transistor N2 in the series branch are both in the off state, and the second NMOS transistor N1 is also in the off state. Therefore, there is no signal input at the first input terminal of the first OR gate OR1. Simultaneously, since the first control signal SWC is low, after passing through the first inverter INV1, the input signal SWCX at the second input terminal of the first OR gate OR1 is high. Therefore, the second control signal SWCX_OR output by the first OR gate OR1 is high. At this time, the fourth NMOS transistor N3 is in the off state, and the fifth NMOS transistor N4 and the fourth PMOS transistor P3 are also in the off state. Therefore, there is no signal output at the second output terminal of the overvoltage detection unit.

[0065] In the second operating scenario, when the first control signal SWC is low and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth), the third NMOS transistor N2 in the series branch is cut off, the second NMOS transistor N1 is also cut off, and the third PMOS transistor P2 is turned on. Since the first NMOS transistor N0 is a native NMOS transistor with a threshold voltage Vth close to 0, it is turned on, making the input signal PAD_DET at the first input terminal of the first OR gate OR1 high. Simultaneously, since the first control signal SWC is low, after passing through the first inverter INV1, the input signal SWCX at the second input terminal of the first OR gate OR1 is high. Therefore, the second control signal SWCX_OR output by the first OR gate OR1 is high. At this time, the fourth NMOS transistor N3 and the fifth NMOS transistor N4 are in the off state, and the fourth PMOS transistor P3 is in the on state. Therefore, the third control signal SWCX_H output from the second output terminal of the overvoltage detection unit is in a high level state, and the voltage of the third control signal SWCX_H is equal to the input analog signal voltage VIN.

[0066] In the third operating scenario, when the first control signal SWC is high and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≤ VDD - Vth), the third PMOS transistor P2 is off, the first NMOS transistor N0 is on, and the third NMOS transistor N2 is on. Under the action of the bias voltage VBIAS, the second NMOS transistor N1 (equivalent to the power source) is turned on, causing the input signal PAD_DET at the first input terminal of the first OR gate OR1 to be low. Simultaneously, since the first control signal SWC is high, after passing through the first inverter INV1, the input signal SWCX at the second input terminal of the first OR gate OR1 is low. Therefore, the second control signal SWCX_OR output by the first OR gate OR1 is low. At this time, the fourth NMOS transistor N3 and the fifth NMOS transistor N4 are on, and the fourth PMOS transistor P3 is off. Therefore, the third control signal SWCX_H output by the second output terminal of the overvoltage detection unit is also low.

[0067] In the fourth operating scenario, when the first control signal SWC is high and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth), the third PMOS transistor P2 and the first NMOS transistor N0 are in the conducting state, as are the third NMOS transistor N2 and the second NMOS transistor N1. At this time, the pull-up capability of the third PMOS transistor P2 and the first NMOS transistor N0 is greater than the pull-down capability of the third NMOS transistor N2 and the second NMOS transistor N1. The first NMOS transistor N0 is a native NMOS transistor, and its source voltage is close to its gate voltage VDD, causing the input signal PAD_DET at the first input terminal of the first OR gate OR1 to be high. Simultaneously, since the first control signal SWC is high, after passing through the first inverter INV1, the input signal SWCX at the second input terminal of the first OR gate OR1 is low. Therefore, the second control signal SWCX_OR output by the first OR gate OR1 is high. At this time, the fourth NMOS transistor N3 and the fifth NMOS transistor N4 are in the off state, and the fourth PMOS transistor P3 is in the on state. Therefore, the third control signal SWCX_H output from the second output terminal of the overvoltage detection unit is also in a high level state, and the voltage of the third control signal SWCX_H is equal to the input analog signal voltage VIN.

[0068] In one embodiment of the present invention, such as Figure 5 As shown, the switching unit includes a fifth PMOS transistor P4, a sixth PMOS transistor P5, a sixth NMOS transistor N5, and a seventh NMOS transistor N6. The drain of the fifth PMOS transistor P4 is connected in series with the source of the sixth PMOS transistor P5, and the drain of the sixth NMOS transistor N5 is connected in series with the source of the seventh NMOS transistor N6. The source of the fifth PMOS transistor P4 and the source of the sixth NMOS transistor N5 are connected in parallel and serve as the input terminal of the switching unit, connected to the PAD_IN port. The drain of the sixth PMOS transistor P5 and the drain of the seventh NMOS transistor N6 are connected in parallel and serve as the output terminal OUT of the switching unit. The gate of the fifth PMOS transistor P4 is connected to the second output terminal of the overvoltage detection unit, the gate of the sixth PMOS transistor P5 is connected to the first output terminal of the overvoltage detection unit, the gate of the sixth NMOS transistor N5 is connected to the power supply voltage VDD terminal, and the gate of the seventh NMOS transistor N6 is connected to the first control signal SWC terminal.

[0069] In the switching unit, the body terminals of all PMOS transistors are connected to the output terminal of the substrate select unit; typically, the body terminals of NMOS transistors are connected to ground.

[0070] In the first operating scenario, the analog switch circuit is in a normally open state, meaning the first control signal SWC is low, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≤ VDD - Vth). At this time, in the switching unit, the second control signal SWCX_OR is high, and the second output terminal of the overvoltage detection unit has no signal output, meaning there is no output of the third control signal SWCX_H. Therefore, both the fifth PMOS transistor P4 and the sixth PMOS transistor P5 are in the off state. Since the first control signal SWC is low, the seventh NMOS transistor N6 is in the off state. Whether the sixth NMOS transistor N5 is turned on depends on whether the difference between VDD and VIN reaches the threshold voltage. Therefore, the entire switching unit is in the off state.

[0071] In the second operating scenario, the analog switching circuit is in the overvoltage off state, i.e., the first control signal SWC is low, and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth). At this time, in the switching unit, the second control signal SWCX_OR is high; the third control signal SWCX_H is high, and its voltage is equal to the input analog signal voltage VIN. Therefore, the gate voltage and source voltage of the fifth PMOS transistor P4 are both VIN, and it remains in the off state. The sixth PMOS transistor P5 is also in the off state. Since the first control signal SWC is low, the seventh NMOS transistor N6 is in the off state. The gate voltage VDD of the sixth NMOS transistor N5 is less than its source voltage VIN, and it is also in the off state. Furthermore, its gate-source voltage Vgs is the difference between VIN and VDD, so no overvoltage phenomenon occurs. Therefore, the entire switching unit remains in the off state, which solves the problem of the analog switch failing to turn off and the device being damaged by overvoltage when an overvoltage is introduced into the PAD_IN port.

[0072] In the third operating scenario, the analog switch circuit is in the normally connected state, i.e., the first control signal SWC is at a high level, and the input analog signal voltage VIN is less than or equal to the difference between the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≤ VDD - Vth). At this time, in the switching unit, the second control signal SWCX_OR is at a low level, the third control signal SWCX_H is also at a low level, the fifth PMOS transistor P4 and the sixth PMOS transistor P5 are both in the conducting state, and simultaneously, the sixth NMOS transistor N5 and the seventh NMOS transistor N6 are also in the conducting state. Therefore, the entire switching unit is in the closed state.

[0073] In the fourth operating scenario, the analog switch circuit is in an "on" state due to input overvoltage. This means that while the analog switch circuit is normally on, the input analog signal voltage VIN suddenly increases beyond the power supply voltage VDD. In this scenario, the first control signal SWC is high, and the input analog signal voltage VIN is greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth). In the switching unit, the second control signal SWCX_OR is high, and the third control signal SWCX_H is also high, with its voltage equal to the input analog signal voltage VIN. The sixth PMOS transistor P5 is off, and the gate-to-source voltage of the fifth PMOS transistor P4 is equal to VIN, also in the off state. Since the input analog signal voltage VIN is greater than the power supply voltage VDD, both the sixth NMOS transistor N5 and the seventh NMOS transistor N6 are in the off state. Furthermore, the gate-to-source voltage Vgs of the sixth NMOS transistor N5 is the difference between VIN and VDD, and no overvoltage occurs. Therefore, the switching unit changes from the closed state to the closed state, which solves the problem of the analog switch failing to turn off and the device being damaged by overvoltage when an overvoltage is introduced into the PAD_IN port.

[0074] Furthermore, it should be noted that under normal operating conditions, the input analog signal voltage VIN of the analog switch circuit is less than or equal to the power supply voltage DVV. In this embodiment, the overvoltage state of the analog switch circuit refers to the input analog signal voltage VIN being greater than or equal to the sum of the power supply voltage VDD and the threshold voltage Vth (i.e., VIN ≥ VDD + Vth). Therefore, when the input analog signal voltage VIN is near the power supply voltage VDD, i.e., VDD + Vth > VIN > VDD - Vth, even if the third PMOS transistor P2 and / or the fourth PMOS transistor P3 in the overvoltage detection unit are in a weakly conducting state, causing an error in the third control signal SWCX_H and resulting in a change in the state of the fifth PMOS transistor P4 in the switching unit, the maximum output voltage of the analog switch circuit will not exceed VDD + Vth. This is not an overvoltage operating condition and will not harm the analog switch circuit or subsequent analog circuits.

[0075] The detailed analysis of the above working states shows that the analog switch circuit with overvoltage protection provided by the present invention can not only work normally in the normal open and normal closed states, but also keep the entire switch unit in the off state or switch it to the off state when an overvoltage occurs at the input terminal in the open or closed state. This avoids technical problems such as the analog switch failing to turn off, device damage, and performance degradation caused by input overvoltage.

[0076] It should be noted that the analog switch circuit provided by the present invention does not limit the circuit structure of the above-mentioned functional units. In other embodiments of the present invention, each functional unit can use other different circuit structures to complete the same function of the unit and ultimately achieve the same analog switch overvoltage protection function.

[0077] Based on the aforementioned analog switch circuit with overvoltage protection, this embodiment of the invention further provides an integrated circuit chip, including the aforementioned analog switch circuit with overvoltage protection. This analog switch circuit is used to provide on / off control of analog signals for the chip system. Alternatively, when the digital I / O port of the SOC chip is multiplexed as an analog GPIO port, the analog switch circuit is used to control the on / off state of external analog signals. Furthermore, it can promptly shut off the analog switch in the event of an overvoltage in the input analog signal, thereby achieving overvoltage protection for the analog switch and subsequent analog circuits. The specific structure of the analog switch circuit with overvoltage protection in this integrated circuit chip will not be described in detail here.

[0078] In summary, compared with existing technologies, the analog switch circuit with overvoltage protection provided by this invention, through the technical solution of using a substrate selection unit to provide a bias voltage to the PMOS transistor body terminal and an overvoltage detection unit to generate a second and a third control signal to provide to the switching unit, controls the analog switch circuit to maintain or switch to the off state when an overvoltage occurs at the input terminal in either the off or on state. This avoids problems such as the analog switch failing to turn off, device damage, and performance degradation caused by input overvoltage, thus achieving overvoltage protection for the analog switch circuit and subsequent analog circuits. Therefore, the analog switch circuit with overvoltage protection provided by this invention has the advantages of ingenious and reasonable structural design, low design cost, high reliability, and excellent circuit performance.

[0079] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0080] The above provides a detailed description of the analog switch circuit and chip with overvoltage protection provided by this invention. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. An analog switching circuit with overvoltage protection, characterized in that... It includes a switching unit, a substrate selection unit, and an overvoltage detection unit; among which, The output terminal of the substrate selection unit is connected to the switching unit and the overvoltage detection unit, and the output terminal of the overvoltage detection unit is connected to the control terminal of the switching unit; the substrate selection unit is used to provide a body bias voltage for the PMOS transistors in the switching unit and the overvoltage detection unit. The switching unit includes a fifth PMOS transistor, a sixth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; wherein the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, and the drain of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor; the source of the fifth PMOS transistor and the source of the sixth NMOS transistor are connected in parallel to serve as the input terminal of the switching unit; the drain of the sixth PMOS transistor and the drain of the seventh NMOS transistor are connected in parallel to serve as the output terminal of the switching unit; the gate of the fifth PMOS transistor is connected to the second output terminal of the overvoltage detection unit, and the gate of the sixth PMOS transistor is connected to the first output terminal of the overvoltage detection unit; the gate of the sixth NMOS transistor is connected to the power supply voltage terminal, and the gate of the seventh NMOS transistor is connected to the first control signal terminal; The overvoltage detection unit includes a second control signal subunit and a third control signal subunit; wherein... The second control signal subunit includes a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first inverter, and a first OR gate. The source terminal of the third PMOS transistor is connected to the input terminal of the analog signal, the gate terminal is connected to the power supply voltage terminal, and the drain terminal is connected to the drain terminal of the first NMOS transistor. The gate terminal of the first NMOS transistor is connected to the power supply voltage terminal, and the source terminal is connected to the drain terminal of the second NMOS transistor and the first input terminal of the first OR gate. The gate terminal of the second NMOS transistor is connected to the bias voltage terminal, and the source terminal is connected to the drain terminal of the third NMOS transistor. The gate terminal of the third NMOS transistor is connected to the first control signal terminal, and the source terminal is connected to the ground potential terminal. The input terminal of the first inverter is connected to the first control signal terminal, and the output terminal is connected to the second input terminal of the first OR gate. The output terminal of the first OR gate serves as the first output terminal of the overvoltage detection unit. The third control signal subunit includes a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The source terminal of the fourth NMOS transistor is connected to the output terminal of the first OR gate, the gate terminal of the fourth NMOS transistor is connected to the first control signal terminal, and the drain terminal is connected to the source terminal of the fifth NMOS transistor. The gate terminal of the fifth NMOS transistor is connected to the power supply voltage terminal, and the drain terminal serves as the second output terminal of the overvoltage detection unit connected to the switching unit, and is also connected to the drain terminal of the fourth PMOS transistor. The gate terminal of the fourth PMOS transistor is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal.

2. The analog switch circuit with overvoltage protection as described in claim 1, characterized in that: When an overvoltage occurs at the input terminal of the analog switch circuit in the open state, the second control signal output by the overvoltage detection unit is at a high level; the third control signal is at a high level, and the voltage of the third control signal is equal to the voltage of the input analog signal.

3. The analog switch circuit with overvoltage protection as described in claim 1, characterized in that: When an overvoltage occurs at the input terminal of the analog switch circuit in the ON state, the second control signal output by the overvoltage detection unit is at a high level; the third control signal is at a high level, and the voltage of the third control signal is equal to the voltage of the input analog signal.

4. The analog switch circuit with overvoltage protection as described in claim 1, characterized in that: The substrate selection unit includes a first PMOS transistor and a second PMOS transistor; wherein... The body and drain terminals of the first PMOS transistor are short-circuited, the gate terminal is connected to the power supply voltage terminal, and the source terminal is connected to the input terminal of the input analog signal. The body and drain terminals of the second PMOS transistor are shorted together, the gate terminal is connected to the input terminal of the input analog signal, and the source terminal is connected to the power supply voltage terminal. The drain terminals of the first PMOS transistor and the second PMOS transistor are connected to each other and serve as the output terminal of the substrate selection unit.

5. An integrated circuit chip, characterized in that... Includes the analog switch circuit with overvoltage protection as described in any one of claims 1 to 4.

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