Heterogeneous implementation method, system and device of LDPC encoder and storage medium

Abstract

The invention relates to the technical field of communication encoding, in particular to a heterogeneous implementation method, system and device of an LDPC encoder and a storage medium. According to the heterogeneous implementation method of the LDPC encoder, a central processing unit (CPU) receives and stores information bits, code lengths, code rates, a basis matrix selection index table and a bit list, obtains a check matrix and parameters, and stores the check matrix and the parameters into a global memory of a parallel computing chip; the parallel computing chip is converted into a parallel form and then is stored in a shared memory, parallel coding computing is carried out, and check bit information is obtained; and the check bit information is sent back to the central processing unit CPU, and the check bit information and the information bits form final coding information. According to the heterogeneous implementation method, system and equipment of the LDPC encoder and the storage medium, the check bit calculation process is parallelized by utilizing the characteristic of flexible development of the CPU and the parallel calculation capability of the parallel calculation chip, the encoding process is further accelerated, and the throughput rate of the encoder is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of communication coding technology, and in particular to a heterogeneous implementation method, system, device and storage medium of an LDPC encoder. Background Art

[0002] In the process of continuous evolution of modern communication systems, 5G communication has become a key force in promoting the development of social digitalization with its high speed, low latency and large connection characteristics. In the 5G communication system, in order to ensure the accurate transmission of data in complex wireless environments, the 5G low-density parity-check code LDPC (Low-Density Parity-Check Code) coding protocol is adopted. As a linear block code with excellent performance, the low-density parity-check code LDPC has excellent error correction capabilities close to the Shannon limit, which makes it play a core role in the physical layer data transmission of 5G communication.

[0003] There are many limitations in the traditional implementation of low-density parity-check code (LDPC) encoders. Although the software implementation approach has certain flexibility, its encoding speed is far from meeting the real-time requirements, resulting in data processing delays and affecting communication quality. Although the implementation based on specific hardware circuits, such as application-specific integrated circuits (ASICs), can provide a higher encoding rate, it faces the problem of a long design cycle, and the flexibility of application-specific integrated circuits (ASICs) is extremely poor. Once the 5G communication standard adjusts or upgrades the low-density parity-check code (LDPC) encoding algorithm in subsequent development, the application-specific integrated circuits (ASICs) almost need to be redesigned and manufactured; field programmable gate arrays (FPGAs) are also used to implement low-density parity-check code (LDPC) encoders, but field programmable gate arrays (FPGAs) need to face the problems of insufficient logic resources, high development difficulty, and high cost.

[0004] Based on the above problems, the present invention proposes a heterogeneous implementation method, system, device and storage medium of an LDPC encoder. Summary of the invention

[0005] In order to overcome the defects of the prior art, the present invention provides a simple and efficient heterogeneous implementation method, system, device and storage medium of an LDPC encoder.

[0006] The present invention is achieved through the following technical solutions: A heterogeneous implementation method of an LDPC encoder, characterized by: Step S1, the central processing unit CPU receives and stores information bits, code length k, code rate R, and a base matrix selection index table and a bit list specified by the 5G low-density parity check code LDPC standard; Step S2, obtaining a check matrix and required parameter data in a central processing unit CPU by using the information received in step S1; In step S2, the check matrix is ​​calculated in the central processing unit CPU, and the obtained check matrix and corresponding parameters are adjusted in real time according to the transformation of the code length k and the code rate R. The implementation process is as follows: Step S2.1, determining the number of columns of the basis matrix and its information bits; According to the input code length k, code rate R, and base matrix selection index table and bit table specified in the 5G low-density parity check code LDPC standard, the corresponding base matrix is ​​determined, and the number of columns L of information bits in the matrix is ​​determined; Step S2.2, calculating the expansion factor Z; Calculate the expansion factor Z of the low-density parity check code LDPC, the calculation formula is as follows: ; Combined with the calculation results, a value of the expansion factor Z is selected from the expansion factor index list specified in the input 5G low-density parity-check code LDPC standard; Step S2.3, determine the number of rows m and columns n of the basis matrix; The calculation formula for the number of columns n of the basis matrix is ​​as follows: ; in, The quotient of the number of columns L of information bits in the base matrix divided by the code rate R is rounded up to an integer; The calculation formula for the number of rows m of the basis matrix is ​​as follows: ; Step S2.4, obtaining a cyclic shift matrix A; According to the value of the expansion factor Z, and in combination with the cyclic shift matrix list specified in the 5G low-density parity check code LDPC standard, a cyclic shift matrix A with m rows and L columns is obtained; Step S2.5, find the check matrix H; According to the expansion factor Z, the cyclic shift matrix list of the base matrix B area specified by the 5G low-density parity-check code LDPC standard is determined to obtain the cyclic shift matrix B, and then the cyclic shift matrix A and the cyclic shift matrix B are horizontally spliced ​​to obtain the check matrix H in the form of [AB].

[0007] Step S3, the central processing unit CPU transfers the check matrix, information bits and required parameter data to the global memory of the parallel computing chip; Step S4, reading the corresponding serial information bit data from the global memory of the parallel computing chip, converting it into a parallel form according to relevant parameters, and storing it in the shared memory; By using shared memory, the number of accesses to global memory is reduced, thereby improving data access efficiency; In step S4, the process of storing and segmenting the information bits in the parallel computing chip is as follows: Step S4.1, under the provisions of the 5G standard, the information bits of the input code length k are divided into L segments according to the scale parameter in the base matrix, and the size of each information bit segment is fixed to Z bits; Step S4.2: The information bits divided into L segments form L parallel information bits, and the L parallel information bits carry their respective segment information bits and are stored in parallel in the shared memory.

[0008] Step S5, performing parallel coding calculation in the parallel computing chip to obtain check bit information; through the parallel computing capability of the parallel computing chip, the check bit calculation process is parallelized to improve the throughput of the encoder; In step S5, the process of calculating the check matrix in the parallel computing chip is as follows: Step S5.1, in the parallel computing chip, the check matrix H is pre-stored in the global memory of the parallel computing chip, each thread is responsible for processing a partial operation related to the check bit calculation, and obtains the corresponding operation vector coefficient from the check matrix H according to the thread index; Step S5.2, the L-way parallel information bits are stored in the shared memory of the parallel computing chip, and after obtaining the operation vector coefficient, the thread performs matrix multiplication and addition operations on the L-way parallel information bits according to the obtained operation vector coefficient; Step S5.3: Obtain the value of the check bits [X1, X2, ..., Xm-1, Xm] through an XOR operation.

[0009] Step S6: Send the check bit information back to the central processing unit CPU to form the final coded information with the information bits.

[0010] In step S6, the process of generating the final coding information in the central processing unit CPU is as follows: Step S6.1, the central processing unit CPU receives the check bits [X1, X2, ..., Xm-1, Xm] calculated from the parallel computing chip; Step S6.2: The received check bits are serially concatenated with the information bits [Data1, Data2, …, DataL - 1, DataL] pre-stored in the memory space of the central processing unit CPU, and the information bits and the check bits are connected in sequence to generate the final coded information [Data1, Data2, …, DataL - 1, DataL,X1, X2, …, Xm-1, Xm].

[0011] A heterogeneous implementation system of an LDPC encoder, used to implement the above method, includes a central processing unit (CPU) and a parallel computing chip; The central processing unit CPU is responsible for receiving and storing information bits, code length k, code rate R, and base matrix selection index table and bit list specified in the 5G low-density parity check code LDPC standard, and using the received information to obtain the check matrix and required parameter data, and transmitting the check matrix and information bits and required parameter data to the parallel computing chip; in addition, the central processing unit CPU is also responsible for using information bits and check bits to form the final coding information; The memory of the parallel computing chip is divided into global memory and shared memory, which is responsible for realizing the storage and segmentation processing of information bits, obtaining segmented information bits and their segment information bits, and performing parallel coding calculations to obtain check bit information, and sending the check bit information back to the central processing unit CPU; Wherein, the global memory is responsible for storing the received check matrix and information bits and required parameter data; The shared memory is responsible for storing the segmented information bits and their segment information bits in parallel.

[0012] A heterogeneous implementation device of an LDPC encoder, characterized by comprising: One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the above methods.

[0013] A readable storage medium, characterized in that: a computer program is stored on the readable storage medium, and the computer program implements the above method when executed by a processor.

[0014] The beneficial effects of the present invention are as follows: the heterogeneous implementation method, system, device and storage medium of the LDPC encoder not only have the characteristics of development flexibility, but also can parallelize the check bit calculation process by utilizing the parallel computing capability of the parallel computing chip, thereby further accelerating the encoding process and greatly improving the throughput of the encoder. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Attached Figure 1 It is a schematic diagram of a heterogeneous implementation method of an LDPC encoder of the present invention.

[0017] Attached Figure 2 Schematic diagram of the calculation method of the check matrix in the CPU of the present invention.

[0018] Attached Figure 3 It is a schematic diagram of the information bit storage and segmentation processing method in GPGPU of the present invention.

[0019] Attached Figure 4 It is a schematic diagram of the method for implementing check bit calculation in GPGPU of the present invention.

[0020] Attached Figure 5 The figure is a schematic diagram of the combination of information bits and coding bits in the CPU of the present invention. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0022] With the rapid development of parallel computing chip technology, its application in the field of general computing has shown great potential. Parallel computing chips have numerous computing cores, which can process massive data threads in parallel at the same time and achieve a higher encoding rate. The central processing unit (CPU) has the characteristics of flexible development, and the central processing unit (CPU) is good at handling complex logic control and serial tasks. This heterogeneous mode can give full play to the respective advantages of the central processing unit (CPU) and the parallel computing chip, realize the optimal allocation of resources, and avoid the performance bottleneck caused by the functional limitations of a single processor. At the same time, heterogeneous systems also have advantages in flexibility. When the 5G communication standard or coding algorithm changes, the tasks can be flexibly redistributed between the central processing unit (CPU) and the parallel computing chip through software adjustment to adapt to new needs. Therefore, a method for implementing a 5G low-density parity check code LDPC encoder can be developed based on parallel computing chips and central processing units (CPU).

[0023] As attached Figure 1 As shown, the heterogeneous implementation method of the LDPC encoder includes the following steps: Step S1, the central processing unit CPU receives and stores information bits, code length k, code rate R, and a base matrix selection index table and a bit list specified by the 5G low-density parity check code LDPC standard; Step S2, obtaining a check matrix and required parameter data in a central processing unit CPU by using the information received in step S1; As attached Figure 2 As shown, in step S2, the check matrix is ​​calculated in the central processing unit CPU, and the obtained check matrix and corresponding parameters are adjusted in real time according to the transformation of the code length k and the code rate R. The implementation process is as follows: Step S2.1, determining the number of columns of the basis matrix and its information bits; According to the input code length k, code rate R, and base matrix selection index table and bit table specified in the 5G low-density parity check code LDPC standard, the corresponding base matrix is ​​determined, and the number of columns L of information bits in the matrix is ​​determined; Step S2.2, calculating the expansion factor Z; Calculate the expansion factor Z of the low-density parity check code LDPC, the calculation formula is as follows: ; Combined with the calculation results, a value of the expansion factor Z is selected from the expansion factor index list specified in the input 5G low-density parity-check code LDPC standard; Step S2.3, determine the number of rows m and columns n of the basis matrix; The calculation formula for the number of columns n of the basis matrix is ​​as follows: ; in, The quotient of the number of columns L of information bits in the base matrix divided by the code rate R is rounded up to an integer; The calculation formula for the number of rows m of the basis matrix is ​​as follows: ; Step S2.4, obtaining a cyclic shift matrix A; According to the value of the expansion factor Z, and in combination with the cyclic shift matrix list specified in the 5G low-density parity check code LDPC standard, a cyclic shift matrix A with m rows and L columns is obtained; Step S2.5, find the check matrix H; According to the expansion factor Z, the cyclic shift matrix list of the base matrix B area specified by the 5G low-density parity-check code LDPC standard is determined to obtain the cyclic shift matrix B, and then the cyclic shift matrix A and the cyclic shift matrix B are horizontally spliced ​​to obtain the check matrix H in the form of [AB].

[0024] Step S3, the central processing unit CPU transfers the check matrix, information bits and required parameter data to the global memory of the parallel computing chip; Step S4, reading the corresponding serial information bit data from the global memory of the parallel computing chip, converting it into a parallel form according to relevant parameters, and storing it in the shared memory; By using shared memory, the number of accesses to global memory is reduced, thereby improving data access efficiency; As attached Figure 3 As shown, in step S4, the process of storing and segmenting the information bits in the parallel computing chip is as follows: Step S4.1, under the provisions of the 5G standard, the information bits of the input code length k are divided into L segments according to the scale parameter in the base matrix, and the size of each information bit segment is fixed to Z bits; Step S4.2: The information bits divided into L segments form L parallel information bits, and the L parallel information bits carry their respective segment information bits and are stored in parallel in the shared memory.

[0025] Because the information bits need to be called repeatedly when calculating the check bits, storing them in shared memory can reduce the number of accesses to the global memory and improve data access efficiency.

[0026] Step S5, performing parallel coding calculation in the parallel computing chip to obtain check bit information; through the parallel computing capability of the parallel computing chip, the check bit calculation process is parallelized to improve the throughput of the encoder; As attached Figure 4 As shown, in step S5, the process of calculating the check matrix in the parallel computing chip is as follows: Step S5.1, in the parallel computing chip, the check matrix H is pre-stored in the global memory of the parallel computing chip, each thread is responsible for processing a partial operation related to the check bit calculation, and obtains the corresponding operation vector coefficient from the check matrix H according to the thread index; The Thread class is the basic class for implementing multithreaded programming. Each thread is described by an instance of the Thread class. For example, Thread 1 obtains the coefficients of the operation vector related to the calculation of check digit 1 from the first row of matrix H, Thread 2 obtains the coefficients related to the calculation of check digit 2 from the first row of matrix A, and so on.

[0027] Step S5.2, the L-way parallel information bits are stored in the shared memory of the parallel computing chip, and after obtaining the operation vector coefficient, the thread performs matrix multiplication and addition operations on the L-way parallel information bits according to the obtained operation vector coefficient; Step S5.3: Obtain the value of the check bits [X1, X2, ..., Xm-1, Xm] through an XOR operation.

[0028] Step S6: Send the check bit information back to the central processing unit CPU to form the final coded information with the information bits.

[0029] As attached Figure 5 As shown, in step S6, the process of generating the final coding information in the central processing unit CPU is as follows: Step S6.1, the central processing unit CPU receives the check bits [X1, X2, ..., Xm-1, Xm] calculated from the parallel computing chip; Step S6.2: The received check bits are serially concatenated with the information bits [Data1, Data2, …, DataL - 1, DataL] pre-stored in the memory space of the central processing unit CPU, and the information bits and the check bits are connected in sequence to generate the final coded information [Data1, Data2, …, DataL - 1, DataL,X1, X2, …, Xm-1, Xm].

[0030] The heterogeneous implementation system of the LDPC encoder is used to implement the above method, including a central processing unit CPU and a parallel computing chip; The central processing unit CPU is responsible for receiving and storing information bits, code length k, code rate R, and base matrix selection index table and bit list specified in the 5G low-density parity check code LDPC standard, and using the received information to obtain the check matrix and required parameter data, and transmitting the check matrix and information bits and required parameter data to the parallel computing chip; in addition, the central processing unit CPU is also responsible for using information bits and check bits to form the final coding information; The memory of the parallel computing chip is divided into global memory and shared memory, which is responsible for realizing the storage and segmentation processing of information bits, obtaining segmented information bits and their segment information bits, and performing parallel coding calculations to obtain check bit information, and sending the check bit information back to the central processing unit CPU; Wherein, the global memory is responsible for storing the received check matrix and information bits and required parameter data; The shared memory is responsible for storing the segmented information bits and their segment information bits in parallel.

[0031] The heterogeneous implementation device of the LDPC encoder includes: One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing any of the above methods.

[0032] The readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0033] In summary, the heterogeneous implementation method, system, device and storage medium of the LDPC encoder can efficiently complete data preprocessing and obtain the required parameters, as well as complete the final serial coding information data splicing through the central processing unit CPU; the parallel computing chip side uses its fast parallel computing capability to parallelize the check bit calculation process, greatly shortening the encoding time and further improving the encoder throughput.

[0034] The embodiment described above is only one specific implementation of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A heterogeneous implementation method of an LDPC encoder, characterized in that: The following steps are involved: Step S1, the central processing unit CPU receives and stores information bits, code length k, code rate R, and a base matrix selection index table and a bit list specified by the 5G low-density parity check code LDPC standard; Step S2, obtaining a check matrix and required parameter data in a central processing unit CPU by using the information received in step S1; Step S3, the central processing unit CPU transfers the check matrix, information bits and required parameter data to the global memory of the parallel computing chip; Step S4, reading the corresponding serial information bit data from the global memory of the parallel computing chip, converting it into a parallel form according to relevant parameters, and storing it in the shared memory; By using shared memory, the number of accesses to global memory is reduced, thereby improving data access efficiency; Step S5, performing parallel coding calculation in the parallel computing chip to obtain check bit information; through the parallel computing capability of the parallel computing chip, the check bit calculation process is parallelized to improve the throughput of the encoder; Step S6: Send the check bit information back to the central processing unit CPU to form the final coded information with the information bits.

2. The heterogeneous implementation method of the LDPC encoder according to claim 1, characterized in that: In step S2, the check matrix is ​​calculated in the central processing unit CPU, and the obtained check matrix and corresponding parameters are adjusted in real time according to the transformation of the code length k and the code rate R. The implementation process is as follows: Step S2.1, determining the number of columns of the basis matrix and its information bits; According to the input code length k, code rate R, and base matrix selection index table and bit table specified in the 5G low-density parity check code LDPC standard, the corresponding base matrix is ​​determined, and the number of columns L of information bits in the matrix is ​​determined; Step S2.2, calculating the expansion factor Z; Calculate the expansion factor Z of the low-density parity check code LDPC, the calculation formula is as follows: ； Combined with the calculation results, a value of the expansion factor Z is selected from the expansion factor index list specified in the input 5G low-density parity-check code LDPC standard; Step S2.3, determine the number of rows m and columns n of the basis matrix; The calculation formula for the number of columns n of the basis matrix is ​​as follows: ； in, The quotient of the number of columns L of information bits in the base matrix divided by the code rate R is rounded up to an integer; The calculation formula for the number of rows m of the basis matrix is ​​as follows: ； Step S2.4, obtaining a cyclic shift matrix A; According to the value of the expansion factor Z, and in combination with the cyclic shift matrix list specified in the 5G low-density parity check code LDPC standard, a cyclic shift matrix A with m rows and L columns is obtained; Step S2.5, find the check matrix H; According to the expansion factor Z, the cyclic shift matrix list of the base matrix B area specified by the 5G low-density parity-check code LDPC standard is determined to obtain the cyclic shift matrix B, and then the cyclic shift matrix A and the cyclic shift matrix B are horizontally spliced ​​to obtain the check matrix H in the form of [AB].

3. The heterogeneous implementation method of the LDPC encoder according to claim 2, characterized in that: In step S4, the process of storing and segmenting the information bits in the parallel computing chip is as follows: Step S4.1, under the provisions of the 5G standard, the information bits of the input code length k are divided into L segments according to the scale parameter in the base matrix, and the size of each information bit segment is fixed to Z bits; Step S4.2: The information bits divided into L segments form L parallel information bits, and the L parallel information bits carry their respective segment information bits and are stored in parallel in the shared memory.

4. The heterogeneous implementation method of the LDPC encoder according to claim 3, characterized in that: In step S5, the process of calculating the check matrix in the parallel computing chip is as follows: Step S5.1, in the parallel computing chip, the check matrix H is pre-stored in the global memory of the parallel computing chip, each thread is responsible for processing a partial operation related to the check bit calculation, and obtains the corresponding operation vector coefficient from the check matrix H according to the thread index; Step S5.2, the L-way parallel information bits are stored in the shared memory of the parallel computing chip, and after obtaining the operation vector coefficient, the thread performs matrix multiplication and addition operations on the L-way parallel information bits according to the obtained operation vector coefficient; Step S5.3: Obtain the value of the check bits [X1, X2, ..., Xm-1, Xm] through an XOR operation.

5. The heterogeneous implementation method of the LDPC encoder according to claim 4, characterized in that: In step S6, the process of generating the final coding information in the central processing unit CPU is as follows: Step S6.1, the central processing unit CPU receives the check bits [X1, X2, ..., Xm-1, Xm] calculated from the parallel computing chip; Step S6.2: The received check bits are serially concatenated with the information bits [Data1, Data2, …, DataL - 1, DataL] pre-stored in the memory space of the central processing unit CPU, and the information bits and the check bits are connected in sequence to generate the final coded information [Data1, Data2, …, DataL - 1, DataL,X1, X2, …, Xm-1, Xm].

6. A heterogeneous implementation system of an LDPC encoder, characterized in that: The method according to any one of claims 1 to 5, comprising a central processing unit (CPU) and a parallel computing chip; The central processing unit CPU is responsible for receiving and storing information bits, code length k, code rate R, and base matrix selection index table and bit list specified in the 5G low-density parity check code LDPC standard, and using the received information to obtain the check matrix and required parameter data, and transmitting the check matrix and information bits and required parameter data to the parallel computing chip; in addition, the central processing unit CPU is also responsible for using information bits and check bits to form the final coding information; The memory of the parallel computing chip is divided into global memory and shared memory, which is responsible for realizing the storage and segmentation processing of information bits, obtaining segmented information bits and their segment information bits, and performing parallel coding calculations to obtain check bit information, and sending the check bit information back to the central processing unit CPU; Wherein, the global memory is responsible for storing the received check matrix and information bits and required parameter data; The shared memory is responsible for storing the segmented information bits and their segment information bits in parallel.

7. A heterogeneous implementation device of an LDPC encoder, characterized in that: include: One or more processors, one or more memories, and one or more programs, wherein the one or more programs are stored in the one or more memories and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing the method according to any one of claims 1 to 5.

8. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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