Circuit substrate

Abstract

The invention discloses a circuit substrate. The circuit substrate comprises a core board, first dielectric layers stacked with each other, second dielectric layers stacked with each other and a first wire, the first dielectric layer is disposed on the core board. The first dielectric layer and the second dielectric layer are formed of different materials and have different thicknesses. The first lead is disposed in the first dielectric layer and the second dielectric layer. The first conductive line includes a first line segment, a second line segment, first conductive holes stacked on each other, and second conductive holes stacked on each other. The first line segment and the second line segment are arranged between the first dielectric layer and the second dielectric layer. The first conductive hole penetrates through the first dielectric layer and is connected with the first line segment. The second conductive hole penetrates through the second dielectric layer and is connected with the first conductive hole and the second line segment.

Description

Technical Field

[0001] The present invention relates to a circuit substrate, and in particular to a wiring structure of the circuit substrate. Background Art

[0002] In the current semiconductor packaging technology, in order to cope with the continuous increase in the operating frequency and power consumption of integrated circuit chips, as well as the requirements of multi-chip integrated packaging and multi-input / output (I / O) end chips, the operating frequency and wiring density of printed circuit boards must be increased accordingly. However, in the application of high-performance computing (HPC) printed circuit boards, maintaining good signal integrity (SI) is becoming increasingly important.

[0003] Therefore, in this technical field, there is a need for an improved printed circuit board. Summary of the invention

[0004] The embodiment of the present invention provides a circuit substrate, including a core board, a plurality of first dielectric layers stacked on each other, a plurality of second dielectric layers stacked on each other, and a first conductive wire. The plurality of first dielectric layers are arranged on the first surface of the core board. Each of the first dielectric layers is formed of a first material and has a first thickness. The plurality of second dielectric layers are arranged below the first dielectric layer. Each of the second dielectric layers is formed of a second material and has a second thickness. The first conductive wire is arranged in the first dielectric layer and the second dielectric layer. The first conductive wire includes a first line segment, a second line segment, a plurality of first conductive holes stacked on each other, and a plurality of second conductive holes stacked on each other. The first line segment is arranged between the first dielectric layers. The second line segment is arranged between the second dielectric layers. The plurality of first conductive holes penetrate the plurality of first dielectric layers and connect the first line segments. The plurality of second conductive holes penetrate the plurality of second dielectric layers and connect the plurality of first conductive holes and the second line segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to make the features and advantages of the present invention more clearly understood, different embodiments are described in detail below with reference to the accompanying drawings:

[0006] Figure 1 Schematic cross-sectional view of a circuit substrate according to some embodiments of the present invention;

[0007] Figure 2A It is a schematic diagram of an exploded view of a conductive layer of some layers of a circuit substrate of some embodiments of the present invention;

[0008] Figure 2B for Figure 2A A partial enlarged view of

[0009] Figure 2C for Figure 2AA partial enlarged view of

[0010] Figure 2D for Figure 2A A partial enlarged view of

[0011] Figure 3A It is a schematic diagram of an exploded view of a conductive layer of some layers of a circuit substrate of some embodiments of the present invention;

[0012] Figure 3B for Figure 3A A partial enlarged view of

[0013] Figure 3C for Figure 3A A partial enlarged view of

[0014] Figure 3D for Figure 3A A partial enlarged view of

[0015] Figure 4A It is a schematic diagram of an exploded view of a conductive layer of some layers of a circuit substrate of some embodiments of the present invention;

[0016] Figure 4B for Figure 4A A partial enlarged view of

[0017] Figure 4C for Figure 4A A partial enlarged view of

[0018] Figure 4D for Figure 4A A partial enlarged view of

[0019] Figure 4E for Figure 4A A partial enlarged view of

[0020] Figure 5 Schematic cross-sectional view of a circuit substrate according to some embodiments of the present invention;

[0021] Figure 6 Schematic cross-sectional views of circuit substrates according to some embodiments of the present invention.

[0022] Explanation of symbols

[0023] 200: Core board

[0024] 200T: First surface

[0025] 200B: Second surface

[0026] 200V: Core conductive vias

[0027] 210, 210T, 210B, 220, 230: Dielectric layer

[0028] 222,232: solder mask

[0029] 240T, 240B: Internal wiring structure

[0030] 250T, 250B: External wiring structure

[0031] 260: Conductive bump

[0032] 270:Solder bump

[0033] 500A, 500B, 500C: Circuit board

[0034] CL1,CL2,CL1',CL2',CL1",CL2",CL1A,CL1B,CL2A,CL2B: Wire

[0035] CL1-1,CL1-2,CL1-2',CL2-1,CL2-2,CL2-2',CL1A-1,

[0036] CL1B-1, CL1A-2, CL1B-2, CL1A-1, CL1B-1, CL1A-2,

[0037] CL1B-2,CL2A-1,CL2B-1,CL2A-2,CL2B-2: Line segment

[0038] D1,D2: diameter

[0039] D100,D110,D120: Direction

[0040] GL: Ground layer

[0041] L1,L2,L3,L4,L5,L6,L7,L8,L9,L10,L11,L12,L13,L14,L15,

[0042] L16, L17, L18: Layer

[0043] P1, P2: Line length

[0044] T210, T220, T230: Thickness

[0045] TV1-1,TV1-2,TV1-3,TV2-1,TV2-2,TV2-3,TV1-3',

[0046] TV2-1',TV2-3',TV1-3”,TV2-3”,TV1A-1,TV1B-1,

[0047] TV2A-1, TV2B-1, TV1A-3, TV1B-3, TV2A-3, TV2B-3: Conductive hole stacking

[0048] TV1-1A,TV1-1B,TV1-2A,TV1-3A,TV1-3B,TV2-1A,

[0049] TV2-1B, TV2-2A, TV2-3A, TV2-3B: Conductive holes

[0050] W1,W2: Line width

[0051] TVG: Grounding conductive hole DETAILED DESCRIPTION

[0052] The present invention is described more fully below with reference to the accompanying drawings of embodiments of the present invention. However, the present invention may also be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the accompanying drawings may be exaggerated for clarity, and the same or similar reference numbers in the various drawings represent the same or similar elements.

[0053] Figure 1 FIG. 5 is a schematic cross-sectional view of a circuit substrate 500A according to some embodiments of the present invention. Figure 2A FIG. 5 is a schematic diagram of an exploded view of a conductive layer of a partial layer of a circuit substrate 500A according to some embodiments of the present invention. Figure 2B , Figure 2C , Figure 2D for Figure 2A The enlarged view of the part shows the arrangement of the wire, the ground layer and the ground conductive hole. In some embodiments, the circuit substrate 500A can be a multi-layer packaging substrate, and the top and bottom surfaces thereof can provide integrated circuit chips and solder bumps mounted thereon, respectively. Figure 1 The circuit substrate 500A shown is an 18-layer circuit substrate as an example, wherein the conductive layers from the top layer to the bottom layer are labeled in sequence as layer L1, layer L2, ... layer L18. Moreover, each conductive layer may include a conductor, a ground layer, or a combination thereof. The number of conductive layers of the circuit substrate 500A of the present invention may be determined according to the setting and is not limited to the disclosed embodiment. Furthermore, Figure 1 , Figure 2A to Figure 2D The directions D100 and D110 indicated in the subsequent figures are defined as horizontal directions (also regarded as the extending directions of the conductive wires / transmission lines), and the direction D120 is defined as the vertical direction (also regarded as the extending direction of the via holes).

[0054] like Figure 1 As shown, the circuit substrate 500A may include a core board 200 , a plurality of dielectric layers 210 , 220 , 230 , and a wire CL1 .

[0055] The core board 200 has a first surface 200T and a second surface 200B opposite to each other. In some embodiments, the first surface 200T may be a chip side surface, and the second surface 200B may be a solder bump side surface. In some embodiments, the material of the core board 200 may include paper phenolic resin, composite epoxy resin, polyimide resin, maleimide triazine resin (Bismaleimide-Triazineresin, BT resin) or a composite material containing glass fiber reinforced resin.

[0056] The core board 200 also has a core conductive through hole 200V. The core conductive through hole 200V runs through the core board 200, and the two ends of the core conductive through hole 200V can be aligned with the first surface 200T and the second surface 200B of the core board 200, respectively. In some embodiments, the core conductive through hole 200V can be a solid cylinder or a hollow cylinder. In some embodiments, the material of the core conductive through hole 200V can be copper or a copper alloy or a conductive metal, and the core conductive through hole 200V can be formed by a laser drilling process and an electroplating process. In some embodiments, the core conductive through hole 200V can be a solid cylinder or a hollow cylinder filled with a plugging material. The plugging material includes a resin, a silver glue, or an ink.

[0057] like Figure 1 As shown, a plurality of dielectric layers 210 (including dielectric layers 210T and 210B) stacked on each other are symmetrically arranged on the first surface 200T and the second surface 200B of the core board 200. In other words, the first surface 200T and the second surface 200B of the core board 200 are provided with dielectric layers 210T and 210B of the same number of layers. In the present embodiment, there are 4 dielectric layers 210T and 210B on the first surface 200T and the second surface 200B of the core board 200, respectively. The material of the dielectric layers 210T and 210B may include bismaleimide triazine resin (Bismaleimide Triazine resin, BT resin), prepreg (Prepreg, PP), FR-4, FR-5, or a combination thereof. The dielectric layers 210T and 210B may contain glass fibers. Therefore, the dielectric layers 210T and 210B may be formed using a hot pressing (lamitation) manufacturing process. In some embodiments, the single dielectric layer 210T, 210B has a thickness T210.

[0058] A plurality of dielectric layers 220 stacked on each other are arranged on the dielectric layer 210T. In the present embodiment, the dielectric layer 210T located at the first surface 200T of the core board 200 is arranged between the dielectric layer 220 and the core board 200. In other words, the dielectric layer 220 can be separated from the core board 200 by the dielectric layer 210T. In some embodiments, there is no other type of dielectric layer between the dielectric layer 210T and the core board 200. In some embodiments, the material of the dielectric layer 220 may include polybenzoxazole (polybenzoxazole, PBO), benzocyclobutene (benzocyclobutene, BCB), polyimide (polyimide, PI), ABF film (ajinomoto build-up film), resin coated copper foil (resin coated copper, RCC), or the above combination. The dielectric layer 220 may not contain glass fiber. Therefore, the dielectric layer 220 can be formed using a coating (coating) or a lamination manufacturing process. In some embodiments, a single dielectric layer 220 has a thickness T220. It is worth noting that compared to the prior art, multiple dielectric layers stacked on each other using the same material are used on the same side of the core board, but in this embodiment, the dielectric layer 210T close to the core board 200 and the dielectric layer 220 away from the core board 200 are formed of different materials.

[0059] like Figure 1 As shown, the circuit substrate 500A also includes a plurality of dielectric layers 230, which are arranged on the dielectric layer 210B. In the present embodiment, the dielectric layer 210B located on the second surface 200B of the core board 200 is arranged between the dielectric layer 230 and the core board 200. In other words, the dielectric layer 230 can be separated from the core board 200 by the dielectric layer 210B. In some embodiments, the dielectric layer 220 and the dielectric layer 230 away from the core board 200 can be formed by the same material. In addition, the thickness T230 of a single dielectric layer 230 can be the same as the thickness T220 of a single dielectric layer 220. In some embodiments, a multi-pass build-up process can be used to simultaneously form the same number of layers (e.g., 4 layers) and symmetrical dielectric layers 220 and dielectric layers 230 on both sides of the core board 200.

[0060] In some embodiments, the dielectric layer 210 has a higher mechanical strength than the dielectric layers 220 and 230 due to the presence of glass fibers. In addition, corresponding to the material and manufacturing process characteristics of the dielectric layers 210, 220, and 230, the thickness T210 of the dielectric layer 210 is different from the thickness T220 of the dielectric layer 220, and is different from the thickness T230 of the dielectric layer 230. In some embodiments, the thickness T220 of the dielectric layer 220 and the thickness T230 of the dielectric layer 230 are both smaller than the thickness T210 of the dielectric layer 210. For example, the thickness T220 of the dielectric layer 220 and the thickness T230 of the dielectric layer 230 are approximately between 20 μm and 40 μm, and the thickness T210 of the dielectric layer 210 is approximately greater than or equal to 60 μm. In some embodiments, a ratio of the thickness T210 of the dielectric layer 210 to the thickness T220 of the dielectric layer 220 may be greater than or equal to 1.5, and a ratio of the thickness T210 of the dielectric layer 210 to the thickness T230 of the dielectric layer 230 may be greater than or equal to 1.5.

[0061] The circuit substrate 500A further includes a plurality of conductive layers (not shown) alternately disposed with the dielectric layers 210, 220, 230 and a plurality of conductive vias penetrating the dielectric layers 210, 220, 230. Furthermore, the conductive line CL1 is formed by electrically connecting the conductive layers and the conductive vias.

[0062] In some embodiments, the dielectric layer 210 close to the first surface 200T and the second surface 200B of the core board 200, the conductive layer alternately arranged with the dielectric layer 210, and the conductive hole penetrating the dielectric layer 210 form the inner wiring structure 240T, 240B. The dielectric layer 220 far away from the core board 200, the conductive layer alternately arranged with the dielectric layer 220, and the conductive hole penetrating the dielectric layer 220 form the outer wiring structure 250T. And, the dielectric layer 230 far away from the core board 200, the conductive layer alternately arranged with the dielectric layer 230, and the conductive hole penetrating the dielectric layer 230 form the outer wiring structure 250B. In some embodiments, corresponding to the material and manufacturing process characteristics of the dielectric layers 210, 220, and 230, the wiring density of the inner wiring structure 240T, 240B is less than the wiring density of the outer wiring structure 250T, 250B. Furthermore, the conductor width and the spacing between the inner wiring structures 240T and 240B are greater than the conductor width and the spacing between the outer wiring structures 250T and 250B.

[0063] In the present embodiment, the conductor CL1 is disposed in the inner wiring structures 240T, 240B and the outer wiring structures 250T, 250B. For example, the conductor CL1 is disposed in the dielectric layers 210, 220, 230. In addition, the two ends of the conductor CL1 are respectively connected to the conductive bump 260 of the integrated circuit chip (not shown) disposed on the first surface (chip side surface) 200T and the solder bump 270 disposed on the second surface (solder bump surface) 200B. In some embodiments, the conductor CL1 includes line segments CL1-1, CL1-2 and a conductive via stack TV1-1.

[0064] In this embodiment, the line segments CL1-1 and CL1-2 of the conductor CL1 are both located in the conductive layer above the first surface 200T of the core board 200. The line segment CL1-1 is located in the outer wiring structure 250T and is disposed between adjacent dielectric layers 220. The line segment CL1-2 is located in the inner wiring structure 240T and is disposed between adjacent dielectric layers 210T. For example, the line segment CL1-1 is formed by the conductive layer located in the layer L2, and the line segment CL1-2 is formed by the conductive layer located in the layer L6. In some embodiments, the line segment CL1-1 has a line length P1 and a line width W1, and the line segment CL1-2 has a line length P2 and a line width W2.

[0065] The line segments CL1-1 and CL1-2 of the conductive line CL1 may extend in the horizontal direction (direction D100) and do not overlap each other in the vertical direction (direction D120). In some embodiments, the line segments CL1-1 and CL1-2 of the conductive line CL1 may be connected to each other through the conductive via stack TV1-1.

[0066] In some embodiments, the conductive via stack TV1-1 includes conductive vias TV1-1A and TV1-1B stacked on each other along a direction D120. The conductive via TV1-1A is located in the outer wiring structure 250T and penetrates the dielectric layer 220. The conductive via TV1-1B is located in the inner wiring structure 240T and penetrates the dielectric layer 210T. The conductive vias TV1-1A and TV1-1B overlap with each other in the direction D120. In some embodiments, the conductive vias TV1-1A and TV1-1B do not overlap with each other in the direction D120 due to design limitations, or there may be a limit on the number of stackings, depending on demand. In some embodiments, the conductive via TV1-1A connects one end of the line segment CL1-1, and the conductive via TV1-1B connects the conductive via TV1-1A and one end of the line segment CL1-2. Figure 1 As shown, in some embodiments, the cross-sectional shape of the conductive holes TV1-1A and TV1-1B is conical. The diameter D1 of the conductive hole TV1-1A gradually narrows toward the core board 200. In addition, the diameter D2 of the conductive hole TV1-1B is larger than the diameter D1 of the conductive hole TV1-1A and gradually narrows toward the core board 200.

[0067] In some embodiments, the conductor CL1 may further include a conductive via stack TV1-2. The two ends of the conductive via stack TV1-2 are respectively connected to the line segment CL1-1 and the conductive bump 260. Furthermore, the opposite ends of the line segment CL1-1 are respectively connected to the conductive via stacks TV1-1 and TV1-2. In some embodiments, the conductive via stack TV1-2 includes one or more conductive vias TV1-2A. In some embodiments, the conductive via TV1-1A and the conductive via TV1-2A may have the same structure. Furthermore, the number of the conductive vias TV1-2A depends on the number of dielectric layers disposed between the conductive bump 260 and the line segment CL1-1, and is not limited to the disclosed embodiments. In the present embodiment, the number of the conductive vias TV1-2A is 1.

[0068] In some embodiments, the line segment CL1 - 1 of the conductive line CL1 is directly connected to the conductive bump 260 through the conductive via TV1 - 2A. In other words, there is no other line segment in the outer wiring structure 250T between the line segment CL1 - 1 of the conductive line CL1 and the conductive bump 260 .

[0069] In some embodiments, the conductor CL1 may further include a conductive hole stack TV1-3. The two ends of the conductive hole stack TV1-3 are respectively connected to the line segment CL1-2 and the solder bump 270. In addition, the opposite ends of the line segment CL1-2 are respectively connected to the conductive hole stacks TV1-1 and TV1-3. In some embodiments, the conductive hole stack TV1-3 includes conductive holes TV1-3A and TV1-3B stacked on each other along the direction D120. When the line segment CL1-2 is arranged above the first surface 200T of the core board 200, the conductive holes TV1-3B stacked on each other may be located in the inner wiring structure 240T, 240B, and penetrate the dielectric layer 210T, 210B, so that the core conductive through hole 200V is located between the two conductive holes TV1-3B. The conductive holes TV1-3A stacked on each other may be located in the outer wiring structure 250B and penetrate the dielectric layer 230. The conductive holes TV1-3A and TV1-3B overlap each other in the direction D120. In some embodiments, the conductive hole TV1-1A and the conductive hole TV1-3A may have similar structures and sizes. The diameter of the conductive hole TV1-3A is equal to the diameter D1 of the conductive hole TV1-1A, and gradually narrows toward the core board 200. In some embodiments, the conductive hole TV1-1B and the conductive hole TV1-3B may have similar structures and sizes, and are mirror-imaged. The diameter of the conductive hole TV1-3B located in the inner wiring structure 240T is equal to the diameter D2 of the conductive hole TV1-1B, and gradually narrows toward the core board 200, while the diameter of the conductive hole TV1-3B located in the inner wiring structure 240B is equal to the diameter D2 of the conductive hole TV1-1B, and gradually narrows toward the core board 200. In addition, the number of conductive holes TV1-3A and TV1-3B depends on the number of dielectric layers 210 and 230 disposed between the solder bump 270 and the line segment CL1-2, and is not limited to the disclosed embodiments. In the present embodiment, the number of conductive holes TV1-3A is 4, and the number of conductive holes TV1-3B is 7.

[0070] In some embodiments, the line segment CL1-2 of the conductive line CL1 is directly electrically connected to the solder bump 270 through the conductive vias TV1-3A and TV1-3B. In other words, there is no other line segment in the outer wiring structure 250B between the line segment CL1-2 of the conductive line CL1 and the solder bump 270, but this embodiment is not limited thereto.

[0071] Since the line width and spacing of the outer wiring structure 250T are smaller than the line width and spacing of the inner wiring structure 240T, in the conductor CL1, the line width W2 of the line segment CL1-2 is larger than the line width W1 of the line segment CL1-1, and the diameter D2 of the conductive hole TV1-1B is larger than the diameter D1 of the conductive hole TV1-1A, so as to improve the electrical performance such as impedance matching, reflection coefficient and insertion loss. On the other hand, in the conductor CL1, the line width W1 of the line segment CL1-1 is smaller than the line width W2 of the line segment CL1-2, and the diameter D1 of the conductive hole TV1-2A is smaller than the diameter D2 of the conductive hole TV1-1B, so that it is suitable for electrical connection with an integrated circuit chip with a smaller line width. In other words, when transmitting a signal through the conductor CL1, because the conductor CL1 is configured in at least two different levels of conductive layers, it will pass through at least two dielectric layers 210 and 220. The line width of the line segment CL1-1 in the dielectric layer 220 is relatively thin, so it is suitable for connecting to the integrated circuit chip, while the line width of the line segment CL1-2 in the dielectric layer 210 is relatively wide, which can be used to improve electrical performance such as impedance matching, reflection coefficient and insertion loss. In some embodiments, the line length P1 of the line segment CL1-1 can be greater than, less than or equal to the line length P2 of the line segment CL1-2. For example, the line length P2 of the line segment CL1-2 is between 20% and 85% of the sum of the line lengths P1 and P2 (P1+P2). If the line length P2 of the line segment CL1-2 is less than 20% of the sum of the line lengths P1 and P2 (P1+P2), the degree of electrical improvement is not significant. If the line length P2 of the line segment CL1-2 is greater than 85% of the sum of the line lengths P1 and P2 (P1+P2), the area occupied by the wire CL1 will be too large, thereby increasing the area of ​​the circuit substrate 500A and the manufacturing process cost.

[0072] The conductive layer of the circuit substrate 500A further includes a plurality of ground layers GL located at layers L1, L2, ..., L18. In some embodiments, part of the ground layer GL is located at layers (e.g., layers L1, L3, L5, L7) adjacent to the line segments CL1-1 and CL1-2. The ground layer GL is located directly above or directly below the line segments CL1-1 and CL1-2, and the projection (vertical projection) of the line segments CL1-1 and CL1-2 in the direction D120 is located within the ground layer GL of the adjacent layer.

[0073] In some embodiments, a portion of the ground layer GL may be located at other layers (e.g., layer L4) disposed between the line segments CL1-1 and CL1-2. The ground layer GL may be disposed between the dielectric layers 210, 220, and 230, depending on the layer positions of the line segments CL1-1 and CL1-2. Furthermore, the ground layer GL may surround the conductive vias TV1-1A, TV1-1B, TV1-2A, TV1-3A, and TV1-3B used to connect the line segments CL1-1 and CL1-2.

[0074] In some embodiments, part of the ground layer GL may also be located at the same level as the line segments CL1-1 and CL1-2 (e.g., level L2, L6). For example, the ground layer GL located at level L2 has an opening (not shown) corresponding to the line segment CL1-1, so as to be separated from the line segment CL1-1 and surround the line segment CL1-1. The ground layer GL located at level L6 has an opening (not shown) corresponding to the line segment CL1-2, so as to be separated from the line segment CL1-2 and surround the line segment CL1-2. In this way, the line segments CL1-1 and CL1-2 can be disposed between the ground layers GL in both the horizontal direction (directions D100, D110) and the vertical direction (direction D120).

[0075] In some embodiments, the circuit substrate 500A further includes a plurality of ground conductive vias TVG ( Figure 2A , Figure 2B , Figure 2C , Figure 2D ). The ground conductive via TVG penetrates the dielectric layers 210, 220, 230 and surrounds the conductive vias TV1-1A, TV1-1B, TV1-2A, TV1-1A, TV1-1B to connect multiple ground layers GL surrounding the line segments CL1-1, CL1-2 and the conductive vias TV1-1A, TV1-1B, TV1-2A, TV1-1A, TV1-1B. For example, the ground conductive via TVG can connect multiple ground layers GL of the layers L1, L2, ..., L18.

[0076] In some embodiments, the projection (vertical projection) of the ground conductive vias TVG in the direction D120 may be arranged around the ends of the line segments CL1-1 and CL1-2 and the conductive vias TV1-1A, TV1-1B, TV1-2A, TV1-3A, and TV1-3B. In addition, the ground conductive vias TVG may be symmetrically arranged relative to the ends of the line segments CL1-1 and CL1-2 and the conductive vias TV1-1A, TV1-1B, TV1-2A, TV1-3A, and TV1-3B.

[0077] The circuit substrate 500A may further include a conductive line CL2 disposed in parallel with the conductive line CL1 .

[0078] Similar to the conductor CL1, the conductor CL2 is disposed in the inner wiring structure 240T, 240B and the outer wiring structure 250T, 250B. In the present embodiment, the conductors CL1 and CL2 may be separated from each other by the ground layer GL and the ground conductive via TVG. In addition, the two ends of the conductor CL2 are respectively connected to another conductive bump 260 of the integrated circuit chip (not shown) disposed above the first surface (chip side surface) 200T and another solder bump 270 disposed above the second surface (solder bump surface) 200B. In some embodiments, the conductor CL2 includes line segments CL2-1, CL2-2 and conductive via stacks TV2-1, TV2-2, and TV2-3.

[0079] The line segments CL2-1 and CL2-2 of the conductor CL2 are respectively located in the outer wiring structure 250T and the inner wiring structure 240T of the first surface 200T of the core board 200. In addition, the line segments CL2-1 and CL2-2 are respectively arranged between the dielectric layer 220 and the dielectric layer 210 suitable for different line width manufacturing processes. In this embodiment, the line segments CL2-1 and CL2-2 of the conductor CL2 and the line segments CL1-1 and CL1-2 of the conductor CL1 are located at different conductive layers. For example, the line segment CL2-1 is located below the line segment CL1-1, which is formed by the conductive layer located at the layer L4. The line segment CL2-2 is located below the line segment CL1-2, which is formed by the conductive layer located at the layer L8. In the vertical direction (direction D120), at least one layer of ground layer GL may be provided between line segments CL1-1, CL1-2 and between line segments CL2-1, CL2-2 to ensure that line segments CL1-1, CL1-2 of conductor CL1 and line segments CL2-1, CL2-2 of conductor CL2 are covered by ground layers GL of upper and lower adjacent layers. In some embodiments, line segments CL1-1, CL1-2 of conductor CL1 and line segments CL2-1, CL2-2 of conductor CL2 have the same or similar relative size relationship.

[0080] Similarly, the line segments CL2-1 and CL2-2 of the conductor CL2 can be connected to each other through the conductive via stack TV2-1. The line segment CL2-1 of the conductor CL2 and the conductive bump 260 can be connected to each other through the conductive via stack TV2-2. The line segment CL2-2 of the conductor CL2 and the solder bump 270 can be connected to each other through the conductive via stack TV2-3.

[0081] In this embodiment, the conductive via stacks TV1-1, TV1-2, TV1-3 and the conductive via stacks TV2-1, TV2-2, TV2-3 may be surrounded by a plurality of ground conductive vias TVG located in the corresponding dielectric layer. In the horizontal direction, the conductive via stacks TV1-1, TV1-2, TV1-3 may be separated from the conductive via stacks TV2-1, TV2-2, TV2-3 by the ground conductive vias TVG.

[0082] In some embodiments, the conductive via stacks TV1-1, TV1-2, TV1-3 and the conductive via stacks TV2-1, TV2-2, TV2-3 may have similar structures. For example, the conductive via stack TV2-1 includes conductive vias TV2-1A and TV2-1B stacked on each other along a direction D120. The conductive via stack TV2-2 includes one or more conductive vias TV2-2A. The conductive via stack TV2-3 includes conductive vias TV2-3A and TV2-3B stacked on each other along a direction D120. In some embodiments, the conductive vias TV2-1A and TV2-1B have the same or similar structures as the conductive vias TV1-1A and TV1-1B, the conductive vias TV2-2A and the conductive vias TV1-2A have the same or similar structures, and the conductive vias TV2-3A and TV2-3B and the conductive vias TV1-3A and TV1-3B have the same or similar structures. In some embodiments, the number and composition of the conductive vias included in the conductive via stacks TV2-1, TV2-2, and TV2-3 respectively depend on the layer positions of the line segments CL2-1 and CL2-2, and are not limited to the disclosed embodiments.

[0083] The circuit substrate 500A also includes solder resist layers 222 and 232 located on the first surface 200T and the second surface 200B. The solder resist layers 222 and 232 cover part of the external wiring structure 250T and 250B, and may have one or more openings, which expose part of the wires CL1 and CL2, and may provide a formation position for subsequent conductive bumps 260 and solder bumps 270. In an embodiment of the present invention, the solder resist layers 222 and 232 may include solder resist materials such as green paint, or may be insulating materials including polyimide, ABF film (ajinomoto build-up film), epoxy resin or acrylic resin or a composite of the former two or polypropylene (PP). The solder resist layers 222 and 232 may be formed by coating, printing, laminating, laminating, etc.

[0084] In some embodiments, the conductors CL1 and CL2 may have different configurations in response to the signal transmission method. In this embodiment, the conductors CL1 and CL2 may be used to transmit single-ended signals. Specifically, the conductors CL1 and CL2 may include a single transmission line coupled to a transmission port or a reception port, respectively, to transmit a signal transmitted from the transmission port or to transmit a signal to the reception port.

[0085] Since the wires coupled to the receiving end have more stringent requirements on signal integrity (SI), when wire CL1 is coupled to the transmitting end and wire CL2 is coupled to the receiving end, the length of the line segment CL2-2 located in the inner wiring structure 240T with a thick line width can be greater than the length P2 of the line segment CL1-2, so as to further improve problems such as impedance mismatch or insertion loss and enhance signal integrity.

[0086] exist Figure 3A to Figure 3D , Figure 4A to Figure 4E In the illustrated embodiment, the conductor CL1 (or the conductor CL2 ) may be used to transmit a differential signal.

[0087] Figure 3A FIG. 5 is a schematic diagram of an exploded view of a conductive layer of a partial layer of a circuit substrate 500A according to some embodiments of the present invention. Figure 3B , Figure 3C , Figure 3D for Figure 3A A partial enlarged view showing the configuration of the conductors, grounding layer, and grounding conductive holes. Figure 1 , Figure 2A to Figure 2D The same or similar element symbols represent the same or similar elements. In this embodiment, the conductor CL1 of the circuit substrate 500A may include a pair of conductors CL1A and CL1B. In the horizontal direction, the conductors CL1A and CL1B are arranged side by side. There is no ground layer GL and ground conductive via TVG between the conductors CL1A and CL1B. The conductor CL2 of the circuit substrate 500A may have a similar structure, which will not be repeated here.

[0088] In some embodiments, the conductors CL1A and CL1B have the same or similar structures as the conductor CL1. For example, the conductor CL1A includes line segments CL1A-1, CL1A-2 and a conductive via stack TV1A-1. The conductor CL1B includes line segments CL1B-1, CL1B-2 and a conductive via stack TV1B-1. In this embodiment, the line segments CL1A-1 and CL1B-1 may be located at the same level, have the same size, and are substantially parallel to each other. The line segments CL1A-2 and CL1B-2 may be located at the same level, have the same size, and are substantially parallel to each other. The conductive via stacks TV1A-1 and TV1B-1 may include the same number of conductive vias and are substantially parallel to each other.

[0089] In this embodiment, the pair of conductors CL1A and CL1B may be coupled to the same transmitting end or the same receiving end to form a pair of differential signal transmission lines.

[0090] Figure 4A FIG. 5 is a schematic diagram of an exploded view of a conductive layer of a partial layer of a circuit substrate 500A according to some embodiments of the present invention. Figure 4B , Figure 4C , Figure 4D , Figure 4E for Figure 4A A partial enlarged view showing the configuration of the conductors, grounding layer, and grounding conductive holes. Figure 1 , Figure 2A to Figure 2D , Figure 3A to Figure 3D The same or similar reference numerals represent the same or similar elements. In this embodiment, the conductor CL1 of the circuit substrate 500A may include two pairs of conductors, including a first pair of conductors CL1A and CL1B, and the conductor CL2 of the circuit substrate 500A may include a second pair of conductors CL2A and CL2B.

[0091] In some embodiments, the line segments CL1A-1 and CL1B-1 of the first pair of conductive lines CL1A and CL1B may be located at different conductive layers from the line segments CL2A-1 and CL2B-1 of the second pair of conductive lines CL2A and CL2B. The line segments CL1A-2 and CL1B-2 of the first pair of conductive lines CL1A and CL1B may be located at different conductive layers from the line segments CL2A-2 and CL2B-2 of the second pair of conductive lines CL2A and CL2B. For example, the line segments CL1A-1 and CL1B-1 of the first pair of conductive lines CL1A and CL1B are located at layer L2, the line segments CL2A-1 and CL2B-1 of the second pair of conductive lines CL2A and CL2B are located at layer L4, the line segments CL1A-2 and CL1B-2 of the first pair of conductive lines CL1A and CL1B are located at layer L6, and the line segments CL2A-2 and CL2B-2 of the second pair of conductive lines CL2A and CL2B are located at layer L8.

[0092] In other embodiments, the line segments CL1A-1 and CL1B-1 of the first pair of conductors CL1A and CL1B may be located in the same conductive layer as the line segments CL2A-1 and CL2B-1 of the second pair of conductors CL2A and CL2B. The line segments CL1A-2 and CL1B-2 of the first pair of conductors CL1A and CL1B may be located in the same conductive layer as the line segments CL2A-2 and CL2B-2 of the second pair of conductors CL2A and CL2B. In the horizontal direction, the conductors CL1A, CL1B, CL2A, CL2B are arranged side by side. The conductors CL1A and CL1B are separated from the conductors CL2A and CL2B by the grounding layer GL and the grounding conductive vias TVG. In the horizontal direction (e.g., direction D110), multiple (e.g., 2) grounding conductive vias TVG are arranged between the conductors CL1B and CL2A of different pairs and adjacent to each other. There is no grounding layer GL and grounding conductive vias TVG between the conductor CL1A and the conductor CL1B. Furthermore, there is no ground layer GL and no ground conductive via TVG between the conductive lines CL2A and CL2B. The above is merely an explanation of the embodiment and is not intended to limit the present invention.

[0093] In some embodiments, the first pair of conductors CL1A and CL1B may have the same or similar structure as the conductor CL1. For example, the conductor CL1A includes line segments CL1A-1, CL1A-2 and conductive via stacks TV1A-1 and TV1A-3. The conductor CL1B includes line segments CL1B-1, CL1B-2 and conductive via stacks TV1B-1 and TV1B-3. The second pair of conductors CL2A and CL2B may have the same or similar structure as the conductor CL2. For example, the conductor CL2A includes line segments CL2A-1, CL2A-2 and conductive via stacks TV2A-1 and TV2A-3. The conductor CL2B includes line segments CL2B-1, CL2B-2 and conductive via stacks TV2B-1 and TV2B-3.

[0094] In this embodiment, the first pair of conductors CL1A and CL1B can be coupled to the transmitting end to form a first pair of differential signal transmission lines. The second pair of conductors CL2A and CL2B can be coupled to the receiving end to form a second pair of differential signal transmission lines. In another embodiment, the signal types transmitted by the two pairs of conductors can be opposite.

[0095] When the first pair of conductors CL1A and CL1B are coupled to the transmitting end and the second pair of conductors CL2A and CL2B are coupled to the receiving end, the line length of the line segments CL2A-2 and CL2B-2 located in the inner wiring structure 240T with thick line width can be greater than the line length of the line segments CL1A-2 and CL1B-2 to further improve impedance mismatch or insertion loss and other problems, thereby improving signal integrity.

[0096] Figure 5 is a schematic cross-sectional view of a circuit substrate 500B according to some embodiments of the present invention, Figure 1 , Figure 2A to Figure 2D , Figure 3A to Figure 3D , Figure 4A to Figure 4E The same or similar reference numerals represent the same or similar components. Figure 1 ) and the circuit substrate 500B( Figure 5 ) is that the line segments of the conductive lines of the circuit substrate 500B, which are located in dielectric layers of different materials, are respectively located on opposite surfaces of the core board.

[0097] like Figure 5 As shown, the circuit substrate 500B includes conductive lines CL1' and CL2'. The conductive line CL1' includes line segments CL1-1 and CL1-2' and conductive via stacks TV1-1, TV1-2 and TV1-3'. The conductive line CL2' includes line segments CL2-1 and CL2-2' and conductive via stacks TV2-1', TV2-2 and TV2-3'.

[0098] In some embodiments, the conductor CL1 ( Figure 1 ) and the conductive line CL1′ may have a similar structure. The line segments CL1-1 and CL1-2′ of the conductive line CL1′ are both located on the first surface 200T of the core board 200.

[0099] In the conductor CL2' of the circuit substrate 500B, the line segment CL2-1 arranged in the outer wiring structure 250T with a thin line width and the line segment CL2-2' arranged in the inner wiring structure 240B with a thick line width are respectively located on the first surface 200T and the second surface 200B of the core board 200. In this embodiment, the conductive hole stack TV2-1' used to connect the line segment CL2-1 and the line segment CL2-2' can connect the core conductive through hole 200V. In addition, the line segment CL1-2' of the conductor CL1' and the line segment CL2-2' of the conductor CL2' can be separated from each other by the ground layer GL formed on the first surface 200T and the second surface 200B of the core board 200.

[0100] By configuring the line segments CL2-1 and CL2-2' of the conductor CL2' of the present embodiment, the number of layers of the dielectric layer 210 of the inner wiring structure 240T and 240B can be further reduced. In addition, the number of conductive holes stacked in the dielectric layer 210 can be further reduced. For example, compared with the circuit substrate 500A, the total number of layers of the dielectric layer 210 of the inner wiring structure 240T and 240B of the circuit substrate 500B can be reduced from 8 layers to 4 layers. In detail, the number of layers of the dielectric layers 210T and 210B located in the core board 200 can be reduced from 4 layers to 2 layers, respectively. In the conductive hole stack TV1-3' of the conductor CL1' and the conductive hole stack TV2-3' of the conductor CL2", the number of conductive holes penetrating the dielectric layer 210 will also be reduced accordingly. Therefore, the total number of conductive layers of the circuit substrate 500B can be reduced from 18 layers to 14 layers, and the total number of conductive layers of the internal wiring structures 240T and 240B of the circuit substrate 500B can be reduced from 10 layers to 6 layers, which can reduce the manufacturing process cost.

[0101] Figure 6 is a schematic cross-sectional view of a circuit substrate 500C according to some embodiments of the present invention, Figure 1 , Figure 2A to Figure 2D , Figure 3A to Figure 3D , Figure 4A to Figure 4E , Figure 5 The same or similar reference numerals represent the same or similar components. Figure 5 ) and the circuit substrate 500C( Figure 6 ) is that the first surface 200T and the second surface 200B of the core board 200 of the circuit substrate 500C have asymmetric build-up layers.

[0102] like Figure 6As shown, the circuit substrate 500C includes conductive lines CL1", CL2". The conductive line CL1" includes line segments CL1-1, CL1-2' and conductive via stacks TV1-1, TV1-2, TV1-3". The conductive line CL2" includes line segments CL2-1, CL2-2' and conductive via stacks TV2-1', TV2-2, TV2-3".

[0103] In the conductors CL1", CL2", no other horizontal conductive line segments are arranged between the line segments CL1-2', CL2-2' located in the inner wiring structures 240T, 240B and the corresponding solder bumps 270 located on the second surface 200B of the core board 200. The above is only an explanation of the embodiment and is not intended to limit the present invention. From the above, it can be seen that the second surface 200B of the core board 200 may only have an inner wiring structure 240B with a thick line width, and there is no need to arrange an outer wiring structure. At this time, the circuit substrate 500C is an asymmetric substrate with different numbers of dielectric layers on both sides of the core board 200.

[0104] Since only the internal wiring structure 240B is provided on the second surface 200B of the circuit substrate 500C, the conductive hole stack TV1-3” of the conductor CL1” and the conductive hole stack TV2-3” of the conductor CL2” can be formed only by conductive holes penetrating the dielectric layer 210. Therefore, the number of conductive holes of the conductive hole stack connected to the solder bump 270 can be further reduced. Moreover, the total number of dielectric layers on both sides of the core board 200 can be further reduced. For example, compared with the circuit substrate 500B, the total number of dielectric layers 220 on both sides of the core board 200 of the circuit substrate 500C can be reduced from 8 layers to 4 layers. Therefore, the total number of conductive layers of the circuit substrate 500C can be reduced from 14 layers to 10 layers, which can effectively reduce the manufacturing process cost.

[0105] An embodiment of the present invention provides a circuit substrate, including a core board, a plurality of first dielectric layers stacked on each other, a plurality of second dielectric layers stacked on each other, and a first conductive wire. The plurality of first dielectric layers are arranged on the first surface of the core board. Each first dielectric layer is formed of a first material and has a first thickness. The plurality of second dielectric layers are arranged below the first dielectric layer. Each second dielectric layer is formed of a second material and has a second thickness. The first conductive wire is arranged in the first dielectric layer and the second dielectric layer. The first conductive wire includes a first line segment, a second line segment, a plurality of first conductive holes stacked on each other, and a plurality of second conductive holes stacked on each other. The first line segment is arranged between the first dielectric layers. The second line segment is arranged between the second dielectric layers. The plurality of first conductive holes penetrate the plurality of first dielectric layers and connect the first line segments. The plurality of second conductive holes penetrate the plurality of second dielectric layers and connect the plurality of first conductive holes and the second line segments.

[0106] In some embodiments, the circuit substrate uses a first dielectric layer with a higher cost and suitable for a fine line width / spacing manufacturing process as a build-up layer of an outer wiring structure, and uses a second dielectric layer with a lower cost and suitable for a thick line width / spacing manufacturing process as a build-up layer of an inner wiring structure to form a hybrid circuit substrate. In the first conductive line of the circuit substrate, the first line segment disposed between the first dielectric layers has a smaller line width, which can correspond to the size and spacing of the conductive bumps of the integrated circuit chip, and the second line segment disposed between the second dielectric layers has a larger line width, which can reduce insertion loss and maintain signal integrity without increasing additional costs when transmitting high-speed signals.

[0107] In some embodiments, the first dielectric layer and the second dielectric layer include different materials. Depending on the materials and corresponding manufacturing processes of the first dielectric layer and the second dielectric layer, the ratio of the second thickness of the second dielectric layer to the first thickness of the first dielectric layer may be greater than or equal to 1.5.

[0108] In some embodiments, the second line segment is disposed on the first surface or the second surface of the core board. When the second line segment is disposed on the second surface of the core board, the number of the second dielectric layer can be further reduced to reduce the manufacturing process cost.

[0109] In some embodiments, the first surface and the second surface of the core board of the circuit substrate have symmetrical build-up layers (including inner wiring structures and outer wiring structures). In some embodiments, the first surface and the second surface of the core board of the circuit substrate have asymmetrical build-up layers. For example, the first surface of the core board of the circuit substrate has inner wiring structures and outer wiring structures, while the second surface of the core board has only inner wiring structures, which can effectively reduce the manufacturing process cost.

[0110] In some embodiments, the length ratio of the first line segment and the second line segment of the first conductive line may be adjusted to achieve impedance matching and signal integrity requirements.

[0111] In some embodiments, the conductors may have different configurations according to the signal transmission method. In some embodiments, the first conductor is used to transmit a single-ended signal. For example, the first conductor is a single transmission line coupled to the transmitting end, used to transmit the signal transmitted from the transmitting end. Alternatively, the first conductor is a single transmission line coupled to the receiving end, used to transmit the signal to the receiving end.

[0112] In some embodiments, the circuit substrate may further include a second conductor arranged side by side with the first conductor. The first conductor and the second conductor may have similar structures. The first conductor and the second conductor are respectively used to transmit single-ended signals. For example, the first conductor is a single transmission line coupled to the transmitting end, and is used to transmit a first signal transmitted from the transmitting end. The second conductor is a single transmission line coupled to the receiving end, and is used to transmit a second signal to the receiving end. In this embodiment, the first conductor and the second conductor may be separated from each other by a ground layer and a ground conductive hole.

[0113] In some embodiments, the circuit substrate may further include a third wire and a fourth wire arranged side by side with the first wire and the second wire. The first wire and the third wire may have the same structure. The second wire and the fourth wire may have the same structure. In some embodiments, the first wire and the second wire are both coupled to the transmitting end to form a first pair of differential signal transmission lines. The third wire and the fourth wire are both coupled to the receiving end to form a second pair of differential signal transmission lines. In this embodiment, the first wire and the second wire are separated from the third wire and the fourth wire by a grounding layer and a grounding conductive hole. In the horizontal direction, a grounding conductive hole is provided between different pairs of adjacent wires (for example, the second wire and the third wire). There may be no grounding layer and grounding conductive hole between the first wire and the second wire. In addition, there may be no grounding layer and grounding conductive hole between the third wire and the fourth wire.

[0114] Although the present invention is disclosed as above by the aforementioned embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the definition of the attached claims.

Claims

1. A circuit substrate, comprising: A core board having a first surface and a second surface opposite to each other; A plurality of first dielectric layers stacked on each other are disposed on the first surface of the core board, wherein each of the first dielectric layers is formed of a first material and has a first thickness; A plurality of second dielectric layers stacked on each other are disposed on the core board, and the first dielectric layers are disposed on the second dielectric layers, wherein each of the second dielectric layers is formed of a second material and has a second thickness; and A first conductive line is disposed in the first dielectric layers and the second dielectric layers, wherein the first conductive line comprises: A first line segment is disposed between the first dielectric layers; A second line segment is disposed between the second dielectric layers; A plurality of first conductive vias stacked on each other, penetrating the first dielectric layers and connecting the first line segments; and A plurality of second conductive vias stacked on each other penetrate the second dielectric layers and connect the first conductive vias and the second line segment. 2 . The circuit substrate as claimed in claim 1 , wherein the first material is different from the second material. The circuit substrate as claimed in claim 1 , wherein the first thickness is smaller than the second thickness. 4 . The circuit substrate as claimed in claim 1 , wherein a ratio of the second thickness to the first thickness is greater than or equal to 1.

5. 5 . The circuit substrate as claimed in claim 1 , wherein the first line segment has a first line length, the second line segment has a second line length, and the second line length is between 20% and 85% of the sum of the first line length and the second line length. 6 . The circuit substrate as claimed in claim 1 , wherein the first line segment has a first line width, the second line segment has a second line width, and the second line width is greater than the first line width.

7. The circuit substrate as claimed in claim 1, wherein the first line segment is located at a first level, the second line segment is located at a second level, and the circuit substrate further comprises: A first ground layer located at the first level, separated from the first line segment and surrounding the first line segment; A second ground layer located at the second level, separated from the second line segment and surrounding the second line segment; as well as A plurality of grounding conductive holes stacked on each other penetrate the first dielectric layers and the second dielectric layers and connect the first grounding layer and the second grounding layer. 8 . The circuit substrate as claimed in claim 1 , wherein the second dielectric layers are disposed between the first surface of the core board and the first dielectric layers.

9. The circuit substrate as claimed in claim 1, wherein the second dielectric layers are disposed on the first surface and the second surface of the core board, and a portion of the second dielectric layers is disposed between the first surface of the core board and the first dielectric layers. 10 . The circuit substrate as claimed in claim 1 , wherein the second line segment is disposed on the first surface or the second surface of the core board. 11 . The circuit substrate as claimed in claim 1 , wherein the core board has a core conductive through hole penetrating the core board and connecting the second conductive holes.

12. The circuit substrate according to claim 11, further comprising: A plurality of third dielectric layers stacked on each other are disposed on the second surface of the core board, wherein each of the third dielectric layers is formed of the first material and has the first thickness. The first conductive line comprises: A plurality of third conductive vias stacked on each other penetrate the third dielectric layers and connect the second conductive vias. 13 . The circuit substrate as claimed in claim 1 , wherein the first conductive line comprises a single transmission line coupled to a transmitting end or a receiving end, for transmitting a first signal transmitted from the transmitting end, or transmitting the first signal to the receiving end.

14. The circuit substrate according to claim 1, further comprising: The second conductive line is disposed in the first dielectric layers and the second dielectric layers and arranged side by side with the first conductive line, wherein the second conductive line comprises: A third line segment is disposed between the first dielectric layers and is substantially parallel to the first line segment; a fourth line segment disposed between the second dielectric layers and substantially parallel to the second line segment; and A plurality of fourth conductive vias stacked on each other, penetrating the first dielectric layers and connecting the third line segment; and A plurality of fifth conductive vias stacked on each other penetrate the second dielectric layers and connect the fourth conductive vias and the fourth line segment. 15 . The circuit substrate as claimed in claim 14 , wherein a line length of the fourth line segment is greater than a line length of the second line segment.

16. The circuit substrate as claimed in claim 14, wherein the first conductive wire is a single transmission line coupled to a transmitting end for transmitting a first signal transmitted from the transmitting end, and the second conductive wire is a single transmission line coupled to a receiving end for transmitting a second signal to the receiving end. 17 . The circuit substrate as claimed in claim 14 , wherein the first conductive line and the second conductive line are both coupled to a transmitting end or a receiving end to form a pair of differential signal transmission lines.

18. The circuit substrate according to claim 14, further comprising: A third wire is disposed in the first dielectric layers and the second dielectric layers, the third wire is substantially parallel to the first wire, and the third wire is located between the first wire and the second wire, wherein the first wire and the third wire have the same structure; as well as The fourth wire is disposed in the first dielectric layers and the second dielectric layers and is substantially parallel to the second wire. The fourth wire is located between the second wire and the third wire, wherein the second wire and the fourth wire have the same structure.

19. The circuit substrate as claimed in claim 18, wherein the first wire and the third wire are coupled to a transmitting end to form a first pair of differential signal transmission lines, and wherein the second wire and the fourth wire are coupled to a receiving end to form a second pair of differential signal transmission lines.

20. The circuit substrate of claim 19, wherein the first line segments of the first conductor and the third conductor are located at a first level, the second line segments of the first conductor and the third conductor are located at a second level, and wherein the third line segments of the second conductor and the fourth conductor are located at a third level, and the fourth line segments of the second conductor and the fourth conductor are located at a fourth level.

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