Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device. The method may include: forming an insulating intermediate layer on a substrate; forming a tungsten pattern inside the insulating intermediate layer and on the insulating intermediate layer; forming an insulating pattern on the insulating intermediate layer to fill a space between the tungsten patterns, the insulating pattern having a lowest point of the upper surface, the lowest point being lower than the upper surface of each tungsten pattern; forming a preliminary tungsten oxide layer on the upper surface of each tungsten pattern; performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer; and forming an etch stop layer on the protective layer and the insulating pattern.

Description

Technical Field

[0001] Various example embodiments relate to methods of manufacturing semiconductor devices. In particular, various example embodiments relate to methods of manufacturing semiconductor devices including conductive structures. Background Art

[0002] The semiconductor device may include a conductive structure. An etch stop layer may be formed on the conductive structure. A contact plug may be formed through the etch stop layer and may contact the conductive structure. In order to reduce defects between the conductive structure and the contact plug, the etch stop layer may be formed to have a more uniform thickness. Summary of the invention

[0003] Various example embodiments provide methods of fabricating semiconductor devices including conductive structures.

[0004] According to some example embodiments, a method for manufacturing a semiconductor device is provided. The method may include: forming an insulating interlayer on a substrate; forming a tungsten pattern inside and on the insulating interlayer; forming an insulating pattern on the insulating interlayer to fill a space between the tungsten patterns, the insulating pattern having a lowest point of an upper surface, the lowest point being lower than an upper surface of each tungsten pattern; forming a preliminary tungsten oxide layer on an upper surface of each tungsten pattern; performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer; and forming an etch stop layer on the protective layer and the insulating pattern.

[0005] According to some example embodiments, a method for manufacturing a semiconductor device is provided. The method may include: forming a bit line structure on a cell region of a substrate; forming a gate structure on a peripheral circuit region of the substrate; forming an insulating interlayer covering the gate structure on the peripheral circuit region of the substrate; forming a lower contact plug contacting the substrate and a landing pad pattern including tungsten on the lower contact plug, the lower contact plug and the landing pad pattern being between the bit line structure; forming a first conductive structure including tungsten on the insulating interlayer, the first conductive structure passing through the insulating interlayer and contacting a surface of the substrate; forming insulating patterns between the landing pad patterns and between the first conductive structures; forming a plurality of conductive structures on the upper surfaces of the landing pad patterns, respectively. The invention relates to a method for forming a tungsten oxide layer on a surface of the substrate and an upper surface of the first conductive structure; performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer; forming an etch stop layer on the protective layer and the insulating pattern; forming a capacitor on the landing pad pattern, the capacitor passing through the etch stop layer, the protective layer and the tungsten oxide layer on a unit area of ​​the substrate; and forming a contact plug contacting the upper surface of the first conductive structure, the contact plug passing through the etch stop layer, the protective layer and the tungsten oxide layer on a peripheral circuit area of ​​the substrate.

[0006] According to some example embodiments, a method for manufacturing a semiconductor device is provided. The method may include: forming a lower structure on a substrate; forming a first lower insulating interlayer including silicon oxide on the lower structure; forming a second lower insulating interlayer including silicon nitride on the first lower insulating interlayer; forming a tungsten pattern on the second lower insulating interlayer, the tungsten pattern passing through the first lower insulating interlayer and the second lower insulating interlayer; forming an insulating pattern including silicon nitride on the second lower insulating interlayer, the insulating pattern filling a space between the tungsten patterns and having a lowest point of an upper surface that is lower than an upper surface of each tungsten pattern; forming a preliminary tungsten oxide layer on an upper surface of each tungsten pattern; performing a CO plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer, the protective layer including at least tungsten and carbon; and forming an etch stop layer on the protective layer and the insulating pattern.

[0007] In the method of manufacturing a semiconductor device according to various example embodiments, a tungsten oxide layer and a protective layer may be formed on the tungsten pattern. The sum of the thicknesses of the tungsten oxide layer and the protective layer may be less than the thickness of the preliminary tungsten oxide layer. As the thicknesses of the tungsten oxide layer and the protective layer become thinner, the height of the upper surface of the protective layer may be more uniform. Therefore, an etch stop layer may be formed on the protective layer to have a more uniform thickness. The adhesion of the etch stop layer on the protective layer may be excellent. Therefore, defects occurring when the etch stop layer has an uneven thickness may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 42 represents various non-limiting example embodiments as described herein.

[0009] Figures 1 to 10 and Fig.12 are a cross-sectional view and an enlarged cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0010] Fig.11 Schematic diagram showing the reaction mechanism of a CO (carbon monoxide) plasma treatment process and a deposition process of an etch stop layer;

[0011] Fig.13 , Fig.14 , Figures 16 to 18 are cross-sectional views and enlarged cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments;

[0012] Fig.15 is a schematic diagram showing the reaction mechanism of a hydrogen plasma treatment process;

[0013] Fig.19 It shows NH 3 Schematic diagram of the reaction mechanism of the (ammonia) plasma treatment process and the deposition process of the etch stop layer; and

[0014] Figures 20 to 42 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments. DETAILED DESCRIPTION

[0015] Hereinafter, various example embodiments will be described in detail with reference to the accompanying drawings.

[0016] Figures 1 to 10 and Fig.12 are cross-sectional views and enlarged cross-sectional views illustrating a method of manufacturing a semiconductor device according to some example embodiments. Fig.11 is a schematic diagram showing the reaction mechanism of a CO plasma treatment process and a deposition process of an etch stop layer.

[0017] Figure 6 , Figure 8 and Fig.10 is an enlarged cross-sectional view showing part of a semiconductor device.

[0018] Reference Figure 1 , a lower structure 25 may be formed on the substrate 10. For example, the lower structure 25 may include a transistor 24. The transistor 24 may include a gate structure 18 and an impurity region 22. The gate structure 18 may include a gate insulating layer 12, a gate electrode 14, and a first capping pattern 16. A gate spacer 20 may be formed on a sidewall of the gate structure 18.

[0019] A lower insulating interlayer 34 may be formed on the substrate 10 to cover the lower structure 25. The lower insulating interlayer 34 may include a plurality of insulating interlayers, and the uppermost lower insulating interlayer 34 may include, for example, silicon nitride. An upper surface of the uppermost lower insulating interlayer 34 may be substantially flat.

[0020] In some example embodiments, the lower insulating interlayer 34 may include a first lower insulating interlayer 30 including silicon oxide and a second lower insulating interlayer 32 including silicon nitride.

[0021] The lower insulating interlayer 34 may be etched to form a first contact hole 36. The first contact hole 36 may pass through the lower insulating interlayer 34, and may expose a surface of the substrate 10.

[0022] Reference Figure 2 A barrier metal layer 40 may be formed on the upper surface of the lower insulating interlayer 34 and the surface of the first contact hole 36. A metal layer 42 may be formed on the barrier metal layer 40.

[0023] The barrier metal layer 40 may include, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, etc. In some example embodiments, the process of forming the barrier metal layer 40 may be omitted.

[0024] In some example embodiments, the metal layer 42 may include tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, etc. For example, the metal layer 42 may include tungsten. Hereinafter, the metal layer 42 is referred to as a tungsten layer.

[0025] Reference Figure 3 , the tungsten layer 42 and the barrier metal layer 40 may be etched to form a conductive structure 44 in which a barrier metal pattern 40a and a tungsten pattern 42a are stacked. The barrier metal pattern 40a may be conformally formed on the surface of the first contact hole 36 and the upper surface of the second lower insulating interlayer 32. The conductive structure 44 may include a first contact plug filling the first contact hole 36 and a wiring line on the first contact plug.

[0026] In some example embodiments, an upper portion of the second lower insulating interlayer 32 may be partially etched together in an etching process of the tungsten layer 42 and the barrier metal layer 40. A first opening 46 may be formed between the conductive structures 44 on the second lower insulating interlayer 32. In some example embodiments, the second lower insulating interlayer 32 including silicon nitride may be exposed through a bottom of the first opening 46.

[0027] Reference Figure 4 , a first insulating layer 48 may be formed on the tungsten pattern 42 a and the second lower insulating interlayer 32 to fill the first opening 46 .

[0028] In some example embodiments, the first insulating layer 48 may be the same material as that of the second lower insulating interlayer 32. For example, the first insulating layer 48 may include silicon nitride.

[0029] Reference Figure 5 and Figure 6 , the first insulating layer 48 may be planarized until an upper surface of the tungsten pattern 42a may be exposed to form an insulating pattern 50. The planarization process may include, for example, a chemical mechanical polishing process or an etch-back process.

[0030] After the planarization process, the lowest point of the upper surface of the insulating pattern 50 may be lower than the upper surface of the tungsten pattern 42a. Therefore, the upper sidewall of the tungsten pattern 42a may be exposed. The upper edge of the tungsten pattern 42a may have a rounded shape.

[0031] As the upper surface of the tungsten pattern 42 a is exposed, oxygen may react with the surface of the tungsten pattern 42 a to form a preliminary tungsten oxide layer 52 on the tungsten pattern 42 a .

[0032] In some example embodiments, the preliminary tungsten oxide layer 52 may be generated by natural oxidation. In some example embodiments, an ashing process may be further performed on the tungsten pattern 42a and the first insulating layer 48, the ashing process being a heat treatment process that introduces oxygen. Thus, the preliminary tungsten oxide layer 52 may be formed on the exposed surface of the tungsten pattern 42a by the ashing process.

[0033] Since the upper edge of the tungsten pattern 42a may have a rounded shape, the preliminary tungsten oxide layer 52 may have a rounded shape on the upper edge of the tungsten pattern 42a. Therefore, the height of the upper surface of the preliminary tungsten oxide layer 52 formed on the central portion of the tungsten pattern 42a may be different from the height of the upper surface of the preliminary tungsten oxide layer 52 formed on the edge portion of the tungsten pattern 42a. For example, the edge portion of the upper surface of the preliminary tungsten oxide layer 52 may be lower than the central portion of the upper surface of the preliminary tungsten oxide layer 52.

[0034] The preliminary tungsten oxide layer 52 may have a first thickness in a vertical direction from an upper surface of a central portion of the tungsten pattern 42 a .

[0035] Reference Figure 7 and Figure 8 , a surface plasma treatment process may be performed on the preliminary tungsten oxide layer 52. By performing the surface plasma treatment process, at least a portion of the preliminary tungsten oxide layer 52 may be removed to form a tungsten oxide layer 52a, and a protective layer 54 may be formed on the tungsten oxide layer 52a.

[0036] In various example embodiments, the surface plasma treatment process may be a CO plasma treatment.

[0037] When the CO plasma treatment process is performed on the surface of the preliminary tungsten oxide layer 52, as shown in FIG. Fig.11 As shown, oxygen included in the preliminary tungsten oxide layer 52 may react with CO to remove a portion of the preliminary tungsten oxide layer 52. In this case, the tungsten oxide layer 52a may be formed to have a second thickness that is less than the first thickness of the preliminary tungsten oxide layer 52. The CO plasma treatment process may be performed for about 5 seconds to about 30 seconds. When the CO plasma treatment process is performed for a time shorter than 5 seconds, the effect of removing the preliminary tungsten oxide layer 52 due to the CO plasma treatment process may be reduced. Even if the CO plasma treatment process is performed for a time exceeding 30 seconds, the thickness of the preliminary tungsten oxide layer 52 is not additionally reduced.

[0038] In addition, a WOC (tungsten-oxide-carbon) bond or a WC (tungsten-carbon) bond may be generated on the tungsten oxide layer 52a. Therefore, a protective layer 54 including carbon may be formed on the tungsten oxide layer 52a. The protective layer 54 may be, for example, a WOC (tungsten oxide carbide) layer or a WC (tungsten carbide) layer.

[0039] In some example embodiments, after performing the surface plasma treatment process, the sum of the thicknesses of the tungsten oxide layer 52a and the protective layer 54 may be less than the thickness of the preliminary tungsten oxide layer 52. Because the sum of the thicknesses of the tungsten oxide layer 52a and the protective layer 54 formed on the upper surface of the tungsten pattern 42a may be less than the thickness of the preliminary tungsten oxide layer 52, the difference between the height of the upper surface of the protective layer 54 and the height of the lowest point of the upper surface of the insulating pattern 50 may be less than the difference between the height of the upper surface of the preliminary tungsten oxide layer 52 and the height of the lowest point of the upper surface of the insulating pattern 50. Therefore, the height difference between the upper surface of the protective layer 54 and the lowest point of the upper surface of the insulating pattern 50 may be reduced by the surface plasma treatment process.

[0040] When the CO plasma treatment process is performed, the preliminary tungsten oxide layer 52 formed on the central portion of the upper surface of the tungsten pattern 42a may be removed more than the preliminary tungsten oxide layer 52 formed on the edge portion of the upper surface of the tungsten pattern 42a. Therefore, when the CO plasma treatment process is performed, the height difference between the upper surface of the tungsten oxide layer 52a formed on the central portion of the tungsten pattern 42a and the upper surface of the tungsten oxide layer 52a formed on the edge portion of the tungsten pattern 42a may be reduced. Therefore, the height of the upper surface of the tungsten oxide layer 52a may be substantially uniform. In addition, the height of the upper surface of the protective layer 54 formed on the tungsten oxide layer 52a may be substantially uniform.

[0041] If the protective layer 54 includes a WOC layer or a WC layer, hydrogen may not be blocked by the protective layer 54. Therefore, if a hydrogen diffusion process in which hydrogen diffuses downward is subsequently performed, the protective layer 54 including the WOC layer or the WC layer may be formed by a CO plasma treatment process before the hydrogen diffusion process.

[0042] Through this process, a conductive structure 44 including a barrier metal pattern 40a and a tungsten pattern 42a may be formed on the second lower insulating interlayer 32 and may pass through the lower insulating interlayer 34. A tungsten oxide layer 52a and a protective layer 54 may be stacked on an upper surface of the tungsten pattern 42a.

[0043] Reference Fig. 9 and Fig.10 , an etch stop layer 60 may be formed on upper surfaces of the protection layer 54 and the insulating pattern 50 .

[0044] The etch stop layer 60 may include SiBN, SiCN, or SiN. If a diffusion process of hydrogen is subsequently performed, hydrogen may not be blocked by the etch stop layer 60. Therefore, the etch stop layer 60 may include, for example, SiBN as a material through which hydrogen may diffuse.

[0045] Because the upper surface of the protective layer 54 is substantially uniform and the height difference between the upper surface of the protective layer 54 and the upper surface of the insulating pattern 50 is reduced, the etch stop layer 60 may be formed on the protective layer 54 to have a more uniform thickness.

[0046] When the etching stop layer 60 does not have a substantially uniform thickness and has a thickness less than the target thickness in some areas, metal may grow on the area with a thin thickness of the etching stop layer. In addition, the conductive particles may not be blocked by the etching stop layer, so that the conductive particles may penetrate into the layer below the etching stop layer. Therefore, a short circuit failure in which the upper contact plug formed subsequently is electrically connected to the adjacent tungsten pattern 42a adjacent to the target tungsten pattern 42a and the target tungsten pattern 42a may occur. However, as described above, because the thickness of the etching stop layer 60 is formed more uniformly, the short circuit failure can be reduced.

[0047] Since the etch stop layer 60 can directly contact the protection layer 54 including WOC or WC, the adhesion of the etch stop layer 60 can be improved. Fig.11 As shown, when the etch stop layer 60 including SiBN is formed on the protective layer 54, a WOC-SiBN bond may be generated. Therefore, the adhesion between the protective layer 54 and the etch stop layer 60 may be improved.

[0048] Reference Fig.12 , an insulating interlayer 62 may be formed on the etch stop layer 60. An upper contact plug 64 may be formed through the insulating interlayer 62, the etch stop layer 60, the protective layer 54, and the tungsten oxide layer 52a, and may contact an upper surface of the target tungsten pattern 42a.

[0049] The upper contact plug 64 may include a metal. The upper contact plug 64 may include a barrier metal pattern and a metal pattern. The metal pattern may include, for example, tungsten.

[0050] As described above, the CO plasma treatment process may be performed on the preliminary tungsten oxide layer 52 to form the tungsten oxide layer 52a and the protective layer 54 having a thickness smaller than that of the preliminary tungsten oxide layer 52. As the uniformity of the upper surface of the protective layer 54 is improved, the etch stop layer 60 may be formed to have a more uniform thickness. Therefore, in the process of forming the upper contact plug 64, a short circuit failure in which the upper contact plug 64 is electrically connected to the adjacent tungsten pattern 42a adjacent to the target tungsten pattern 42a and the target tungsten pattern 42a may be reduced.

[0051] Fig.13 , Fig.14 , Figures 16 to 18 are cross-sectional views and enlarged cross-sectional views illustrating a method of manufacturing a semiconductor device according to some example embodiments. Fig.15is a schematic diagram showing the reaction mechanism of the hydrogen plasma treatment process.

[0052] Fig.14 , Fig.17 and Fig.18 is an enlarged cross-sectional view showing part of a semiconductor device.

[0053] The method of manufacturing a semiconductor device described below can be compared with the method described in reference Figures 1 to 12 The method described is the same except for the surface plasma treatment process of the preliminary tungsten oxide layer.

[0054] Reference Fig.13 and Fig.14 , first, you can perform a reference Figures 1 to 6 The process described is to form Figure 5 and Figure 6 The structure shown.

[0055] A first surface plasma treatment process may be performed on the preliminary tungsten oxide layer 52, thereby removing at least a portion of the preliminary tungsten oxide layer 52. The first surface plasma treatment process may be hydrogen (H 2 ) Plasma treatment process.

[0056] like Fig.15 As shown, when the hydrogen plasma treatment process is performed on the surface of the preliminary tungsten oxide layer 52, the preliminary tungsten oxide layer 52 may be reduced to tungsten by the following reaction equation. Therefore, the preliminary tungsten oxide layer 52 may be removed.

[0057] WOx+H 2 →W+H 2 O

[0058] In various example embodiments, a portion of the preliminary tungsten oxide layer 52 may be removed by a hydrogen plasma treatment process. Fig.14 As shown, the thickness of the preliminary tungsten oxide layer 52 may be reduced.

[0059] In some example embodiments, the preliminary tungsten oxide layer 52 may be completely removed by a hydrogen plasma treatment process. In this case, an upper surface of the tungsten pattern 42a may be exposed.

[0060] Reference Fig.16 and Fig.17 After performing the first surface plasma treatment process, a second surface plasma treatment process is performed. Through the second surface plasma treatment process, at least a portion of the preliminary tungsten oxide layer 52 may be removed to form a tungsten oxide layer 52a, and a protective layer 54 may be formed on the tungsten oxide layer 52a.

[0061] The second surface plasma treatment process may be a CO plasma treatment process.

[0062] When CO plasma treatment is performed on the preliminary tungsten oxide layer 52, a portion of the surface of the preliminary tungsten oxide layer 52 may be removed to form a tungsten oxide layer 52a having a second thickness less than the first thickness. The protective layer 54 may be formed by generating a WOC bond or a WC bond on the tungsten oxide layer 52a. The protective layer 54 may be, for example, a WOC layer or a WC layer.

[0063] Through the above process, Fig.17 As shown, a conductive structure 44 including a barrier metal pattern 40a and a tungsten pattern 42a may be formed on the second lower insulating interlayer 32, and a tungsten oxide layer 52a and a protective layer 54 may be formed on an upper surface of the tungsten pattern 42a.

[0064] In some example embodiments, the tungsten oxide layer 52a may be completely removed by a hydrogen plasma treatment process. In this case, the upper surface of the tungsten pattern 42a may be bonded to -OC or -C, so that the protective layer 54 may be directly formed on the tungsten pattern 42a. The protective layer 54 may be a WOC layer or a WC layer. Fig.18 As shown, a conductive structure 44 including a barrier metal pattern 40 a and a tungsten pattern 42 a may be formed on the second lower insulating interlayer 32 , and a protection layer 54 may be formed on an upper surface of the tungsten pattern 42 a .

[0065] Afterwards, reference can be performed in the same way Fig. 9 , Fig.10 and Fig.12 The process described above is used to form an etching stop layer 60, an insulating interlayer 62 and an upper contact plug 64, as shown in FIG. Fig.12 shown.

[0066] As described above, the surface plasma treatment process of the preliminary tungsten oxide layer may include a CO plasma treatment process. In some example embodiments, before performing the CO plasma treatment process, a hydrogen plasma treatment process may be further performed.

[0067] In some example embodiments, only hydrogen plasma treatment may be performed on the preliminary tungsten oxide layer. When only hydrogen plasma treatment is performed, a protective layer may not be formed. Therefore, the etch stop layer may directly contact the tungsten pattern or the tungsten oxide layer. Therefore, the adhesion of the etch stop layer may not be good.

[0068] The surface plasma treatment process performed on the preliminary tungsten oxide layer may be variously modified. Hereinafter, the surface plasma treatment process that may be performed on the preliminary tungsten oxide layer may be described.

[0069] Fig.19 It shows NH 3 Schematic diagram of the reaction mechanism of the plasma treatment process and the deposition process of the etch stop layer.

[0070] First, execute the reference Figures 1 to 6 The process described is to form Figure 5 and Figure 6 The structure shown.

[0071] Thereafter, a surface plasma treatment process may be performed on the preliminary tungsten oxide layer 52. Through the surface plasma treatment process, at least a portion of the preliminary tungsten oxide layer 52 may be removed to form a tungsten oxide layer 52a, and a protective layer 54 may be formed on the tungsten oxide layer 52a. The surface plasma treatment process may be, for example, NH 3 Plasma treatment process.

[0072] like Fig.19 As shown, when NH 3 During the plasma treatment process, the oxygen included in the preliminary tungsten oxide layer 52 may react with NH 3 The reaction is performed to remove at least a portion of the preliminary tungsten oxide layer 52. Figure 7 and Figure 8 As shown, the preliminary tungsten oxide layer 52 may be transformed into a tungsten oxide layer 52a. A protective layer 54 may be formed on the tungsten oxide layer 52a. The protective layer 54 may include nitrogen and may be, for example, a WON (tungsten oxynitride) layer or a WN (tungsten nitride) layer.

[0073] Adhesion between the protective layer 54 and an etch stop layer formed subsequently may be improved by the protective layer 54. Damage to the tungsten pattern 42a may be reduced due to the formation of the protective layer 54. As the upper surface of the tungsten oxide layer 52a below the protective layer 54 becomes more uniform, the upper surface of the protective layer 54 may be more uniform.

[0074] NH 3 The plasma treatment process may be performed for about 5 seconds to about 30 seconds. 3 If the plasma treatment process is performed for a time shorter than 5 seconds, the effect of removing the preliminary tungsten oxide layer due to the surface plasma treatment may be reduced. 3 The thickness of the preliminary tungsten oxide layer does not further decrease when the plasma treatment process is performed for a time longer than 30 seconds.

[0075] In various example embodiments, the sum of the thicknesses of the tungsten oxide layer 52 a and the protective layer 54 after the surface plasma treatment process is performed may be less than the thickness of the preliminary tungsten oxide layer 52 .

[0076] In various example embodiments, in NH3 In the plasma treatment process, not only NH 3 , and H can be additionally introduced 2 and / or N 2 gas.

[0077] Afterwards, reference can be performed in the same way Fig. 9 , Fig.10 and Fig.12 The process described above is used to form an etching stop layer 60, an insulating interlayer 62 and an upper contact plug 64, as shown in FIG. Fig.12 shown.

[0078] As described above, the surface plasma treatment process of the preliminary tungsten oxide layer 52 may include only NH 3 Plasma treatment.

[0079] When only NH is executed 3 During plasma treatment, the protective layer may include a WON layer or a WN layer. In this case, hydrogen can be blocked by the protective layer. If hydrogen needs to diffuse downward in a subsequent process, other surface plasma treatments may be performed in addition.

[0080] In various example embodiments, when executing NH 3 Before the plasma treatment, CO plasma treatment and / or hydrogen plasma treatment may be further performed. The nitrogen included in the protective layer may be reduced by the CO plasma treatment and / or hydrogen plasma treatment so that hydrogen may not be blocked by the protective layer in subsequent processes.

[0081] As described above, the surface plasma treatment process of the preliminary tungsten oxide layer 52 may include, for example, CO plasma treatment, H 2 Plasma treatment, NH 3 Plasma treatment, etc. The plasma treatment process can be performed alone, or can be performed with CO plasma treatment, H 2 Plasma treatment and NH 3 The plasma treatment may be performed by combining two or more of the above processes. For example, when the preliminary tungsten oxide layer 52 is subjected to a CO plasma treatment process and an NH 3 During the plasma treatment process, the protection layer 54 may include a WOC layer, a WC layer, a WCN (tungsten carbonitride) layer or a WOCN (tungsten oxycarbonitride) layer.

[0082] By H 2 The effect of plasma treatment on removing the tungsten oxide layer can be greater than that of CO plasma treatment or NH 3 The plasma treatment can remove the tungsten oxide layer. Therefore, CO plasma treatment and NH 3 Perform H before plasma treatment2 The plasma treatment may remove the entire tungsten oxide layer or a local portion of the tungsten oxide layer.

[0083] The semiconductor device formed by the above process may have the following structural features.

[0084] Refer again Fig.12 , the lower structure 25 may be formed on the substrate 10. The lower insulating interlayer 34 may be formed on the substrate 10 and the lower structure 25. The lower insulating interlayer 34 may include a plurality of insulating layers, and the uppermost lower insulating interlayer may include silicon nitride. In various example embodiments, the lower insulating interlayer 34 may include a first lower insulating interlayer 30 including silicon oxide and a second lower insulating interlayer 32 including silicon nitride.

[0085] In various example embodiments, Fig.14 and Fig.17 As shown, a conductive structure 44 including a barrier metal pattern 40a and a tungsten pattern 42a may be formed on the lower insulating interlayer 34. A tungsten oxide layer 52a and a protective layer 54 may be stacked on an upper surface of the tungsten pattern 42a.

[0086] In some example embodiments, Fig.18 As shown, a conductive structure 44 including a barrier metal pattern 40a and a tungsten pattern 42a may be formed on the lower insulating interlayer 34. A protective layer 54 may be formed on an upper surface of the tungsten pattern 42a.

[0087] A plurality of conductive structures 44 may be formed. The conductive structures 44 may pass through the lower insulating interlayer 34, and the conductive structures 44 may contact an upper portion of the substrate 10.

[0088] In some example embodiments, the protective layer 54 may be formed by performing a CO plasma treatment process on the preliminary tungsten oxide layer. Therefore, the protective layer 54 may include, for example, tungsten and carbon. For example, the protective layer 54 may include a WOC layer or a WC layer.

[0089] In some example embodiments, the protective layer 54 may be formed by performing NH 3 In this case, the protection layer 54 may include a WON layer or a WN layer.

[0090] In some example embodiments, the protective layer 54 may be formed by performing a CO plasma treatment process and an NH 3 In this case, the protection layer 54 may include a WOC layer, a WC layer, a WCN layer or a WOCN layer.

[0091] The insulating pattern 50 may be formed between the plurality of conductive structures 44. The insulating pattern 50 may include the same material as that of the second lower insulating interlayer 32. In some example embodiments, the insulating pattern 50 may include silicon nitride.

[0092] In various example embodiments, a top surface of the insulating pattern 50 may be lower than a top surface of the protective layer 54. In some example embodiments, a lowest point of an upper surface of the insulating pattern 50 may be lower than a top surface of the tungsten oxide layer 52a.

[0093] The etch stop layer 60 may cover the upper surfaces of the plurality of conductive structures 44, the tungsten oxide layer 52a, the protection layer 54, and the insulating pattern 50. The etch stop layer 60 may include, for example, SiBN, SiCN, or SiN. For example, the etch stop layer 60 may include SiBN.

[0094] An insulating interlayer 62 may be disposed on the etch stop layer 60. An upper contact plug 64 may penetrate the insulating interlayer 62 and the etch stop layer 60. The upper contact plug 64 may contact an upper surface of the target tungsten pattern.

[0095] Figures 20 to 42 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to various example embodiments.

[0096] Fig. 20 , Fig.23 , Fig.28 and Fig.36 It is a floor plan. Fig.21 , Figure 24 to Figure 27 , Figure 29 to Figure 35 and Figures 37 to 42 It is a cross-sectional view taken along the lines AA' and BB' in the plan view. Fig. 22 It is a cross-sectional view taken along the line CC' in the plan view.

[0097] In the following detailed description, two directions parallel to the upper surface of the substrate and perpendicular to each other are defined as a first direction D1 and a second direction D2, respectively. A direction parallel to the upper surface of the substrate and having an acute angle with each of the first direction D1 and the second direction D2 is defined as a third direction D3.

[0098] The semiconductor device may be a DRAM device, and the DRAM device may include a conductive structure.

[0099] Reference Figure 20 to Figure 22 , first active patterns 103 and second active patterns 105 may be formed on the substrate 100 including the first region I and the second region II, respectively. Isolation patterns 110 may be formed between the first active patterns 103 , between the second active patterns 105 , and between the first active patterns 103 and the second active patterns 105 .

[0100] The first region I of the substrate 100 may be a cell region where a memory cell is formed. The second region II of the substrate 100 may surround the first region I, and the second region II may be a peripheral circuit region where a peripheral circuit pattern for operating the memory cell is formed.

[0101] The first active pattern 103 and the second active pattern 105 may be defined by a first groove formed by removing an upper portion of the substrate 100. The first active pattern 103 may extend in the third direction D3, and a plurality of first active patterns 103 may be spaced apart from each other in each of the first direction D1 and the second direction D2. The second active pattern 105 may be formed at an area for forming a peripheral circuit pattern. In order to avoid drawing complexity, only one isolated second active pattern 105 is shown. The isolation pattern 110 may be formed in the first groove.

[0102] After forming an impurity region (not shown) at the first region I of the substrate 100 by, for example, performing an ion implantation process, the first active pattern 103 and the isolation pattern 110 may be partially etched to form a first recess extending in the first direction D1.

[0103] A first gate structure 160 may be formed in the first recess. The first gate structure 160 may include a first gate insulating pattern 130 formed on the bottom and sidewalls of the first recess, a gate electrode formed on the first gate insulating pattern 130 to fill a lower portion of the first recess, and a first gate mask 150 formed on the first gate electrode 140 to fill an upper portion of the first recess. The first gate structure 160 may extend in a first direction D1 on the first region I of the substrate 100, and a plurality of first gate structures 160 may be spaced apart from each other in a second direction D2.

[0104] Reference Fig.23 and Fig.24 , an insulating layer structure 200 may be formed on the first region I and the second region II of the substrate 100. The insulating layer structure 200 located on the second region II may be removed. A second gate insulating layer 210 may be formed on the second active region of the second region II of the substrate 100 by performing, for example, a thermal oxidation process.

[0105] The insulating layer structure 200 may include a first insulating layer 170, a second insulating layer 180, and a third insulating layer 190 stacked sequentially. The first insulating layer 170 and the third insulating layer 190 may include oxides such as silicon oxide, and the second insulating layer 180 may include nitrides such as silicon nitride.

[0106] Thereafter, the insulating layer structure 200 may be patterned, and then the first active pattern, the isolation pattern, and a portion of the first gate mask included in the first gate structure may be etched using the insulating layer structure 200 as an etching mask to form a first opening 220 .

[0107] In various example embodiments, the insulating layer structure 200 after the etching process may have a circular shape or an elliptical shape in a plan view. A plurality of insulating layer structures 200 may be spaced apart from each other and may be aligned in each of the first direction D1 and the second direction D2. The insulating layer structures 200 may respectively cover ends of adjacent first active patterns 103 in the third direction D3.

[0108] Reference Fig.25 A first conductive layer 230, a first barrier layer 240, a second conductive layer 250, and a first mask layer 260 may be sequentially stacked on the insulating layer structure 200, the first active pattern 103 and the isolation pattern 110 exposed by the first opening 220 on the first region I, and the second gate insulating layer 210 and the isolation pattern 110 on the second region II. The first conductive layer 230 may fill the first opening 220.

[0109] The first conductive layer 230 may include, for example, polysilicon doped with impurities, and the first barrier layer 240 may include metal silicon nitride, such as titanium silicon nitride (TiSiN). The second conductive layer 250 may include a metal, such as tungsten, and the first mask layer 260 may include a nitride, such as silicon nitride.

[0110] Reference Fig.26 , a first etching mask pattern (not shown) covering the first region I and exposing a portion of the second region II may be formed on the first mask layer 260. The first mask layer 260, the second conductive layer 250, the first barrier layer 240, and the first conductive layer 230 on the second region II of the substrate 100 may be sequentially etched using the first etching mask pattern as an etching mask to form a second gate structure 320 on the second region II of the substrate 100. The second gate structure 320 may include a second gate insulating pattern 270, a first conductive pattern 280, a first barrier pattern 290, a second conductive pattern 300, and a second gate mask 310. The first conductive pattern 280, the first barrier pattern 290, and the second conductive pattern 300, which are sequentially stacked, may be used as a gate electrode.

[0111] A gate spacer structure 350 may be formed on a sidewall of the second gate structure 320. The gate spacer structure 350 may include a first gate spacer 330 and a second gate spacer 340 sequentially stacked in a horizontal direction parallel to the upper surface of the substrate 100. In various example embodiments, the first gate spacer 330 may include, for example, silicon nitride, and the second gate spacer 340 may include, for example, silicon oxide.

[0112] After forming the second gate structure 320 , a first impurity region serving as a source / drain region may be formed at an upper portion of the second active pattern 105 adjacent to the second gate structure 320 by performing, for example, an ion implantation process.

[0113] Thereafter, a first etch stop layer 360 may be formed on the first mask layer 260, the isolation pattern 110, the second active pattern 105, the second gate structure 320, and the gate spacer structure 350 on the first and second regions I and II of the substrate 100. The first etch stop layer 360 may include, for example, silicon nitride.

[0114] Reference Fig. 27 , a first insulating interlayer 370 may be formed on the first etch stop layer 360 to have a sufficient height to cover the second gate structure 320. The upper surface of the first insulating interlayer 370 may be planarized until the upper surface of the first etch stop layer 360 located on the second gate structure 320 and the first mask layer 260 may be exposed. Therefore, the first insulating interlayer 370 may fill the space between the gate spacer structures 350 on the sidewalls of the second gate structure 320.

[0115] Thereafter, a first capping layer 380 including an insulating material may be formed on the first insulating interlayer 370 and the first etch stop layer 360 .

[0116] The first insulating interlayer 370 may include, for example, silicon oxide, and the first capping layer 380 may include, for example, silicon nitride.

[0117] Reference Fig.28 and Fig.29 , a portion of the first capping layer 380 on the first region I of the substrate 100 may be etched to form a first capping pattern 385. The first etch stop layer 360, the first mask layer 260, the second conductive layer 250, the first barrier layer 240, and the first conductive layer 230 may be etched using the first capping pattern 385 as an etching mask.

[0118] In various example embodiments, the first capping pattern 385 may extend in the second direction D2 on the first region I of the substrate 100. A plurality of first capping patterns 385 may be spaced apart from each other in the first direction D1. The first capping layer 380 may remain on the second region II of the substrate 100.

[0119] As the etching process is performed, the third conductive pattern 235, the second barrier pattern 245, the fourth conductive pattern 255, the first mask 265, the first etch stop pattern 365, and the first capping pattern 385 may be sequentially stacked in the first opening 220 on the first region I of the substrate 100. In addition, the third insulating pattern 195, the third conductive pattern 235, the second barrier pattern 245, the fourth conductive pattern 255, the first mask 265, the first etch stop pattern 365, and the first capping pattern 385 may be sequentially stacked on the second insulating layer 180 in the insulating layer structure 200 outside the first opening 220.

[0120] Hereinafter, the third conductive pattern 235 , the second barrier pattern 245 , the fourth conductive pattern 255 , the first mask 265 , the first etch stop pattern 365 , and the first capping pattern 385 , which are sequentially stacked, are referred to as a bit line structure 395 .

[0121] In various example embodiments, the bit line structure 395 may extend in the second direction D2 on the first region I of the substrate 100. A plurality of the bit line structures 395 may be spaced apart from each other in the first direction D1. The bit line structure 395 may extend in the second direction D2 while contacting a surface of the first active pattern 103 exposed by the first opening 220.

[0122] Reference Fig.30 , a preliminary spacer structure 460 may be formed on the sidewalls of the bit line structure 395. The preliminary spacer structure 460 may include a plurality of spacers. In some example embodiments, the preliminary spacer structure 460 may include a first spacer 400, a second spacer 410, a third spacer 420, a fourth spacer 430, and a fifth spacer 450 that are stacked laterally.

[0123] Reference Fig.31 A fence insulating pattern (not shown) may be formed in the gap between the preliminary spacer structures 460 . For example, the fence insulating pattern may include a nitride, such as silicon nitride. The fence insulating pattern may overlap the first gate structure 160 .

[0124] The second opening 440 having an isolation shape may be formed between the fence insulation pattern and the bit line structure 395. A central portion of the first active pattern 103 in the third direction D3 may be exposed by the second opening 440.

[0125] A lower contact plug layer may be formed on the first region I of the substrate 100 to fill the second opening 440 so as to have a sufficient height. An upper portion of the lower contact plug layer may be etched to form a lower contact plug 475. In the etching process, the lower contact plug layer formed on the second region II may be completely removed. The lower contact plug 475 may include, for example, polysilicon doped with impurities. The lower contact plug 475 may contact the isolation region of the substrate 100 between the bit line structures 395 and between the first gate structures 160.

[0126] Reference Fig.32 In the preliminary spacer structure 460 exposed by the upper portion of the lower contact plug 475, the upper portion of the preliminary spacer structure 460 may be partially removed to form a spacer structure. For example, portions of the fourth spacer 430 and the fifth spacer 450 may be removed.

[0127] Thereafter, a capping insulating layer may be formed on the bit line structure 395, the spacer structure 460a, the first capping pattern 385, the lower contact plug 475, and the first capping layer 380. The capping insulating layer may be anisotropically etched to form the capping insulating pattern 490. Thus, upper surfaces of the lower contact plugs 475 may be exposed between the capping insulating patterns 490.

[0128] Thereafter, a first metal silicide pattern 500 may be formed on the exposed upper surface of the lower contact plug 475. The first metal silicide pattern 500 may include, for example, cobalt silicide, nickel silicide, or titanium silicide.

[0129] Reference Fig.33 A second sacrificial layer 392 may be formed on the first capping layer 380, the capping insulating pattern 490, the first metal silicide pattern 500, and the lower contact plug 475. An upper surface of the second sacrificial layer 392 may be planarized until upper surfaces of the capping insulating pattern 490 and the first capping layer 380 are exposed.

[0130] The second sacrificial layer 392 may include, for example, silicon on hard mask (SOH), an amorphous carbon layer (ACL), or the like.

[0131] Thereafter, a first contact hole 510 may be formed on the second region II of the substrate 100 through the first capping layer 380, the first insulating interlayer 370, and the first etch stop layer 360. The first contact hole 510 may expose the first impurity region 102 of the second active pattern 105. A second metal silicide pattern 512 may be formed on an upper surface of the second active pattern 105 exposed by a bottom of the first contact hole 510.

[0132] The second sacrificial layer 392 may be removed.

[0133] Reference Fig.34A second barrier layer 530 may be formed on the capping insulating pattern 490, the first metal silicide pattern 500, and the lower contact plug 475 on the first region I of the substrate 100, and on the first capping layer 380, the surface of the first contact hole 510, and the second metal silicide pattern 512 on the second region II of the substrate 100. A first metal layer 540 may be formed on the second barrier layer 530 to fill the space between the bit line structures 395 and the first contact hole 510.

[0134] In some example embodiments, the second barrier layer 530 may include titanium, titanium nitride, tantalum, or tantalum nitride, and the first metal layer 540 may include tungsten.

[0135] Thereafter, a planarization process may be additionally performed on an upper portion of the first metal layer 540. The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0136] Reference Fig.35 and Fig.36 , a third etching mask pattern (not shown) may be formed on the first metal layer 540. The first metal layer 540, the second barrier layer 530, and the first capping layer 380 on the first region I and the second region II of the substrate 100 may be etched using the third etching mask pattern as an etching mask. Therefore, a landing pad pattern 584 and a third opening 590 may be formed on the first region I of the substrate 100, and a first conductive structure 556 and a fourth opening 560 may be formed on the second region II of the substrate 100.

[0137] The landing pad pattern 584 may include a third barrier pattern 580 and a first metal pattern 582 The first conductive structure 556 may include a fourth barrier pattern 550 and a second metal pattern 552 .

[0138] The first conductive structure 556 may include a first contact plug in the first contact hole 510 and a first conductive line on the first capping layer 380 and the first contact plug. For example, the first contact plug may contact the first impurity region 102 of the second region II of the substrate 100. The first conductive structure 556 may be electrically connected to a transistor for a peripheral circuit formed on the second region II of the substrate 100.

[0139] The third etch mask pattern may be removed.

[0140] Reference Fig.37 , a fourth insulating layer may be formed on the landing pad pattern 584 and the first conductive structure 556 to fill the third opening 590 and the fourth opening 560. The fourth insulating layer may include, for example, silicon nitride.

[0141] Thereafter, the fourth insulating layer may be planarized until upper surfaces of the first conductive structure 556 and the landing pad pattern 584 are exposed to form a first upper insulating pattern 572 in the third opening 590 and the fourth opening 560 .

[0142] In various example embodiments, an upper surface of the first upper insulating pattern 572 may be lower than upper surfaces of the first conductive structure 556 and the landing pad pattern 584 .

[0143] The lower contact plug 475 , the first metal silicide pattern 500 , and the landing pad pattern 584 sequentially stacked on the first region I of the substrate 100 may serve as a contact plug structure.

[0144] The first metal pattern 582 included in the landing pad pattern 584 and the second metal pattern 552 included in the first conductive structure 556 may include, for example, tungsten. Hereinafter, it may be explained that the first metal pattern 582 and the second metal pattern 552 include tungsten.

[0145] The upper surfaces of the first metal pattern 582 and the second metal pattern 552 may be exposed, and thus the upper surfaces of the first metal pattern 582 and the second metal pattern 552 may react with oxygen through natural oxidation to form a preliminary tungsten oxide layer 600 .

[0146] In various example embodiments, an ashing process, which is a heat treatment process that introduces oxygen, may be further performed on the first metal pattern 582 and the second metal pattern 552. When the ashing process is performed, a preliminary tungsten oxide layer 600 may be formed on upper surfaces of the first metal pattern 582 and the second metal pattern 552 to have a relatively thicker thickness than a preliminary tungsten oxide layer formed by natural oxidation.

[0147] Reference Fig.38 and Fig.39 , a surface plasma treatment process may be performed on the preliminary tungsten oxide layer 600. Therefore, at least a portion of the preliminary tungsten oxide layer 600 may be removed to form a tungsten oxide layer 600a, and a protective layer 602 may be generated on the tungsten oxide layer 600a.

[0148] In various example embodiments, the surface plasma treatment process may include a CO plasma treatment process. In this case, a portion of the preliminary tungsten oxide layer 600 may be removed to form a tungsten oxide layer 600a having a thickness less than that of the preliminary tungsten oxide layer 600. In addition, a protective layer 602 may be formed on the tungsten oxide layer 600a by generating a WOC bond or a WC bond on the tungsten oxide layer 600a. The protective layer 602 may be, for example, a WOC layer or a WC layer.

[0149] For example, the surface plasma treatment process may include only the CO plasma treatment process. For example, the surface plasma treatment process may include the CO plasma treatment process and the hydrogen plasma treatment process. The CO plasma treatment process may be performed after the hydrogen plasma treatment process is performed. When the hydrogen plasma treatment process is performed, all or part of the preliminary tungsten oxide layer 600 may be removed.

[0150] In some example embodiments, the surface plasma treatment process may include NH 3 Plasma treatment process. In this case, a portion of the preliminary tungsten oxide layer 600 may be removed to form a tungsten oxide layer 600a. Therefore, the tungsten oxide layer 600a may be formed to have a thickness smaller than that of the preliminary tungsten oxide layer 600. In addition, a protective layer 602 may be formed on the tungsten oxide layer 600a by generating a WON bond or a WN bond on the tungsten oxide layer 600a. The protective layer 602 may include nitrogen and may be, for example, a WON layer or a WN layer.

[0151] For example, the surface plasma treatment process may include only NH 3 Plasma treatment process. For example, the surface plasma treatment process may include NH 3 Plasma Treatment Process and Hydrogen Plasma Treatment Process The surface plasma treatment process may be performed after performing the hydrogen plasma treatment process.

[0152] In some example embodiments, the surface plasma treatment process may include only hydrogen plasma treatment.

[0153] In some example embodiments, the surface plasma treatment process may include CO plasma treatment and NH 3 Plasma treatment process.

[0154] When performing CO plasma treatment processes or NH 3 During the plasma treatment process, a tungsten oxide layer 600a and a protective layer 602 may be formed on the first metal pattern 582 and the second metal pattern 552. Fig.38 shown.

[0155] When a CO plasma treatment process or an NH 3 During the plasma treatment process, only the protective layer 602 may be formed on the first metal pattern 582 and the second metal pattern 552. Fig.39 shown.

[0156] In the following drawings, a tungsten oxide layer 600 a and a protective layer 602 may be shown on the first metal pattern 582 and the second metal pattern 552 .

[0157] Alternatively, only the hydrogen plasma treatment may be performed so that the protective layer may not be formed on the first metal pattern 582 and the second metal pattern 552. Therefore, only the tungsten oxide layer may be formed on the first metal pattern 582 and the second metal pattern 552, or the tungsten oxide layer may not be formed on the first metal pattern 582 and the second metal pattern 552.

[0158] Reference Fig.40 , a second etch stop layer 604 may be formed on the protection layer 602 and the first upper insulating pattern 572. The second etch stop layer 604 may include, for example, SiBN, SiCN, or SiN. For example, the second etch stop layer 604 may include SiBN as a material through which hydrogen may diffuse.

[0159] By performing the surface plasma treatment process, the upper surface of the protection layer 602 may become more uniform, and the second etch stop layer 604 may be formed on the protection layer 602 to have a more uniform thickness.

[0160] Reference Fig.41 , the unit capacitor 706 may be formed through the second etch stop layer 604, the protection layer 602, and the tungsten oxide layer 600a, and may contact the landing pad pattern 584 on the first region I of the substrate 100. The unit capacitor 706 may include a lower electrode 700, a dielectric layer 702, and an upper electrode 704. A plate electrode 708 may be formed on the upper electrode 704. The plate electrode 708 may include, for example, polysilicon and / or silicon germanium. In some example embodiments, the unit capacitor 706 may not be formed on the second region II of the substrate 100.

[0161] In the process of forming the unit capacitor 706 , most of the protection layer 602 and the tungsten oxide layer 600 a on the first region I of the substrate 100 may be removed.

[0162] Reference Fig.42 , a second insulating interlayer 710 may be formed to cover the plate electrode 708 and the second etch stop layer 604 .

[0163] A planarization process may be performed on the second insulating interlayer 710. Thus, an upper surface of the second insulating interlayer 710 may be substantially flat. The unit capacitor 706 may be formed only on the first region I of the substrate 100, and thus a thickness of the second insulating interlayer 710 on the second region II of the substrate 100 may be greater than a thickness of the second insulating interlayer 710 on the first region I of the substrate 100.

[0164] The upper contact plug 720 may be formed on the second region II of the substrate 100 through the second insulating interlayer 710, the second etch stop layer 604, the protective layer 602, and the tungsten oxide layer 600a, and may contact the second metal pattern 552. The upper contact plug 720 may include a metal. The upper contact plug 720 may include a barrier metal pattern and a metal pattern. The metal pattern may include, for example, tungsten.

[0165] Thereafter, a multilayer interconnection (not shown) may be formed on the upper contact plug 720, and a hydrogen diffusion insulating layer 730 for hydrogen diffusion may be formed on the multilayer interconnection. For example, the hydrogen diffusion insulating layer 730 may be a high density plasma (HDP) oxide layer. Hydrogen included in the hydrogen diffusion insulating layer 730 may diffuse to the surface of the substrate 100. Dangling bonds on the surface of the substrate 100 may be removed by hydrogen, and thus the characteristics of the semiconductor device may be improved.

[0166] A semiconductor device can be manufactured through the above-mentioned processes.

[0167] The semiconductor device may have the following structural features.

[0168] Refer again Fig.36 and Fig.42 , a semiconductor device may be formed on a substrate 100 including a first region I and a second region II.

[0169] The first active pattern 103 may be formed on the first region I of the substrate 100, and the second active pattern 105 may be formed on the second region II of the substrate 100. An isolation pattern 110 may be formed between the first active pattern 103 and the second active pattern 105.

[0170] The first gate structure 160, the bit line structure 395, the spacer structure 460a, the first upper insulating pattern 572, the contact plug structure, and the cell capacitor 706 may be formed on the first region I of the substrate 100. The second gate structure 320, the first insulating interlayer 370, the first capping layer 380, the first conductive structure 556, the tungsten oxide layer 600a, the protection layer 602, the first upper insulating pattern 572, the second etch stop layer 604, the second insulating interlayer 710, and the upper contact plug 720 may be formed on the second region II of the substrate 100. In some example embodiments, the tungsten oxide layer 600a may not be formed on the first conductive structure 556, and the protection layer 602 may be formed on the first conductive structure 556.

[0171] In addition, an upper wiring and a hydrogen diffusion insulating layer 730 may be further included on the first region I and the second region II of the substrate 100 .

[0172] like Fig. 22As shown, the first gate structure 160 may be buried in the first region I of the substrate 100. The first gate structure 160 may extend in the first direction D1. A plurality of first gate structures 160 may be spaced apart from each other in the second direction D2. An impurity region may be formed at an upper portion of the first active pattern 103 adjacent to the first gate structure 160. The first gate structure 160 and the impurity region may function as a cell transistor.

[0173] The insulating pattern structure may be disposed on the first active pattern 103 and the isolation pattern 110 on the first region I. The insulating pattern structure may include a first insulating pattern 175, a second insulating pattern 185, and a third insulating pattern 195 sequentially stacked.

[0174] The bit line structure 395 may be disposed on the first region I, and the bit line structure 395 may include a third conductive pattern 235, a second barrier pattern 245, a fourth conductive pattern 255, a first mask 265, a first etch stop pattern 365, and a first capping pattern 385 stacked in sequence. In various example embodiments, the bit line structure 395 may be formed on the first active pattern 103 and the third insulating pattern 195, and may extend in the second direction D2. A plurality of bit line structures 395 may be spaced apart from each other in the first direction D1. The bottom of the bit line structure 395 may include a portion contacting a portion of the surface of the first active pattern 103 and a portion contacting the third insulating pattern 195.

[0175] The second gate structure 320 may be disposed on the second active pattern 105 on the second region II of the substrate 100 .

[0176] The second gate structure 320 may include a second gate insulating pattern 270 , a first conductive pattern 280 , a first barrier pattern 290 , a second conductive pattern 300 , and a second gate mask 310 , which are sequentially stacked.

[0177] The gate spacer structure 350 may be formed on the sidewalls of the second gate structure 320. The gate spacer structure 350 may include, for example, a first gate spacer 330 and a second gate spacer 340.

[0178] The first impurity region 102 may be disposed at the second active pattern 105 adjacent to the second gate structure 320. The second gate structure 320 and the first impurity region 102 may function as a transistor for a peripheral circuit.

[0179] The first etch stop layer 360 may be formed along surface profiles of the second gate structure 320, the gate spacer structure 350, and the second active pattern 105. The first etch stop layer 360 may include, for example, silicon nitride.

[0180] The first insulating interlayer 370 may be disposed on the first etch stop layer 360 to fill the space between the second gate structures 320. The first capping layer 380 may be disposed on the first insulating interlayer 370 and the first etch stop layer 360. The first insulating interlayer 370 may include, for example, silicon oxide, and the first capping layer 380 may include, for example, silicon nitride.

[0181] The stacked structure including the third conductive pattern 235, the second barrier pattern 245, the fourth conductive pattern 255 and the first mask 265 included in the bit line structure 395 can be basically the same as the stacked structure including the first conductive pattern 280, the first barrier pattern 290, the second conductive pattern 300 and the second gate mask 310 included in the second gate structure 320.

[0182] The first etch stop pattern 365 of the bit line structure 395 may be formed by the same deposition process as the deposition process of the first etch stop layer 360 on the second region II of the substrate 100. Therefore, the first etch stop pattern 365 and the first etch stop layer 360 may include the same material. The first capping pattern 385 of the bit line structure 395 may be formed by the same deposition process as the first capping layer 380 on the second region II of the substrate 100. Therefore, the first capping pattern 385 and the first capping layer 380 may include the same material.

[0183] The spacer structure 460a may be disposed on a sidewall of the bit line structure 395. The spacer structure 460a may include a plurality of spacers stacked from the sidewall of the bit line structure 395. In some example embodiments, the spacer structure 460a may include a first spacer 400, a second spacer 410, a third spacer 420, a fourth spacer 430, and a fifth spacer 450 sequentially stacked from the sidewall of the bit line structure 395.

[0184] A fence insulation pattern (not shown) may be disposed on the first gate structure 160 between the bit line structures 395 .

[0185] A second opening 440 exposing the first active pattern 103 may be formed between the bit line structure 395 and the fence insulation pattern. A lower contact plug 475 and a landing pad pattern 584 may be disposed in the second opening 440. The lower contact plug 475 and the landing pad pattern 584 may serve as a contact plug structure.

[0186] The lower contact plug 475 may include, for example, polysilicon doped with impurities.

[0187] In various example embodiments, the first metal silicide pattern 500 may be disposed between the lower contact plug 475 and the landing pad pattern 584. The first metal silicide pattern 500 may include, for example, cobalt silicide, nickel silicide, or titanium silicide.

[0188] The first upper insulating pattern 572 may be disposed between the landing pad patterns 584 .

[0189] The first contact hole 510 may pass through the first capping layer 380, the first insulating interlayer 370, and the first etch stop layer 360 on the second region II of the substrate 100. The first impurity region 102 may be exposed by the first contact hole 510.

[0190] The first conductive structure 556 may be disposed on the first capping layer 380 to fill the first contact hole 510. The first conductive structure 556 may include a fourth barrier pattern 550 and a second metal pattern 552. The first conductive structure 556 may include a first contact plug in the first contact hole 510 and a first conductive line on the first contact plug and the first capping layer 380. The second metal pattern 552 may include, for example, tungsten.

[0191] The second metal silicide pattern 512 may be disposed between the bottom of the first contact plug and the second active pattern 105 .

[0192] The fourth opening 560 may be formed between the first conductive structures 556 .

[0193] The first upper insulating pattern 572 may be formed in the fourth opening 560 . An upper surface of the first upper insulating pattern 572 may be lower than an upper surface of the second metal pattern 552 .

[0194] In some example embodiments, the tungsten oxide layer 600a and the protective layer 602 may be stacked on an upper surface of the second metal pattern 552. The tungsten oxide layer 600a and the protective layer 602 may not be formed on the first upper insulating pattern 572. The protective layer 602 may include, for example, WOC, WC, WON, WN, etc.

[0195] In some example embodiments, only the protection layer 602 may be disposed on the second metal pattern 552 .

[0196] The second etch stop layer 604 may cover the protection layer 602 and the first upper insulating pattern 572. The second etch stop layer 604 may include, for example, SiBN, SiCN, or SiN. For example, the second etch stop layer 604 may include SiBN as a material through which hydrogen may diffuse.

[0197] The unit capacitor 706 may pass through the second etch stop layer 604 and may contact the landing pad pattern 584 on the first region I of the substrate 100. The upper electrode 704 may further include a plate electrode 708 thereon.

[0198] The second insulating interlayer 710 may cover the cell capacitor 706 and the second etch stop layer 604. The upper contact plug 720 may pass through the second insulating interlayer 710, the second etch stop layer 604, the protection layer 602, and the tungsten oxide layer 600a. The upper contact plug 720 may contact the second metal pattern 552.

[0199] Multilayer wirings and a hydrogen diffusion insulating layer 730 for hydrogen diffusion may be disposed on the upper contact plug 720 .

[0200] The foregoing is an illustration of various example embodiments and is not to be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept.

[0201] This application claims the priority of Korean Patent Application No. 10-2023-0140495 filed on October 19, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an insulating intermediate layer on the substrate; forming a tungsten pattern inside and on the insulating interlayer; forming an insulating pattern on the insulating interlayer to fill the space between the tungsten patterns, the insulating pattern having a lowest point of an upper surface, the lowest point being lower than an upper surface of each of the tungsten patterns; forming a preliminary tungsten oxide layer on the upper surface of each of the tungsten patterns; performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer; as well as An etch stop layer is formed on the protection layer and the insulating pattern.

2. The method according to claim 1, wherein: The first surface plasma treatment includes a CO plasma treatment.

3. The method according to claim 2, wherein: The protection layer includes a WOC layer or a WC layer.

4. The method according to claim 1, wherein: The first surface plasma treatment includes NH 3 plasma treatment.

5. The method according to claim 4, wherein: The protection layer includes a WON layer or a WN layer.

6. The method according to claim 1, wherein: Before performing the first surface plasma treatment, hydrogen plasma treatment is further performed to remove all or a portion of the preliminary tungsten oxide layer.

7. The method according to claim 1, wherein: The etch stop layer includes SiBN, SiCN or SiN.

8. The method according to claim 1, wherein: The first surface plasma treatment is performed so that a sum of thicknesses of the tungsten oxide layer and the protective layer is smaller than a thickness of the preliminary tungsten oxide layer.

9. The method according to claim 1, wherein: After forming the etch stop layer, the method further comprises: forming a second insulating interlayer on the etch stop layer; and A contact plug is formed through the second insulating interlayer, the etch stop layer, the protection layer, and the tungsten oxide layer and contacts each of the tungsten patterns.

10. The method according to claim 1, wherein: Forming the tungsten pattern includes: Etching the insulating interlayer to form a contact hole exposing the upper surface of the substrate; forming a tungsten layer on the insulating interlayer to fill the contact hole; and The tungsten layer on the insulating interlayer is patterned.

11. The method according to claim 1, wherein: Forming the preliminary tungsten oxide layer includes performing a heat treatment process to introduce oxygen.

12. A method for manufacturing a semiconductor device, comprising: forming a bit line structure on a cell region of a substrate; forming a gate structure on a peripheral circuit region of the substrate; forming an insulating intermediate layer covering the gate structure on the peripheral circuit region of the substrate; forming a lower contact plug contacting the substrate and a landing pad pattern including tungsten on the lower contact plug, the lower contact plug and the landing pad pattern being between the bit line structure; forming a first conductive structure including tungsten on the insulating interlayer, the first conductive structure passing through the insulating interlayer and contacting a surface of the substrate; forming an insulating pattern between the landing pad patterns and between the first conductive structures; forming a preliminary tungsten oxide layer on an upper surface of the landing pad pattern and an upper surface of the first conductive structure, respectively; performing a first surface plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer; forming an etch stop layer on the protection layer and the insulating pattern; forming a capacitor on the landing pad pattern, the capacitor penetrating the etch stop layer, the protection layer, and the tungsten oxide layer on the cell region of the substrate; as well as A contact plug is formed to contact an upper surface of the first conductive structure, the contact plug passing through the etch stop layer, the protection layer, and the tungsten oxide layer on the peripheral circuit region of the substrate.

13. The method according to claim 12, wherein: The first surface plasma treatment includes CO plasma treatment or NH 3 plasma treatment.

14. The method according to claim 13, wherein: The protection layer includes a WOC layer, a WC layer, a WON layer or a WN layer.

15. The method according to claim 12, wherein: Before performing the first surface plasma treatment, hydrogen plasma treatment is further performed to remove all or a portion of the preliminary tungsten oxide layer.

16. The method according to claim 12, wherein: The etch stop layer includes SiBN, SiCN or SiN.

17. The method according to claim 12, wherein: The first surface plasma treatment is performed so that a sum of thicknesses of the tungsten oxide layer and the protective layer is smaller than a thickness of the preliminary tungsten oxide layer.

18. A method for manufacturing a semiconductor device, comprising: forming a lower structure on the substrate; forming a first lower insulating interlayer including silicon oxide on the lower structure; forming a second lower insulating interlayer including silicon nitride on the first lower insulating interlayer; forming a tungsten pattern on the second lower insulating interlayer, the tungsten pattern passing through the first lower insulating interlayer and the second lower insulating interlayer; forming an insulating pattern including silicon nitride on the second lower insulating interlayer, the insulating pattern filling a space between the tungsten patterns and having a lowest point of an upper surface that is lower than an upper surface of each of the tungsten patterns; forming a preliminary tungsten oxide layer on the upper surface of each of the tungsten patterns; performing a CO plasma treatment on the preliminary tungsten oxide layer to remove at least a portion of the preliminary tungsten oxide layer, thereby forming a tungsten oxide layer and a protective layer on the tungsten oxide layer, the protective layer including at least tungsten and carbon; and An etch stop layer is formed on the protection layer and the insulating pattern.

19. The method according to claim 18, wherein: Before performing the CO plasma treatment, hydrogen plasma treatment is further performed to remove all or a portion of the preliminary tungsten oxide layer.

20. The method according to claim 18, wherein: The etch stop layer includes SiBN, SiCN or SiN.

Images