Semiconductor laminate, semiconductor element, and method for manufacturing semiconductor laminate

Abstract

The invention provides a high-quality semiconductor laminate, a semiconductor element, and a method for manufacturing the semiconductor laminate. This semiconductor laminate is provided with: a substrate that contains silicon carbide and has a main surface; a first layer that is provided on the main surface of the substrate and contains crystals of aluminum nitride; the second layer is arranged on the first layer and comprises any crystal of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride; and a third layer that is provided on the second layer and contains a crystal of gallium nitride, the first layer having a tensile strain at 27 DEG C in a direction along the main surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor stack, a semiconductor element, and a method for manufacturing a semiconductor stack. Background Art

[0002] High Electron Mobility Transistor (HEMT) of group III nitride is widely used as a power amplifier for mobile phone base stations (e.g., Patent Document 1). In group III nitride HEMT, the power that can be input per element can be greatly increased compared to conventional Si-based devices. This makes it possible to miniaturize base stations and significantly reduce installation costs.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-228642 Summary of the invention

[0006] Problems to be solved by the invention

[0007] An object of the present invention is to obtain a high-quality semiconductor stack and a semiconductor element.

[0008] Means of solving the problem

[0009] According to one embodiment of the present invention, there is provided a semiconductor stack comprising:

[0010] A substrate comprising silicon carbide and having a main surface;

[0011] a first layer provided on the main surface of the substrate and comprising a crystal of aluminum nitride;

[0012] A second layer disposed on the first layer, comprising any one of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride;

[0013] a third layer of crystals comprising gallium nitride disposed on the second layer,

[0014] The first layer has a tensile strain along the main surface at 27°C.

[0015] According to another aspect of the present invention, there is provided a semiconductor device, wherein:

[0016] The third layer included in the semiconductor stack described in the above aspect is provided as at least a part of the handling layer.

[0017] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor stack, comprising the following steps:

[0018] (a) a step of preparing a substrate including silicon carbide and having a main surface;

[0019] (b) a step of growing a first layer of crystals including aluminum nitride on the main surface of the substrate;

[0020] (c) performing an annealing process on the first layer;

[0021] (d) a step of growing a second layer including any one of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride crystals on the first layer;

[0022] (e) a step of growing a third layer of crystals including gallium nitride on the second layer,

[0023] In (c), by annealing the first layer, the dislocation density in the main surface of the first layer is made lower than the dislocation density in the main surface of the first layer after (b).

[0024] Effects of the Invention

[0025] According to the present invention, a high-quality semiconductor stack and semiconductor element can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic cross-sectional view showing a semiconductor stack according to one embodiment of the present invention.

[0027] Figure 2 This is a schematic cross-sectional view showing a semiconductor element according to one embodiment of the present invention.

[0028] Figure 3 This is a flowchart showing a method for manufacturing a semiconductor stack and a method for manufacturing a semiconductor element according to one embodiment of the present invention.

[0029] Figure 4A This is a diagram showing the full width at half maximum of (0002) diffraction of the electron transport layer obtained by X-ray rocking curve measurement, corresponding to the Al composition ratio of the intermediate layer.

[0030] Figure 4B This is a diagram showing the full width at half maximum of the (0002) diffraction of the electron transport layer obtained by X-ray rocking curve measurement corresponding to the (0002) diffraction angle 2θ of the electron transport layer.

[0031] Figure 5A This is a graph showing the full width at half maximum of (0002) diffraction of the electron transport layer obtained by X-ray rocking curve measurement, corresponding to the thickness of the electron transport layer.

[0032] Figure 5B This is a graph showing the full width at half maximum of (10-12) diffraction of the electron transport layer obtained by X-ray rocking curve measurement, corresponding to the thickness of the electron transport layer.

[0033] Explanation of symbols

[0034] 1Semiconductor laminate (laminate)

[0035] 2 Semiconductor components

[0036] 10 Substrate

[0037] 20 Bottom Floor

[0038] 30 Middle Layer

[0039] 40 Electron transport layer

[0040] 50 Electron supply layer

[0041] 60 Overlay DETAILED DESCRIPTION

[0042] <Knowledge acquired by the inventors>

[0043] First, the findings obtained by the present inventors will be described.

[0044] Silicon carbide (SiC), aluminum nitride (AlN), and gallium nitride (GaN) that constitute the III-nitride HEMT have the linear expansion coefficient, a-axis length (lattice constant in the a-axis direction), and c-axis length (lattice constant in the c-axis direction) shown in Table 1 below in the bulk state. In addition, the linear expansion coefficient has a large change due to temperature and is also dependent on the concentration of doping, so there is a large degree of uncertainty. However, the absolute value relationship of the linear expansion coefficient (6H-SiC<GaN<AlN) is clear.

[0045]

Table 1

[0046]

[0047] In a stacked product for manufacturing a HEMT, the lattice constant of each crystal, the linear expansion coefficient of each crystal, and the temperature-dependent state of each layer affect the crystal quality.

[0048] Here, referring to Table 2 below, a comparison is made between a conventional laminate for manufacturing a HEMT, the laminate of Patent Document 1, and the laminate of the present invention discovered by the inventors.

[0049]

Table 2

[0050]

[0051] [Existing laminated material]

[0052] The conventional stacked product has, in order, a SiC substrate, an AlN layer as a bottom layer, a GaN layer as an electron transport layer, and an aluminum gallium nitride (AlGaN) layer as an electron supply layer.

[0053] In the conventional AlN layer growth process, for example, an AlN layer is grown on a SiC substrate with a thickness of, for example, 100 nm or less. Since the AlN layer is grown on a different substrate, the AlN layer obtained has a thickness of 10 9 ~10 10 cm －2 The extremely high threading dislocation density of about 1000 nm indicates poor crystallinity. In the conventional method, it is found that the dislocation density of the AlN layer does not improve even if the thickness of the AlN layer is several μm.

[0054] In the conventional GaN layer growth process, the GaN layer is grown on the AlN layer with a large dislocation density. Therefore, the obtained GaN layer also has a dislocation density of 10 9 cm －2 The layer with poor crystallinity above the level.

[0055] In addition, in the conventional GaN layer growth process, since the GaN layer with a relatively large lattice constant is grown on the AlN layer with a relatively small lattice constant, compressive strain is applied to the GaN layer during the growth of the GaN layer. Therefore, new dislocations caused by crystal strain occur in the GaN layer. As a result, the crystallinity of the GaN layer is reduced in the conventional stack.

[0056] Even with the conventional method, when the thickness of the GaN layer is made to be 2 μm or more, the number of dislocations decreases as the GaN layer grows thicker. As a result, the GaN layer has a dislocation density of 10 8 cm －2 However, when the thickness of the GaN layer is less than 2 μm, it is difficult to achieve a dislocation density of 10 8 cm －2 Below level.

[0057] [Laminate of Patent Document 1]

[0058] The stacked product of Patent Document 1 includes, in order: a SiC substrate; an AlN layer as a bottom layer; a first AlGaN layer as an intermediate layer; a GaN layer as an electron transit layer; and a second AlGaN layer as an electron supply layer.

[0059] In Patent Document 1, since no special treatment for reducing the dislocation density of the AlN layer is performed, it is estimated that the AlN layer has a dislocation density of 10 9 ~1010 cm －2 The very high threading dislocation density of about 10 indicates poor crystallinity. In the growth of the AlGaN layer and the GaN layer on the AlN layer, no special measures were taken to reduce the dislocation density. Therefore, it is believed that the GaN layer, which is the electron transport layer, also has a dislocation density of 10 9 cm －2 The layer with poor crystallinity above the level.

[0060] Here, in Patent Document 1, the lattice constant of the AlGaN layer is replaced with a value close to the lattice constant of the bulk GaN crystal by doping the AlGaN layer with impurities. This is believed to be for the purpose of suppressing the generation of new dislocations in the GaN layer due to lattice distortion. However, as mentioned above, the dislocation density of the AlN layer as the underlying layer and the dislocation density of the AlGaN layer that inherits the dislocation density of the AlN layer are inherently high. Therefore, it is believed that even if the AlGaN layer is doped with impurities, the dislocation density of the GaN layer will remain unchanged at 10 9 cm －2 High value above level.

[0061] In addition, Patent Document 1 states that the lattice constant of the entire GaN layer is substantially equal to the lattice constant of the bulk GaN crystal, that is, the GaN layer is lattice relaxed at room temperature (Paragraph 0016). That is, the GaN layer is lattice relaxed at room temperature, which is equivalent to applying compressive strain to the GaN layer at the growth temperature of the GaN layer based on the magnitude relationship and absolute value of the linear expansion coefficient mentioned above. Therefore, in the GaN layer growth process, new dislocations caused by crystal strain occur in the GaN layer. As a result, it is believed that the crystallinity of the GaN layer is reduced in the stack of Patent Document 1.

[0062] [Overview of the Laminated Product of the Present Invention]

[0063] The inventors of the present invention have studied a semiconductor stack, which, as a stack for manufacturing HEMT, has in order: a SiC substrate; an AlN layer as a bottom layer that has been annealed; an AlGaN layer as an intermediate layer; a GaN layer as an electron transport layer; and an AlGaN layer as an electron supply layer.

[0064] As a result of intensive studies, the present inventors have successfully found the following structure.

[0065] In the structure of the present invention, the dislocation density of the AlN layer is reduced by annealing the AlN layer. As a result, the AlN layer has tensile strain in the direction along the main surface of the SiC substrate at 27°C. Based on such a structure, since the layers above the AlN layer (AlGaN layer and GaN layer) inherit the low dislocation density of the AlN layer, the layers above the AlN layer can be grown in a state of low dislocation density at the growth temperature of the III-nitride crystal.

[0066] In addition, in the structure of the present invention, an AlGaN layer having these intermediate compositions is interposed between the AlN layer and the GaN layer. As described above, the AlGaN layer has a low dislocation density inherited from the dislocation density of the AlN layer, and contains Ga that weakens the bonding force between atoms. Thus, the GaN layer can be grown on the AlGaN layer in a state close to no strain at the growth temperature of the III-nitride crystal.

[0067] As a result, the GaN layer has tensile strain in the direction along the main surface of the SiC substrate at 27° C. The GaN layer has tensile strain at room temperature, which is equivalent to the GaN layer growing in a state close to no strain at the growth temperature of the GaN layer based on the magnitude relationship and absolute value of the linear expansion coefficient mentioned above.

[0068] By growing the GaN layer in a state close to being strain-free in this way, the occurrence of new dislocations due to crystal strain can be suppressed in the GaN layer having a low dislocation density inherited from the AlN layer via the AlGaN layer. As a result, a GaN layer with good crystallinity can be obtained in the structure of the present invention.

[0069] The present invention described below is based on the above-mentioned findings found by the present inventors.

[0070] [Details of Embodiments of the Invention]

[0071] Next, one embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to these examples, and is intended to include all modifications within the scope of the claims and within the meaning and scope of the claims.

[0072] <One embodiment of the present invention>

[0073] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

[0074] (1) Semiconductor stack

[0075] Reference Figure 1 , a semiconductor stack (Group III nitride stack substrate) 1 according to this embodiment will be described.

[0076] Hereinafter, in crystals of group III nitride semiconductors having a wurtzite structure, the <0001> axis is referred to as the "c-axis", and the (0001) plane is referred to as the "c-plane". In addition, the (0001) plane is sometimes referred to as the "+c plane (group III element polar plane)", and the (000-1) plane is referred to as the "-c plane (nitrogen (N) polar plane)". In addition, the <1-100> axis (for example, the [1-100] axis) is referred to as the "m-axis", and the {1-100} plane is referred to as the "m-plane". In addition, the <11-20> axis (for example, the [11-20] axis) is referred to as the "a-axis", and the {11-20} plane is referred to as the "a-plane".

[0077] Hereinafter, the lattice constant of a crystal in a state where no lattice distortion occurs (a state without strain) may be referred to as a "bulk lattice constant" or a "completely relaxed lattice constant". The "arcsec" used as the unit of the full width at half maximum FWHM in the X-ray rocking curve measurement described later means arcsecond.

[0078] like Figure 1 As shown, the semiconductor stack 1 of this embodiment (hereinafter also referred to as "stack 1") includes, for example, a substrate 10, a bottom layer (first layer) 20, an intermediate layer (second layer, buffer layer) 30, an electron transport layer (third layer) 40, and an electron supply layer (fourth layer) 50. In addition, the stack 1 may also include a capping layer (fourth layer) 60. However, as described later, the capping layer 60 may not be provided.

[0079] (Substrate)

[0080] The substrate 10 is formed of, for example, silicon carbide (SiC). The polytype of the SiC substrate used as the substrate 10 is not limited, and may be, for example, 4H, 6H, or 3C. Alternatively, the substrate 10 may be a substrate other than SiC, such as Si, sapphire, or a composite substrate in which only the uppermost surface is 4H, 6H, or 3C.

[0081] The conductivity of the substrate 10 is not particularly limited, but is preferably semi-insulating.

[0082] The substrate 10 has a main surface (basal surface) 11. In the present embodiment, the low-index crystal plane closest to the main surface 11 is, for example, a c-plane ((0001) plane, Si plane).

[0083] The c-axis of the substrate 10 can be tilted at a predetermined angle relative to the normal of the main surface 11. The magnitude of the angle of the main surface 11 can be, for example, higher than 0° and lower than 1°, or higher than 0° and lower than 0.1°. The angle of the main surface 11 can have a distribution within the above range. In addition, the tilt direction (deviation direction) of the angle of the main surface 11 is not limited, and can be, for example, the a-axis direction, or the m-axis direction.

[0084] The diameter of the substrate 10 may be, for example, 2 inches (50.8 mm) or more, or 4 inches (100 mm) or more, or 6 inches (150 mm) or more.

[0085] The thickness of the substrate 10 is not particularly limited, but is determined by the diameter of the substrate 10. Specifically, the thickness of the substrate 10 with a diameter of 2 inches is, for example, 300 μm or more and 500 μm or less (usually 430 μm), the thickness of the substrate 10 with a diameter of 4 inches is, for example, 400 μm or more and 1000 μm or less (usually 500 μm), and the thickness of the substrate 10 with a diameter of 6 inches is, for example, 400 μm or more and 1500 μm or less (usually 600 μm).

[0086] The root mean square roughness RMS of a 5 μm square region of the main surface 11 of the substrate 10 is measured by an atomic force microscope (AFM) and is, for example, 1 nm or less, or may be 0.5 nm or less.

[0087] (Ground Floor)

[0088] The bottom layer 20 is, for example, formed by replacing the crystal of the main surface 11 of the substrate 10 which is 4H, 6H or 3C with 2H of the group III nitride semiconductor of the wurtzite structure. Specifically, the bottom layer 20 is, for example, provided on the main surface 11 of the substrate 10 and is formed of AlN crystal. The bottom layer 20 is, for example, formed by heteroepitaxially growing AlN crystal on the main surface 11 of the substrate 10.

[0089] The underlying layer 20 has a primary surface 21. The low-index crystal plane closest to the primary surface 21 of the underlying layer 20 is, for example, a c-plane ((0001) plane, Al plane).

[0090] The base layer 20 is, for example, continuously provided over the entire main surface 11 of the substrate 10. In other words, the base layer 20 is, for example, not separated into a plurality of islands. Thus, the main surface 21 of the entire base layer 20 can be converted into a 2H structure.

[0091] In this embodiment, as described later, by performing the annealing step S30 after the base layer forming step S20, the dislocation density of the main surface 21 of the base layer 20 after the annealing step S30 is reduced compared to the dislocation density of the main surface 21 of the base layer 20 after the base layer forming step S20. Specifically, the dislocation density of the main surface 21 of the base layer 20 after the base layer forming step S20 is 10 10 cm －2 The dislocation density of the primary surface 21 of the base layer 20 after the annealing step S30 is reduced to, for example, 1×10 10 cm －2 Below, or 1×10 9 cm －2As a result, the intermediate layer 30 including AlGaN crystal and the electron transport layer 40 including GaN crystal can be grown above the bottom layer 20 at the growth temperature of the group III nitride crystal in a state with low dislocation density. As a result of this annealing step S30, the bottom layer 20 composed of AlN crystal has tensile strain in the direction along the main surface 11 of the substrate 10 (for example, the a-axis direction) at 27°C.

[0092] The strain amount of the underlying layer 20 in the a-axis direction and the strain amount of the underlying layer 20 in the c-axis direction depend on, for example, the lattice constants of the substrate 10 and the underlying layer 20, the linear expansion coefficients of the substrate 10 and the underlying layer 20, the conditions of the annealing step S30, etc.

[0093] The "strain amount in the a-axis direction" mentioned here means, for example, the ratio of the a-axis length (lattice constant in the a-axis direction) of the crystal constituting the specified layer to the a-axis length of the unstrained bulk crystal. When the strain amount is a positive value, it means that the crystal has tensile strain. When the strain amount is a negative value, it means that the crystal has compressive strain. The "strain amount in the c-axis direction" is defined in the same way as the "strain amount in the a-axis direction", except that the a-axis direction is replaced by the c-axis direction.

[0094] In the present embodiment, as described above, at 27° C., since the primary layer 20 has tensile strain in the direction along the main surface 11 , the strain amount of the primary layer 20 in the a-axis direction is a positive value.

[0095] On the other hand, in the present embodiment, at 27° C., the underlying layer 20 has a compressive strain in a direction perpendicular to the main surface 11 , that is, the strain amount in the c-axis direction of the underlying layer 20 is a negative value.

[0096] The strain amount ε1 (%) of the base layer 20 in the c-axis direction at 27° C. can be obtained, for example, by the following formula (1).

[0097] ε1=(c1-c AlN ) / c AlN ×100…(1)

[0098] Here, c1 is the c-axis length of the AlN crystal constituting the underlying layer 20. c1 is obtained by measuring the diffraction angle of the (0002) plane of the underlying layer 20 by X-ray diffraction measurement (2θ-ω scanning). AlN is the c-axis length of the unstrained bulk AlN crystal.

[0099] Specifically, the strain amount ε1 (%) of the base layer 20 in the c-axis direction at 27° C. is also determined by the linear expansion coefficient of the substrate 10 , but is generally, for example, not less than −0.1% and less than −0.01%.

[0100] In the present embodiment, the thickness of the underlying layer 20 is, for example, not less than 200 nm and not more than 800 nm, or may be not less than 300 nm and not more than 500 nm.

[0101] By setting the thickness of the underlying layer 20 to be 200 nm or more, the primary surface 11 of the substrate 10 can be stably covered and the underlying layer 20 can be grown by hydride vapor phase epitaxy (HVPE). The thickness of the underlying layer 20 can also be stably controlled by HVPE.

[0102] By making the thickness of the bottom layer 20 greater than 200 nm, it is possible to suppress the diffusion of impurities from the substrate 10 to the electron transport layer 40 via the bottom layer 20. Specifically, when the substrate 10 is a SiC substrate, it is possible to suppress the diffusion of Si from the substrate 10 to the electron transport layer 40. Thus, even if there is no high-concentration doping of impurities such as Fe and C that form deep energy levels between the bottom layer 20 including AlN crystals and the electron transport layer 40 including GaN crystals, buffer leakage can be suppressed.

[0103] On the other hand, by setting the thickness of the primary layer 20 to 800 nm or less, a decrease in productivity can be suppressed.

[0104] By setting the thickness of the primary coat 20 to be 800 nm or less, warping of the laminate 1 and cracking of the primary coat 20 and the like caused by differences in linear expansion coefficients between the primary coat 20 and other layers can be suppressed.

[0105] In this embodiment, the HVPE method that can grow at a high speed is used to grow the bottom layer 20. In the conventional MOVPE method, it takes several hours to grow the bottom layer 20 including AlN crystals of 200 nm or more and 800 nm or less. In contrast, in this embodiment, the bottom layer 20 can be grown in a few minutes by using the HVPE method.

[0106] In this embodiment, the base layer 20 is grown by the HVPE method without using an organic raw material, and it is possible to suppress the excessive carbon (C) from entering the base layer 20. Specifically, the C concentration in the base layer 20 is, for example, 1×10 19 cm －3 Below, or 1×10 18 cm －3 Below, or 1×10 17 cm －3 the following.

[0107] In the present embodiment, the underlying layer 20 having a thickness within the above range is grown by the HVPE method, and then the annealing step S30 described later is performed, so that the crystallinity of the underlying layer 20 can be improved.

[0108] Here, when the thickness of the underlying layer 20 is measured by X-ray rocking curve and the obtained full width at half maximum (FWHM) of diffraction of a predetermined crystal plane of AlN is plotted, the full width at half maximum of the X-ray diffraction of AlN shows a downward convex tendency.

[0109] Specifically, for example, when the thickness of the underlying layer 20 is greater than 200 nm and less than 800 nm, the half-maximum full width of the (0002) diffraction of the underlying layer 20 obtained by X-ray rocking curve measurement is less than 200 seconds (arcsec), and the half-maximum full width of the (10-12) diffraction of the underlying layer 20 obtained by X-ray rocking curve measurement is less than 400 seconds.

[0110] For example, when the thickness of the base layer 20 is greater than or equal to 300 nm and less than or equal to 500 nm, the half maximum full width of the (0002) diffraction of the base layer 20 obtained by X-ray rocking curve measurement is less than or equal to 180 seconds, and the half maximum full width of the (10-12) diffraction of the base layer 20 obtained by X-ray rocking curve measurement is less than or equal to 380 seconds.

[0111] By improving the crystallinity of the underlying layer 20 in this manner, the crystallinity of each layer grown on the underlying layer 20 can be improved.

[0112] (Middle layer)

[0113] The intermediate layer 30 is provided on the main surface 21 of the bottom layer 20, for example, and is formed of AlGaN crystals. The intermediate layer 30 is formed, for example, by heteroepitaxially growing AlGaN crystals on the main surface 21 of the bottom layer 20. That is, the intermediate layer 30 formed of AlGaN crystals having these intermediate compositions is interposed between the bottom layer 20 and the electron transit layer 40. Thus, the lattice distortion caused by the lattice mismatch between the bottom layer 20 including AlN crystals and the electron transit layer 40 including GaN crystals can be further alleviated.

[0114] The intermediate layer 30 has a primary surface 31. The low-index crystal plane closest to the primary surface 31 of the intermediate layer 30 is, for example, a c-plane ((0001) plane, a Group III element polar plane).

[0115] In the present embodiment, the intermediate layer 30 including AlGaN crystal is coherently provided (coherently grown) on the primary surface 21 of the underlying layer 20 having tensile strain, for example. In other words, the intermediate layer 30 is pseudomorphic to the underlying layer 20 having tensile strain, for example.

[0116] The state of "coherent arrangement (coherent growth)" or "pseudo-lattice matching" mentioned here refers to a state in which the upper layer is grown in such a way that the crystal axis of the upper layer is pseudo-aligned with the crystal axis of the lower layer. This state of the present embodiment means that in the inverted lattice image near the (11-24) diffraction of AlN obtained by X-ray diffraction measurement, the a-axis length of the intermediate layer 30 containing AlGaN crystals is consistent with the a-axis length of the bottom layer 20 containing AlN crystals.

[0117] As described above, by providing the intermediate layer 30 coherently on the underlying layer 20 , the good crystallinity of the underlying layer 20 can be transferred to the intermediate layer 30 . As a result, the crystallinity of the electron transport layer 40 including GaN crystal can be improved via the intermediate layer 30 .

[0118] In this embodiment, the intermediate layer 30 including AlGaN crystal is coherently arranged on the main surface 21 of the bottom layer 20 including AlN crystal having tensile strain, and the intermediate layer 30 has tensile strain in the direction along the main surface 11 (for example, the a-axis direction) at 27°C.

[0119] In this embodiment, as described above, at 27° C., the intermediate layer 30 has tensile strain in the direction along the main surface 11 (eg, the a-axis direction), and therefore the strain amount of the base layer 20 in the a-axis direction is a positive value.

[0120] On the other hand, in the present embodiment, at 27° C., the intermediate layer 30 has a compressive strain in a direction perpendicular to the main surface 11 , that is, the strain amount in the c-axis direction of the intermediate layer 30 is a negative value.

[0121] The amount of strain ε2 (%) of the intermediate layer 30 in the c-axis direction can be obtained, for example, from the following formula (2).

[0122] ε2=(c2-c AlGaN ) / c AlGaN ×100…(2)

[0123] Here, c2 is the c-axis length of the AlGaN crystal constituting the intermediate layer 30. c2 is obtained by measuring the diffraction angle of the (0002) plane of the intermediate layer 30 by X-ray diffraction measurement (2θ-ω scanning). AlGaN is the c-axis length of the unstrained bulk AlGaN crystal.

[0124] Specifically, the strain ε2 (%) of the intermediate layer 30 in the c-axis direction at 27° C. depends on the linear expansion coefficient of the SiC substrate as the substrate 10 and the Al composition ratio x of the intermediate layer 30 including the AlGaN crystal, but is usually greater than −0.1% and less than −0.01%.

[0125] In this embodiment, the intermediate layer 30 is made of Alx Ga 1－x The crystal represented by the composition formula of N is formed. The Al composition ratio x in the intermediate layer 30 is, for example, 0.75 or more and 0.96 or less.

[0126] By making the Al composition ratio x in the intermediate layer 30 0.75 or more, it is possible to suppress the overlap of the (0006) diffraction peak of SiC as the substrate 10 and the (0002) diffraction peak of AlGaN as the intermediate layer 30 in X-ray diffraction measurement. Thus, the Al composition ratio in the intermediate layer 30 can be stably managed.

[0127] By setting the Al composition ratio x in the intermediate layer 30 to be 0.75 or more, the intermediate layer 30 can be stably coherently grown on the underlying layer 20 composed of AlN crystals having tensile strain. Thus, the good crystallinity of the underlying layer 20 can be stably transferred to the intermediate layer 30 .

[0128] On the other hand, when the Al composition ratio x in the intermediate layer 30 is higher than 0.96, at least in the initial stage of growth of the electron transit layer 40 including GaN crystals, the electron transit layer 40 grows coherently with respect to the intermediate layer 30 including AlGaN crystals. Therefore, during the growth of the electron transit layer 40, the GaN crystals constituting the electron transit layer 40 are deformed, and new dislocations may occur in the electron transit layer 40. As a result, the effect of improving the crystallinity of the electron transit layer 40 brought about by the intervention of the intermediate layer 30 including AlGaN crystals may not be fully obtained.

[0129] In contrast, by making the Al composition ratio x in the intermediate layer 30 less than 0.96, the electron transport layer 40 including GaN crystals can be stably grown in a state close to strain-free at the growth temperature of the electron transport layer 40 on the intermediate layer 30 including AlGaN crystals. Thus, it is possible to suppress the occurrence of new dislocations during the growth of the electron transport layer 40. As a result, the effect of improving the crystallinity of the electron transport layer 40 brought about by the intervention of the intermediate layer 30 including AlGaN crystals can be stably obtained.

[0130] In this embodiment, the thickness of the intermediate layer 30 is, for example, greater than 30 nm and less than 600 nm. By making the thickness of the intermediate layer 30 greater than 30 nm, the lattice distortion mitigation effect of the electron transport layer 40 brought by the intermediate layer 30 can be stably obtained. On the other hand, by making the thickness of the intermediate layer 30 less than 600 nm, the intermediate layer 30 can be stably coherently grown on the bottom layer 20.

[0131] In this embodiment, the intermediate layer 30 may be doped with impurities other than Al, Ga, and N that constitute the matrix. Examples of such impurities include oxygen (O), carbon (C), silicon (Si), and iron (Fe). Specifically, the total concentration of impurities in the intermediate layer 30 may be, for example, less than 3×10 19 cm －3 When the total concentration of impurities in the intermediate layer 30 is within the above range, it is confirmed by X-ray diffraction measurement that the lattice constant of the intermediate layer 30 including the AlGaN crystal is equivalent to the lattice constant of the AlGaN crystal when the undoped AlGaN crystal is coherently grown on the AlN crystal.

[0132] (Electron Transport Layer)

[0133] The electron transport layer 40 is configured to generate a two-dimensional electron gas (2DEG) in a region near the electron supply layer 50, as described later, and to transport electrons when the semiconductor element 2 is driven. Specifically, the electron transport layer 40 is provided on the main surface 31 of the intermediate layer 30, for example, and is formed of a GaN crystal. The electron transport layer 40 is formed by heteroepitaxially growing a GaN crystal on the main surface 31 of the intermediate layer 30, for example.

[0134] The electron transport layer 40 has, for example, a primary surface 41. In the present embodiment, the low-index crystal plane closest to the primary surface 41 of the electron transport layer 40 is, for example, a c-plane ((0001) plane, Ga plane).

[0135] In this embodiment, the electron transport layer 40 is epitaxially grown on the main surface 31 of the intermediate layer 30, and the electron transport layer 40 has tensile strain in the direction along the main surface 11 (for example, the a-axis direction) at 27° C. In addition, the electron transport layer 40 is lattice mismatched with the intermediate layer 30.

[0136] In the present embodiment, as described above, at 27° C., the electron transport layer 40 has tensile strain in the direction along the primary surface 11 , and therefore the amount of strain in the a-axis direction of the electron transport layer 40 is a positive value.

[0137] On the other hand, in the present embodiment, at 27° C., the electron transport layer 40 has a compressive strain in the direction perpendicular to the main surface 11 , that is, the strain amount of the underlayer 20 in the c-axis direction is a negative value.

[0138] The strain amount ε3 (%) of the electron transport layer 40 in the c-axis direction can be obtained, for example, from the following formula (3).

[0139] ε3=(c3-c GaN ) / c GaN ×100…(3)

[0140] Here, c3 is the c-axis length of the GaN crystal constituting the electron transport layer 40. c3 is obtained by measuring the diffraction angle of the (0002) plane of the electron transport layer 40 by X-ray diffraction measurement (2θ-ω scanning). GaN is the c-axis length of unstrained bulk GaN crystal.

[0141] Specifically, the amount of strain ε3 (%) in the c-axis direction of the electron transport layer 40 at 27° C. is, for example, not less than −0.1% and less than −0.01%, or not less than −0.06% and not more than −0.02%.

[0142] As described above, the strain amount ε3 of the electron transport layer 40 in the c-axis direction at room temperature is within the above range, which means that the electron transport layer 40 is grown in a state close to being strain-free at the growth temperature of the electron transport layer 40 .

[0143] In this way, the electron transit layer 40 is grown in a state close to being strain-free at the growth temperature of GaN, and a high-quality electron transit layer 40 can be grown even if the thickness of the electron transit layer 40 is reduced.

[0144] In the present embodiment, the thickness of the electron transport layer 40 is, for example, less than 1 μm. In the present embodiment, by making the thickness of the electron transport layer 40 less than 1 μm, the warping of the stack 1 caused by the difference in linear expansion coefficient between the electron transport layer 40 and other layers can be suppressed. Thus, the photolithography accuracy can be improved. In addition, in the present embodiment, by making the thickness of the electron transport layer 40 less than 1 μm, the buffer leakage current caused by the slight conductivity of GaN itself constituting the electron transport layer 40 can be suppressed.

[0145] The lower limit of the thickness of the electron transport layer 40 is not limited. However, from the viewpoint of generating a predetermined two-dimensional electron gas (2DEG) in the electron transport layer 40, the thickness of the electron transport layer 40 may be, for example, 100 nm or more.

[0146] In the present embodiment, even if the thickness of the electron transport layer 40 is within the above range, the half-maximum full width of the diffraction peak of the electron transport layer 40 obtained by X-ray rocking curve measurement becomes smaller. Specifically, the half-maximum full width of the (0002) diffraction of the electron transport layer 40 obtained by X-ray rocking curve measurement is, for example, less than 300 seconds, or less than 270 seconds, or less than 250 seconds. The half-maximum full width of the (10-12) diffraction of the electron transport layer 40 obtained by X-ray rocking curve measurement is, for example, less than 410 seconds, or less than 380 seconds, or less than 350 seconds.

[0147] In the present embodiment, by growing the electron transport layer 40 in a state close to being strain-free, the dislocation density of the electron transport layer 40 can be reduced.

[0148] Here, in the conventional method, when the electron transport layer 40 is grown three-dimensionally, the dislocation density can be reduced by converging dislocations during the three-dimensional growth. However, in this case, impurities such as O may be mixed in through facets other than the c-plane during the three-dimensional growth.

[0149] When the electron transport layer 40 is not grown three-dimensionally but is grown in a step flow, the dislocation density decreases as the thickness of the grown film increases. However, in this case, the degree of reduction in dislocation density is lower than that in the case of three-dimensional growth. Therefore, if the electron transport layer 40 is not grown very thick, the dislocation density cannot be sufficiently reduced.

[0150] In contrast, in the present embodiment, by growing the electron transport layer 40 in a nearly strain-free state on the intermediate layer 30 containing AlGaN crystals having a low dislocation density, the dislocation density of the electron transport layer 40 can be reduced even if the electron transport layer 40 is not grown three-dimensionally and even if it does not need to be grown very thick.

[0151] Specifically, even if the thickness of the electron transport layer 40 is within the above range, the dislocation density of the primary surface 41 of the electron transport layer 40 is, for example, less than 1×10 9 cm －2 Below, or you can also use 5×10 8 cm －2 Below, or you can also use 1×10 8 cm －2 The dislocation density of the primary surface 41 of the electron transport layer 40 can be measured, for example, using a multiphoton excitation microscope or the like.

[0152] As described above, by reducing the dislocation density of the primary surface 41 of the electron transport layer 40, gate leakage (current) can be reduced when driving the semiconductor element 2. This can suppress degradation of the gate electrode when driving the semiconductor element 2. As a result, the reliability of the semiconductor element 2 as a HEMT can be improved.

[0153] Since a non-three-dimensional growth method is used, the lower limit of the dislocation density of the primary surface 41 of the electron transport layer 40 is considered to be, for example, 1×10 7 cm －2 .

[0154] In this embodiment, the electron transport layer 40 is not grown three-dimensionally by the manufacturing method described later, but is grown with the c-plane as the growth plane (step flow growth), thereby suppressing the mixing of impurities such as O through facets other than the c-plane. Specifically, the O concentration in the electron transport layer 40 is 1×10 16 cm －3 As follows. In this way, by suppressing the mixing of O as an n-type impurity (donor) in the electron transport layer 40, the increase in the free electron concentration in the electron transport layer 40 can be suppressed. Here, the reason for "excluding the area to a depth of 200nm" is as follows. Generally, secondary ion mass spectrometry (SIMS) used for impurity analysis is affected by contamination on the sample surface. Therefore, the reliability of the analysis results of the area before the depth reaches 200nm is low. As a result, the impurity concentration in this area tends to be measured to be higher than the actual concentration. Therefore, in this embodiment, the actual O concentration in the electron transport layer 40 can be estimated to be 1×10 16 cm －3 the following.

[0155] In this embodiment, the thickness of the underlying layer 20 is set to be 200 nm or more, thereby suppressing the diffusion of Si from the substrate 10 to the electron transport layer 40. Specifically, the Si concentration in the electron transport layer 40 is, for example, 1×10 16 cm －3 As follows. In this way, by suppressing the incorporation of Si as an n-type impurity (donor) in the electron transport layer 40, the increase in the free electron concentration in the electron transport layer 40 can be suppressed. Here, the reason for "excluding the region up to a depth of 200 nm" is the same as the reason for the regulation of the O concentration. Therefore, in this embodiment, the actual Si concentration in the electron transport layer 40 can be estimated to be 1×10 16 cm －3 the following.

[0156] In this way, by suppressing the increase in the free electron concentration in the electron transport layer 40, the increase in the buffer leakage current can be suppressed. By suppressing the increase in the buffer leakage current when pinching off the 2DEG of the second layer, the decrease in the On / Off current ratio can be suppressed. In addition, by suppressing the increase in the buffer leakage current, the leakage current between elements can be suppressed, and the operation interference between adjacent elements can be suppressed.

[0157] In this embodiment, as described above, by suppressing the mixing of Si and O as n-type impurities in the electron transport layer 40, it is also possible to prevent the electron transport layer 40 from being doped with impurities such as Fe and C that form deep energy levels at high concentrations. Specifically, for example, excluding the region from the main surface 41 of the electron transport layer 40 to a depth of 200 nm, the Fe concentration and C concentration in the electron transport layer 40 are 1×10 16 cm －3 As a result, when the semiconductor element 2 is driven, the charging and discharge of impurities that form deep energy levels can be suppressed. That is, the occurrence of hysteresis associated with the charging and discharge of impurities can be suppressed. As a result, the semiconductor element 2 can be operated stably. Here, the reason for "excluding the area up to a depth of 200nm" is the same as the reason for the provisions related to the O concentration. Therefore, in this embodiment, it can be inferred that the actual Fe concentration and C concentration in the electron transport layer 40 are 1×10 16 cm －3 the following.

[0158] In this embodiment, according to the manufacturing method described later, the electron transport layer 40 is grown with the c-plane as the growth plane (step flow growth), and the electron transport layer 40 has good surface flatness. Specifically, the root mean square roughness RMS of a 5 μm square area (AFM) of the main surface 41 of the electron transport layer 40 is measured by an atomic force microscope, for example, less than 1 nm, or can also be less than 0.5 nm.

[0159] (Electron Donating Layer)

[0160] The electron supply layer 50 is configured, for example, to generate 2DEG in the electron transport layer 40. Specifically, the electron supply layer 50 is formed of a crystal of a group III nitride having a wider band gap than GaN constituting the electron transport layer 40 and a lattice constant smaller than that of GaN. Examples of the group III nitride constituting the electron supply layer 50 include AlN, AlGaN, InAlN, or AlInGaN. x In y Ga 1－x－y N (here, 0<x≤1, 0≤y<1, 0<x+y≤1) is represented by a composition formula. In addition, the group III nitride constituting the electron supply layer 50 may also contain scandium (Sc) as a constituent element. The electron supply layer 50 is, for example, provided on the electron transport layer 40. The electron supply layer 50 is, for example, formed by heteroepitaxially growing the crystal of the above-mentioned group III nitride on the main surface 41 of the electron transport layer 40.

[0161] The electron supply layer 50 has a primary surface 51. In the present embodiment, the low-index crystal plane closest to the primary surface 51 of the electron supply layer 50 is, for example, a c-plane ((0001) plane, a group III element polar plane).

[0162] The electron supply layer 50 is coherently provided (coherently grown) on the primary surface 41 of the electron transit layer 40 including GaN crystal, for example. In other words, the electron supply layer 50 is pseudomorphic to the electron transit layer 40, for example.

[0163] The thickness of the electron supply layer 50 is, for example, 5 nm or more and 50 nm or less, or 10 nm or more and 30 nm or less. By making the thickness of the electron supply layer 50 5 nm or more, or 10 nm or more, the gate leakage current can be reduced. On the other hand, by making the thickness of the electron supply layer 50 50 nm or less, or 30 nm or less, the threshold voltage can be made below a predetermined value, and the switching characteristics can be improved.

[0164] In this embodiment, the electron supply layer 50 has good surface flatness like the electron transport layer 40. Specifically, the root mean square roughness RMS of a 5 μm square area of ​​the main surface 51 of the electron supply layer 50 is measured by an atomic force microscope (AFM), and is equivalent to the RMS of the electron transport layer 40, for example.

[0165] (Overlay)

[0166] The capping layer 60 is provided on the electron supply layer 50 and is formed of GaN, for example. The capping layer 60 is formed, for example, by heteroepitaxially growing GaN crystals on the main surface 51 of the electron supply layer 50. By forming the capping layer 60 on the main surface 51 of the electron supply layer 50 in this way, for example, when the electron supply layer 50 includes AlGaN crystals, selective evaporation of Ga from the AlGaN surface during cooling after growth can be suppressed, and formation of an AlGaN layer rich in aluminum can be suppressed.

[0167] The thickness of the cover layer 60 is, for example, 1 nm or more and 10 nm or less, or 2 nm or more and 5 nm or less. By making the thickness of the cover layer 60 1 nm or more, or 2 nm or more, the evaporation of the Ga component or the In component can be stably suppressed. On the other hand, by making the thickness of the cover layer 60 10 nm or less, or 5 nm or less, the generation of the current component flowing in the cover layer 60 can be suppressed. Thus, it is possible to suppress the cover layer 60 from hindering the operation of the device.

[0168] The stack 1 constructed as above can reduce the warping of the stack 1 by thinning the thickness of the electron transport layer 40 as described above. Specifically, the warping of the stack 1 per 50.8 mm length is, for example, 20 μm or less, or 10 μm or less. Thus, the reduction in lithography accuracy caused by the warping of the stack 1 can be suppressed. As a result, the manufacturing yield of the semiconductor element 2 can be improved.

[0169] The smaller the warping of the laminate 1 is, the better, for example, 0 μm or more.

[0170] (2) Semiconductor components

[0171] Next, refer to Figure 2 , a semiconductor element according to this embodiment is described.

[0172] like Figure 2 As shown, the semiconductor element 2 of this embodiment is manufactured using the above-mentioned stacked product 1, for example, and is configured as a HEMT. Specifically, the semiconductor element 2 has, for example, a substrate 10, a base layer 20, an intermediate layer 30, an electron transport layer 40, an electron supply layer 50, a cap layer 60, a gate electrode 61, a source electrode 62, and a drain electrode 63. That is, the semiconductor element 2 has the above-mentioned electron transport layer 40 containing GaN crystals as at least a part of the operating layer.

[0173] (electrode)

[0174] The gate electrode 61 is provided on the electron supply layer 50. The gate electrode 61 may be in contact with the electron supply layer 50, or may be provided on the electron supply layer 50 via the cap layer 60. The gate electrode 61 is formed of, for example, a multilayer structure (Ni / Au) of nickel (Ni) and gold (Au).

[0175] The source electrode 62 is provided on the electron supply layer 50 via the cap layer 60, for example. The source electrode 62 is disposed at a predetermined distance from the gate electrode 61. The source electrode 62 is formed of, for example, a multilayer structure (Ti / Al) of titanium (Ti) and aluminum (Al).

[0176] The drain electrode 63 is provided on the electron supply layer 50 via the cap layer 60, for example. The drain electrode 63 is arranged on the opposite side of the source electrode 62 with the gate electrode 61 interposed therebetween and at a position separated by a predetermined distance from the gate electrode 61. The drain electrode 63 is formed of, for example, a multilayer structure of Ti and Al, similarly to the source electrode 62. In addition, in the source electrode 62 and the drain electrode 63, a multilayer structure of Ni / Au may be stacked on a multilayer structure of Ti / Al.

[0177] (3) Method for manufacturing semiconductor stack and method for manufacturing semiconductor element

[0178] Next, refer to Figures 1 to 3 , a method for manufacturing a semiconductor stack and a method for manufacturing a semiconductor element according to this embodiment are described.

[0179] The method for manufacturing a semiconductor element of the present embodiment includes, for example: a substrate preparation step S10; a bottom layer formation step S20; an annealing step S30; an intermediate layer formation step S40; an electron transport layer formation step S50; an electron supply layer formation step S60; a cap layer formation step S70; and an electrode formation step S80.

[0180] (S10: Substrate Preparation Step)

[0181] First, the substrate 10 is prepared. As the substrate 10, for example, a semi-insulating SiC substrate of polytype 6H is prepared.

[0182] (S20: Base layer forming step)

[0183] Next, an underlayer 20 composed of AlN crystal is heteroepitaxially grown on the main surface 11 of the substrate 10. The growth of the underlayer 20 is performed by, for example, the HVPE method.

[0184] As the III group (Al) raw material gas, for example, aluminum chloride (AlCl) gas or aluminum chloride (AlCl3) gas is used. AlCl gas or AlCl3 gas can be generated by supplying hydrogen chloride (HCl) gas to the metal Al set in the HVPE device. As the N raw material gas, for example, ammonia (NH3) gas is used. These raw material gases can also be mixed with a carrier gas containing hydrogen (H2) gas, nitrogen (N2) gas or a mixed gas thereof and supplied.

[0185] As the crystal growth conditions, for example, at least one of the growth temperature, V / III ratio, growth rate and growth pressure is appropriately controlled. Thus, a high-quality bottom layer 20 can be grown. The "V / III ratio" mentioned here is the ratio of the supply amount (partial pressure) of the V group (N) raw material gas to the supply amount (partial pressure) of the III group (Al) raw material gas.

[0186] Specifically, the crystal growth conditions are set, for example, in the following manner.

[0187] Growth temperature: above 900℃ and below 1300℃

[0188] V / III ratio: 0.2 or more and 200 or less

[0189] Growth rate: 0.5 nm / min or more and 3000 nm / min or less

[0190] Growth pressure: 0.9 atmospheres (atm) or more and 1.3 atmospheres or less

[0191] At this time, by making the growth pressure 0.9 atmospheres or more, that is, by growing at a higher pressure than when using a reduced pressure growth apparatus, it is possible to easily grow the bottom layer 20 with good surface flatness. On the other hand, since a growth apparatus that can withstand high pressure requires a pressure-resistant structure, the growth pressure can be made 1.3 atmospheres or less from the viewpoint of manufacturing cost.

[0192] In addition, at this time, in order to prevent AlN from adhering to the nozzle of the gas supply pipe for introducing various gases into the growth chamber of the HVPE device, HCl gas may also be circulated. In this case, the ratio of the supply amount of HCl gas to the supply amount of AlCl gas or AlCl3 gas is, for example, 0.1 or more and 100 or less.

[0193] By controlling the crystal growth conditions in the above manner, the surface flatness of the underlying layer 20 can be improved.

[0194] After the bottom layer forming step S20, the bottom layer 20 has a thickness higher than 10 10 cm －2 In the bottom layer forming step S20, since the lattice constant of bulk AlN is greater than that of SiC, the bottom layer 20 is compressively strained in the direction along the main surface 11 of the substrate 10 at the growth temperature of the bottom layer 20. However, since the linear expansion coefficient of AlN is greater than that of SiC, the bottom layer 20 including AlN crystals is deformed in the tensile direction during the cooling process after the growth of the bottom layer 20. Therefore, the bottom layer 20 including AlN crystals may be in any strain state of tension, no strain, or compression at 27°C.

[0195] (S30: Annealing process)

[0196] After the base layer forming step S20 is completed, the base layer 20 is subjected to an annealing treatment.

[0197] The annealing step S30 is, for example, not performed by lowering the temperature after the base layer forming step S20, but is performed continuously in the growth chamber of the same HVPE apparatus. Alternatively, the annealing step S30 may be performed by heat treatment in a different apparatus after the base layer forming step S20.

[0198] In the annealing step S30 of the present embodiment, the atoms in the base layer 20 move relatively freely by annealing the base layer 20, and the atomic arrangement changes. As a result, the atoms are rearranged in a manner that reduces the dislocations in a high energy state. As a result, the dislocation density of the main surface 21 of the base layer 20 is reduced compared to the dislocation density of the main surface 21 of the base layer 20 after the base layer forming step S20. Specifically, the dislocation density of the main surface 21 of the base layer 20 is, for example, 1×10 10cm －2 Below, or 1×10 9 cm －2 the following.

[0199] In this process, the base layer 20 undergoes lattice relaxation at the annealing temperature from the state where the base layer 20 is compressively strained at the growth temperature of the base layer 20 in the base layer forming step S20. As a result, after the annealing step S30, the base layer 20 undergoes tensile strain in the direction along the main surface 11 of the substrate 10 at 27°C.

[0200] At this time, in the present embodiment, for example, the annealing treatment is performed on the bottom layer 20 in an atmosphere containing nitrogen (N2) gas. In other words, instead of supplying hydrogen (H2) gas and NH3 gas to the growth chamber, the annealing treatment is performed in an atmosphere that does not substantially contain H2 gas. The "substantially contains no H2 gas" mentioned here means, for example, that the partial pressures of the H2 gas in the growth chamber and the NH3 gas that releases H2 gas upon decomposition are each less than 1% relative to the total pressure. By performing the treatment in such an atmosphere, the occurrence of point defects in the bottom layer 20 caused by H2 gas can be suppressed. In addition, N2 gas and an inert gas such as argon (Ar gas) can also be supplied in a mixed manner.

[0201] At this time, in the present embodiment, the temperature of the annealing treatment can be, for example, 1350°C to 1550°C or 1390°C to 1490°C. By setting the temperature of the annealing treatment to 1350°C or 1390°C or more, the above-mentioned atomic rearrangement is performed to reduce the number of dislocations in a high-energy state. In this process, the bottom layer 20 undergoes lattice relaxation at the temperature of the annealing treatment from the state in which the bottom layer 20 is compressively strained at the growth temperature of the bottom layer 20 in the bottom layer forming step S20. On the other hand, by setting the temperature of the annealing treatment to 1550°C or less, or 1490°C or less, the decomposition of the substrate 10 made of SiC can be suppressed.

[0202] At this time, in this embodiment, the annealing treatment time is, for example, 10 minutes or more and 300 minutes or less. By setting the annealing treatment time to 10 minutes or more, the underlying layer 20 can be sufficiently lattice relaxed. On the other hand, by setting the annealing treatment time to 300 minutes or less, the reduction in the flatness of the main surface 21 of the underlying layer 20 can be suppressed.

[0203] By annealing the base layer 20 under the above conditions, atoms in the base layer 20 move freely, and thus lattice relaxation occurs in the base layer 20 at the annealing temperature. Therefore, when the temperature is lowered after the annealing step S30, due to the difference in linear expansion coefficients between the substrate 10 and the base layer 20, tensile strain occurs in the base layer 20 along the main surface 11 of the substrate 10 at 27°C.

[0204] Furthermore, by performing the annealing treatment on the underlying layer 20 under the above-mentioned conditions, the crystallinity of the underlying layer 20 can be improved.

[0205] Specifically, for example, when the thickness of the underlying layer 20 is set to be greater than 200 nm and less than 800 nm, the half-maximum full width of the (0002) diffraction of the underlying layer 20 obtained by X-ray rocking curve measurement can be set to be less than 200 seconds, and the half-maximum full width of the (10-12) diffraction of the underlying layer 20 obtained by X-ray rocking curve measurement can be set to be less than 400 seconds.

[0206] For example, when the thickness of the base layer 20 is set to be greater than or equal to 300 nm and less than or equal to 500 nm, the half-maximum full width of the (0002) diffraction of the base layer 20 obtained by X-ray rocking curve measurement can be set to be less than or equal to 180 seconds, and the half-maximum full width of the (10-12) diffraction of the base layer 20 obtained by X-ray rocking curve measurement can be set to be less than or equal to 380 seconds.

[0207] (S40: Intermediate Layer Forming Step)

[0208] After the annealing step S30 is completed, the intermediate layer 30 including AlGaN crystal is heteroepitaxially grown on the primary surface 21 of the annealed underlying layer 20. The intermediate layer 30 is grown, for example, by metalorganic vapor phase epitaxy (MOVPE).

[0209] As the III group raw material gas, for example, trimethylaluminum (Al(CH3)3, TMA) gas and trimethylgallium (Ga(CH3)3, TMG) ​​gas are used. As the N raw material gas, for example, NH3 gas is used. These raw material gases may also be mixed with H2 gas, N2 gas, or a carrier gas containing these mixed gases and supplied.

[0210] At this time, in the present embodiment, the growth temperature of the intermediate layer 30 is set lower than the temperature of the annealing step S30. Specifically, the growth temperature of the intermediate layer 30 is set to, for example, 900°C or higher and 1200°C or lower.

[0211] At this time, in the present embodiment, the intermediate layer 30 is coherently grown on the main surface 21 of the base layer 20 , for example.

[0212] Here, as described above, the intermediate layer forming step S40 is performed at a growth temperature lower than the temperature of the annealing step S30. Therefore, the base layer 20 that is free of strain in the annealing step S30 has tensile strain at the growth temperature of the intermediate layer forming step S40 due to the difference in linear expansion coefficient between the substrate 10 and the base layer 20. The intermediate layer 30 is coherently grown on the base layer 20 that has been tensilely strained.

[0213] As the crystal growth conditions, for example, at least one of the V / III ratio, the growth rate, and the growth pressure is appropriately controlled together with the above-mentioned growth temperature. In this way, the intermediate layer 30 can be coherently grown on the base layer 20 .

[0214] Specifically, other crystal growth conditions are set, for example, as follows.

[0215] V / III ratio: 1 or more and 10000 or less

[0216] Growth rate: 0.1 nm / min or more and 100 nm / min or less

[0217] Growth pressure: 0.01 atmosphere (atm) or more and 1 atmosphere or less

[0218] At this time, in the present embodiment, the Al composition ratio x in the intermediate layer 30 is set to, for example, 0.75 or more and 0.96 or less.

[0219] At this time, in the present embodiment, the thickness of the intermediate layer 30 is set to, for example, 30 nm or more and 600 nm or less.

[0220] (S50: Electron Transport Layer Formation Step)

[0221] After the intermediate layer forming step S40 is completed, an electron transport layer 40 including GaN crystals is heteroepitaxially grown on the primary surface 31 of the intermediate layer 30. The growth of the electron transport layer 40 is performed, for example, by MOVPE method, and is performed continuously in the growth chamber of the same MOVPE device as the intermediate layer forming step S40.

[0222] At this time, TMG gas is used as Ga source gas. Other gases used in the electron transport layer forming step S50 are the same as those in the intermediate layer forming step S40.

[0223] In this embodiment, the intermediate layer 30 including AlGaN crystals is interposed between the base layer 20 and the electron transit layer 40 , so that the occurrence of compressive strain in the electron transit layer 40 including GaN can be suppressed, and the electron transit layer 40 can be grown in a state close to being strain-free.

[0224] In this embodiment, the electron transport layer 40 is not grown three-dimensionally but is grown in a step flow manner (two-dimensional growth). That is, no facets other than the c-plane are generated in the electron transport layer 40, and the electron transport layer 40 is grown with the c-plane as the growth plane.

[0225] As the crystal growth conditions, for example, at least any one of the growth temperature, the growth rate, and the growth pressure is appropriately controlled.

[0226] Specifically, the crystal growth conditions are set, for example, as follows.

[0227] Growth temperature: above 900℃ and below 1200℃

[0228] V / III ratio: 1 or more and 30,000 or less

[0229] Growth rate: 0.1 nm / min or more and 10 nm / min or less

[0230] Growth pressure: 0.01 atmosphere (atm) or more and 1 atmosphere or less

[0231] By the above-described crystal growth, the thickness of the electron transport layer 40 can be reduced, and the electron transport layer 40 with high crystallinity can be formed.

[0232] Specifically, for example, the electron transport layer 40 can be formed in the following manner, wherein the thickness of the electron transport layer 40 is less than 1 μm, the half-maximum full width of the (0002) diffraction of the electron transport layer 40 obtained by X-ray rocking curve measurement is less than 300 seconds, and the half-maximum full width of the (10-12) diffraction of the electron transport layer 40 obtained by X-ray rocking curve measurement is less than 410 seconds.

[0233] In this embodiment, by growing the electron transport layer 40 in a state close to being strain-free, the dislocation density of the primary surface 41 of the electron transport layer 40 can be set to 1×10 9 cm －2 Below, or 5×10 8 cm －2 the following.

[0234] In the present embodiment, by the above-described crystal growth, the impurity concentration in the electron transport layer 40 can be reduced as follows.

[0235] O concentration in the electron transport layer 40: 1×10 16 cm －3 the following,

[0236] Si concentration in the electron transport layer 40: 1×10 16 cm －3 the following,

[0237] The Fe concentration and C concentration in the electron transport layer 40 are 1×10 16 cm －3 the following.

[0238] (S60: Electron Supply Layer Formation Step)

[0239] Next, an electron supply layer 50 formed of a crystal of a group III nitride having a wider band gap than GaN constituting the electron transport layer 40 is heteroepitaxially grown on the primary surface 41 of the electron transport layer 40. The growth of the electron supply layer 50 is performed, for example, by MOVPE method, and is continuously performed in the growth chamber of the same MOVPE device as the electron transport layer forming step S50.

[0240] In the present embodiment, the electron supply layer 50 formed of a crystal of, for example, AlN, AlGaN, InAlN, or AlInGaN is grown.

[0241] At this time, as Al raw material gas, for example, TMA gas is used. As In raw material gas, for example, trimethylindium (In(CH3)3, TMI) gas is used. Other gases used in the electron supply layer forming step S60 are the same as those in the electron transport layer forming step S50.

[0242] At this time, in the present embodiment, the electron supply layer 50 is coherently grown on, for example, the primary surface 41 of the electron transport layer 40 .

[0243] As the crystal growth conditions, for example, at least any one of the growth temperature, the V / III ratio, the growth rate, and the growth pressure is appropriately controlled.

[0244] Specifically, for example, the crystal growth conditions are set as follows.

[0245] Growth temperature: above 900℃ and below 1200℃

[0246] V / III ratio: 1 or more and 10000 or less

[0247] Growth rate: 0.1 nm / min or more and 10 nm / min or less

[0248] Growth pressure: 0.01 atmosphere (atm) or more and 1 atmosphere or less

[0249] At this time, in the present embodiment, the thickness of the electron supply layer 50 is set to, for example, 5 nm or more and 50 nm or less.

[0250] (S70: Covering Layer Forming Step)

[0251] Next, a cap layer 60 made of GaN is grown on the primary surface 51 of the electron supply layer 50. The growth of the cap layer 60 is performed, for example, by MOVPE method, and is performed continuously in the growth chamber of the same MOVPE apparatus as in the electron supply layer forming step S60.

[0252] At this time, the thickness of the cover layer 60 is set to, for example, 1 nm or more and 10 nm or less.

[0253] Based on the above, the laminated product 1 of the present embodiment is manufactured.

[0254] (S80: Electrode Forming Step)

[0255] After the stacked product 1 is manufactured, the gate electrode 61 , the source electrode 62 , and the drain electrode 63 are formed above the electron supply layer 50 .

[0256] Based on the above, the semiconductor element 2 of the present embodiment is manufactured.

[0257] (4) Summary of this embodiment

[0258] According to this embodiment, one or more of the following effects can be obtained.

[0259] (a) In the present embodiment, by performing annealing on the underlayer 20 composed of AlN crystal on the substrate 10 composed of SiC, the dislocation density of the primary surface 21 of the underlayer 20 can be reduced by the above-mentioned rearrangement of atoms.

[0260] In this process, the base layer 20 undergoes lattice relaxation at the annealing temperature from the state where the base layer 20 is compressively strained at the growth temperature of the base layer 20 in the base layer forming step S20. Therefore, after the annealing step S30, due to the difference in linear expansion coefficients between the substrate 10 and the base layer 20, the base layer 20 undergoes tensile strain in the direction along the main surface 11 of the substrate 10 at 27°C.

[0261] Through such a structure, since the layers above the bottom layer 20 containing AlN crystals (intermediate layer 30 and electron transport layer 40) inherit the low dislocation density of the bottom layer 20, the layers above the bottom layer 20 can be grown in a state with low dislocation density at the growth temperature of the group III nitride crystal.

[0262] (b) In addition, in the present embodiment, the intermediate layer 30 including AlGaN crystal having these intermediate compositions is interposed between the bottom layer 20 including AlN crystal and the electron transit layer 40 including GaN crystal. The intermediate layer 30 has a low dislocation density inherited from the dislocation density of the bottom layer 20 as described above, and contains Ga that weakens the bonding force between atoms. Thus, the electron transit layer 40 including GaN crystal can be grown in a state close to strain-free on the intermediate layer 30 including AlGaN crystal at the growth temperature of the group III nitride crystal.

[0263] Here, the mechanism by which the electron transport layer 40 including GaN crystal grows in a state close to being strain-free due to the presence of the intermediate layer 30 including AlGaN crystal having a low dislocation density is not yet clear, but is considered to be, for example, the following mechanism.

[0264] The bonds between the atoms of AlN are stronger than those of GaN. Therefore, it is difficult for the atomic planes to slide between the AlN layer and the GaN layer. Therefore, the GaN layer grows coherently on the AlN layer.

[0265] In contrast, the AlGaN layer contains GaN that weakens the bonding force between atoms. As a result, atomic plane sliding is likely to occur between the AlGaN layer and the GaN layer. It is believed that due to this atomic plane sliding phenomenon, the crystal strain in the GaN layer is released when the GaN layer grows on the AlGaN layer.

[0266] In addition, other studies have also confirmed that the bottom layer containing AlN crystals has a high dislocation density (e.g., 10 10 cm －2 When the Al composition ratio x of the AlGaN layer is in the range of 0.5 to 1, for example, the GaN layer grown on the AlGaN layer cannot be strain-free. This is believed to be because when there are many dislocations, the dislocations hinder the sliding of the interface between the GaN layer and the AlGaN layer.

[0267] Conversely, in the present embodiment, the phenomenon that the electron transport layer 40 including GaN crystals grows in a nearly strain-free state on the intermediate layer including AlGaN crystals having a low dislocation density is considered to be a phenomenon unique to the presence of the underlying layer 20 including AlN crystals having a low dislocation density.

[0268] In this embodiment, based on the above-mentioned mechanism, on the intermediate layer 30 including AlGaN crystals, by growing the electron transport layer 40 including GaN crystals in a nearly strain-free state, the electron transport layer 40 including GaN crystals has tensile strain in the direction of the main surface 11 of the substrate 10 at 27°C based on the above-mentioned relationship between the magnitudes of the linear expansion coefficients and their absolute values.

[0269] By growing the electron transport layer 40 including GaN crystal in a state close to being strain-free as described above, the occurrence of new dislocations due to crystal strain can be suppressed in the electron transport layer 40 having a low dislocation density inherited from the base layer 20 via the intermediate layer 30. As a result, an electron transport layer 40 with good crystallinity can be obtained.

[0270] As described above, according to the present embodiment, high-quality semiconductor stacked product 1 and semiconductor element 2 can be obtained.

[0271] (c) In the present embodiment, by growing the electron transport layer 40 in a state close to being strain-free at the growth temperature of GaN, the crystallinity of the electron transport layer 40 can be improved even if the thickness of the electron transport layer 40 is reduced. Specifically, the thickness of the electron transport layer 40 is 1 μm or less, the half-maximum full width of the (0002) diffraction of the electron transport layer 40 obtained by X-ray rocking curve measurement is 300 seconds or less, and the half-maximum full width of the (10-12) diffraction of the electron transport layer 40 obtained by X-ray rocking curve measurement is 410 seconds or less. By improving the crystallinity of the electron transport layer 40 in this way, the mobility of the electron transport layer 40 can be improved, and the degradation of the gate electrode can be suppressed, thereby improving the reliability of the element.

[0272] <Other embodiments>

[0273] The embodiments of the present invention are described in detail above. However, the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the present invention. In addition, the so-called "the above embodiments" includes one embodiment and a second embodiment.

[0274] In the above-mentioned embodiment, the case where the intermediate layer 30 is formed of a crystal of AlGaN is described, but the present invention is not limited to this case. The intermediate layer 30 may also be formed of any one of crystals such as aluminum indium nitride (AlInN) or aluminum indium gallium nitride (AlInGaN). InN crystals are also known to be crystals with weaker bonding force than AlN crystals. Therefore, when the intermediate layer 30 is formed of AlIN crystals or AlInGaN crystals, the strain relaxation effect brought about by the sliding phenomenon of the atomic plane can be obtained, as in the case where the intermediate layer 30 is formed of AlGaN crystals.

[0275] In the above-mentioned embodiment, the case where the cover layer 60 is provided is described, but the cover layer 60 may not be provided.

[0276] In the above-mentioned embodiment, the region other than the electrode on the upper surface of the cover layer 60 is shown as being free of any arrangement, but a protective film may be provided to cover the region other than the electrode on the upper surface of the cover layer 60. Examples of the protective film include silicon nitride (SiN) and the like.

[0277] In the above-mentioned embodiment, the semiconductor element 2 is described as a so-called MES gate (Metal-Semiconductor) type in which the gate electrode 61 is in direct contact with the semiconductor layer such as the electron supply layer 50. However, an insulating layer formed of silicon oxide (SiO2) or aluminum oxide (Al2O3) or the like may be inserted between the semiconductor layer such as the electron supply layer 50 and the gate electrode 61 to form the semiconductor element 2 as a so-called MIS gate (Metal-Insulator-Semiconductor) type.

[0278] In the above-mentioned embodiment, the case where the growth of the underlying layer 20 is performed by the HVPE method is described, but the growth of the underlying layer 20 may also be performed by the MOVPE method.

[0279] In the above-described embodiment, the case where the intermediate layer 30 and the electron transport layer 40 are grown by the MOVPE method is described. However, at least one of the intermediate layer 30 and the electron transport layer 40 may be grown by the HVPE method.

[0280] [Example]

[0281] Various experimental results that confirmed the effects of the present invention are described below.

[0282] (1) Experiment 1

[0283] (1-1) Preparation of semiconductor stack

[0284] Under the following conditions, a plurality of stacked products having intermediate layers formed of AlGaN crystals with different Al composition ratios were prepared.

[0285] [Preparation conditions of laminate]

[0286] (Substrate)

[0287] Material: SiC (semi-insulating)

[0288] Diameter: 4 inches

[0289] Thickness: 400μm

[0290] Low-index crystal plane closest to the main surface: c-plane (main surface without pattern processing) Polytype: 6H

[0291] (Ground Floor)

[0292] Material: AlN

[0293] Growth method: HVPE method

[0294] Growth temperature: 1020℃

[0295] Growth pressure: 0.987atm (100kPa)

[0296] V / III ratio: 50

[0297] Growth rate: 100nm / min

[0298] Thickness: 400nm

[0299] (Annealing process)

[0300] Atmosphere: N2 gas

[0301] Annealing temperature: 1400℃

[0302] Annealing time: 60 minutes

[0303] (Middle layer)

[0304] Material: AlGaN (or AlN)

[0305] Growth method: MOVPE method

[0306] Growth temperature: 1020℃

[0307] Growth pressure: 0.1atmV / III ratio: 10

[0308] Growth rate: 5nm / min

[0309] Thickness: 80nm

[0310] Also, there is no intentional adulteration.

[0311] Al composition ratio: varied within a range of 65% to 100%.

[0312] (Electron Transport Layer)

[0313] Material: GaN

[0314] Growth method: MOVPE method Growth conditions: GaN crystal is grown under the following conditions under step flow growth Growth temperature: 1120℃

[0315] Growth pressure: 0.4atm

[0316] TMG flow rate: 50sccm

[0317] V / III ratio: 5000

[0318] Growth rate: 20nm / min

[0319] Also, there is no intentional adulteration.

[0320] Thickness: 400nm

[0321] (1-2) Evaluation

[0322] (X-ray diffraction measurement: 2θ-ω scanning)

[0323] X-ray diffraction measurements (2θ-ω scans) were performed on the laminates of Experiment 1 described above. As a result, the strain of the bottom layer was confirmed based on the angle of the (0002) diffraction peak of AlN constituting the bottom layer. The Al composition ratio of the middle layer was obtained based on the angle of the diffraction peak of Al(Ga)N constituting the middle layer. In addition, the angle 2θ of the (0002) diffraction peak of GaN constituting the electron transport layer was obtained.

[0324] (X-ray rocking curve measurement)

[0325] For the stacked product of Experiment 1, the X-ray rocking curve of the (0002) diffraction of GaN constituting the electron transport layer and the X-ray rocking curve of the (10-12) diffraction of GaN constituting the electron transport layer were measured. As a result, the full width at half maximum (FWHM) of the (0002) diffraction of GaN and the full width at half maximum of the (10-12) diffraction of GaN were obtained.

[0326] (1-3) Results

[0327] (Bottom layer strain)

[0328] As a result of 2θ-ω scanning of X-ray diffraction measurement, in any stack, the angle of the (0002) diffraction peak of AlN constituting the bottom layer is smaller than the angle of the (0002) diffraction peak of completely relaxed AlN (bulk AlN). This means that at room temperature, the c-axis length of the bottom layer is shortened, that is, the a-axis length of the bottom layer is elongated. This confirms that at room temperature, the bottom layer composed of AlN crystals has tensile strain in the direction along the main surface of the substrate.

[0329] (Dependence of the Strain of the Electron Transport Layer on the Al Composition Ratio of the Intermediate Layer)

[0330] like Figure 4BAs shown, when the Al composition ratio of the intermediate layer is taken as 100%, the angle 2θ of the (0002) diffraction peak of GaN constituting the electron transport layer is smaller than the angle (34.567°) of the (0002) diffraction peak of completely relaxed GaN (bulk GaN). This means that the c-axis length of the electron transport layer is elongated, that is, the a-axis length of the electron transport layer is shortened. It is thus confirmed that when the intermediate layer is AlN, the electron transport layer has a compressive strain in the direction along the main surface of the substrate at room temperature. Considering that the linear expansion coefficient of GaN and AlN is greater than the linear expansion coefficient of SiC constituting the substrate, in this case, it can be considered that at the growth temperature of the electron transport layer, the electron transport layer formed by the GaN crystal is subjected to a strong compressive strain. Considering that the lattice constant of AlN is smaller than the lattice constant of GaN, the electron transport layer formed by the GaN crystal, at least in the initial stage of growth, is co-lattice grown on the intermediate layer formed by the AlN crystal, so it can be considered that at the growth temperature of the electron transport layer, the electron transport layer is subjected to a compressive strain.

[0331] In contrast, when the Al composition ratio of the intermediate layer is less than 100%, especially when it is less than 96%, the angle 2θ of the (0002) diffraction peak of GaN constituting the electron transport layer is greater than the angle of the (0002) diffraction peak of GaN that is completely relaxed. This means that the c-axis length of the electron transport layer is shortened, that is, the a-axis length of the electron transport layer is elongated. It is thus confirmed that, through the intervention of the intermediate layer formed by the AlGaN crystal, the electron transport layer has tensile strain in the direction along the main surface of the substrate at room temperature.

[0332] As the Al composition ratio of the intermediate layer decreases, the angle 2θ of the (0002) diffraction peak of GaN constituting the electron transport layer gradually increases. This means that as the Al composition ratio of the intermediate layer decreases, the c-axis length of the electron transport layer gradually shortens, that is, the a-axis length of the electron transport layer gradually lengthens. It is thus confirmed that as the Al composition ratio of the intermediate layer decreases, the absolute value of the strain amount as the tensile strain of the electron transport layer increases.

[0333] (Crystallinity of the Electron Transport Layer and Dependence of the Intermediate Layer on Al Composition Ratio)

[0334] like Figure 4A As shown in the figure, when the Al composition ratio of the intermediate layer is 100%, the half-maximum full width of the (0002) diffraction of GaN constituting the electron transport layer is higher than 270 seconds, and the half-maximum full width of the (10-12) diffraction is higher than 410 seconds. It can be considered that when the Al composition ratio of the intermediate layer is 100%, that is, when the intermediate layer formed by AlGaN crystal is not provided, at the growth temperature of the electron transport layer, the electron transport layer undergoes compressive strain, and the crystallinity of the electron transport layer decreases (dislocation density increases).

[0335] In contrast, when the Al composition ratio of the intermediate layer is less than 100%, the half-maximum full width of the (0002) diffraction of GaN constituting the electron transport layer is less than 270 seconds, and the half-maximum full width of the (10-12) diffraction is less than 410 seconds. It is thus confirmed that the electron transport layer can be grown in a state close to strain-free at the growth temperature of the electron transport layer by the intervention of the intermediate layer formed by the AlGaN crystal, and the crystallinity of the electron transport layer can be improved.

[0336] As the Al composition ratio of the intermediate layer decreases within the range below 96%, the full width at half maximum of each diffraction of the electron transport layer gradually decreases. This confirms that as the Al composition ratio of the intermediate layer decreases, the lattice distortion of the electron transport layer can be further alleviated at the growth temperature of the electron transport layer, and the crystallinity of the electron transport layer can be stably improved.

[0337] (2) Experiment 2

[0338] (2-1) Preparation of semiconductor stack

[0339] A plurality of stacked products were prepared under the same conditions as in Experiment 1 except that the thickness of the electron transport layer was varied within a range of 100 nm to 1 μm. In Experiment 2, the Al composition ratio of the intermediate layer was 84%.

[0340] (2-2) Evaluation

[0341] (X-ray rocking curve measurement)

[0342] For the stacked product of Experiment 2, the X-ray rocking curve of the (0002) diffraction of GaN constituting the electron transport layer and the X-ray rocking curve of the (10-12) diffraction of GaN constituting the electron transport layer were measured. As a result, the full width at half maximum (FWHM) of the (0002) diffraction of GaN and the full width at half maximum of the (10-12) diffraction of GaN were obtained.

[0343] (Observation using multiphoton excitation microscopy)

[0344] The main surface of the electron supply layer was observed using a multiphoton excitation microscope for each of the stacked products in Experiment 2. As a result, the dislocation density of the main surface of the electron supply layer was determined.

[0345] (1-3) Results

[0346] (Crystallinity of electron transport layer, thickness dependence of electron transport layer)

[0347] like Figure 5A and Figure 5BAs shown in the figure, when the thickness of the electron transport layer is within the range of 100 nm to 1 μm, the half-maximum width of the (0002) diffraction of GaN constituting the electron transport layer is less than 300 seconds, and the half-maximum width of the (10-12) diffraction is less than 410 seconds. It is thus confirmed that by growing the electron transport layer in a state close to strain-free, the crystallinity of the electron transport layer can be improved even if the thickness of the electron transport layer is less than 1 μm.

[0348] (Dislocation density)

[0349] The results of multiphoton excitation microscopy showed that the dislocation density of the main surface of the electron supply layer was 5×10 8 cm －2 This confirmed that by growing the electron transport layer in a state close to being strain-free, the dislocation density of the electron transport layer can be reduced even if the electron transport layer does not grow three-dimensionally and even if it does not grow thickly.

[0350] <Preferred embodiment of the present invention>

[0351] Hereinafter, preferred embodiments of the present invention will be described.

[0352] (Note 1)

[0353] A semiconductor stack comprising:

[0354] A substrate comprising silicon carbide and having a main surface;

[0355] a first layer provided on the main surface of the substrate and comprising a crystal of aluminum nitride;

[0356] A second layer disposed on the first layer, comprising any one of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride;

[0357] a third layer of crystals comprising gallium nitride disposed on the second layer,

[0358] The first layer has a tensile strain along the main surface at 27°C.

[0359] (Note 2)

[0360] The semiconductor stack according to Supplementary Note 1, wherein the third layer has a tensile strain in a direction along the main surface at 27°C.

[0361] (Note 3)

[0362] The semiconductor stack according to Note 1 or Note 2, wherein:

[0363] The thickness of the third layer is less than 1 μm,

[0364] The full width at half maximum of (0002) diffraction of the third layer obtained by X-ray rocking curve measurement is 300 seconds or less,

[0365] The full width at half maximum of (10-12) diffraction of the third layer obtained by X-ray rocking curve measurement is 410 seconds or less.

[0366] (Note 4)

[0367] The semiconductor stack according to any one of Notes 1 to 3, wherein the dislocation density of the main surface of the third layer is 1×10 9 cm －2 the following.

[0368] (Note 5)

[0369] The semiconductor stack according to any one of Supplementary Notes 1 to 4, wherein the thickness of the first layer is greater than or equal to 200 nm and less than or equal to 800 nm.

[0370] (Note 6)

[0371] The semiconductor stack according to any one of Supplementary Notes 1 to 5, wherein the second layer is coherently disposed on the first layer.

[0372] (Note 7)

[0373] The semiconductor stack according to any one of Notes 1 to 6, wherein the second layer comprises Al x Ga 1－x A crystal represented by the composition formula of N,

[0374] The Al composition ratio x in the second layer is 0.75 or more and 0.96 or less.

[0375] (Note 8)

[0376] The semiconductor stack according to any one of Notes 1 to 7, wherein the oxygen concentration in the third layer is 1×10 16 cm －3 the following.

[0377] (Note 9)

[0378] The semiconductor stack according to any one of Notes 1 to 8, wherein the silicon concentration in the third layer is 1×10 16 cm －3 the following.

[0379] (Note 10)

[0380] The semiconductor stack according to any one of Notes 1 to 9, wherein the iron concentration and the carbon concentration in the third layer are 1×10 16 cm －3 the following.

[0381] (Note 11)

[0382] The semiconductor stack according to any one of Notes 1 to 10, wherein at 27° C., the strain ε3 of the third layer in the c-axis direction obtained by the following formula (3) is not less than −0.1% and less than −0.01%,

[0383] ε3=(c3-c GaN ) / c GaN ×100…(3)

[0384] Here,

[0385] c3 is the c-axis length of the GaN crystal constituting the third layer,

[0386] c GaN is the c-axis length of unstrained bulk GaN crystal.

[0387] (Note 12)

[0388] The semiconductor stack according to any one of Supplementary Notes 1 to 11, further comprising a fourth layer provided on the third layer and comprising a crystal of a Group III nitride having a wider band gap than gallium nitride.

[0389] (Note 13)

[0390] A semiconductor element comprising the third layer of the semiconductor stack according to any one of Appendix 1 to Appendix 12 as at least a part of a handling layer.

[0391] (Note 14)

[0392] A method for manufacturing a semiconductor stack, comprising the following steps

[0393] (a) a step of preparing a substrate including silicon carbide and having a main surface;

[0394] (b) a step of growing a first layer of crystals including aluminum nitride on the main surface of the substrate;

[0395] (c) performing an annealing process on the first layer;

[0396] (d) a step of growing a second layer including any one of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride crystals on the first layer;

[0397] (e) a step of growing a third layer of crystals including gallium nitride on the second layer,

[0398] In (c), the dislocation density of the main surface of the first layer is reduced by annealing the first layer compared to the dislocation density of the main surface of the first layer after (b).

[0399] (Note 15)

[0400] The method for manufacturing a semiconductor stack according to Supplementary Note 14, wherein after (c), the first layer is subjected to tensile strain at 27°C in a direction along the main surface of the substrate.

[0401] (Note 16)

[0402] The method for manufacturing a semiconductor stack according to Note 14 or Note 15, wherein in (e), the third layer is grown in such a manner that a tensile strain is applied to the third layer in a direction along the main surface of the substrate at 27°C.

Claims

1. A semiconductor stack comprising: A substrate comprising silicon carbide and having a main surface; a first layer provided on the main surface of the substrate and comprising a crystal of aluminum nitride; A second layer disposed on the first layer, comprising any one of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride; a third layer of crystals comprising gallium nitride disposed on the second layer, The first layer has a tensile strain along the main surface at 27°C.

2. The semiconductor stack according to claim 1, wherein The third layer has a tensile strain along the main surface at 27°C.

3. The semiconductor stack according to claim 1 or claim 2, wherein: The thickness of the third layer is less than 1 μm, The full width at half maximum of (0002) diffraction of the third layer obtained by X-ray rocking curve measurement is 300 seconds or less, The full width at half maximum of (10-12) diffraction of the third layer obtained by X-ray rocking curve measurement is 410 seconds or less.

4. The semiconductor stack according to claim 1 or claim 2, wherein: The dislocation density in the primary surface of the third layer is 1×10 9 cm －2 the following.

5. The semiconductor stack according to claim 1 or claim 2, wherein: The thickness of the first layer is greater than or equal to 200 nm and less than or equal to 800 nm.

6. The semiconductor stack according to claim 1 or claim 2, wherein: The second layer is coherently disposed on the first layer.

7. The semiconductor stack according to claim 1 or claim 2, wherein: The second layer comprises Al x Ga 1－ x A crystal represented by the composition formula of N, The Al composition ratio x in the second layer is 0.75 or more and 0.96 or less.

8. The semiconductor stack according to claim 1 or claim 2, wherein: The oxygen concentration in the third layer, excluding the region from the main surface of the third layer to a depth of 200 nm, is 1×10 16 cm －3 the following.

9. The semiconductor stack according to claim 1 or claim 2, wherein: The silicon concentration in the third layer is 1×10 16 cm －3 the following.

10. The semiconductor stack according to claim 1 or claim 2, wherein: The iron concentration and carbon concentration in the third layer are 1×10 16 cm －3 the following.

11. The semiconductor stack according to claim 1 or claim 2, wherein: At 27° C., the strain amount ε3 of the third layer in the c-axis direction obtained by the following formula (3) is not less than −0.1% and less than −0.01%. ε3=(c3-c GaN ) / c GaN ×100 …(3) Here, c3 is the c-axis length of the GaN crystal constituting the third layer, c GaN is the c-axis length of unstrained bulk GaN crystal. 12 . A semiconductor element comprising the third layer of the semiconductor stack according to claim 1 or claim 2 as at least a part of a handling layer.

13. A method for manufacturing a semiconductor stack, wherein: The following processes are available: (a) a step of preparing a substrate including silicon carbide and having a main surface; (b) a step of growing a first layer of crystals including aluminum nitride on the main surface of the substrate; (c) performing an annealing process on the first layer; (d) a step of growing a second layer including any one of aluminum gallium nitride, aluminum indium nitride or aluminum indium gallium nitride crystals on the first layer; (e) a step of growing a third layer of crystals including gallium nitride on the second layer, In (c), by annealing the first layer, the dislocation density in the main surface of the first layer is made lower than the dislocation density in the main surface of the first layer after (b).

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