Semiconductor device including transistor and method of manufacturing same

Abstract

The invention relates to a semiconductor device including a transistor and a method of manufacturing the same. A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a semiconductor pattern; an impurity region disposed on one side of the semiconductor pattern and having a lower surface forming a flat surface with a lower surface of the semiconductor pattern; a gate structure disposed under the semiconductor pattern; and a contact plug disposed over the impurity region and electrically connected to the impurity region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0135933, filed on October 12, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a semiconductor technology, and more particularly, to a semiconductor device including a transistor and a method for manufacturing the same. Background Art

[0004] With the development of the electronics industry, electronic products are gradually moving towards miniaturization, high performance and high integration. In order to meet these needs, it is necessary to develop technologies that can maintain and / or improve the characteristics of unit elements (such as transistors) that constitute electronic products while reducing the area they occupy. Summary of the invention

[0005] In an embodiment of the present disclosure, a semiconductor device may include: a semiconductor pattern; an impurity region, which is arranged on one side of the semiconductor pattern and has a lower surface that forms a flat surface with the lower surface of the semiconductor pattern; a gate structure, which is arranged under the semiconductor pattern; and a contact plug, which is arranged above the impurity region and electrically connected to the impurity region.

[0006] In an embodiment of the present disclosure, a semiconductor device is provided, which includes a semiconductor pattern and an impurity region disposed on one side of the semiconductor pattern, wherein the impurity region has a bottom surface that forms a flat surface with the bottom surface of the semiconductor pattern. The semiconductor device also includes a gate structure disposed under the semiconductor pattern. The gate structure can completely overlap with the semiconductor pattern in the lateral direction. The semiconductor device may also include a contact plug disposed on the impurity region. The contact plug may be electrically connected to the impurity region. The semiconductor device may also include an insulating layer disposed under the impurity region and that may cover the impurity region.

[0007] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a gate structure or a sacrificial gate pattern on a semiconductor substrate; forming an impurity region by doping impurities into the semiconductor substrate exposed by the gate structure or the sacrificial gate pattern; after turning the semiconductor substrate with the impurity region formed therein upside down, performing a planarization process to expose the impurity region; and forming a contact plug on the planarized impurity region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1F is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0009] Figure 2is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0010] Figure 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0011] FIG. 4A to FIG. 4D is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0012] FIG. 5A to FIG. 5D is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0013] FIG. 6A to FIG. 6E is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0015] The drawings are not necessarily drawn to scale. In some cases, the proportions of at least some structures in the drawings may be exaggerated to clearly illustrate certain features of the described embodiments. When presenting a specific example in a drawing or description of two or more layers in a multilayer structure, the relative positioning relationship of these layers shown or the order in which the layers are arranged reflect the specific implementation of the described or illustrated example and different relative positioning relationships or the order in which the layers are arranged are possible. In addition, the example of the multilayer structure described or illustrated may not reflect all the layers present in the particular multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the multilayer structure described or illustrated is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0016] Figures 1A to 1F is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0017] Next, the manufacturing method will be described first.

[0018] Reference Figure 1A, a semiconductor substrate 100 may be provided. The semiconductor substrate 100 may include a semiconductor material such as silicon or silicon germanium. The semiconductor substrate 100 may include a first surface 101, an initial second surface 102 opposite to the first surface 101, and a side surface connecting the first surface 101 and the second surface. In this process, the semiconductor substrate 100 may be arranged so that the first surface 101 is located above the initial second surface 102.

[0019] Subsequently, an isolation layer 105 may be formed in the semiconductor substrate 100 to define an active region. The isolation layer 105 may be formed by etching the semiconductor substrate 100 to a predetermined depth to form a trench; depositing an insulating material having a thickness sufficient to fill the trench; and performing a planarization process such as CMP (chemical mechanical polishing) to expose the upper surface of the semiconductor substrate 100. Etching for forming the trench may be performed using a mask pattern (not shown) covering the active region of the semiconductor substrate 100 as an etch barrier. The isolation layer 105 may include at least one of a plurality of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0020] Subsequently, a gate structure 110 may be formed over the semiconductor substrate 100. The gate structure 110 may include a gate insulating layer 112, a gate electrode 114, and a gate hard mask 116 sequentially stacked over the semiconductor substrate 100. The gate structure 110 may further include a gate spacer 118 formed over the sidewall of the gate structure 110. The gate insulating layer 112 may include at least one of a plurality of insulating materials, such as silicon oxide or a high dielectric constant material having a dielectric constant higher than silicon oxide. The gate electrode 114 may include at least one of a plurality of conductive materials, for example, a metal such as lanthanum (La), tantalum (Ta), titanium (Ti), niobium (Nb), aluminum (Al), tungsten (W), ruthenium (Ru), copper (Cu), or molybdenum (Mo), a metal nitride containing at least one of these metals, a metal oxide containing at least one of these metals, or an alloy containing two or more of these metals. The gate electrode 114 may have a single-layer structure or a multi-layer structure. Each of the gate hard mask 116 and the gate spacer 118 may include at least one of a variety of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure or a multi-layer structure. For example, the gate structure 110 may be formed by the following steps: depositing an insulating material for forming a gate insulating layer 112, a conductive material for forming a gate electrode 114, and an insulating material for forming a gate hard mask 116 on the semiconductor substrate 100; then selectively etching the deposited materials to form a stacked structure of the gate insulating layer 112, the gate electrode 114, and the gate hard mask 116; and finally forming a gate spacer 118 on the sidewalls of the stacked structure. The gate structure 110 is not limited to the configuration shown, and as long as the gate structure 110 includes a gate electrode separated from the semiconductor substrate by a gate insulating layer, the shape, layer structure, and formation process of the gate structure 110 may be modified in various ways. For example, as Figure 3 As shown, another type of gate structure may be formed by a replacement metal gate (RMG) process.

[0021] Reference Figure 1B , the initial impurity region 120 may be formed by, for example, doping impurities into the semiconductor substrate 100 exposed by the gate structure 110 via ion implantation. The depth of the initial impurity region 120 may be less than the depth of the isolation layer 105. The lower surface (also referred to as the bottom surface) of the initial impurity region 120 may be located above the lower surface (also referred to as the bottom surface) of the isolation layer 105. After the initial impurity region 120 is formed, a heat treatment process may be performed to activate the impurities, such as, for example, a rapid thermal annealing (RTA) process.

[0022] Subsequently, a first interlayer insulating layer 130 covering the gate structure 110 may be formed over the semiconductor substrate 100. The first interlayer insulating layer 130 may include at least one of various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single layer structure or a multilayer structure.

[0023] Reference Figure 1C , in Figure 1B In a state where the initial second surface 102 of the semiconductor substrate 100 is flipped upside down so that the initial second surface 102 is located above the first surface 101, a planarization process such as CMP may be performed to remove a portion from the initial second surface 102 of the semiconductor substrate 100. The planarization process may be performed to expose the initial impurity region 120, and thus a portion of the initial impurity region 120 and a portion of the isolation layer 105 may be removed.

[0024] The planarized semiconductor substrate 100 will be referred to as a semiconductor pattern 100A hereinafter, the planarized initial impurity region 120 will be referred to as an impurity region 120A hereinafter, and the planarized isolation layer 105 will be referred to as an isolation pattern 105A hereinafter. The semiconductor pattern 100A may include a first surface 101 and a second surface 102A located above the first surface 101. The second surface 102A may be located below the initial second surface 102. The impurity region 120A may include a lower surface forming a flat surface with the first surface 101 and an upper surface forming a flat surface with the second surface 102A. The isolation pattern 105A may include a lower surface forming a flat surface with the first surface 101 and an upper surface forming a flat surface with the second surface 102A. That is, the semiconductor pattern 100A, the impurity region 120A, and the isolation pattern 105A may be located at the same level in the vertical direction and may have a flat upper surface and a flat lower surface. The gate structure 110 may be disposed under the semiconductor pattern 100A to completely overlap the semiconductor pattern 100A in the lateral direction (from left to right direction), which means that the sidewalls of the gate structure 110 are aligned with the sidewalls of the semiconductor pattern 100A in the lateral direction. The lateral direction refers to a horizontal direction, which is a direction parallel to a plane defined by the top surface of the semiconductor substrate 100. However, the embodiments of the present disclosure are not limited thereto, and the sidewalls of the semiconductor pattern 100A and the sidewalls of the gate structure 110 may not be precisely aligned with each other depending on the shape of the impurity region 120A. The first interlayer insulating layer 130 may be formed to cover the gate structure 110 under the impurity region 120A and the isolation pattern 105A, thereby covering the impurity region 120A and the isolation pattern 105A. That is, the first interlayer insulating layer 130 may contact the lower surface of the impurity region 120A and the lower surface of the isolation pattern 105A.

[0025] As a result of this process, a transistor including a gate structure 110, a semiconductor pattern 100A, and an impurity region 120A may be formed. The gate structure 110 may correspond to a gate of the transistor, the semiconductor pattern 100A may correspond to a channel of the transistor, and the impurity region 120A may correspond to a source or drain of the transistor.

[0026] In addition, a silicidation process may be performed to reduce the resistance of the impurity region 120A. This will be referred to as Figure 1D and Figure 1E Give a description.

[0027] Reference Figure 1D , you can Figure 1C A sacrificial insulating pattern 140 covering the semiconductor pattern 100A is formed on the result of the process. The sacrificial insulating pattern 140 may include at least one of a variety of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0028] Subsequently, a metal layer 150 may be formed over the sacrificial insulating pattern 140, the impurity region 120A, and the isolation pattern 105A along the contours of the sacrificial insulating pattern 140, the impurity region 120A, and the isolation pattern 105A. The metal layer 150 may be formed by deposition and may include at least one of a variety of metals such as cobalt (Co), nickel (Ni), or titanium (Ti).

[0029] Reference Figure 1E , can be Figure 1D A heat treatment process is performed as a result of the process of the metal layer 150 to react the metal of the metal layer 150 with the silicon of the impurity region 120A. Through the reaction of the metal and the silicon, a metal silicide layer 155 may be formed. In this process, the upper portion of the impurity region 120A may be transformed into the metal silicide layer 155, and the remaining portion of the impurity region 120A is hereinafter represented as the impurity region 120B. As a result, the metal silicide layer 155 may be located above the impurity region 120B, and the sidewall of the impurity region 120B may be aligned with the sidewall of the metal silicide layer 155. The upper surface of the impurity region 120B may be located below the second surface 102A of the semiconductor pattern 100A, and the upper surface (i.e., the top surface) of the metal silicide layer 155 may be at the same level as the second surface 102A of the semiconductor pattern 100A. The upper surface (i.e., the top surface) of the metal silicide layer 155 may form a flat surface with the second surface 102A of the semiconductor pattern 100A. However, embodiments of the present disclosure are not limited thereto, and the sidewalls of the impurity region 120B may not be aligned with the sidewalls of the metal silicide layer 155 depending on the shape of the sacrificial insulating pattern 140 .

[0030] Subsequently, unreacted portions of the metal layer 150 and the sacrificial insulating pattern 140 may be removed.

[0031] The above Figure 1D and Figure 1E The process may be optional and thus may be omitted.

[0032] Reference Figure 1F , you can Figure 1E A second interlayer insulating layer 160 and a contact plug 170 penetrating the second interlayer insulating layer 160 to be connected to the metal silicide layer 155 are formed on the result of the process.

[0033] The second interlayer insulating layer 160 may include at least one of a variety of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure or a multi-layer structure. The contact plug 170 may include at least one of a variety of conductive materials, for example, a metal such as lanthanum (La), tantalum (Ta), titanium (Ti), niobium (Nb), aluminum (Al), tungsten (W), ruthenium (Ru), copper (Cu), or molybdenum (Mo), a metal nitride containing at least one of these metals, a metal oxide containing at least one of these metals, or an alloy containing two or more of these metals, and may have a single-layer structure or a multi-layer structure. Figure 1E An insulating material for forming the second interlayer insulating layer 160 is deposited on the process result, the insulating material is selectively etched to form a hole exposing the metal silicide layer 155, and the hole is filled with a conductive material to form the second interlayer insulating layer 160 and the contact plug 170.

[0034] The contact plug 170 may be in direct contact with the metal silicide layer 155 , and may be electrically connected to the impurity region 120B via the metal silicide layer 155 .

[0035] when omitted Figure 1D and Figure 1E During the process, the Figure 1F The process of forming the second interlayer insulating layer 160 and the contact plug 170 may be performed at Figure 1C In this case, the contact plug 170 may directly contact the impurity region 120A to be electrically connected to the impurity region 120A.

[0036] The semiconductor device of this embodiment can be manufactured through the above-mentioned process.

[0037] Refer again Figure 1FThe semiconductor device of the present embodiment may include a semiconductor pattern 100A, a stacked structure including a structure in which an impurity region 120B and a metal silicide layer 155 are stacked and disposed at one side of the semiconductor pattern 100A, an isolation pattern 105A disposed at one side of the stacked structure, a gate structure 110 disposed under the semiconductor pattern 100A, a first interlayer insulating layer 130 disposed under the impurity region 120B and the isolation pattern 105A to cover them, a second interlayer insulating layer 160 disposed over the semiconductor pattern 100A, the metal silicide layer 155, and the isolation pattern 105A to cover them, and a contact plug 170 passing through the second interlayer insulating layer 160 and contacting the metal silicide layer 155. The contact plug 170 may be electrically connected to the impurity region 120B via the metal silicide layer 155.

[0038] Here, the stacked structure of the semiconductor pattern 100A, the impurity region 120B and the metal silicide layer 155, and the isolation pattern 105A may be located at the same level in the vertical direction, and thus may have upper surfaces planarized with each other and lower surfaces planarized with each other. When the metal silicide layer 155 is omitted, the semiconductor pattern 100A, the impurity region (see Figure 1C The isolation pattern 120A) and the isolation pattern 105A may be located at the same level in a vertical direction and thus may have upper surfaces planarized with each other and lower surfaces planarized with each other.

[0039] According to the above-described semiconductor device and the method for manufacturing the same, the following effects can be obtained.

[0040] First, because the gate structure 110 and the contact plug 170 are located at different levels in the vertical direction and are spatially separated from each other by the semiconductor pattern 100A having a fully depleted state, there are several advantages compared to the prior art in which the gate structure is disposed between two contact plugs. For example, the space between the two contact plugs 170 can be reduced, and sufficient space for forming the gate structure 110 and for forming the contact plug 170 can be ensured, so that the semiconductor device can be advantageously reduced in size. In addition, various defects that may occur when the contact plug and the gate structure are adjacent to each other, such as an electrical short circuit defect between the contact plug and the gate structure, can be prevented. That is, an electrical short circuit does not occur between the contact plug 170 and the gate structure 110. In addition, since there is no need to consider the electrical short circuit between the contact plug 170 and the gate structure 110, the gate spacer 118 of the gate structure 110 can be omitted, thereby simplifying the process. In addition, since the parasitic capacitance between the contact plug 170 and the gate structure 110 is reduced, the performance of the transistor can be improved. In addition, as will be described later, the wiring of the wire can become more favorable (see Figure 2 ), the RMG process that needs to ensure sufficient gate line width can be made easier (see Figure 3), and the degree of freedom in process sequencing can be increased, further improving transistor performance (see FIG. 4A to FIG. 6E ).

[0041] In addition, since the lower surface of the impurity region 120B is covered by the first interlayer insulating layer 130, the impurity region 120B may have a completely depleted state. Therefore, leakage current through the impurity region 120B may be prevented or reduced.

[0042] Figure 2 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0043] Now refer to Figure 2 ,Apart from Figure 1F In addition to the components of the semiconductor device, the semiconductor device of this embodiment may further include a gate contact 210, a first conductive line 220 and a second conductive line 230.

[0044] The gate contact 210 may be electrically connected to the gate electrode 114 by passing through the first interlayer insulating layer 130 and the gate hard mask 116 .

[0045] The first conductive line 220 may be disposed under the first interlayer insulating layer 130 and connected to the gate contact 210 .

[0046] The second conductive line 230 may be disposed over the second interlayer insulating layer 160 and connected to the contact plug 170 .

[0047] The gate contact 210 and the first conductive line 220 may be formed after forming the gate structure 110 and the first interlayer insulating layer 130. For example, the process of forming the gate contact 210 and the first conductive line 220 may be performed in the following manner: Figure 1B After the process, or can be performed Figure 1F The process result is flipped upside down and then executed.

[0048] The second conductive line 230 may be formed after forming the contact plug 170. For example, Figure 1F The second conductive line 230 is formed after the process of FIG.

[0049] In the present embodiment, the first conductive line 220 electrically connected to the gate structure 110 and the second conductive line 230 electrically connected to the contact plug 170 may be located at different levels in the vertical direction. Therefore, the space for forming the first conductive line 220 and the space for forming the second conductive line 230 may be increased, thereby facilitating the wiring of the first conductive line 220 and the second conductive line 230.

[0050] Figure 3 is a cross-sectional view showing a semiconductor device according to another embodiment of the present disclosure.

[0051] Reference Figure 3 , the semiconductor device of the present embodiment may include: a semiconductor pattern 300A; a stacked structure including a structure in which an impurity region 320B and a metal silicide layer 355 are stacked and disposed at one side of the semiconductor pattern 300A; an isolation pattern 305A disposed at one side of the stacked structure; a gate structure 310 disposed under the semiconductor pattern 300A; a first interlayer insulating layer 330 disposed under the impurity region 320B and the isolation pattern 305A to cover them; a second interlayer insulating layer 360 disposed over the semiconductor pattern 300A, the metal silicide layer 355, and the isolation pattern 305A to cover them; and a contact plug 370 that passes through the second interlayer insulating layer 360 and contacts the metal silicide layer 355. The contact plug 370 may be electrically connected to the impurity region 320B via the metal silicide layer 355.

[0052] Here, the gate structure 310 may be different from the gate structure of the above-mentioned embodiment (see Figure 1F 110 in). The gate structure 310 may include a gate insulating layer 312, a gate electrode 314, and a gate spacer 318. The gate insulating layer 312 may be formed along the inner wall of the space defined by the gate spacer 318, that is, along the inner wall of the gate spacer 318 and the lower surface of the semiconductor pattern 300A. The gate electrode 314 may be formed to fill the remaining portion of the space defined by the gate spacer 318, and thus may have a sidewall and an upper surface surrounded by the gate insulating layer 312.

[0053] The process for forming the gate structure 310 may include: forming a sacrificial gate pattern on a semiconductor substrate; forming a gate spacer 318 on a sidewall of the sacrificial gate pattern; providing a space by selectively removing the sacrificial gate pattern; forming a gate insulating layer 312 along the inner wall of the provided space; filling the remaining space with a conductive material to form a gate electrode 314; and turning the semiconductor substrate upside down to provide a gate structure 310. Figure 3 A gate structure 310 is shown.

[0054] Because the sacrificial gate pattern is replaced with the gate electrode 314, the process may be referred to as an RMG process. In the RMG process, because a space for filling the conductive material is required, the gate structure 310 may be required to have a large line width. In the present embodiment, it is advantageous to have the contact plug 370 located at a different level from the gate structure 310 in the vertical direction because it is easier to increase the line width of the gate structure 310.

[0055] FIG. 4A to FIG. 4D is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0056] Reference Figure 4A, an isolation layer 405 may be formed in the semiconductor substrate 400 to define an active region.

[0057] Subsequently, a sacrificial gate pattern 425 may be formed over the semiconductor substrate 400. The sacrificial gate pattern 425 may expose a region where an impurity region is to be formed. The sacrificial gate pattern 425 may include polysilicon. However, the embodiments of the present disclosure are not limited thereto, and the sacrificial gate pattern 425 may include at least one of a variety of materials that are easily removed.

[0058] Subsequently, a preliminary impurity region 420 may be formed by doping impurities into the semiconductor substrate 400 exposed by the sacrificial gate pattern 425. After the preliminary impurity region 420 is formed, a thermal treatment process for activating the impurities may be performed.

[0059] Reference Figure 4B After removing the sacrificial gate pattern 425 , an initial gate structure 410 may be formed over the semiconductor substrate 400 having the initial impurity region 420 formed therein. The initial gate structure 410 may include an initial gate insulating layer 412 , an initial gate electrode 414 , and an initial gate hard mask 416 .

[0060] Reference Figure 4C , the initial gate structure 410 may be selectively etched to form a gate structure 410A in which a gate insulating layer 412A, a gate electrode 414A, and a gate hard mask 416A are stacked. The gate structure 410A may be formed to cover an area overlapping an area covered by the sacrificial gate pattern 425. Therefore, the initial impurity region 420 may be located in the semiconductor substrate 400 on both sides of the gate structure 410A.

[0061] Subsequently, a first interlayer insulating layer 430 may be formed over the semiconductor substrate 400 to cover the gate structure 410A.

[0062] Reference Figure 4D ,exist Figure 4C After the process result is flipped upside down, the same Figure 1C to Figure 1F The processes described in the above are basically the same as those described in the above, namely, the planarization process, the silicidation process, and the contact plug formation process. Thus, the semiconductor pattern 400A, the impurity region 420B, the metal silicide layer 455, the isolation pattern 405A, the second interlayer insulating layer 460, and the contact plug 470 can be formed.

[0063] According to the present embodiment, after forming the initial impurity region 420 and the thermal treatment process, the gate structure 410A may be formed. Therefore, degradation of the gate structure 410A due to the thermal treatment process may be prevented.

[0064] FIG. 5A to FIG. 5Dis a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0065] Reference Figure 5A , an isolation layer 505 may be formed in the semiconductor substrate 500 to define an active region.

[0066] Subsequently, after forming a sacrificial gate pattern 525 over the semiconductor substrate 500, an initial impurity region 520 may be formed by doping impurities into the semiconductor substrate 500 exposed by the sacrificial gate pattern 525. Subsequently, a thermal treatment process may be performed to activate the impurities in the initial impurity region 520.

[0067] Reference Figure 5B ,exist Figure 5A After the process result is flipped upside down, the same Figure 1C to Figure 1F The processes described in the above are basically the same as those described in the above, namely, the planarization process, the silicide process, and the contact plug formation process. Thus, the semiconductor pattern 500A, the impurity region 520B, the metal silicide layer 555, the isolation pattern 505A, the second interlayer insulating layer 560, and the contact plug 570 can be formed.

[0068] Reference Figure 5C After removing the sacrificial gate pattern 525, an initial gate structure 510 may be formed under the semiconductor pattern 500A, the impurity region 520B, and the isolation pattern 505A. The initial gate structure 510 may include a stacked initial gate insulating layer 512, an initial gate electrode 514, and an initial gate hard mask 516.

[0069] Reference Figure 5D , the initial gate structure 510 may be selectively etched to form a gate structure 510A in which a gate insulating layer 512A, a gate electrode 514A, and a gate hard mask 516A are stacked.

[0070] Figure 5C and Figure 5D The process can be Figure 5B The process result is flipped upside down and then executed.

[0071] Subsequently, although not shown, a process of forming a first interlayer insulating layer covering the gate structure 510A may be further performed. Figure 5B The first interlayer insulating layer forming process is performed after the process result is turned upside down.

[0072] According to the present embodiment, the gate structure 510A may be formed after the formation process of the initial impurity region 520, the heat treatment process for activating the impurities and / or for forming the metal silicide layer 555, and the formation process of the contact plug 570. Therefore, the degradation of the gate structure 510A due to the heat treatment process or the formation process of the contact plug 570 may be prevented.

[0073] FIG. 6A to FIG. 6E is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0074] Reference Fig. 6A , can be executed with Figures 1A to 1C A process substantially the same as the process described in is used to form a structure including a first semiconductor pattern 600A, an impurity region 620A, a first isolation pattern 605A, a gate structure 610 including a gate insulating layer 612, a gate electrode 614, a gate hard mask 616, a gate spacer 618, and a first interlayer insulating layer 630.

[0075] Reference Figure 6B , a second semiconductor substrate 700 may be provided. In addition, a second isolation layer 705 may be formed in the second semiconductor substrate 700 to define an active region. Fig. 6A When bonding the structure of the second isolation layer 705 to the first isolation pattern 605A, the second isolation layer 705 may be used to overlap and contact the first isolation pattern 605A. The second isolation layer 705 may be formed at a position overlapping the first isolation pattern 605A.

[0076] Subsequently, a sacrificial insulating pattern 725 may be formed on the second semiconductor substrate 700 to cover the second semiconductor substrate 700 and the Fig. 6A The structure is bonded to an area overlapping with the first semiconductor pattern 600A.

[0077] Subsequently, a metal layer 750 may be formed over surface profiles of the sacrificial insulating pattern 725 , the semiconductor substrate 700 , and the second isolation layer 705 .

[0078] Reference Figure 6C , can be Figure 6B A heat treatment process is performed on the result of the process to react the metal of the metal layer 750 with the silicon of the semiconductor substrate 700 to form a metal silicide layer 755. The metal silicide layer 755 may be formed in the second semiconductor substrate 700, and may have an upper surface forming a flat surface with an upper surface of the second semiconductor substrate 700 and a lower surface higher than a lower surface of the second isolation layer 705.

[0079] Subsequently, unreacted portions of the metal layer 750 and the sacrificial insulating pattern 725 may be removed.

[0080] Reference Fig.6D , Figure 6C The process result can be flipped upside down and bonded to Fig. 6A In this case, the second isolation layer 705 may overlap and contact the first isolation pattern 605A, the metal silicide layer 755 may overlap and contact the impurity region 620A, and the remaining portion of the second semiconductor substrate 700 except the metal silicide layer 755 may overlap and contact the first semiconductor pattern 600A.

[0081] Reference Fig. 6E , a planarization process such as CMP may be performed to remove a portion from the upper surface of the second semiconductor substrate 700 and expose the metal silicide layer 755. Therefore, a portion of the metal silicide layer 755 and a portion of the second isolation layer 705 may be removed.

[0082] The planarized second semiconductor substrate 700 will be referred to as a second semiconductor pattern 700A hereinafter, the planarized metal silicide layer 755 will be referred to as a metal silicide pattern 755A hereinafter, and the planarized second isolation layer 705 will be referred to as a second isolation pattern 705A hereinafter. The second semiconductor pattern 700A, the metal silicide pattern 755A, and the second isolation pattern 705A may be located at the same level as each other in a vertical direction and may have a planar upper surface and a planar lower surface.

[0083] Since the first isolation pattern 605A and the second isolation pattern 705A are formed by separate processes, they may overlap each other and may have sidewalls that are not aligned with each other. The metal silicide pattern 755A and the impurity region 620A may overlap each other and may have sidewalls that are not aligned with each other. The first semiconductor pattern 600A and the second semiconductor pattern 700A may overlap each other and may have sidewalls that are not aligned with each other. However, the embodiments of the present disclosure are not limited thereto, and at least a portion of the sidewalls may be aligned with each other.

[0084] Subsequently, a second interlayer insulating layer 760 may be formed over the second semiconductor pattern 700A, the metal silicide pattern 755A, and the second isolation pattern 705A. A contact plug 770 may be formed through the second interlayer insulating layer 760 to be connected to the silicide pattern 755A.

[0085] According to the present embodiment, the metal silicide layer 755 may be formed separately from other components of the semiconductor device, and thus the quality of the metal silicide layer 755 may be improved.

[0086] According to the above-described embodiments of the present disclosure, the performance of a transistor may be enhanced and the manufacturing process may be improved.

[0087] Although for illustrative purposes described various embodiments of the present disclosure, it will be apparent to those skilled in the art that, without departing from the spirit and scope of the present teachings as defined in the appended claims, various changes and modifications may be made. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Semiconductor patterning; an impurity region disposed at one side of the semiconductor pattern and having a lower surface forming a flat surface with a lower surface of the semiconductor pattern; a gate structure disposed under the semiconductor pattern; as well as A contact plug is disposed on the impurity region and electrically connected to the impurity region.

2. The semiconductor device according to claim 1, further comprising: An insulating layer is disposed under the impurity region and covers the impurity region.

3. The semiconductor device according to claim 1, wherein An upper surface of the impurity region forms a flat surface with an upper surface of the semiconductor pattern.

4. The semiconductor device according to claim 1, further comprising: A metal silicide layer is disposed between the impurity region and the contact plug.

5. The semiconductor device according to claim 4, wherein: The sidewalls of the metal silicide layer are aligned with the sidewalls of the impurity region, and An upper surface of the metal silicide layer forms a flat surface with an upper surface of the semiconductor pattern.

6. The semiconductor device according to claim 1, further comprising: An isolation pattern is disposed at one side of the impurity region and has a lower surface forming a flat surface with the lower surface of the semiconductor pattern and an upper surface forming a flat surface with the upper surface of the semiconductor pattern.

7. The semiconductor device according to claim 1, further comprising: A first conductive line disposed under the gate structure and electrically connected to a gate electrode of the gate structure; as well as A second conductive line is disposed over the contact plug and electrically connected to the contact plug.

8. The semiconductor device according to claim 1, wherein The gate structure includes a gate electrode and a gate insulating layer interposed between the gate electrode and the semiconductor pattern.

9. The semiconductor device according to claim 1, wherein: The gate structure includes a gate electrode and a gate insulating layer disposed between the gate electrode and the semiconductor pattern and covering a sidewall of the gate electrode.

10. The semiconductor device according to claim 1, further comprising: an additional semiconductor pattern disposed on and contacting the semiconductor pattern; as well as a metal silicide pattern disposed on one side of the additional semiconductor pattern and contacting the impurity region, The contact plug is disposed on the metal silicide pattern and connected to the impurity region via the metal silicide pattern.

11. The semiconductor device according to claim 10, wherein: The upper surface of the impurity region forms a flat surface with the upper surface of the semiconductor pattern, and The metal silicide pattern has a lower surface forming a flat surface with a lower surface of the additional semiconductor pattern and an upper surface forming a flat surface with an upper surface of the additional semiconductor pattern.

12. The semiconductor device according to claim 10, further comprising: an isolation pattern disposed at one side of the impurity region and having a lower surface forming a flat surface with the lower surface of the semiconductor pattern and an upper surface forming a flat surface with the upper surface of the semiconductor pattern; as well as An additional isolation pattern is disposed at one side of the metal silicide pattern and has a lower surface forming a flat surface with a lower surface of the additional semiconductor pattern and an upper surface forming a flat surface with an upper surface of the additional semiconductor pattern.

13. A method for manufacturing a semiconductor device, the method comprising: forming a gate structure or a sacrificial gate pattern on a semiconductor substrate; forming an impurity region by doping impurities into the semiconductor substrate exposed by the gate structure or the sacrificial gate pattern; After turning the semiconductor substrate having the impurity region formed thereon upside down, performing a planarization process to expose the impurity region; as well as A contact plug is formed on the planarized impurity region.

14. The method according to claim 13, further comprising: After performing the planarization process and before forming the contact plug, a portion of the planarized impurity region is converted into a metal silicide layer.

15. The method according to claim 14, wherein: The contact plug is disposed on the metal silicide layer and connected to the planarized impurity region via the metal silicide layer.

16. The method according to claim 13, further comprising: When the sacrificial gate pattern is formed on the semiconductor substrate, removing the sacrificial gate pattern; as well as The gate structure is formed.

17. The method according to claim 16, wherein: Forming the gate structure is performed after forming the impurity region.

18. The method according to claim 16, further comprising: After the planarization process and before forming the contact plug, a portion of the planarized impurity region is converted into a metal silicide layer, wherein forming the gate structure is performed after forming the metal silicide layer and after forming the contact plug.

19. The method according to claim 13, further comprising: providing an additional semiconductor substrate; forming a metal silicide layer in the additional semiconductor substrate; After the additional semiconductor substrate on which the metal silicide layer is formed is turned upside down, the additional semiconductor substrate on which the metal silicide layer is formed is bonded onto the flat surface formed by the flattening process.

20. The method according to claim 19, wherein: During the bonding, the metal silicide layer contacts the impurity region.

21. The method of claim 19, further comprising: After the bonding, an additional planarization process is performed to expose the metal silicide layer.

22. A semiconductor device comprising: Semiconductor patterning; an impurity region disposed at one side of the semiconductor pattern, the impurity region having a bottom surface forming a flat surface with a bottom surface of the semiconductor pattern; A gate structure, which is disposed under the semiconductor pattern, wherein the gate structure and the semiconductor pattern completely overlap in a lateral direction; A contact plug disposed on the impurity region, the contact plug being electrically connected to the impurity region; as well as An insulating layer is disposed under the impurity region and covers the impurity region.

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