Thin film transistor and manufacturing method thereof, array substrate and display device

Abstract

The invention discloses a thin film transistor and a manufacturing method thereof, an array substrate and a display device, the manufacturing method of the thin film transistor solves the problem that a copper or copper alloy metal circuit is easy to oxidize and corrode in the prior art, and the contrast ratio and the reliability of the display device are improved. According to the invention, a blackening process is added after etching of a copper or copper alloy metal circuit used as a grid electrode or a source / drain electrode is completed, and blackening treatment is carried out on the cross section or the cross section and the surface of the exposed copper or copper alloy circuit, so that an oxidation-resistant metal protection layer is formed; the copper or copper alloy circuit is effectively prevented from being further oxidized and corroded in the follow-up manufacturing process or the using process, the light emissivity of the copper or copper alloy circuit is reduced, and therefore the reliability and the contrast ratio of the display device are improved.

Description

Technical Field

[0001] The present invention relates to the field of light-emitting display technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background Art

[0002] Flat panel display technology plays a vital role in modern electronic products. Thin-film transistor liquid crystal displays and organic light-emitting diodes have become the mainstream choice in the market due to their advantages such as small size and diverse display effects. The core of these display technologies lies in driving the circuits and thin-film transistors on the backplane, which are key components for achieving high-resolution display and precise control.

[0003] In the process of manufacturing these core components, a series of thin film layers need to be constructed on the substrate, including gate electrode, gate insulation layer, active layer, source / drain electrode, etc., to finally form a complex circuit structure. Specifically, the existing array substrate preparation process usually involves sputtering to form a gate electrode on the substrate, followed by depositing a gate insulation layer, then depositing an active layer, then sputtering a source / drain electrode, and finally depositing a passivation layer and pixel electrode. This continuous process has extremely high requirements for accuracy and material properties.

[0004] However, the copper or copper alloy materials used in the prior art for preparing gate electrodes and source / drain electrodes have some defects. Copper, as a relatively active metal, easily reacts with oxygen in the environment, resulting in oxidation or diffusion into the active layer. This uncontrolled copper diffusion will contaminate the active layer and affect the mobility of carriers, thereby reducing the performance of the display device and ultimately causing product defects. In addition, copper surface oxidation can also cause lead corrosion, resulting in a serious decline in product performance. In order to solve these problems, the industry usually adds at least one metal or non-metal protective layer on the upper and lower surfaces of copper or copper alloys to protect the copper leads from environmental influences.

[0005] Nevertheless, the existing process is to first deposit a protective layer and copper metal in a vacuum, and then perform photolithography to form copper leads. Although this method sets a protective layer on the upper and lower surfaces of the copper lead, the cross-section of the copper lead is still exposed after etching, and each additional layer of protective layer makes the process more complicated. Since the thickness of the copper layer is usually about 500 nanometers, the copper on these unprotected cross-sections may still diffuse into the active layer, or undergo oxidation reactions, causing corrosion. In fact, copper corrosion has become one of the most prominent defects in copper-process flat-panel display devices. Therefore, the development of new protection technologies and materials to effectively prevent the oxidation and diffusion of copper is of great significance to improving the reliability and life of flat-panel display devices. Summary of the invention

[0006] The main purpose of the present invention is to provide an improved method for manufacturing a thin film transistor array substrate, aiming to solve the problems of easy oxidation corrosion and high reflectivity of copper or copper metal lines in the prior art, and to improve the reliability and contrast of the display device.

[0007] In order to achieve the above object, the present invention provides a method for manufacturing a thin film transistor, which is applied to the above thin film transistor. The method for manufacturing the thin film transistor comprises the following steps:

[0008] Forming a pattern including a gate electrode on the base substrate, wherein the gate electrode includes a first gate protection layer and a gate electrode metal layer sequentially formed on the base substrate, wherein the gate electrode metal layer is made of copper or a copper alloy;

[0009] forming a pattern including a gate insulating layer covering the gate electrode and the base substrate on the substrate on which the gate electrode is formed;

[0010] Forming a pattern including an active layer located above the gate electrode and a pattern including an etching stopper layer located above the active layer on the substrate on which the gate insulating layer is formed;

[0011] Forming a pattern including a source / drain electrode on the substrate on which the etching stop layer is formed, wherein the source / drain electrode comprises a first source / drain protection layer and a source / drain electrode metal layer sequentially formed on the base substrate, wherein the source / drain electrode metal layer is made of copper or a copper alloy;

[0012] forming a pattern including a passivation layer on the substrate on which the source / drain electrode pattern is formed;

[0013] A pattern including a pixel electrode is formed on the substrate on which the passivation layer pattern is formed.

[0014] In one embodiment, after depositing the gate electrode metal layer, the second gate protection layer is then deposited, and after the deposition is completed, they are patterned together to obtain a gate electrode pattern;

[0015] The substrate formed with the gate electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40°C. The reaction is carried out for 0.5-2 minutes to form a third gate protection layer (blackening layer) on the exposed gate electrode cross section, and the blackening layer is metal palladium.

[0016] In one embodiment, a substrate having a metal palladium layer forming a third gate protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 40° C. for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as the third gate protection layer (blackening layer).

[0017] In one embodiment, after depositing the source / drain electrode metal layer, a second source / drain electrode protection layer is then deposited, and after the deposition is completed, they are patterned together to obtain a source / drain electrode pattern;

[0018] The substrate formed with the source / drain electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40°C. The reaction is carried out for 0.5-2 minutes to form a third source / drain electrode protection layer (blackening layer) on the exposed source / drain electrode cross section, and the blackening layer is metal palladium.

[0019] In one embodiment, a substrate having a metal palladium layer forming a third source / drain electrode protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 40° C. for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as a third source / drain electrode protection layer (blackening layer).

[0020] In one embodiment, after depositing the gate electrode metal layer, the gate electrode pattern is obtained by patterning;

[0021] The substrate formed with the gate electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40°C. The reaction is carried out for 0.5-2 minutes to form a third gate protection layer (blackening layer) on the exposed gate electrode surface and cross-section, and the blackening layer is metal palladium.

[0022] In one embodiment, a substrate having a metal palladium layer forming a third gate protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 60° C. for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as the third gate protection layer (blackening layer).

[0023] In one embodiment, after depositing the source / drain electrode metal layer, the gate electrode pattern is patterned;

[0024] The substrate formed with the source / drain electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40°C. The reaction is carried out for 0.5-2 minutes to form a third source / drain electrode protection layer (blackening layer) on the exposed source / drain electrode surface and cross-section, and the blackening layer is metal palladium.

[0025] In one embodiment, a substrate having a metal palladium layer forming a third source / drain electrode protection layer (blackening layer) is immersed in an aqueous solution consisting of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25 to 60° C. for 0.5 to 2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as a third source / drain electrode protection layer (blackening layer).

[0026] In one embodiment, the thin film transistor is a bottom-gate thin film transistor or a top-gate thin film transistor.

[0027] In one embodiment, the material of the active layer is metal oxide semiconductor, crystalline silicon or amorphous silicon.

[0028] The present invention further provides a thin film transistor, comprising a gate electrode, an active layer and a source / drain electrode formed on a substrate, and a gate insulating layer located between the gate electrode and the active layer, wherein:

[0029] The gate electrode comprises a gate electrode metal layer and a first gate protection layer, wherein the first protection layer is located between the gate electrode metal layer and the substrate to isolate the substrate from the gate electrode metal layer;

[0030] The gate electrode metal layer is made of copper or copper alloy;

[0031] The source / drain electrode comprises a source / drain electrode metal layer and a first source / drain protection layer, wherein the first source / drain protection layer is located between the source / drain electrode metal layer and the active layer to isolate the source / drain electrode metal layer from the active layer;

[0032] The material of the source / drain electrode metal layer is copper or copper alloy;

[0033] The thin film transistor is obtained by the above-mentioned method for manufacturing the thin film transistor.

[0034] The gate electrode further includes a second gate protection layer, which is located on the side of the gate electrode metal layer away from the first protection layer; the gate electrode further includes a third gate protection layer (blackening layer), which is located on both sides of the cross section of the gate electrode metal layer between the first and second gate protection layers of the gate electrode metal layer;

[0035] The material of the third gate protection layer (blackened layer) is metal palladium;

[0036] Preferably, the third gate protection layer (blackening layer) is palladium and nickel.

[0037] In one embodiment, the source / drain electrode further includes a second source / drain protection layer, which is located on the side of the source / drain electrode metal layer away from the first source / drain protection layer; the source / drain electrode further includes a third source / drain protection layer (blackening layer), which is located on both sides of the cross section of the source / drain electrode metal layer between the first and second source / drain protection layers of the source / drain electrode metal layer;

[0038] The material of the third source / drain protection layer (blackened layer) is metal palladium;

[0039] Preferably, the third source / drain protection layer (blackened layer) is palladium and nickel.

[0040] In one embodiment, the gate electrode further includes a third gate protection layer (blackening layer) located on a side of the gate electrode metal layer away from the first protection layer and on both sides of a cross section of the gate electrode metal layer;

[0041] The material of the third gate protection layer (blackened layer) is metal palladium;

[0042] Preferably, the third gate protection layer (blackening layer) is palladium and nickel.

[0043] In one embodiment, the source / drain electrode further includes a third source / drain protection layer (blackened layer), which is located on a side of the source / drain electrode metal layer away from the first source / drain protection layer and on both sides of a cross section of the source / drain electrode metal layer;

[0044] The material of the third source / drain protection layer (blackened layer) is metal palladium;

[0045] Preferably, the third source / drain protection layer (blackened layer) is palladium and nickel.

[0046] The present invention further provides an array substrate, which includes the above-mentioned thin film transistor.

[0047] The present invention further provides a display device, which includes the above-mentioned array substrate.

[0048] The technical solution of the present invention adds a blackening process after the etching of the copper or copper alloy metal circuit serving as the gate or source / drain is completed, and the exposed copper or copper alloy circuit cross section or the cross section and surface are blackened to form an oxidation-resistant metal protective layer, which effectively prevents further oxidation corrosion of the copper or copper alloy circuit in subsequent processes or during use, and reduces the emissivity of the copper or copper alloy circuit to light, thereby improving the reliability and contrast of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic structural diagram of an array substrate of a thin film transistor of the present invention;

[0050] Figure 2 It is an enlarged structural diagram of the gate electrode of the thin film transistor of the present invention;

[0051] Figure 3 It is an enlarged structural diagram of the source / drain electrodes of the thin film transistor of the present invention;

[0052] Figure 4 A schematic diagram of the manufacturing process of an array substrate of an existing thin film transistor;

[0053] Figure 5 A schematic diagram of a process flow of a method for manufacturing a thin film transistor according to an embodiment of the present invention;

[0054] Figure 6An enlarged structural diagram of a gate electrode of an embodiment of a thin film transistor of the present invention;

[0055] Figure 7 An enlarged structural diagram of source / drain electrodes of an embodiment of a thin film transistor of the present invention;

[0056] Figure 8 It is an enlarged structural diagram of the gate electrode of the thin film transistor of the present invention;

[0057] Fig. 9 It is an enlarged structural diagram of the source / drain electrodes of the thin film transistor of the present invention;

[0058] Fig.10 A schematic diagram of a process of another embodiment of a method for manufacturing a thin film transistor of the present invention;

[0059] In the figure: 1-substrate, 2-gate electrode, 3-gate insulating layer, 4-active layer, 5-etching barrier layer, 6-source / drain electrode, 7-passivation layer, 8-pixel electrode, 21-first gate protection layer, 22-second gate protection layer, 20-gate electrode metal layer, 23-third gate protection layer (blackening layer), 61-first source / drain electrode protection layer, 60-source / drain electrode metal layer, 62-second source / drain electrode protection layer, 63-third source / drain electrode protection layer (blackening layer). DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0063] In the description of the present invention, it should be understood that the terms "upper", "lower", "inside", "outside", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use, or are directions or positional relationships commonly understood by those skilled in the art. These directions or positional relationships are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0064] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.

[0065] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms such as "setting" and "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0066] like Figure 1-10 As shown, the present application proposes a method for manufacturing a thin film transistor, comprising the following steps:

[0067] Step P1: Substrate processing.

[0068] Take a substrate (substrate), which can be a glass substrate 1 or a resin material substrate, and clean, dry and / or plasma treat it to ensure the cleanliness of the substrate. In order to increase the adhesion of the subsequent film layer to the substrate, an inorganic thin film such as silicon nitride or silicon oxide can be deposited on the substrate 1, or other inorganic insulating materials with the same or similar properties as silicon nitride or silicon oxide can be deposited, with a thickness of 10nm-300nm.

[0069] Step P2: Fabrication of gate electrode 2. This step includes five sub-steps P21 to P25.

[0070] P21: On the cleaned substrate, a first gate protection layer 21 is deposited. The protection layer is metal, and the main material used can be an alloy material formed by three metals: Mo, Al, and Nb. Among them, Al can be replaced by elements such as W, Zr, V, Ta, Ni, Cr, Co, Pd, Pt, Hf, Rh, Mn, Ti, and Si, and Nb can be replaced by elements such as W, Zr, V, Ta, Ni, Cr, Co, Pd, Pt, Hf, Rh, Mn, Ti, and Si. The thickness is 10~100nm, preferably 30~70nm. The first gate protection layer can improve the adhesion between the gate metal layer 20 and the substrate 1, and at the same time protect the gate metal layer 20 from oxidation corrosion by water and oxygen that penetrate the substrate.

[0071] P22: depositing a gate metal layer 20, the material of the layer is copper or copper alloy, and the thickness is 100-700 nm, preferably 300-500 nm.

[0072] P23: Depositing a second gate protection layer 22, which is a metal layer, and the material used is the same as the gate protection layer 21. The thickness is 20-100 nm, preferably 40-80 nm. The protection layer separates the gate metal layer 20 from the active layer 3, and can also prevent the copper ions of the gate metal layer 20 from migrating into the active layer 3 while protecting the gate metal layer 20 from oxidation corrosion.

[0073] P24: The substrate 1 on which the gate metal layer 20 and the first and second protective layers 21 and 22 are deposited is patterned, that is, a series of processes such as coating, exposure, development and stripping are adopted to form the desired gate 2 pattern.

[0074] P25: Blackening protection of the interface of the gate metal layer 20.

[0075] In the previous steps P21 to P24, although the upper and lower surfaces of the gate electrode layer 20 are protected, after patterning in step P24, the interface copper of the gate electrode layer 20 will be exposed. In the subsequent process or use, oxidation corrosion or copper ion migration is likely to occur here. In this step, a blackening step is added to deposit a metal layer on this cross section for protection.

[0076] Take 0.001mol / L palladium catalyst aqueous solution, 0.01g / L diethylenetetramine, and 1g / L sulfuric acid, adjust the pH value of the solution to 2, and heat it to 25°C to prepare a blackening solution; take a substrate including a gate 2 pattern and place it in the blackening solution for about 0.5~2min, plate a third metal layer on the cross section of the gate metal layer 20, and blacken it to form a blackening layer with a thickness of 5~100nm, preferably 30~60nm, wherein the palladium catalyst is palladium oxide or palladium chloride. Prepare a gate 2 pattern with a third gate protection layer (blackening layer) 23 on the cross section of the gate metal layer 20. The chemical reaction of this step is: Cu + Pd2+ → Cu2+ + Pd.

[0077] Preferably, in order to further enhance the performance of this third gate protection layer (blackening layer) 23, continue to mix 70g / L nickel sulfate and 0.1g / L sodium dihydrogen hypophosphite solution, adjust the pH value to 4 with boric acid, and heat to 45°C to obtain a second blackening solution. Take the substrate on which the third protection layer (blackening layer) 23 has been deposited and intrude it into the second blackening solution for 0.5~2min, deposit a nickel metal layer on the third metal layer (blackening layer) 23, and form a third gate protection layer (blackening layer) 23 containing palladium and nickel, and its thickness is 5~100nm, preferably 30~60nm. The chemical reaction of this step is: Ni2+ + H2PO2-+ H2O → H2PO3- +2H+ + Ni.

[0078] Step P3: forming a pattern of the gate insulating layer 3 on the substrate 1 on which the gate electrode 2 is formed.

[0079] P31: Depositing an insulating layer 3 thin film, wherein the insulating layer 3 is made of silicon nitride, silicon oxide, or other inorganic insulating materials having the same or similar properties as silicon nitride and silicon oxide.

[0080] P32: The insulating layer 3 is patterned by a yellow light process.

[0081] Step P4: forming a pattern including an active layer 4 located above the gate electrode 2 on the substrate 1 with the gate insulating layer 3 formed thereon.

[0082] P41: depositing an active layer 4 thin film, wherein the active layer 4 is made of metal oxide semiconductor, crystalline silicon or amorphous silicon.

[0083] P42: The active layer 4 pattern is formed by yellow light process.

[0084] Step P5: forming a pattern of an etching stop layer 5 on the substrate 1 on which the active layer 4 is formed.

[0085] P51: Depositing an etching stop layer 5 thin film, wherein the etching stop layer 5 is made of silicon nitride, silicon oxide, or other inorganic insulating materials having the same or similar properties as silicon nitride and silicon oxide.

[0086] P52: The pattern of the etching stop layer 5 is formed by a yellow light process. The etching stop layer 5 is used to prevent the active layer from being etched when the data line layer forms a channel.

[0087] Step P6: forming a pattern including source / drain electrodes 6 on the substrate 1 on which the etching stop layer 5 is formed.

[0088] P61: On the substrate 1 including the etching stop layer 5, a first source / drain electrode protection layer 61 is deposited. The protection layer is metal, and the main material used can be an alloy material formed by three metals: Mo, Al, and Nb, wherein Al can be replaced by elements such as W, Zr, V, Ta, Ni, Cr, Co, Pd, Pt, Hf, Rh, Mn, Ti, and Si, and Nb can be replaced by elements such as W, Zr, V, Ta, Ni, Cr, Co, Pd, Pt, Hf, Rh, Mn, Ti, and Si. The thickness is 10 to 100 nm, preferably 30 to 70 nm. The first source / drain electrode protection layer 61 separates the source / drain electrode metal layer 60 from the active layer 3, and can also prevent the copper ions of the gate metal layer 60 from migrating into the active layer 3 while protecting the source / drain electrode metal layer 60 from oxidation corrosion.

[0089] P62: depositing a source / drain electrode metal layer 60, the material of the layer is copper or copper alloy, and the thickness is 200-800 nm, preferably 300-600 nm.

[0090] P63: Deposit a second source / drain electrode protection layer 62. The protection layer is metal and is made of the same material as the first source / drain electrode protection layer 61. The thickness is 20-100 nm, preferably 40-80 nm. The protection layer can protect the source / drain electrode metal layer 60 from being oxidized and corroded by water and oxygen that penetrate the substrate.

[0091] P64: The substrate 1 on which the source / drain electrode metal layer 60 and the first and second protective layers 61, 62 are deposited is patterned, that is, a series of processes such as coating, exposure, development and stripping are adopted to form the required source / drain electrode 6 pattern.

[0092] P65: Blackening protection of the gate metal layer 60 interface.

[0093] In the previous steps P61 to P64, although the upper and lower surfaces of the gate electrode layer 60 are protected, after patterning in step P64, the interface copper of the source / drain electrode layer 60 will be exposed. In the subsequent process or use, oxidation corrosion or copper ion migration is likely to occur here. In this step, a blackening step is added to deposit a metal layer on this cross-section for protection.

[0094] Take 0.001mol / L palladium catalyst aqueous solution, 0.01g / L diethylenetetramine, and 1g / L sulfuric acid, adjust the pH value of the solution to 2, and heat it to 25°C to prepare a blackening solution; take a substrate including a source / drain electrode 6 pattern and place it in the blackening solution for about 0.5~2min, plate a third metal layer on the cross section of the source / drain electrode metal layer 60, and blacken it to form a blackening layer with a thickness of 5~100nm, preferably 30~60nm, wherein the palladium catalyst is palladium oxide or palladium chloride. Prepare a source / drain electrode 6 pattern with a third source / drain electrode protective layer (blackening layer) 63 on the cross section of the source / drain electrode metal layer 60. The chemical reaction of this step is: Cu + Pd2+ →Cu2+ + Pd.

[0095] Preferably, in order to further enhance the performance of the third source / drain electrode protection layer (blackening layer) 63, continue to mix 70g / L nickel sulfate and 0.1g / L sodium dihydrogen hypophosphite solution, adjust the pH value to 4 with boric acid, and heat to 45°C to obtain a second blackening solution. Take the substrate on which the third protection layer (blackening layer) 63 has been deposited and intrude it into the second blackening solution for 0.5~2min, deposit a nickel metal layer on the third metal layer (blackening layer) 63, and form a third source / drain electrode protection layer (blackening layer) 63 containing palladium and nickel, with a thickness of 5~100nm, preferably 30~60nm. The chemical reaction of this step is: Ni2+ + H2PO2-+ H2O →H2PO3- + 2H+ + Ni.

[0096] Step P7: forming a pattern including a passivation layer 7 on the substrate 1 on which the source / drain electrodes 6 are formed.

[0097] P71: Deposit a passivation layer 7 thin film. The passivation layer material can be a thin film formed of silicon oxide, silicon nitride, or other inorganic insulating materials with the same or similar material properties as the above-mentioned materials. The optimization of the passivation layer can also be achieved by combining inorganic and organic insulating layer materials. Organic materials are usually resin-based materials or acrylic-based materials.

[0098] P72: Through the yellow light process and patterning process and making vias, the passivation layer 7 pattern is formed.

[0099] Step P8: forming a pattern including a pixel electrode 8 on the substrate 1 including the passivation layer 7 .

[0100] P81: Deposit pixel electrode 8 thin film. The pixel electrode layer usually uses transparent and conductive metal oxide or metal film materials such as ITO and IZO.

[0101] P82: A pixel electrode 8 pattern is formed by a yellow light process and a graphic process.

[0102] In the embodiment of the present application, the deposition process includes chemical vapor deposition (CVD) and / or physical sputtering deposition (PVD). Usually, the metal or metal oxide film layer is deposited by PVD process, and the inorganic film layer is deposited by CVD process. The graphical or patterned composition process usually includes cleaning, film formation, coating, exposure, development, dry or wet etching, photoresist stripping and other processes. In the embodiment of the present application, since the blackening process is added in the process of making the gate electrode 2 and the source / drain electrode 6, the exposed cross-section of the external gate metal layer 20 and the source / drain electrode metal layer is protected, which can prevent copper or copper alloy from contacting with external water and oxygen or the migration of copper ions, thereby reducing the oxidation corrosion of copper or copper alloy, while reducing the reflection of the gate and source / drain electrode lines, and improving the reliability and contrast of the product.

[0103] Another embodiment of the present application provides a method for manufacturing a thin film transistor. The manufacturing method includes the following steps: Figure 8 As shown, compared with the method for manufacturing a thin film transistor in the fourth embodiment, in the process of manufacturing the gate 2 in step P2, the second gate protection layer 22 is not deposited, and the gate 2 pattern is formed by patterning after the first gate protection layer 21 and the gate metal layer 20 are deposited, and then a blackening process is performed in step P24. The specific operation method is the same as step P25 in the fourth embodiment, and a cross section of the gate metal layer 20 and the other surface away from the first gate protection layer 21 are formed as shown in FIG. Fig. 9 The third gate protection layer (blackened layer) 23 is formed. Preferably, the formed third gate protection layer (blackened layer) 23 includes palladium and nickel metal layers.

[0104] In the process of manufacturing the source / drain electrode 6 in step P6, the second source / drain electrode protection layer 62 is not deposited. After the first source / drain electrode protection layer 61 and the source / drain electrode metal layer 60 are deposited, the source / drain electrode 6 pattern is formed by patterning. Then, a blackening process is performed in step P64. The specific operation is the same as step P65 in the fourth embodiment. The cross section of the source / drain electrode metal layer 60 and the other surface relative to the first source / drain electrode protection layer 61 are formed as follows: Fig.10 The third source / drain electrode protection layer (blackened layer) 63 is formed. Preferably, the formed third source / drain electrode protection layer (blackened layer) 63 includes palladium and nickel metal layers.

[0105] In one embodiment, the thin film transistor is a bottom-gate thin film transistor or a top-gate thin film transistor.

[0106] In one embodiment, the material of the active layer is metal oxide semiconductor, crystalline silicon or amorphous silicon.

[0107] The manufacturing method of the thin film transistor of the present invention solves the problem of easy oxidation corrosion of copper or copper alloy metal circuits in the prior art, and improves the contrast and reliability of the display device. The present application adds a blackening process after the etching of the copper or copper alloy metal circuit as the gate or source / drain is completed, and the exposed copper or copper alloy circuit cross section or cross section and surface are blackened to form an oxidation-resistant metal protective layer, which effectively prevents further oxidation corrosion of the copper or copper alloy circuit in subsequent processes or during use, and reduces the emissivity of the copper or copper alloy circuit to light, thereby improving the reliability and contrast of the display device.

[0108] Figure 5 Schematic diagram of the structure of an array substrate including a thin film transistor of the present application. The array substrate provided by the present application includes a plurality of thin film transistors arranged in an array. Figure 5 The thin film transistor in the array substrate is a bottom-gate type. The present application is also applicable to a top-gate thin film transistor. The thin film transistor of the present application includes a gate electrode 2, an active layer 4 and a source / drain electrode 6, a gate insulating layer 3 located between the gate electrode 2 and the active layer 4, an etching barrier layer 5 located on the active layer, a passivation layer 7 located on the etching barrier layer 5, the source / drain electrode 6 and the gate insulating layer 3, and a pixel electrode 8 located on the passivation layer 7 and connected to the source / drain.

[0109] like Figure 2-3 As shown, the gate electrode 2 of the existing thin film transistor includes a gate electrode metal layer 20, a first gate protection layer 21 and a second gate electrode protection layer 22, wherein the gate electrode metal layer 20 is copper or a copper alloy. The first gate protection layer 21 and the second gate electrode protection layer 22 protect the gate electrode metal layer 20 to prevent it from oxidative corrosion or contact with the active layer causing copper ions to migrate to the active layer. The source / drain electrode 6 includes a source / drain electrode metal layer 60, a first source / drain protection layer 61 and a second source / drain protection layer 62, wherein the source / drain electrode metal layer 60 is copper or a copper alloy. The first source / drain protection layer 61 and the second source / drain protection layer 62 protect the source / drain electrode metal layer 60 to prevent it from oxidative corrosion or contact with the active layer causing copper ions to migrate to the active layer.

[0110] Its production method is as follows Figure 4 As shown, the process is performed in sequence: P1 substrate (substrate) 1 processing, P2 gate electrode 2 manufacturing, P3 gate insulation layer 3 manufacturing, P4 active layer 4 manufacturing, P5 etching barrier layer 5 manufacturing, P6 source / drain 6 manufacturing, P7 passivation layer 7 manufacturing, and P8 pixel electrode 8 manufacturing. The manufacturing of P2 gate electrode 2 and P6 source / drain 6 also includes the deposition and patterning of first protective layer 21, 61, gate metal layer 20, source / drain metal layer 60 and second protective layer 22, 62.

[0111] Although the first and second protective layers protect the upper and lower surfaces of the gate electrode 2 and the source / drain electrode 6, their cross sections are still exposed. In the subsequent manufacturing process and use, copper oxidation corrosion or copper ion migration on the cross section surface may still easily cause instability of the thin film transistor, thereby causing poor reliability of the array substrate or the display device using the array substrate. At the same time, the existing protective layer has a high metal reflectivity, which makes the display device uncontrollable in real light, resulting in poor display contrast.

[0112] like Figure 6-7 As shown, the present application also proposes a thin film transistor, which includes a gate electrode 2, an active layer 4 and a source / drain electrode 6 made on a substrate 1, and a gate insulating layer 3 located between the gate electrode and the active layer, wherein the gate electrode 2 includes a gate electrode metal layer 20 and a first gate protection layer 21, the first protection layer 21 is located between the gate electrode metal layer 20 and the substrate 3, and isolates the gate electrode metal layer 2 from the substrate 1; the gate electrode metal layer 20 is made of copper or copper alloy; the source / drain electrode 6 includes a source / drain electrode metal layer 60 and a first source / drain protection layer 61, the first source / drain protection layer 61 is located between the source / drain electrode metal layer 60 and the active layer 4, and isolates the source / drain electrode metal layer 60 from the active layer 4; the source / drain electrode metal layer 60 is made of copper or copper alloy.

[0113] In this embodiment, the gate electrode 2 also includes a second gate protection layer 22, which is located on the side of the gate electrode metal layer 20 away from the first protection layer; the gate electrode 2 also includes a third gate protection layer (blackening layer) 23, which is located on both sides of the cross section of the gate electrode metal layer 20 between the first and second gate protection layers 21 and 22 of the gate electrode metal layer; the material of the third gate protection layer (blackening layer) 23 is metal palladium.

[0114] Preferably, the third gate protection layer (blackened layer) 23 is palladium and nickel.

[0115] In this embodiment, the source / drain electrode 6 also includes a second source / drain protection layer 62, which is located on the side of the source / drain electrode metal layer 60 away from the first source / drain protection layer 61; the source / drain electrode 6 also includes a third source / drain protection layer (blackening layer) 63, which is located on both sides of the cross section of the source / drain electrode metal layer between the first and second source / drain protection layers 61, 62 of the source / drain electrode metal layer; the material of the third source / drain protection layer (blackening layer) 63 is metal palladium.

[0116] Preferably, the third source / drain protection layer (blackened layer) 63 is palladium and nickel.

[0117] like Figure 9-10As shown, the second embodiment of the present application takes a thin film transistor as an example, a thin film transistor, the thin film transistor comprising a gate electrode 2, an active layer 4 and a source / drain electrode 6 made on a substrate 1, and a gate insulating layer 3 located between the gate electrode and the active layer, wherein the gate electrode 2 comprises a gate electrode metal layer 20 and a first gate protection layer 21, the first protection layer 21 is located between the gate electrode metal layer 20 and the substrate 3, and isolates the gate electrode metal layer 2 from the substrate 1; the gate electrode metal layer 20 is made of copper or copper alloy; the source / drain electrode 6 comprises a source / drain electrode metal layer 60 and a first source / drain protection layer 61, the first source / drain protection layer 61 is located between the source / drain electrode metal layer 60 and the active layer 4, and isolates the source / drain electrode metal layer 60 from the active layer 4; the source / drain electrode metal layer 60 is made of copper or copper alloy.

[0118] In this embodiment, the gate electrode 2 further includes a third gate protection layer (blackening layer) 23, which is located on the side of the gate electrode metal layer 20 away from the first protection layer 21 and on both sides of the cross section of the gate electrode metal layer 20; the material of the third gate protection layer (blackening layer) is metal palladium.

[0119] Preferably, the third gate protection layer (blackened layer) 63 is palladium and nickel.

[0120] In this embodiment, the source / drain electrode 6 also includes a third source / drain protection layer (blackening layer) 63, which is located on the side of the source / drain electrode metal layer 60 away from the first source / drain protection layer 61 and on both sides of the cross section of the source / drain electrode metal layer 60; the material of the third source / drain protection layer (blackening layer) 63 is metal palladium.

[0121] Preferably, the third source / drain protection layer (blackened layer) 63 is palladium and nickel.

[0122] The present application also proposes an array substrate, including the above-mentioned thin film transistor; the specific structure of the thin film transistor refers to the above-mentioned embodiment. Since the array substrate adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0123] The present application also provides a display device, comprising the above-mentioned array substrate.

[0124] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a thin film transistor, characterized in that: The method for manufacturing the thin film transistor comprises the following steps: Forming a pattern including a gate electrode on the base substrate, wherein the gate electrode includes a first gate protection layer and a gate electrode metal layer sequentially formed on the base substrate; forming a pattern including a gate insulating layer covering the gate electrode and the base substrate on the substrate on which the gate electrode is formed; Forming a pattern including an active layer located above the gate electrode and a pattern including an etching stopper layer located above the active layer on the substrate on which the gate insulating layer is formed; Forming a pattern including source / drain electrodes on the substrate on which the etching stop layer is formed, wherein the source / drain electrodes include a first source / drain protection layer and a source / drain electrode metal layer sequentially formed on the base substrate; forming a pattern including a passivation layer on the substrate on which the source / drain electrode pattern is formed; A pattern including a pixel electrode is formed on the substrate on which the passivation layer pattern is formed.

2. The method for manufacturing a thin film transistor according to claim 1, wherein: After depositing the gate electrode metal layer, a second gate protection layer is deposited, and after the deposition is completed, they are patterned together to obtain a gate electrode pattern; The substrate formed with the gate electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40° C., and reacts for 0.5-2 minutes to form a third gate protection layer (blackening layer) on the exposed gate electrode cross section; The substrate of the metal palladium layer forming the third gate protection layer (blackening layer) is immersed in an aqueous solution composed of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25-40°C for 0.5-2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as the third gate protection layer (blackening layer).

3. The method for manufacturing a thin film transistor according to claim 1, wherein: After depositing the source / drain electrode metal layer, a second source / drain electrode protection layer is then deposited, and after the deposition is completed, they are patterned together to obtain a source / drain electrode pattern; The substrate formed with the source / drain electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40° C., and the reaction is carried out for 0.5-2 minutes to form a third source / drain electrode protection layer (blackening layer) on the exposed source / drain electrode cross section; The substrate of the metal palladium layer forming the third source / drain electrode protection layer (blackening layer) is immersed in an aqueous solution composed of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25~40°C for 0.5~2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as the third source / drain electrode protection layer (blackening layer).

4. The method for manufacturing a thin film transistor according to claim 1, wherein: After depositing the gate electrode metal layer, patterning is performed to obtain a gate electrode pattern; The substrate including the gate electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40° C., and reacts for 0.5-2 minutes to form a third gate protection layer (blackening layer) on the exposed gate electrode surface and cross section; The substrate of the metal palladium layer forming the third gate protection layer (blackening layer) is immersed in an aqueous solution composed of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25-60°C for 0.5-2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as the third gate protection layer (blackening layer).

5. The method for manufacturing a thin film transistor according to claim 1, wherein: After depositing the source / drain electrode metal layer, the gate electrode pattern is obtained by patterning; The substrate formed with the source / drain electrode pattern is immersed in a blackening solution in which a palladium catalyst aqueous solution is mixed with diethylenetetramine and sulfuric acid, the pH value is 2-3, and the temperature is 25-40° C., and reacts for 0.5-2 minutes to form a third source / drain electrode protection layer (blackening layer) on the surface and cross section of the exposed source / drain electrode; The substrate of the metal palladium layer forming the third source / drain electrode protection layer (blackening layer) is immersed in an aqueous solution composed of nickel sulfate and sodium dihydrogen hypophosphite at a temperature of 25~60°C for 0.5~2 minutes to form a nickel metal protection layer on the surface of the palladium metal layer as the third source / drain electrode protection layer (blackening layer).

6. A thin film transistor, characterized in that: The thin film transistor comprises a gate electrode, an active layer and a source / drain electrode formed on a substrate, and a gate insulating layer located between the gate electrode and the active layer; The gate electrode comprises a gate electrode metal layer and a first gate protection layer, wherein the first protection layer is located between the gate electrode metal layer and the substrate to isolate the substrate from the gate electrode metal layer; The gate electrode metal layer is made of copper or copper alloy; The source / drain electrode comprises a source / drain electrode metal layer and a first source / drain protection layer, wherein the first source / drain protection layer is located between the source / drain electrode metal layer and the active layer to isolate the source / drain electrode metal layer from the active layer; The material of the source / drain electrode metal layer is copper or copper alloy; The thin film transistor is obtained by the method for manufacturing a thin film transistor according to any one of claims 1 to 5.

7. The thin film transistor according to claim 6, characterized in that: The gate electrode further includes a second gate protection layer, which is located on the side of the gate electrode metal layer away from the first protection layer; the gate electrode further includes a third gate protection layer (blackening layer), which is located on both sides of the gate electrode metal layer cross section between the first and second gate protection layers of the gate electrode metal layer; The material of the third gate protection layer (blackened layer) is metal palladium.

8. The thin film transistor according to claim 6, characterized in that: The source / drain electrode further includes a second source / drain protection layer, which is located on the side of the source / drain electrode metal layer away from the first source / drain protection layer; the source / drain electrode further includes a third source / drain protection layer (blackening layer), which is located on both sides of the cross section of the source / drain electrode metal layer between the first and second source / drain protection layers of the source / drain electrode metal layer; The material of the third source / drain protection layer (blackened layer) is metal palladium.

9. An array substrate, characterized in that: The array substrate comprises the thin film transistor as described in any one of claims 6 to 8.

10. A display device, characterized in that: The display device comprises the array substrate as claimed in claim 9.

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