Semiconductor structure, memory and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure, a memory and a manufacturing method thereof. The semiconductor structure comprises a substrate; the phase inverter is arranged on the substrate, the phase inverter comprises a pull-down transistor, the pull-down transistor comprises a first semiconductor layer extending along a first direction, the first direction is parallel to the top surface of the substrate, and the first semiconductor layer comprises a first channel region; the pull-up transistor comprises a second semiconductor layer extending in the first direction, the second semiconductor layer is arranged above the first semiconductor layer at intervals in the second direction perpendicular to the top surface of the substrate, and the second semiconductor layer comprises a second channel region; the common grid electrode is arranged on the substrate in the second direction, and the common grid electrode covers the first channel region and the second channel region; the conductive plug is arranged on one side of the common grid electrode in the first direction, one end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug, and the integration density of devices in the semiconductor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a memory and a manufacturing method thereof. Background Art

[0002] According to Moore's Law, the performance of integrated circuits will double as the number of semiconductor devices in an integrated circuit doubles. In order to improve the performance of integrated circuits, it is necessary to continuously reduce the feature size of semiconductor devices to increase the integration. However, there is a limit to the reduction of the feature size of semiconductor devices, and after the feature size of semiconductor devices is reduced to a certain extent, the impact of the reduction in feature size on improving the integration density of semiconductor devices is minimal.

[0003] In order to continue the effectiveness of Moore's Law, integrated circuits began to develop from planar structures to three-dimensional structures. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure, a memory and a manufacturing method thereof to address the problem that the integration density of semiconductor devices in the prior art is difficult to further improve.

[0005] In order to achieve the above objectives, in a first aspect, the present invention provides a semiconductor structure, comprising:

[0006] substrate;

[0007] An inverter is arranged on the substrate, and the inverter comprises:

[0008] A pull-down transistor, comprising a first semiconductor layer extending along a first direction, the first direction being parallel to a top surface of the substrate, the first semiconductor layer comprising a first channel region;

[0009] A pull-up transistor, comprising a second semiconductor layer extending along the first direction, the second semiconductor layer being spaced above the first semiconductor layer along a second direction perpendicular to the top surface of the substrate, the second semiconductor layer comprising a second channel region;

[0010] A common gate is arranged on the substrate along the second direction, and the common gate covers the first channel region and the second channel region;

[0011] A conductive plug is arranged on one side of the common gate along the first direction, the conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer, and an end of the first semiconductor layer and an end of the second semiconductor layer are connected through the conductive plug.

[0012] In one of the embodiments, along the first direction, the source of the pull-down transistor and the drain of the pull-down transistor are relatively arranged in the first semiconductor layer on both sides of the first channel region;

[0013] The source of the pull-up transistor and the drain of the pull-up transistor are arranged oppositely in the second semiconductor layer at two sides of the second channel region;

[0014] The source of the pull-down transistor and the source of the pull-up transistor are arranged on the same side, and the drain of the pull-down transistor and the drain of the pull-up transistor are arranged on the same side.

[0015] In one of the embodiments, the conductive plug is disposed on the first semiconductor layer, and the drain of the pull-down transistor and the drain of the pull-up transistor are connected through the conductive plug.

[0016] In one embodiment, along the first direction, two ends of the second semiconductor layer are retracted relative to the first semiconductor layer.

[0017] In one embodiment, the pull-down transistor is a dual-gate transistor and / or the pull-up transistor is a dual-gate transistor.

[0018] In one embodiment, the pull-down transistor is a dual-gate transistor, and the first semiconductor layer includes a bottom first semiconductor layer and a top first semiconductor layer spaced apart along the second direction.

[0019] In one embodiment, the conductivity type of the first semiconductor layer is opposite to the conductivity type of the second semiconductor layer.

[0020] In a second aspect, the present invention provides a memory, comprising a substrate and at least one static random access memory unit arranged on the substrate, each of the static random access memory units comprising a first inverter and a second inverter, the first inverter, the second inverter and the inverter in the semiconductor structure described in any one of claims 1 to 7 having the same structure, the input end of the first inverter is connected to the output end of the second inverter, and the output end of the first inverter is connected to the input end of the second inverter;

[0021] Each of the static random access memory cells further comprises:

[0022] A first transmission transistor is disposed above the first inverter, and the first transmission transistor is connected to an input terminal of the first inverter or an output terminal of the first inverter;

[0023] The second transmission transistor is arranged above the second inverter, and the second transmission transistor is connected to the output terminal of the second inverter or the input terminal of the second inverter.

[0024] In one embodiment, the first inverter includes a first pull-down transistor, a first pull-up transistor, a first conductive plug, and a first common gate, the first pull-down transistor and the first pull-up transistor share the first common gate, and the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected through the first conductive plug;

[0025] The second inverter includes a second pull-down transistor, a second pull-up transistor, a second conductive plug and a second common gate. The second pull-down transistor and the second pull-up transistor share the second common gate. The drain of the second pull-down transistor and the drain of the second pull-up transistor are connected through the second conductive plug. The second common gate is connected to the first conductive plug, and the second conductive plug is connected to the first common gate.

[0026] In one embodiment, the memory further comprises:

[0027] A power supply terminal, a source of the first pull-up transistor, a source of the second pull-up transistor and the power supply terminal are connected;

[0028] A ground terminal, a source of the first pull-down transistor, a source of the second pull-down transistor and the ground terminal are connected.

[0029] In one embodiment, the first transfer transistor includes a drain, a channel region, and a source arranged in sequence in a direction away from the first inverter, and the first transfer transistor also includes a gate, the gate of the first transfer transistor surrounds and covers the circumference of the channel region of the first transfer transistor, and the drain of the first transfer transistor is connected to the first inverter;

[0030] The second transfer transistor includes a drain, a channel region and a source which are sequentially arranged in a direction away from the second inverter. The second transfer transistor also includes a gate. The gate of the second transfer transistor surrounds and covers the circumference of the channel region of the second transfer transistor. The drain of the second transfer transistor is connected to the second inverter.

[0031] In one embodiment, the memory further comprises:

[0032] a first bit line, the first bit line being connected to the source of the first transfer transistor;

[0033] a first word line, wherein the extending directions of the first word line and the first bit line intersect vertically, and the first word line is connected to the gate of the first transfer transistor;

[0034] a second bit line, the second bit line being connected to the source of the second transfer transistor;

[0035] A second word line, wherein the extending directions of the second word line and the second bit line intersect vertically, and the second word line is connected to the gate of the second transfer transistor.

[0036] In a third aspect, the present invention provides a method for manufacturing a memory, comprising the following steps:

[0037] Providing a composite substrate, the composite substrate comprising a stacked substrate base, at least one first semiconductor material layer and at least one second semiconductor material layer, wherein adjacent first semiconductor material layers and / or second semiconductor material layers are spaced apart, and the first semiconductor material layer and the second semiconductor material layer have opposite conductivity types;

[0038] Etching the composite substrate to form a plurality of fin-shaped portions, wherein the fin-shaped portions extend along a first direction, and the fin-shaped portions are arranged at intervals along a third direction, wherein the first direction and the third direction are parallel to the top surface of the substrate base, the first semiconductor material layer retained in the fin-shaped portion forms a first semiconductor layer, and the second semiconductor material layer retained in the fin-shaped portion forms a second semiconductor layer, and along a direction away from the substrate base, the lengths of at least one layer of the first semiconductor layer and at least one layer of the second semiconductor layer in the fin-shaped portion in the first direction decrease in sequence;

[0039] forming a common gate, the common gate extending on the substrate base along a second direction, the second direction being perpendicular to the top surface of the substrate base, the common gate covering the surface of the first semiconductor layer and the surface of the second semiconductor layer located in the middle region of the fin-shaped portion, to form a common-gate pull-down transistor and a pull-up transistor;

[0040] A conductive plug is formed, and the conductive plug is arranged on one side of the fin-shaped portion along the first direction. The conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer. One end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug. The pull-down transistor and the pull-up transistor are connected through the conductive plug to form an inverter.

[0041] In one embodiment, before forming the common gate, the method further includes the following steps:

[0042] forming a dummy gate, wherein the dummy gate extends along the third direction and covers the middle region of the fin-shaped portion arranged along the third direction;

[0043] Etching the fin-shaped portion exposed by the dummy gate to remove part of the fin-shaped portion, forming a gap between adjacent first semiconductor layers and / or second semiconductor layers along the second direction, and exposing surfaces of the first semiconductor layer and the second semiconductor layer outside the middle region;

[0044] An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the first semiconductor layer and the second semiconductor layer outside the middle region and fills a gap between the first semiconductor layer and / or the second semiconductor layer.

[0045] In one embodiment, forming a common gate includes:

[0046] removing the dummy gate to expose the fin-shaped portion in the middle region;

[0047] Etching and removing a portion of the fin-shaped portion in the middle region to expose surfaces of the first semiconductor layer and the second semiconductor layer in the middle region;

[0048] forming a gate dielectric layer, wherein the gate dielectric layer covers surfaces of the first semiconductor layer and the second semiconductor layer in the middle region;

[0049] The common gate is formed, and the common gate covers the gate dielectric layer and fills the area between the first semiconductor layer and / or the second semiconductor layer in the middle area.

[0050] In one embodiment, forming a conductive plug includes:

[0051] forming a contact hole in the interlayer dielectric layer, wherein the contact hole exposes a portion of the surface of the first semiconductor layer and the second semiconductor layer located on one side of the middle region;

[0052] The conductive plug is formed in the contact hole.

[0053] In one embodiment, the method for manufacturing the memory further includes the following steps:

[0054] forming a word line, wherein the word line extends along the first direction and is correspondingly arranged above the inverter;

[0055] forming a transfer transistor, wherein the transfer transistor is disposed above the inverter, a gate of the transfer transistor is connected to the word line, and a drain of the transfer transistor is connected to the common gate of the inverter or the conductive plug;

[0056] forming a bit line, the bit line extending above the inverter along the second direction, the bit line being connected to a source of the transfer transistor;

[0057] Along the third direction, the two transfer transistors connected to the two adjacent inverters, the drain of one of the transfer transistors is connected to the common gate of one inverter, and the drain of the other of the transfer transistors is connected to the conductive plug of the other inverter.

[0058] In one embodiment, a composite substrate is provided, comprising:

[0059] Providing a first substrate and a second substrate, wherein the first substrate and the second substrate include a first semiconductor material, wherein the first substrate includes a first back substrate, a first buried oxide layer and a first top substrate which are arranged in sequence;

[0060] The second substrate is disposed on the first top substrate, and the second substrate is bonded and connected to the first top substrate;

[0061] Providing a third substrate, and epitaxially forming an epitaxial substrate layer on the third substrate, wherein the epitaxial substrate layer includes a second semiconductor material;

[0062] The epitaxial substrate layer is disposed on the second substrate, and the epitaxial substrate layer is bonded to the surface of the second substrate on a side away from the first substrate;

[0063] The third substrate is removed by etching, and the first substrate, the second substrate and the epitaxial substrate layer together form the composite substrate.

[0064] In one embodiment, epitaxially forming an epitaxial substrate layer on the third substrate includes:

[0065] Placing the third substrate in a reaction chamber, introducing a gas source of the first semiconductor material and a gas source of the second semiconductor material into the reaction chamber, epitaxially growing the epitaxial substrate layer on the top surface of the third substrate, and gradually reducing the content of the gas source of the first semiconductor material introduced into the reaction chamber and gradually increasing the content of the gas source of the second semiconductor material introduced into the reaction chamber during the epitaxial growth of the epitaxial substrate layer;

[0066] In the process of etching and removing the third substrate, a portion of the epitaxial substrate layer is etched and removed, and a portion of the structure on the top of the epitaxial substrate layer is retained to form the composite substrate.

[0067] In one embodiment, epitaxially forming an epitaxial substrate layer on the third substrate includes:

[0068] epitaxially forming at least one second semiconductor epitaxial layer on the top surface of the third substrate, wherein the concentration of the second semiconductor material in the at least one second semiconductor epitaxial layer increases in a direction away from the top surface of the third substrate;

[0069] epitaxially forming the epitaxial substrate layer on the top surface of at least one layer of the second semiconductor epitaxial layer;

[0070] In the process of etching and removing the third substrate, at least one layer of the second semiconductor epitaxial layer is etched and removed.

[0071] The semiconductor structure, memory and manufacturing method thereof of the present invention utilize a dimension perpendicular to the top surface of the substrate to stack pull-down transistors and pull-up transistors above the substrate to form an inverter, thereby improving the integration density of the transistors, reducing the occupied area of ​​the inverter, and increasing the applicable area of ​​the semiconductor structure, which is beneficial to improving the integration density of devices in the semiconductor structure and arranging more semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0073] Figure 1 FIG. 4 is a schematic diagram of the structure of an inverter provided in an embodiment.

[0074] Figure 2 for Figure 1 Cross-sectional view along line AA.

[0075] Figure 3 FIG. 4 is a schematic structural diagram of a first inverter and a second inverter provided in an embodiment.

[0076] Figure 4 Schematic diagram of the structure of an SRAM unit provided in one embodiment.

[0077] Figure 5 for Figure 4 Cross-sectional view along line BB.

[0078] Figure 6 FIG. 4 is a circuit diagram of an SRAM unit provided in an embodiment.

[0079] Figure 7 The present invention is a flowchart of a method for manufacturing a memory provided in an embodiment.

[0080] Figure 8FIG. 4 is a schematic structural diagram of a first substrate provided in an embodiment.

[0081] Fig. 9 FIG. 4 is a schematic structural diagram of a second substrate provided in an embodiment.

[0082] Fig.10 FIG. 1 is a schematic diagram of a structure after a first substrate and a second substrate are bonded together in one embodiment.

[0083] Fig.11 It is a schematic diagram of the structure after removing the second back substrate and the second buried oxide layer in one embodiment.

[0084] Fig.12 It is a schematic diagram of the structure after an epitaxial substrate layer is formed on a third substrate in one embodiment.

[0085] Fig.13 FIG. 4 is a schematic diagram of forming an epitaxial substrate layer on a third substrate in an embodiment.

[0086] Fig.14 FIG. 4 is a schematic diagram of forming an epitaxial substrate layer on a third substrate in an embodiment.

[0087] Fig.15 It is a schematic diagram of the structure after a fourth oxide layer is formed on the epitaxial substrate layer in one embodiment.

[0088] Fig.16 It is a schematic diagram of the structure after the epitaxial substrate layer and the second top substrate are bonded together in one embodiment.

[0089] Fig.17 FIG. 4 is a schematic diagram of the structure of a composite substrate provided in an embodiment.

[0090] Fig.18 It is a schematic diagram of the structure after etching away part of the composite substrate in one embodiment.

[0091] Fig.19 FIG. 4 is a schematic diagram of a stepped structure formed in an embodiment.

[0092] Fig. 20 FIG. 4 is a schematic diagram of a structure after a fourth dielectric layer is formed in an embodiment.

[0093] Fig.21 FIG. 1 is a schematic structural diagram from a viewing angle after a fin-shaped portion is formed in an embodiment.

[0094] Fig. 22 FIG. 1 is a schematic structural diagram from another perspective after a fin-shaped portion is formed in an embodiment.

[0095] Fig.23 FIG. 1 is a schematic structural diagram from another perspective after a fin-shaped portion is formed in an embodiment.

[0096] Fig.24 FIG. 1 is a schematic diagram of a structure after a dummy gate material layer is formed in an embodiment.

[0097] Fig.25 It is a structural schematic diagram of a viewing angle after forming a dummy gate in an embodiment.

[0098] Fig.26 FIG. 1 is a schematic structural diagram of another viewing angle after forming a dummy gate in an embodiment.

[0099] Fig. 27 FIG. 1 is a schematic structural diagram from another viewing angle after a dummy gate is formed in an embodiment.

[0100] Fig.28 for Fig. 27 Cross-section along line BB.

[0101] Fig.29 Schematic diagram of the structure after the first semiconductor layer and the second semiconductor layer outside the middle region of the fin-shaped portion are exposed in one embodiment.

[0102] Fig.30 It is a structural schematic diagram from a viewing angle after an interlayer dielectric layer is formed in one embodiment.

[0103] Fig.31 FIG. 1 is a schematic structural diagram from another perspective after an interlayer dielectric layer is formed in one embodiment.

[0104] Fig.32 FIG. 1 is a schematic diagram of a structure after removing the dummy gate in an embodiment.

[0105] Fig.33 for Fig.32 Cross-sectional view along line CC.

[0106] Fig.34 It is a schematic diagram of the structure after the first semiconductor layer and the second semiconductor layer in the middle area are exposed in one embodiment.

[0107] Fig.35 for Fig.34 Cross-sectional view along line DD.

[0108] Fig.36 FIG. 1 is a schematic diagram of a structure after a common gate is formed in an embodiment.

[0109] Fig.37 FIG. 1 is a schematic diagram of a structure after a conductive plug is formed in an embodiment.

[0110] Fig.38 FIG. 1 is a top view after a conductive plug is formed in one embodiment.

[0111] Fig.39FIG. 4 is a schematic diagram of a structure after a dielectric layer is formed in one embodiment.

[0112] Fig.40 FIG. 1 is a schematic diagram of a structure after a wiring layer is formed in an embodiment.

[0113] Fig.41 FIG. 1 is a top view after forming a wiring layer in one embodiment.

[0114] Fig.42 FIG. 1 is a schematic diagram of a structure after a third conductive material layer is formed in an embodiment.

[0115] Fig.43 FIG. 4 is a schematic diagram of a structure after word lines are formed in one embodiment.

[0116] Fig.44 FIG. 1 is a top view after bit lines are formed in one embodiment.

[0117] Fig.45 FIG. 4 is a schematic diagram of the structure of a transfer transistor formed in an embodiment.

[0118] Description of reference numerals:

[0119] NOT, inverter; T1, pull-down transistor; S1, source of pull-down transistor; D1, drain of pull-down transistor; T2, pull-up transistor; S2, source of pull-up transistor; D2, drain of pull-up transistor; C1, first channel region; C2, second channel region;

[0120] NOT1, first inverter; T11, first pull-down transistor; S11, source of first pull-down transistor; D11, drain of first pull-down transistor; T12, first pull-up transistor; S12, source of first pull-up transistor; D12, drain of first pull-up transistor; NOT2, second inverter; T21, second pull-down transistor; S21, source of second pull-down transistor; D21, drain of second pull-down transistor; T22, second pull-up transistor; S22, source of second pull-up transistor; D22, drain of second pull-up transistor; T3, transmission transistor; S3, source of transmission transistor; D3, drain of transmission transistor; C3, transmission transistor The channel region of the body tube; G3, the gate of the transfer transistor; T31, the first transfer transistor; S31, the source of the first transfer transistor; D31, the drain of the first transfer transistor; C31, the channel region of the first transfer transistor; G31, the gate of the first transfer transistor; T32, the second transfer transistor; S32, the source of the second transfer transistor; D32, the drain of the second transfer transistor; C32, the channel region of the second transfer transistor; G32, the gate of the second transfer transistor; BL, the bit line; BL1, the first bit line; BL2, the second bit line; WL, the word line; WL1, the first word line; WL2, the second word line; VDD, the power supply terminal; VSS, the ground terminal;

[0121] 10. substrate; 20. common gate; 30. conductive plug; 40. first semiconductor layer; 140. bottom first semiconductor layer; 240. top first semiconductor layer; 50. second semiconductor layer; 120. first common gate; 220. second common gate; 130. first conductive plug; 230. second conductive plug; 70. interconnect layer; 170. first interconnect; 270. second interconnect; 300. composite substrate; 310. substrate base; 320. first semiconductor material layer; 132. bottom first semiconductor material layer; 232. top first semiconductor material layer; 330. second semiconductor material layer; 350. fin-shaped portion; 171. first dielectric layer; 271. second dielectric layer; 371. third dielectric layer; 471. fourth dielectric layer; 571. fifth dielectric layer; 671. sixth dielectric layer; 771. seventh dielectric layer; 181. interlayer dielectric layer; 281, dielectric layer; 410, dummy gate material layer; 420, dummy gate; 40, third conductive material layer; 510, first trench; 520, second trench; 161, first wire; 261, second wire; 801, first oxide layer; 802, second oxide layer; 803, third oxide layer; 804, fourth oxide layer; 810, first substrate; 811, first back substrate; 812, first buried oxide layer; 813, first top Substrate; 820, second substrate; 821, second back substrate; 822, second buried oxide layer; 823, second top substrate; 830, third substrate; 831, third back substrate; 832, third buried oxide layer; 833, third top substrate; 840, germanium silicon layer; 850, epitaxial substrate layer; 860, germanium epitaxial layer; 870, second semiconductor epitaxial layer; 871, first second semiconductor epitaxial layer; 872, second second semiconductor epitaxial layer;

[0122] IM, middle area; E1, first end; E2, second end; D1, first direction; D2, second direction; D3, third direction. DETAILED DESCRIPTION

[0123] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0124] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0125] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0126] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0127] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0128] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0129] The exemplary embodiments of the present disclosure provide a semiconductor structure, referring to Figure 1 , Figure 2 As shown, the semiconductor structure includes a substrate 10 and an inverter NOT disposed on the substrate 10. The inverter NOT is disposed on the substrate 10, and the inverter NOT includes a pull-down transistor T1, a pull-up transistor T2, a common gate 20, and a conductive plug 30. The pull-down transistor T1 includes a first semiconductor layer 40 extending along a first direction D1, the first direction D1 is parallel to the top surface of the substrate 10, and the first semiconductor layer 40 includes a first channel region C1. The pull-up transistor T2 includes a second semiconductor layer 50 extending along the first direction D1, and the second semiconductor layer 50 is spaced above the first semiconductor layer 40 along a second direction D2 perpendicular to the top surface of the substrate 10, and the second semiconductor layer 50 includes a second channel region C1. The common gate 20 is arranged on the substrate 10 along the second direction D2, and the common gate 20 covers the first channel region 31 and the second channel region C2; the conductive plug 30 is arranged on one side of the common gate 20 along the first direction D1, and the conductive plug 30 covers a portion of the surface of the first semiconductor layer 30 and a portion of the surface of the second semiconductor layer 50, and one end of the first semiconductor layer 40 and one end of the second semiconductor layer 50 are connected through the conductive plug 30.

[0130] It should be noted that, refer to Figure 3 As shown, one or more inverters 20 may be disposed on the substrate 10. When multiple inverters 20 are disposed on the substrate 10, the multiple inverters 20 may be arranged in an array along a preset direction on the substrate 10, and the preset direction may be a first direction D1, or a third direction D3 perpendicular to the first direction D1, or other directions parallel to the top surface of the substrate 10. In specific applications, the number of inverters 20 may be set as required.

[0131] The semiconductor structure of the present embodiment utilizes a dimension perpendicular to the top surface of the substrate 10 to stack the pull-down transistor T1 and the pull-up transistor T2 above the substrate 10 to form an inverter NOT, thereby improving the integration density of the transistors, reducing the footprint of the inverter 20, and increasing the applicable area of ​​the semiconductor structure, which is beneficial to improving the integration density of devices in the semiconductor structure and arranging more semiconductor devices.

[0132] Reference Figure 1 , Figure 2 As shown, along the first direction D1, the source S1 of the pull-down transistor T1 and the drain D1 of the pull-down transistor T1 are relatively arranged in the first semiconductor layer 40 on both sides of the first channel region C1. The source S2 of the pull-up transistor T2 and the drain D2 of the pull-up transistor T2 are relatively arranged in the second semiconductor layer 50 on both sides of the second channel region C2. Among them, the source S1 of the pull-down transistor T1 and the source S2 of the pull-up transistor T2 are arranged on the same side, and the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 are arranged on the same side. The source S1 of the pull-down transistor T1 and the source S2 of the pull-up transistor T2 are connected through the conductive plug 30, or the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 are connected through the conductive plug 30.

[0133] In some embodiments, reference Figure 1 , Figure 2 As shown, the conductive plug 30 is disposed on the first semiconductor layer 40 , and the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 are connected through the conductive plug 30 .

[0134] In some embodiments, reference Figure 1 , Figure 2 As shown, along the first direction D1, the two ends of the second semiconductor layer 50 are retracted relative to the first semiconductor layer 40, and along the second direction D2, the two ends of the first semiconductor layer 40 and the second semiconductor layer 50 form steps. That is, the length of the second semiconductor layer 50 in the first direction D1 is less than the length of the first semiconductor layer 40 in the first direction D1, and the two ends of the first semiconductor layer 40 are equivalent to the second semiconductor layer 50 extending outward, so that the conductive plug 30 can be set on the end of the first semiconductor layer 10, and the conductive plug 30 covers the partial surface of the end of the first semiconductor layer 40 on the drain side of the inverter NOT and the partial surface of the end of the second semiconductor layer 50 on the drain side, so as to connect the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 together, further reducing the occupied area of ​​the inverter NOT, and further releasing the applicable area of ​​the semiconductor structure.

[0135] Similarly, wires may be provided at the ends of the first semiconductor layer 40 and the second semiconductor layer 50 on the source side of the inverter NOT, respectively, to lead out the source S1 of the pull-down transistor T1 and the source S2 of the pull-up transistor T2 and connect them to other structures or devices. For example, the source S1 of the pull-down transistor T1 may be led out to connect to the ground terminal VSS through a wire, and the source S2 of the pull-up transistor T2 may be led out to connect to the power supply terminal VDD through another wire, so as to facilitate the wiring of the semiconductor structure.

[0136] In some embodiments, reference Figure 1 , Figure 2 As shown, the pull-down transistor T1 is a dual-gate transistor and / or the pull-up transistor T2 is a dual-gate transistor.

[0137] In some embodiments, reference Figure 1 , Figure 2 As shown, the pull-down transistor T1 is a dual-gate transistor, and the first semiconductor layer 40 includes a bottom first semiconductor layer 140 and a top first semiconductor layer 240 which are spaced apart along the second direction D2.

[0138] In some embodiments, reference Figure 1 , Figure 2 As shown, the conductivity type of the first semiconductor layer 40 is opposite to the conductivity type of the second semiconductor layer 50. For example, the first semiconductor layer 40 has an N-type conductivity type, the pull-down transistor T1 is an NMOS transistor, the second semiconductor layer 50 has a P-type conductivity type, and the pull-up transistor T2 is a PMOS transistor. Alternatively, the first semiconductor layer 40 has a P-type conductivity type, the pull-down transistor T1 is a PMOS transistor, the second semiconductor layer 50 has an N-type conductivity type, and the pull-up transistor T2 is an NMOS transistor.

[0139] Exemplarily, the material of the first semiconductor layer 40 may include silicon, the material of the second semiconductor layer 50 may include germanium, the pull-down transistor T1 is a dual-gate NMOS transistor, and the pull-up transistor T2 is a PMOS transistor. The hole mobility of the germanium channel is 1.2 times the electron mobility of the silicon channel. In this example, the pull-down transistor T1 adopts a dual-gate structure to match the drive current of the pull-down transistor T1 and the pull-up transistor T2.

[0140] According to an exemplary embodiment, this embodiment provides a memory, referring to Figure 3 , Figure 4 , Figure 5 Combined with Fig.44As shown, the memory includes a substrate 10 and at least one static random access memory cell (SRAM cell) disposed on the substrate 10, each static random access memory cell includes a first inverter NOT1 and a second inverter NOT2, the first inverter NOT1, the second inverter NOT2 and the inverter NOT in the semiconductor structure of the above embodiment have the same structure, refer to Figure 6 As shown, the input end of the first inverter NOT1 is connected to the output end of the second inverter NOT1, and the output end of the first inverter NOT1 is connected to the input end of the second inverter NOT2. Figure 3 , Figure 4 , Figure 6 Each static random access memory cell further includes a first transmission transistor T31 and a second transmission transistor T32. The first transmission transistor T31 is arranged above the first inverter NOT1, and the first transmission transistor T31 is connected to the input end of the first inverter NOT1 or the output end of the first inverter NOT1; the second transmission transistor T32 is arranged above the second inverter NOT2, and the second transmission transistor T32 is connected to the output end of the second inverter NOT2 or the input end of the second inverter NOT2.

[0141] Reference Figure 3 , Figure 4 , Figure 5 As shown, the first inverter NOT1 includes a first pull-down transistor T11, a first pull-up transistor T12, a first conductive plug 130 and a first common gate 120. The first pull-down transistor T11 and the first pull-up transistor T12 share the first common gate 120. The first common gate 120 serves as an input terminal of the first inverter NOT1. The drain D11 of the first pull-down transistor T11 and the drain D12 of the first pull-up transistor T12 are connected through the first conductive plug 130 as an output terminal of the first inverter NOT1.

[0142] Reference Figure 3 , Figure 4 As shown, the second inverter NOT2 includes a second pull-down transistor T21, a second pull-up transistor T22, a second conductive plug 230 and a second common gate 220. The second pull-down transistor T21 and the second pull-up transistor T22 share the second common gate 220. The second common gate 220 serves as the input terminal of the second inverter NOT2. The drain D21 of the second pull-down transistor T21 and the drain D22 of the second pull-up transistor T22 are connected through the second conductive plug 230, serving as the output terminal of the second inverter NOT2. The second common gate 220 of the second inverter NOT2 is connected to the first conductive plug 130 of the first inverter NOT1, and the second conductive plug 230 of the second inverter NOT2 is connected to the first common gate 120 of the first inverter NOT1.

[0143] In some embodiments, reference Figure 4 Combined with Fig.44 As shown, the memory also includes an interconnection line layer 70, which includes at least a first interconnection line 170 and a second interconnection line 270. The second common gate 220 of the second inverter NOT2 and the first conductive plug 130 of the first inverter NOT1 are connected via the first interconnection line 170, and the second conductive plug 230 of the second inverter NOT2 and the first common gate 120 of the first inverter NOT1 are connected via the second interconnection line 270.

[0144] Reference Figure 3 , Figure 4 , Figure 5 Combined with Fig.44 As shown, the first transmission transistor T31 includes a drain D31, a channel region C31 and a source S31 sequentially arranged in a direction away from the first inverter NOT1, and the first transmission transistor T31 also includes a gate G31, and the gate G31 of the first transmission transistor T31 surrounds and covers the peripheral surface of the channel region C31 of the first transmission transistor T31, and the drain D31 of the first transmission transistor T31 is connected to the first inverter NOT1. In this embodiment, the first transmission transistor T31 is a vertical wrap-around transistor. The drain D31 of the first transmission transistor T31 is coupled to the input end (first common gate 120) of the first inverter NOT1 or the output end (first conductive plug 130) of the first inverter NOT1 through the interconnection line layer 70.

[0145] The second transmission transistor T32 includes a drain D32, a channel region C32 and a source S32 sequentially arranged in a direction away from the second inverter NOT2, and the second transmission transistor T32 also includes a gate G32, the gate G32 of the second transmission transistor T32 surrounds and covers the circumference of the channel region C32 of the second transmission transistor T32, and the drain D32 of the second transmission transistor T32 is connected to the second inverter NOT2. In this embodiment, the second transmission transistor T32 is a vertical wrap-around transistor. The drain D32 of the second transmission transistor T32 is coupled to the output end (first conductive plug 130) of the first inverter NOT1 or the input end (first common gate 120) of the first inverter NOT1 through the interconnection line layer 70.

[0146] In some embodiments, reference Figure 4 , Figure 5 Combined with Fig.44 As shown, the memory further includes a first bit line BL1 , which extends above the first inverter NOT1 along the second direction D2 , and is connected to the source S31 of the first transfer transistor T31 .

[0147] Reference Figure 4Combined with Fig.44 As shown, the memory also includes a first word line WL1, which is arranged above the first inverter NOT1. In this embodiment, the first word line WL1 extends above the first inverter NOT1 along a first direction D1, and the extension directions of the first word line WL1 and the first bit line BL1 intersect vertically above the first inverter NOT1. The first word line WL1 is connected to the gate G31 of the first transfer transistor T31.

[0148] Reference Figure 4 Combined with Fig.44 As shown, the memory further includes a second bit line BL2 , which extends above the second inverter NOT2 along the second direction D2 , and is connected to the source S32 of the second transfer transistor T32 .

[0149] Reference Figure 4 Combined with Fig.44 As shown, the memory also includes a second word line WL2, which is arranged above the second inverter NOT2. In this embodiment, the second word line WL2 extends above the second inverter NOT2 along the first direction D1, and the extension direction of the second word line WL2 and the second bit line BL2 intersects vertically above the second inverter NOT2. The second word line WL2 is connected to the gate G32 of the second transfer transistor T32.

[0150] Reference Figure 6 The memory also includes a power supply terminal VDD and a ground terminal VSS, a source S12 of the first pull-up transistor T12 and a source S22 of the second pull-up transistor T22 are respectively connected to the power supply terminal VDD, and a source S11 of the first pull-down transistor T11 and a source S21 of the second pull-down transistor T21 are connected to the ground terminal VSS.

[0151] The memory of this embodiment utilizes the dimension perpendicular to the top surface of the substrate and integrates six transistors in the footprint of two transistors to form a 6T static random access memory cell (6T SRAM cell), which greatly improves the integration density of the transistors and reduces the footprint of the SRAM cell, which is conducive to the continuous improvement of the device integration density of the memory.

[0152] In an exemplary embodiment of the present disclosure, a method for manufacturing a memory is provided, such as Figure 7 As shown, Figure 7 A flowchart of a method for manufacturing a memory provided according to an exemplary embodiment of the present disclosure is shown. Figure 8-Figure 44 The schematic diagram of each stage of the memory manufacturing method is shown below. Figure 8-Figure 44 And refer to Figure 1-Figure 6 A method for manufacturing the memory of this embodiment is introduced.

[0153] The present embodiment does not limit the semiconductor structure. The semiconductor structure will be described below by taking a static random access memory (SRAM) as an example, but the present embodiment is not limited thereto. The semiconductor structure in the present embodiment may also be other structures.

[0154] like Figure 8 As shown, a method for manufacturing a memory provided by an exemplary embodiment of the present disclosure includes the following steps:

[0155] Step S110: providing a composite substrate, the composite substrate comprising a stacked substrate base, at least one first semiconductor material layer and at least one second semiconductor material layer, adjacent first semiconductor material layers and / or second semiconductor material layers are separated, and the first semiconductor material layers and the second semiconductor material layers have opposite conductivity types.

[0156] Step S120: Etching the composite substrate to form a plurality of fin-shaped portions, wherein the fin-shaped portions extend along a first direction, and the fin-shaped portions are spaced apart along a third direction, wherein the first direction and the third direction are parallel to the top surface of the substrate base, and the first semiconductor material layer retained in the fin-shaped portions forms a first semiconductor layer, and the second semiconductor material layer retained in the fin-shaped portions forms a second semiconductor layer, and along a direction away from the substrate base, the lengths of at least one first semiconductor layer and at least one second semiconductor layer in the fin-shaped portions in the first direction decrease successively.

[0157] Step S130: forming a gate, the gate extending on the substrate base along a second direction, the second direction being perpendicular to the top surface of the substrate base, the gate covering the surface of the first semiconductor layer and the surface of the second semiconductor layer located in the middle area of ​​the fin-shaped portion, forming a common-gate pull-down transistor and a pull-up transistor.

[0158] Step S140: forming a conductive plug, wherein the conductive plug is arranged on one side of the fin-shaped portion along a first direction, and the conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer, and one end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug, and the pull-down transistor and the pull-up transistor are connected through the conductive plug to form an inverter.

[0159] In step S110, the composite substrate is a stacked structure 300, and the composite substrate 300 includes a substrate base 310. The material of the substrate base 310 may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other materials with semiconductor properties, such as III / V group compounds or II / VI group compounds.

[0160] Reference Fig.17As shown, the composite substrate 300 also includes at least one first semiconductor material layer 320, at least one first semiconductor material layer 320 is stacked on the substrate base 310, the first semiconductor material layer 320 and the substrate base 310 are separated, and adjacent first semiconductor material layers 320 are separated. For example, the first semiconductor material layer 320 and the substrate base 310 are separated by other film layers, and adjacent first semiconductor material layers 320 are separated by other film layers, and the other film layers can be insulating film layers and / or conductive film layers. The material of the first semiconductor material layer 320 can include silicon, germanium, or silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide or other materials with semiconductor properties, such as III / V group compounds or II / VI group compounds, and the first semiconductor material layer 320 has a first conductivity type, for example, the first semiconductor material layer 320 can be doped with conductive doping ions with the first conductivity type.

[0161] The composite substrate 300 further includes at least one second semiconductor material layer 330, and the at least one second semiconductor material layer 330 is stacked on the at least one first semiconductor material layer 320. The second semiconductor material layer 330 and the first semiconductor material layer 320 are separated, and adjacent second semiconductor material layers 330 are separated. For example, the second semiconductor material layer 330 and the first semiconductor material layer 320 are separated by other film layers, and adjacent second semiconductor material layers 330 are separated by other film layers, and the other film layers may be insulating film layers and / or conductive film layers. The material of the second semiconductor material layer 330 may include silicon, germanium, or silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide or other materials with semiconductor properties, such as III / V group compounds or II / VI group compounds, and the second semiconductor material layer 330 has a second conductivity type, for example, the second semiconductor material layer 330 may be doped with conductive doping ions with the second conductivity type. The first semiconductor material layer 320 and the second semiconductor material layer 330 have opposite conductivity types. For example, the conductivity type of the first semiconductor material layer 320 may be N-type or P-type, and the conductivity type of the second semiconductor material layer 330 may be P-type or N-type.

[0162] In this embodiment, the composite substrate 300 includes two first semiconductor material layers 320 and one second semiconductor material layer 330. Fig.17 As shown, the composite substrate 300 includes a substrate base 310, a first dielectric layer 171, a bottom first semiconductor material layer 132, a second dielectric layer 271, a top first semiconductor material layer 232, a third dielectric layer 371 and a second semiconductor material layer 330 which are stacked in sequence.

[0163] Among them, the material of the bottom first semiconductor material layer 132 and the top first semiconductor material layer 232 includes silicon, and the conductivity type of the bottom first semiconductor material layer 132 and the top first semiconductor material layer 232 is N-type; the material of the second semiconductor material layer 330 includes germanium, and the conductivity type of the second semiconductor material layer 330 is P-type; the material of the first dielectric layer 171, the second dielectric layer 271, and the third dielectric layer 371 can include at least one of silicon oxide or silicon oxynitride.

[0164] In step S120, in this embodiment, the composite substrate is etched to form a plurality of fin-shaped portions, and the following implementation methods may be adopted:

[0165] First, if Fig.18 As shown, refer to Fig.17 A photoresist mask (not shown) is formed on the top surface of the composite substrate 300. The photoresist mask exposes a portion of the surface of both ends of the composite substrate 300 along the first direction D1. The composite substrate 300 is etched according to the photoresist mask, using the top surface of the second dielectric layer 271 as an etching stop layer. Then, as shown in FIG. Fig.19 As shown, refer to Fig.18 , trim the photoresist mask, remove part of the structure at both ends of the photoresist mask along the first direction D1, and increase the surface of both ends of the composite substrate 300 exposed by the photoresist mask. Etch the composite substrate 300 according to the trimmed photoresist mask, use the top surface of the third dielectric layer 371 as an etching stop layer, and etch away part of the second semiconductor material layer 330.

[0166] Reference Fig.19 As shown, the composite substrate 300 after etching has Fig.19 In the stepped structure shown in the figure, along the first direction D1, the length of the bottom first semiconductor material layer 132 is greater than the length of the top first semiconductor material layer 232, and both ends of the bottom first semiconductor material layer 132 extend outward relative to the top first semiconductor material layer 232, the length of the top first semiconductor material layer 232 is greater than the length of the second semiconductor material layer 330, and both ends of the top first semiconductor material layer 232 extend outward relative to the second semiconductor material layer 330.

[0167] Then, if Fig. 20 As shown, refer to Fig.19, forming a fourth dielectric layer 471, the fourth dielectric layer 471 fills the etched and removed portion of the composite substrate 300. For example, any suitable deposition process can be selected to deposit dielectric material to form a fourth dielectric material layer (not shown in the figure), the fourth dielectric material layer covers the top surface of the second semiconductor material layer 330 and fills the etched and removed portion of the composite substrate 300, and the top surface of the fourth dielectric material layer is higher than the top surface of the second semiconductor material layer 330. Then, the fourth dielectric material layer is polished by chemical mechanical polishing (CMP) until the top surface of the second semiconductor material layer 330 is exposed, and the fourth dielectric material layer is polished to form a fourth dielectric layer 471, the top surface of the fourth dielectric layer 471 is flush with the top surface of the second semiconductor material layer 300, so that a process plane is provided for subsequent process steps to facilitate the subsequent process steps.

[0168] The material of the fourth dielectric layer 471 may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0169] Then, if Fig.21 , Fig. 22 , Fig.23 As shown, refer to Fig. 20 , forming a first mask layer (not shown in the figure), the first mask layer exposes part of the top surface of the second semiconductor material layer 330 and the fourth dielectric layer 471, and etching the fourth dielectric layer 471 and the composite substrate 330 according to the first mask layer to form a plurality of first grooves 510, the first grooves 510 extend along the first direction D1 and penetrate the composite substrate 300, and the plurality of first grooves 510 are arranged at intervals along the third direction D3, wherein the first direction D1 and the third direction D3 are parallel to the top surface of the substrate base 310, and the first direction D1 and the third direction D3 are perpendicular, and the first grooves 510 extend into the first dielectric layer 171, and the first grooves 510 expose the first dielectric layer 171. It can be understood that in other embodiments, the first grooves 510 can expose the top surface of the substrate base 310.

[0170] Reference Fig.21 , Fig. 22 , Fig.23As shown, the first groove 510 divides the composite substrate 300 above the substrate base 310 into a plurality of fin-shaped portions 350 arranged at intervals. The fin-shaped portions 350 extend along the first direction D1 and are arranged at intervals along the third direction D3. The bottom first semiconductor material layer 132 retained in each fin-shaped portion 350 forms a bottom first semiconductor layer 140, the top first semiconductor material layer 232 forms a top first semiconductor layer 240, and the second semiconductor material layer 330 forms a second semiconductor layer 50. In the direction away from the substrate base 310, the lengths of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 in the first direction D1 decrease successively, and steps are formed at both ends of the fin-shaped portion 350. The steps of the fin-shaped portion 350 are covered by the fourth dielectric layer 471.

[0171] It is understandable that in some other embodiments, the composite substrate 300 may be etched first to form a first groove 510 in the composite substrate 300 above the substrate base 310, and the first groove 510 divides the composite substrate 300 above the substrate base 310 into a plurality of independently arranged strip structures, the strip structures extending along the first direction D1 and arranged at intervals along the third direction D3. Then, the two ends of the strip structures are etched to form steps at the two ends of the strip structures, so that the lengths of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 in the first direction D1 decrease in sequence in the direction away from the substrate base 310.

[0172] In some embodiments, after step S120 and before step S130, the following steps are further performed:

[0173] Step S1201 : forming a dummy gate, wherein the dummy gate extends along a third direction and covers a middle region of the fin-shaped portion arranged along the third direction.

[0174] First, if Fig.24 As shown, refer to Fig.23 The pseudo gate material layer 410 can be formed by depositing any one of the deposition processes including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering. The pseudo gate material layer 410 fills the first trench 510 and covers the top surfaces of the second semiconductor layer 50 and the fourth dielectric layer 471.

[0175] Then, if Fig.25 , Fig.26 , Fig. 27 , Fig.28 As shown, refer to Fig.24, a second mask layer (not shown in the figure) is formed on the top surface of the dummy gate material layer 410, and the second mask layer is located above the middle region IM of the fin-shaped portion 350. The dummy gate material layer 410 is etched according to the second mask layer, and the dummy gate material layer 410 exposed by the second mask layer is completely removed, and the retained dummy gate material layer 410 is etched to form a dummy gate 420, which extends along the third direction D2 and covers the middle region IM of the fin-shaped portion 350, and the ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 are all located outside the dummy gate 420. Among them, the dummy gate 420 material may include single crystal silicon or polycrystalline silicon. In this embodiment, the dummy gate material layer 410 may be etched by a dry process or a wet process.

[0176] Step S1202: etching the fin-shaped portion exposed by the dummy gate to remove part of the fin-shaped portion, forming a gap between adjacent first semiconductor layers and / or second semiconductor layers along the second direction, and exposing the surfaces of the first semiconductor layer and the second semiconductor layer outside the middle area.

[0177] In this embodiment, Fig.29 As shown, refer to Fig.25 , Fig.26 , Fig. 27 The fin-shaped portion 350 can be etched by a dry process or a wet process. The etching process has a high etching selectivity relative to the first semiconductor layer 40 (including the bottom first semiconductor layer 140 and the top first semiconductor layer 240) and the second semiconductor layer 50, so as to completely remove the first dielectric layer 171, the second dielectric layer 271, the third dielectric layer 371, and the fourth dielectric layer 471 exposed by the pseudo gate 420. In this way, the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the two ends of the second semiconductor layer 50 in the fin-shaped portion 350 are exposed.

[0178] In this embodiment, the bottom first semiconductor layer 140, the top first semiconductor layer 240 and the second semiconductor layer 50 of the composite substrate 300 all include semiconductor materials doped with conductive ions. Therefore, in subsequent steps, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240 and the second semiconductor layer 50 can be directly used as the source or drain of the transistor. In this embodiment, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240 and the second semiconductor layer 50 are no longer doped.

[0179] In other embodiments, after etching the fin-shaped portion 350 exposed by the dummy gate 420 to form a gap between adjacent first semiconductor layers 40 and / or second semiconductor layers 50, doping treatment can be performed on both ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 to form doped regions at both ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50, respectively. Subsequently, the doped regions at both ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 serve as the source or drain of the transistor.

[0180] Step S1203 : forming an isolation layer, wherein the isolation layer covers the exposed surface of the first semiconductor layer and the exposed surface of the second semiconductor layer 50 .

[0181] In this embodiment, refer to Fig.29 An atomic layer deposition process can be used to deposit a blocking material to form an isolation layer (not shown in the figure), which covers the exposed surface of the substrate base 310, the exposed surface of the bottom first semiconductor layer 140, the exposed surface of the top first semiconductor layer 240, and the exposed surface of the second semiconductor layer 50.

[0182] The material of the isolation layer has a high etching selectivity relative to the first semiconductor layer 40 (the bottom first semiconductor layer 140 and the top first semiconductor layer 240), the material of the isolation layer has a high etching selectivity relative to the second semiconductor layer 50, and the material of the isolation layer has a high etching selectivity relative to the dielectric layer (the first dielectric layer 171, the second dielectric layer 271, the third dielectric layer 371, and the fourth dielectric layer 471). This is to avoid the first semiconductor layer 40 and the second semiconductor layer 50 being damaged by the etching process when etching the intermediate region IM in subsequent steps.

[0183] In this embodiment, the material of the first dielectric layer 171, the second dielectric layer 271, the third dielectric layer 371 and the fourth dielectric layer 471 includes silicon oxide, the material of the first semiconductor layer 40 (the bottom first semiconductor layer 140 and the top first semiconductor layer 240) includes silicon, the material of the second semiconductor layer 50 includes germanium, and the material of the isolation layer may include at least one of silicon carbon nitride (SiCN) or silicon carbon oxynitride (SiOCN).

[0184] Step S1204: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the first semiconductor layer and the second semiconductor layer outside the middle region and fills the gap between the first semiconductor layer and / or the second semiconductor layer.

[0185] like Fig.30 , Fig.31 As shown, refer to Fig.29The interlayer dielectric layer 181 can be formed by deposition using a fluid chemical vapor deposition process (Flowable Chemical Vapor Deposition, FCVD). The interlayer dielectric layer 181 covers the surface of the bottom first semiconductor layer 140 and the top first semiconductor layer 240 outside the middle region IM, the surface of the second semiconductor layer 50, and fills the gap between the bottom first semiconductor layer 140 and the top first semiconductor layer 240 and the gap between the top first semiconductor layer 240 and the second semiconductor layer 50. The interlayer dielectric layer 181 also fills the area between adjacent fin-shaped portions 350. After the interlayer dielectric layer 181 is formed, the top surface of the interlayer dielectric layer 181 is polished using a chemical mechanical polishing process until the top surface of the dummy gate 420 is exposed, so that the top surface of the interlayer dielectric layer 181 is flush with the top surface of the dummy gate 420.

[0186] The material of the interlayer dielectric layer 181 may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0187] In step S130, forming a common gate includes the following steps:

[0188] Step S131 : removing the dummy gate to expose the fin-shaped portion in the middle region.

[0189] like Fig.32 , Fig.33 As shown, refer to Fig.31 The dummy gate 420 may be removed by etching using a dry process or a wet process. For example, in this embodiment, an etching solution may be used to dissolve and remove the dummy gate 420 to expose the middle region IM of the fin-shaped portion 350. The etching solution has a high etching selectivity ratio to the interlayer dielectric layer 181 and the composite substrate 300.

[0190] Step S132 : etching and removing a portion of the fin-shaped portion in the middle region to expose the surfaces of the first semiconductor layer and the second semiconductor layer 50 in the middle region.

[0191] like Fig.34 , Fig.35 As shown, refer to Fig.32 , Fig.33, the middle region IM of the fin-shaped portion 350 can be etched by a dry process or a wet process, and the first dielectric layer 171, the second dielectric layer 271 and the third dielectric layer 371 in the middle region IM are etched and removed. The etching process has a high etching selectivity relative to the first semiconductor layer 40 (the bottom first semiconductor layer 140, the top first semiconductor layer 240) and the second semiconductor layer 50, and at the same time, the first semiconductor layer 40 (the bottom first semiconductor layer 140, the top first semiconductor layer 240) and the second semiconductor layer 50 in the middle region IM of the fin-shaped portion 350 are covered by the interlayer dielectric layer 181, thereby avoiding damage to the first semiconductor layer 40 (the bottom first semiconductor layer 140, the top first semiconductor layer 240) and the second semiconductor layer 50 during the process.

[0192] like Fig.34 , Fig.35 As shown, after the first dielectric layer 171, the second dielectric layer 271 and the third dielectric layer 371 of the middle region 350 are removed, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240 and the second semiconductor layer 50 are supported by the interlayer dielectric layer 181, and the bottom first semiconductor layer 140, the top first semiconductor layer 240 and the second semiconductor layer 50 of the middle region IM are suspended, and the surfaces of the bottom first semiconductor layer 140, the top first semiconductor layer 240 and the second semiconductor layer 50 of the middle region IM are exposed in the process space.

[0193] Step S133: forming a first epitaxial layer on the exposed surface of the second semiconductor layer.

[0194] Reference Fig.34 , Fig.25 As shown, the semiconductor structure is placed in a reaction chamber, the exposed surface of the second semiconductor layer 50 is used as a seed crystal, a gas source for forming a first epitaxial layer (not shown in the figure) is introduced into the reaction chamber, and the first epitaxial layer is formed by epitaxial growth using a chemical vapor deposition process. The material of the first epitaxial layer may include silicon, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the first epitaxial layer is a silicon epitaxial layer, and the first epitaxial layer may be doped with conductive ions, and may be doped with P-type doping ions or N-type doping ions.

[0195] It can be understood that, during the epitaxial growth process, a silicon epitaxial layer is also grown on the surface of the first semiconductor layer 40 (the bottom first semiconductor layer 140 and the top first semiconductor layer 140 ).

[0196] In this embodiment, before forming a gate dielectric layer (which will be described in detail in subsequent steps), a first epitaxial layer is formed on the surface of the second semiconductor layer 50 in the middle area IM to reduce the energy band gap of the contact interface between the second semiconductor layer 50 and the gate dielectric layer, thereby reducing the threshold voltage of the transistor formed by the second semiconductor layer 50 in subsequent steps.

[0197] Step S134: forming a gate dielectric layer, wherein the gate dielectric layer covers the surfaces of the first semiconductor layer and the second semiconductor layer 50 in the middle region.

[0198] Reference Fig.34 , Fig.35 As shown, a gate dielectric layer (not shown in the figure) can be formed by deposition using a chemical vapor deposition process or an atomic layer deposition process, and the gate dielectric layer covers the surface of the bottom first semiconductor layer 140 of the middle region IM, the surface of the top first semiconductor layer 240 of the middle region IM, and the surface of the second semiconductor layer 50 of the middle region IM.

[0199] The gate dielectric layer may include aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )、Hafnium oxynitride (HfON), Zirconium oxide (ZrO 2 ), Tantalum Oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), Strontium Titanium Oxide (SrTiO 3 ), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); alternatively, the material of the gate dielectric layer may include at least one of hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSiON).

[0200] Step S135: forming a gate, the gate covering the gate dielectric layer and filling the area between the first semiconductor layer and / or the second semiconductor layer in the middle area.

[0201] Reference Fig.34 , Fig.35 As shown, any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering deposition processes can be used to deposit and form a gate material layer (not shown in the figure). The gate material layer covers the gate dielectric layer, the gap between the bottom first semiconductor layer 140 and the substrate base layer 310 in the middle region IM, the gap between the bottom first semiconductor layer 140 and the top first semiconductor layer 240 in the middle region IM, and the gap between the top first semiconductor layer 240 and the second semiconductor layer 50 in the middle region IM. The gate material layer extends along a third direction D3, and the gate material layer also fills the unfilled area between the middle regions IM of adjacent fin-shaped portions 350.

[0202] like Fig.36 As shown, refer to Figure 2A third mask layer (not shown in the figure) is formed on the top surface of the gate material layer, the third mask layer defines the pattern of the common gate 20 to be formed, the gate material layer is etched according to the third mask layer to form a second groove 520, the second groove 520 divides the gate material layer into a plurality of independently arranged common gates 20, the plurality of common gates 20 are arranged along a third direction D3, the common gates 20 are arranged along a second direction D2 perpendicular to the top surface of the substrate base 310, each common gate 20 corresponds to the surface of the first semiconductor layer 40 (the bottom first semiconductor layer 140 and the top first semiconductor layer 240) and the second semiconductor layer 50 covering the middle area IM of each fin-shaped portion 350.

[0203] The material of the common gate 20 includes a work function metal, and the work function metal may include at least one of titanium, tantalum, tungsten or an alloy thereof.

[0204] Reference Figure 1 , Figure 2 , Fig.36 The bottom first semiconductor layer 140, the top first semiconductor layer 240 and the common gate 20 form a pull-down transistor T1. The pull-down transistor T1 is a double-gate transistor. The bottom first semiconductor layer 140 and the top first semiconductor layer 240 arranged on one side of the common gate 20 along the first direction D1 serve as the source S1 of the pull-down transistor T1, and the bottom first semiconductor layer 140 and the top first semiconductor layer 240 arranged on the other side of the common gate 20 serve as the drain D1 of the pull-down transistor T1. The second semiconductor layer 50 and the common A pull-up transistor T2 is formed by using the gate 20, and a second semiconductor layer 50 arranged on one side of the common gate 20 along the first direction D1 serves as a source S1 of the pull-up transistor T2, and a second semiconductor layer 50 arranged on the other side of the common gate 20 serves as a drain D2 of the pull-up transistor T2. The pull-down transistor T1 and the pull-up transistor T2 share the common gate 20, and the source S2 of the pull-up transistor T2 and the source S1 of the pull-down transistor T1 are arranged on the same side, and the drain D1 of the pull-up transistor T2 and the drain D2 of the pull-down transistor T1 are arranged on the same side.

[0205] In this embodiment, the material of the bottom first semiconductor layer 140 and the top first semiconductor layer 240 includes silicon, the pull-down transistor T1 is an NMOS transistor, the material of the second semiconductor layer 50 includes germanium, and the pull-up transistor T2 is a PMOS transistor. The hole mobility of the germanium channel of the pull-up transistor T2 is 1.2 times the electron mobility of the silicon channel of the pull-down transistor T1. In order to adapt the driving current of the pull-down transistor T1 and the pull-up transistor T2, the present embodiment uses two layers of the first semiconductor layer 40 to form a double-gate pull-down transistor T1. However, the electron mobility of the silicon channel of the double-gate pull-down transistor T1 is higher than the hole mobility of the germanium channel of the pull-up transistor T2. In order to further balance the driving current of the pull-down transistor T1 and the pull-up transistor T2, the material of the common gate 20 in this embodiment uses silicon nitride, which is more conducive to the pull-up transistor T2, to improve the hole mobility of the germanium channel of the pull-up transistor T2, so that the driving current of the pull-down transistor T1 and the pull-up transistor T2 is more adapted.

[0206] Then, a fifth dielectric layer 571 is formed to fill the second trench 520 and cover the top surface of the second semiconductor layer 50 and the top surface of the interlayer dielectric layer 181 . The material of the second fifth dielectric layer 571 may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0207] It is understood that in other embodiments, reference Fig.29 In the process of forming the dummy gate 420 in step S1201, the dummy gate material layer 410 may be etched to form a plurality of independently arranged dummy gates 420, the plurality of dummy gates 420 are arranged at intervals along the third direction D3, and each dummy gate 420 covers the middle region IM of each fin-shaped portion 350. Then, referring to Fig.30 , Fig.31 , an interlayer dielectric layer 181 is formed to cover both ends of the fin-shaped portion 350 and fill the unfilled area of ​​the first trench 510. Fig.36 In the process of forming the common gate 20, after removing the dummy gate 420, a common gate 20 is formed correspondingly in each region where the dummy gate 420 is removed. In this way, the step of etching the gate material layer to form the second trench 520 and the step of forming the fifth dielectric layer 571 can be saved. By forming the interlayer dielectric layer 181, the self-alignment of the common gate 20 and the isolation of the common gate 20 can be completed at one time, saving process steps and process costs.

[0208] In step S140, a conductive plug is formed, including the following steps:

[0209] Step S141: forming a contact hole in the interlayer dielectric layer, wherein the contact hole exposes a portion of the surface of the first semiconductor layer and the second semiconductor layer located on one side of the middle region.

[0210] Reference Fig.37A fourth mask layer (not shown in the figure) is formed on the fifth dielectric layer 571, and the fourth mask layer defines a pattern of a contact hole to be formed. The fifth dielectric layer 571, the interlayer dielectric layer 181, and the isolation layer are etched according to the fourth mask layer to form a contact hole (not shown in the figure) penetrating the interlayer dielectric layer 181, and the contact hole exposes a portion of the surface of the bottom first semiconductor 140 at one end of the fin-shaped portion 350, a portion of the surface of the top first semiconductor layer 240, and a portion of the surface of the second semiconductor layer 50.

[0211] Step S142: forming a conductive plug in the contact hole.

[0212] In this embodiment, the conductive plug may be formed by the following implementations:

[0213] Reference Fig.37 Combined with Figure 1 , Figure 2 First, a first barrier layer (not shown in the figure) is deposited by any deposition process including chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering. The first barrier layer covers the hole wall of the contact hole (including the bottom first semiconductor 140, the top first semiconductor layer 240 and the second semiconductor layer 50 exposed by the contact hole). The material of the first barrier layer may include titanium or a titanium compound or tantalum (Ta) or a tantalum compound.

[0214] Then, a conductive material is deposited by any of the above deposition processes to form a first conductive material layer, the first conductive material layer covers the first barrier layer and fills the unfilled area of ​​the contact hole, and the first conductive material layer also covers the top surface of the fifth dielectric layer 571. The first conductive material layer on the top surface of the fifth dielectric layer 571 is polished away by a chemical mechanical polishing process, and the first conductive material layer in the contact hole forms a conductive plug 30. The material of the conductive plug 30 may include metal tungsten (W) or a tungsten compound. The conductive plug 30 formed in this embodiment is separated from other film layers by the first barrier layer to prevent the metal material in the conductive plug 30 from diffusing into other film layers, causing contamination of other film layers or conductive devices, and affecting the electrical properties of the semiconductor structure.

[0215] The bottom first semiconductor 140, the top first semiconductor layer 240 and the second semiconductor layer 50 are connected via a conductive plug 30, that is, the drain D1 of the common-gate pull-down transistor T1 and the drain D2 of the pull-up transistor T2 are connected via the conductive plug 30, or the source S1 of the common-gate pull-down transistor T1 and the source S2 of the pull-up transistor T2 are connected via the conductive plug 30, and the common-gate pull-down transistor T1 and the pull-up transistor T2 form an inverter NOT.

[0216] The manufacturing method of the memory of the present embodiment utilizes a second direction perpendicular to the top surface of the substrate to stack the pull-down transistor and the pull-up transistor above the substrate to form an inverter, thereby improving the integration density of the transistor, reducing the occupied area of ​​the inverter, and increasing the applicable area of ​​the semiconductor structure, which is beneficial to improving the integration density of devices in the semiconductor structure and arranging more semiconductor devices.

[0217] It can be understood that, in some embodiments, while forming the conductive plug, the following steps are also performed:

[0218] Reference Fig.37 , while forming a contact hole in the interlayer dielectric layer 181, a portion of the fifth dielectric layer 571, a portion of the interlayer dielectric layer 181 and a portion of the isolation layer are etched away to form a first hole and a second hole penetrating the interlayer dielectric layer 181. Along the first direction D1, the first hole and the second hole are formed at an end away from the contact hole. The first hole exposes a portion of the surface of the bottom first semiconductor layer 140 and a portion of the surface of the top first semiconductor layer 240, and the second hole exposes a portion of the surface of the second semiconductor layer 50.

[0219] In this embodiment, the formed first barrier layer covers the hole wall of the first hole and the hole wall of the second hole. The first conductive material layer covers the first barrier layer and fills the unfilled areas of the first hole and the second hole. After the first conductive material layer on the top surface of the fifth dielectric layer 571 is removed by grinding, the first conductive material layer retained in the first hole forms the first conductive wire 161, and the first conductive material layer retained in the second hole forms the second conductive wire 261.

[0220] In this way, the source S1 of the pull-down transistor T1 of the inverter NOT is connected to the source S2 of the pull-up transistor T2, the drain D1 of the pull-down transistor T1 can be led out through the first wire 161 and connected to other devices or structures, and the drain S2 of the pull-up transistor T2 can be led out through the second wire 261 and connected to other devices or structures; or, the drain D1 of the pull-down transistor T1 of the inverter NOT is connected to the drain D2 of the pull-up transistor T2, the source S1 of the pull-down transistor T1 can be led out through the first wire 161 and connected to other devices or structures, and the source S2 of the pull-up transistor T2 can be led out through the second wire 261 and connected to other devices or structures.

[0221] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment, the fin-shaped portion 350 includes a first end E1 and a second end E2 arranged opposite to each other along the first direction D1, and in the process of forming the contact hole, the contact holes are alternately formed at the first end E1 and the second end E2 of the fin-shaped portion 350 arranged along the third direction D3. In this way, the conductive plug 30 of one of the two inverters NOT adjacent to each other along the third direction D3 is arranged at the first end E1, and the conductive plug 30 of the other inverter NOT of the two inverters NO is arranged at the second end E2.

[0222] In this embodiment, the common gate 20 shared by the pull-down transistor T1 and the pull-up transistor T2 of the inverter NOT is connected as the input end of the inverter NOT; the drain D1 of the pull-down transistor T1 of the inverter NOT and the drain D2 of the pull-up transistor T1 are connected as the output end of the inverter NOT through the conductive plug 30; the source S1 of the pull-down transistor T1 is connected to the first wire 161, and the source S2 of the pull-up transistor T2 is connected to the second wire 261. That is, the output ends of the two adjacent inverters NOT along the third direction D2 are arranged opposite to each other.

[0223] Reference Fig.37 , Fig.38 The inverter NOT having an output terminal set at the first end E1 is defined as the first inverter NOT1, and the inverter NOT having an output terminal set at the second end E2 is defined as the second inverter NOT2. In the semiconductor structure formed by the above embodiment, the first inverter NOT1 and the second inverter NOT2 are alternately arranged along the third direction D3. After forming the conductive plug 30 in step S140, the present embodiment further performs the following steps:

[0224] Step S150: forming a wiring layer.

[0225] In this embodiment, the wiring layer is formed using the following implementation methods:

[0226] First, if Fig.39 As shown, refer to Fig.37, a dielectric material is deposited by any deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering to form a dielectric layer 281, and the dielectric layer 281 covers the top surface of the fifth dielectric layer 571. The material of the dielectric layer 281 may include an ultra-low dielectric constant (Ultra Low-k, ULK) material or an ultra-low dielectric constant (Extra Low-K, ELK) material. Among them, the dielectric constant of the low dielectric constant (Ultra Low-k, ULK) material is lower than 2.4, and the dielectric constant of the ultra-low dielectric constant (Extra Low-K, ELK) material is lower than 3.4. Alternatively, the material of the dielectric layer 281 may also be other oxides. Exemplarily, the material of the dielectric layer 281 may include fluorinated silicate glass, polyimide, fluorinated polyimide, siloxane or porous silicon dioxide, etc.

[0227] Reference Fig.38 , Fig.39 , taking the first inverter NOT1 and the second inverter NOT2 adjacent thereto as a group, etching the dielectric layer 281, and forming a first connection groove (not shown in the figure) and a second connection groove (not shown in the figure) in the dielectric layer 281 above each group of the first inverter NOT1 and the second inverter NOT2. The first connection groove exposes the top surface of the common gate 20 of the first inverter NOT1 and the top surface of the conductive plug 30 of the second inverter NOT2, and the second connection groove exposes the top surface of the common gate 20 of the second inverter NOT2 and the top surface of the conductive plug 30 of the first inverter NOT1.

[0228] Next, a second barrier layer (not shown in the figure) is deposited by any deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering, and the second barrier layer covers the groove wall of the first connection groove and the groove wall of the second connection groove and covers the top surface of the dielectric layer 281. The material of the second barrier layer may include titanium or a titanium compound, tantalum or a tantalum compound.

[0229] Then, if Fig.40 , Fig.41 As shown, refer to Fig.39, a second conductive material layer (not shown in the figure) is deposited by any of the above deposition processes, and the second conductive material layer covers the second barrier layer and fills the unfilled areas of the first connection groove and the second connection groove. The second conductive material layer and the second barrier layer covering the top surface of the dielectric layer 281 are removed by grinding by a chemical mechanical polishing process, and the second conductive material layer located in the first connection groove forms the first interconnection line 171, and the second conductive material located in the second connection groove forms the second interconnection line 172. The material of the first interconnection line 171 and the second interconnection line 172 may include metal tungsten or metal copper. The first interconnection line 171 and the second interconnection line 172 formed in this embodiment are separated by the second barrier layer and other material layers and devices, thereby preventing the materials of the first interconnection line 171 and the second interconnection line 172 from diffusing to other material layers or devices, causing other material layers or devices to contaminate and affect the electrical properties of the semiconductor structure, and further improving the performance and service life of the semiconductor structure.

[0230] In the semiconductor structure formed in this embodiment, the input terminals and output terminals of two adjacent inverters along the third direction are arranged relatively to each other, so that the inverters can be arranged more compactly, which is convenient for subsequent wiring connection between the inverters or between the inverters and other devices. In this way, after the wiring layer is formed, the input terminal of the first inverter and the output terminal of the second inverter in each group are connected through the first interconnection line, and the output terminal of the first inverter and the input terminal of the second inverter are connected, so that the layout of the interconnection lines in the wiring layer is more reasonable.

[0231] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment, and this embodiment further performs the following steps:

[0232] Step S160: forming a word line, wherein the word line extends along a first direction and is correspondingly disposed above the inverter.

[0233] Step S170: forming a transfer transistor, which is disposed above the inverter, wherein the gate of the transfer transistor is connected to the word line, and the drain of the transfer transistor is connected to the common gate of the inverter or a conductive plug.

[0234] Step S180: forming a bit line, wherein the bit line extends above the inverter along the second direction, and the bit line is connected to the source of the transfer transistor.

[0235] Step S160, step S170 and step S180 are performed after step S150. In this embodiment, word lines, transfer transistors and bit lines are formed, and the following implementation methods are adopted:

[0236] First, if Fig.42 As shown, refer to Fig.40The sixth dielectric layer 671 is formed by deposition using any deposition process of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering, and the sixth dielectric layer 671 covers the top surface of the interconnect layer 70. The material of the sixth dielectric layer 671 may include at least one of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), ultra low dielectric constant (ULK) material or extra low dielectric constant (ELK) material.

[0237] Then, if Fig.42 As shown, any of the above deposition processes is used to deposit and form the third conductive material layer 440, and the third conductive material layer 440 covers the top surface of the sixth dielectric layer 671. The material of the third conductive material layer 440 includes a conductive metal, for example, the material of the third conductive material layer 440 may include at least one of metal titanium or its alloy, metal tantalum or its alloy, and metal tungsten or its alloy. In this embodiment, the material of the third conductive material layer 440 includes tungsten.

[0238] Then, if Fig.43 As shown, part of the third conductive material layer 440 is etched away to form a plurality of independently arranged word lines WL, the plurality of word lines WL extend along the first direction D1 correspondingly above the plurality of inverters NOT, and the plurality of word lines WL are spaced apart along the third direction D3.

[0239] Then, if Fig.44 As shown, a seventh dielectric layer 771 is deposited to cover the word lines WL and fill the area between adjacent word lines WL. The material of the seventh dielectric layer 771 is the same as that of the sixth dielectric layer 671, and will not be described again.

[0240] Then, if Fig.44 Shown and combined Figure 3 , Figure 4 A fifth mask layer (not shown in the figure) is formed on the top surface of the seventh dielectric layer 771, and the fifth mask layer defines the pattern of the bit line BL to be formed. The seventh dielectric layer 771, the word line WL, the sixth dielectric layer 671 and the dielectric layer 181 are etched layer by layer according to the fifth mask layer until the top surface of the first interconnection line 171 or the top surface of the second interconnection line 172 of the interconnection line layer 70 is exposed, and trenches (not shown in the figure) are formed, wherein each trench extends along the second direction D2 and passes through a corresponding word line WL, and each trench exposes the top surface of the first interconnection line 171 or the top surface of the second interconnection line 172.

[0241] Next, a gate oxide layer (not shown in the figure) is deposited by any deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering. The gate oxide layer covers the groove wall of the trench. The material of the gate oxide layer may include aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )、Hafnium oxynitride (HfON), Zirconium oxide (ZrO 2 ), Tantalum Oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), Strontium Titanium Oxide (SrTiO 3 ), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); alternatively, the material of the gate oxide layer may include at least one of hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSiON).

[0242] Then, if Fig.44 Shown and combined Figure 3 , Figure 4 , an atomic layer deposition process is used to deposit metal oxide, the metal oxide covers the gate oxide layer and fills the unfilled area in the channel groove, and the metal oxide also covers the top surface of the seventh dielectric layer 771. A chemical mechanical polishing process or etching is used to remove the metal oxide covering the top surface of the seventh dielectric layer 771 to form a transfer transistor T3, the metal oxide covered by the word line WL forms a channel region of the transfer transistor T3, a portion of the metal oxide located below the channel region forms a drain D3 of the transfer transistor T3, and a portion of the metal oxide located above the channel region forms a source S3 of the transfer transistor T3, and at the same time, the metal oxide located in the seventh dielectric layer 771 forms a bit line BL.

[0243] The structure of the transfer transistor T3 formed in this embodiment is a vertical annular channel (Channel-All-Around, CAA) transistor, the gate G3 of the transfer transistor T3 surrounds and covers the periphery of the channel region C3, the gate G3 is connected to the word line WL, wherein the source S3 of the transfer transistor T3 is arranged above the channel region C3, the source S3 of the transfer transistor T3 is connected to the bit line BL, the drain D3 of the transfer transistor T3 is arranged below the channel region C3, the drain D3 of the transfer transistor T3 is connected to the first interconnection line 170 or the second interconnection line 270, and is connected to the common gate 20 of the inverter NOT or the conductive plug 30 of the inverter NOT through the first interconnection line 170 or the second interconnection line 270.

[0244] The material of the metal oxide may be indium gallium zinc oxide (IGZO). For example, the material of the metal oxide may include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiOx), indium zinc oxide (InSnOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), indium tin zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

[0245] like Fig.44 , Fig.45 As shown, combined with Figure 3 , Figure 4 The transmission transistor T3 formed in this embodiment is an IGZO NMOS transistor, and the channel material of the transmission transistor T3 is indium gallium zinc oxide, which can reduce the leakage current of the channel region C3 of the transmission transistor T3 and improve the control of the transmission transistor T3 on the channel region C3.

[0246] In this embodiment, the word line WL located above the first inverter NOT1 is defined as the first word line WL1, and the bit line BL located above the first inverter NOT1 is defined as the first bit line BL1. The first bit line BL1 is arranged above the first interconnection line 171, the source S31 of the first transfer transistor T31 is connected to the first bit line BL1, and the drain D31 of the first transfer transistor T31 is connected to the common gate 20 of the first inverter NOT1.

[0247] The word line WL located above the second inverter NOT2 is defined as the second word line WL2, and the bit line BL located in the direction of the second inverter NOT2 is defined as the second bit line BL2. The second bit line BL2 and the second word line WL2 intersect vertically in the extension direction above the second inverter NOT2. The source S32 of the second transfer transistor T32 is connected to the second bit line BL2, and the drain D32 of the second transfer transistor T32 is connected to the common gate 20 of the second inverter NOT2.

[0248] In this way, the first inverter NOT1 of each group and the first transfer transistor T31 located above it, the second inverter NOT2 and the second transfer transistor T32 located above it together constitute a 6T static random access memory unit. This embodiment forms a semiconductor structure, integrating two inverters and two transfer transistors on the area of ​​two transistors to form a 6T static random access memory unit, saving the occupied area and improving the integration density.

[0249] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment. In this embodiment, step S110 provides a composite substrate, including the following steps:

[0250] Step S111: providing a first substrate and a second substrate, wherein the first substrate and the second substrate include a first semiconductor material, wherein the first substrate includes a first back substrate, a first buried oxide layer and a first top substrate which are arranged in sequence.

[0251] Step S112: disposing the second substrate on the first top substrate, and bonding and connecting the second substrate and the first top substrate.

[0252] Step S113: providing a third substrate, and epitaxially forming an epitaxial substrate layer on the third substrate, wherein the epitaxial substrate layer includes a second semiconductor material.

[0253] Step S114: disposing an epitaxial substrate layer on the second substrate, and bonding the epitaxial substrate layer to a surface of the second substrate away from the first substrate.

[0254] Step S115: etching and removing the third substrate, and the first substrate, the second substrate and the epitaxial substrate layer together form a composite substrate.

[0255] In step S111, first, Figure 8 , Fig. 9 As shown, a first substrate 810 and a second substrate 820 are provided. In this embodiment, the first substrate 810 and the second substrate 820 are both SOI substrates. Figure 8 As shown, the first substrate 810 includes a first back substrate 811, a first buried oxide layer 812 and a first top substrate 813 which are arranged in sequence. Fig. 9As shown, the second substrate 820 includes a second back substrate 821, a second buried oxide layer 822 and a second top substrate 823 which are arranged in sequence.

[0256] The first substrate 810 and the second substrate 820 both include a first semiconductor material. In this embodiment, the first substrate 810 and the second substrate 820 are both silicon substrates. The first back substrate 811, the first top substrate 813, the second back substrate 821, and the second back substrate 821 all include silicon.

[0257] In step S112, if Figure 8 As shown, a first oxide layer 801 is formed on the top surface of a first top substrate 813 of a first substrate 810 by using any deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering. Fig. 9 As shown, similarly, a second oxide layer 802 is formed on the top surface of the second top substrate 823 of the second substrate 820 , and the materials of the first oxide layer 801 and the second oxide layer 802 may include at least one of silicon oxide or silicon oxynitride.

[0258] like Fig.10 As shown, the second top substrate 823 of the second substrate 820 is arranged toward the first top substrate 813 of the first substrate 810, and the second substrate 820 is arranged on the first substrate 810. The first substrate 810 and the second substrate 820 are connected in a face-to-back manner through the first oxide layer 801 and the second oxide layer 802, and the first oxide layer 801 and the second oxide layer 802 together form a second dielectric layer 271.

[0259] Below, the present embodiment is described by assuming that the formed composite substrate 300 includes two first semiconductor material layers 320:

[0260] Hydrogen ions or helium ions are injected into the second back substrate 821 of the second substrate 820, and then the first substrate 810 and the second substrate 820 are placed under 400° C. to 500° C. for annealing, so that the second back substrate 821 is cracked in the hydrogen ion or helium ion enriched region, and then the cracked second back substrate 821 is peeled off and removed. In this embodiment, the annealing process can be performed in a furnace tube.

[0261] The second back substrate 821 is polished by a chemical mechanical polishing process to completely remove the second back substrate 821 and expose the top surface of the second buried oxide layer 822 .

[0262] Reference Fig.11 , a buffered oxide etchant is used to clean and remove the second buried oxide layer 822 of the second substrate 820, exposing the second top substrate 823. The buffered oxide etchant in this embodiment may be a mixture of hydrogen peroxide and hydrofluoric acid.

[0263] Reference Fig.11 A third oxide layer 803 is formed on the top surface of the second top substrate 823 by using any deposition process including chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering. The material of the third oxide layer 803 may include at least one of silicon oxide or silicon oxynitride.

[0264] It can be understood that the composite substrate 300 formed in other embodiments may include only one layer of first semiconductor material layer 320. When forming the composite substrate 300, the second substrate 820 may be omitted, and the first substrate 810 and the subsequent epitaxial substrate layer 850 may be used to form the composite substrate 300 together; or, the composite substrate 300 formed in other embodiments may include three or more layers of first semiconductor material layer 320, and the second back substrate 821 of the second substrate 820 may not be removed, and the second back substrate 821 may be retained as one of the first semiconductor material layers 320 in the composite substrate 300.

[0265] In step S113, if Fig.12 As shown, a third substrate 830 is provided, and the material of the third substrate 830 includes a first semiconductor material, wherein the third substrate 830 may be a single silicon substrate, or the third substrate 830 may also be an SOI substrate.

[0266] The third substrate 830 provided in this embodiment is an SOI substrate, and includes a third back substrate 831, a third buried oxide layer 832, and a third top substrate 833 arranged in sequence. It can be understood that in other embodiments, the third substrate 830 can be a whole silicon wafer.

[0267] In some embodiments, an epitaxial substrate layer 850 is formed on the surface of the third substrate 830, and the following implementation methods may be adopted:

[0268] Reference Fig.12 , Fig.13 , place the third substrate 830 in a reaction chamber, introduce a gas source of the first semiconductor material and a gas source of the second semiconductor material into the reaction chamber, and epitaxially grow an epitaxial substrate layer 850 on the top surface of the third substrate 830. During the process of epitaxially growing the epitaxial substrate layer 850, gradually reduce the content of the gas source of the first semiconductor material introduced into the reaction chamber, and gradually increase the content of the gas source of the second semiconductor material introduced into the reaction chamber.

[0269] In the process of etching and removing the third substrate 850 , part of the epitaxial substrate layer 850 is etched and removed, and a part of the structure on the top of the epitaxial substrate layer 850 is retained to form the composite substrate 300 .

[0270] In this embodiment, the second semiconductor material is germanium, and the epitaxial substrate layer 850 is a germanium epitaxial layer to illustrate this embodiment:

[0271] The third substrate 830 is placed in a reaction chamber, and silicon source gas and germanium source gas are introduced into the reaction chamber. The top surface of the third substrate 830 is used as a seed layer, and a germanium silicon layer 840 is epitaxially grown on the top surface of the third substrate 830. The material of the germanium silicon layer 840 includes germanium silicon SixGey, 0≤x≤1, 0≤y≤1, wherein. In the process of forming the germanium silicon layer 840, the content of the silicon source gas introduced into the reaction chamber is gradually reduced, and the content of the germanium source gas introduced into the reaction chamber is increased, so that the concentration of germanium in the formed germanium silicon layer 840 gradually increases from the bottom surface to the top surface.

[0272] like Fig.13 As shown, in the process of forming the silicon germanium layer 840 in this embodiment, the concentration of Ge in the silicon germanium in the silicon germanium layer 840 increases in steps of 0.1 from the bottom surface of the silicon germanium layer 840 to the top surface of the silicon germanium layer 840. For every increase of 0.1 in the concentration of Ge in the silicon germanium layer 840, the thickness of the silicon germanium layer 840 increases by 0.1 μm. The concentration of Ge in the silicon germanium in the silicon germanium layer 840 increases from 0.1 to 1, and the total thickness of the silicon germanium layer 840 is 1 μm. The silicon germanium layer 840 formed in this embodiment includes Si arranged in sequence from the bottom surface to the top surface. 0.9 Ge 0.1 Layer, Si 0.8 Ge 0.2 Layer, Si 0.7 Ge 0.3 Layer, Si 0.6 Ge 0.4 Layer, Si 0.5 Ge 0.5 Layer, Si 0.4 Ge 0.6 Layer, Si 0.7 Ge 0.3 Layer, Si 0.8 Ge 0.2 Layer, Si 0.9 Ge 0.1 That is, the top layer of the germanium silicon layer 840 formed in this embodiment is a germanium crystal layer.

[0273] Next, a germanium source gas is introduced into the reaction chamber, and the top surface of the germanium silicon layer 840 is used as a seed layer, and a germanium epitaxial layer 860 is formed on the top surface of the germanium silicon layer 840 by epitaxial growth. In this way, the formed germanium epitaxial layer 860 has fewer defects and a higher germanium crystal purity. In this embodiment, the thickness of the germanium epitaxial layer 860 is 100 μm.

[0274] The epitaxial substrate layer 850 formed in this embodiment includes a germanium silicon layer 840 and a germanium epitaxial layer 860 . In this embodiment, during the process of etching away the third substrate 850 , the germanium silicon layer 840 is etched away to form the second semiconductor material layer 330 of the composite substrate 300 with the high-purity germanium epitaxial layer 860 .

[0275] In some other embodiments, the epitaxial substrate layer 850 is formed on the surface of the third substrate 830, and the following implementation methods may be adopted:

[0276] Step S1131: epitaxially forming at least one second semiconductor epitaxial layer on the top surface of the third substrate, and the concentration of the second semiconductor material in the at least one second semiconductor epitaxial layer increases in a direction away from the top surface of the third substrate.

[0277] In this embodiment, the second semiconductor epitaxial layer 870 is a germanium silicon layer. This embodiment is described by forming two layers of the second semiconductor epitaxial layer 870:

[0278] Reference Fig.12 , Fig.14 First, the first and second semiconductor epitaxial layers 871 are formed by epitaxy on the top surface of the third substrate 830. For example, the third substrate 830 is placed in a reaction chamber, the reaction temperature in the reaction chamber is adjusted to 350°C to 450°C, silicon source gas and germanium source gas are introduced into the reaction chamber, and the first and second semiconductor epitaxial layers 871 are formed by epitaxy on the top surface of the third substrate 830. The materials of the first and second semiconductor epitaxial layers 871 include Si 0.4 Ge 0.6 The thickness of the first and second semiconductor epitaxial layers 871 is 1 μm.

[0279] Then, if Fig.14 As shown, a second second semiconductor epitaxial layer 872 is formed by epitaxy on the top surface of the first second semiconductor epitaxial layer 871, and the concentration of germanium in the second second semiconductor epitaxial layer 872 is greater than the concentration of germanium in the first second semiconductor epitaxial layer 871. For example, the reaction temperature in the reaction chamber can be adjusted to 550° C. to 650° C., and the second second semiconductor epitaxial layer 872 is formed by epitaxy on the top surface of the first second semiconductor epitaxial layer 871. The material of the second second semiconductor epitaxial layer 872 includes Si 0.3 Ge 0.7 , the thickness of the second semiconductor epitaxial layer 872 is 1 μm.

[0280] Step S1132: epitaxially forming an epitaxial substrate layer on the top surface of at least one second semiconductor epitaxial layer.

[0281] Reference Fig.12 , Fig.14 , epitaxially forming an epitaxial substrate layer 850 on the top surface of the second second semiconductor epitaxial layer 872, using the top surface of the second second semiconductor epitaxial layer 872 as a seed layer, epitaxially growing on the top surface of the second second semiconductor epitaxial layer 872 to form an epitaxial substrate layer 850, so that the formed epitaxial substrate layer 850 has fewer defects and a higher purity of germanium crystal. In this embodiment, the thickness of the epitaxial substrate layer 850 is 100 μm.

[0282] In this embodiment, after the epitaxial substrate layer 850 is formed, during the process of etching away the third substrate 830 , at least one second semiconductor epitaxial layer 870 is etched away.

[0283] In step S114, if Fig.15 As shown, first, a fourth oxide layer 804 is formed on the top surface of the epitaxial substrate layer 850 by using any one of the deposition processes of chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), high density plasma deposition (HDP), high aspect ratio process (HARP), and plasma enhanced chemical vapor deposition (PECVD). The material of the fourth oxide layer 804 may include at least one of silicon oxide or silicon oxynitride. In this way, the density of the formed fourth oxide layer 804 is higher, the fourth oxide layer 804 and the epitaxial substrate layer 850 are more closely combined, and the fourth oxide layer 804 has a higher bonding ability, and the subsequent epitaxial substrate layer 850 can be more firmly bonded to the second top substrate 823, and the stability and yield of the formed composite substrate 300 are the highest, and the thermal treatment of the composite substrate 300 can be avoided to cause device degradation.

[0284] Then, if Fig.16 As shown, the epitaxial substrate layer 850 is disposed toward the second top substrate 823 of the second substrate 820 , and the epitaxial substrate layer 850 is disposed on the second substrate 820 . The epitaxial substrate layer 850 and the second top substrate 823 are bonded and connected via the third oxide layer 803 and the fourth oxide layer 804 .

[0285] Next, hydrogen ions or helium ions are implanted into the third back substrate 831 of the third substrate 830, and then the third substrate 830 is annealed at 400° C. to 500° C. to cause the third back substrate 831 to crack in the hydrogen ion or helium ion enriched region, and then the cracked third back substrate 831 is peeled off and removed. In this embodiment, the annealing process can be performed in a furnace tube.

[0286] The third back substrate 831 is polished by a chemical mechanical polishing process to completely remove the third back substrate 831 and expose the top surface of the third buried oxide layer 832 .

[0287] The third buried oxide layer 832 of the third substrate 830 is cleaned and removed by using a buffered oxide etching solution to expose the third top substrate 833. The buffered oxide etching solution in this embodiment can be a mixture of hydrogen peroxide and hydrofluoric acid.

[0288] Then, the third top substrate 833 of the third substrate 830 is removed. In this embodiment, the method of removing the third top substrate 833 is the same as the method of removing the third back substrate 831 , and will not be described in detail herein.

[0289] Next, the germanium silicon layer 840 or at least one second semiconductor epitaxial layer 870 is removed by a wet process until the epitaxial substrate layer 850 is exposed. Fig.17 As shown, a composite substrate 300 is formed. Among them, the first back substrate 811 of the first substrate 810 serves as the substrate base 310 of the composite substrate 300, the first buried oxide layer 812 serves as the first dielectric layer 171 of the composite substrate 300, the first top substrate 813 serves as the bottom first semiconductor material layer 132 of the composite substrate 300, the first oxide layer 801 and the second oxide layer 802 jointly form the second dielectric layer 271 of the composite substrate 300, the second top substrate 823 of the second substrate 820 serves as the top first semiconductor material layer 232 of the composite substrate 300, the third oxide layer 803 and the fourth oxide layer 804 jointly form the third dielectric layer 371 of the composite substrate 300, and the epitaxial substrate layer 850 serves as the second semiconductor material layer 330 of the composite substrate 300.

[0290] In the composite substrate 300 formed in this embodiment, the materials of the substrate base 310 and the first semiconductor material layer 320 include silicon, and the material of the second semiconductor material layer 330 includes germanium. It can be understood that this embodiment is only an example of the composite substrate 300 provided in step S110. In other embodiments, the composite substrate 300 can be manufactured in any other reasonable manner, and the number and material of the first semiconductor material layer 320 and the second semiconductor material layer 330 in the composite substrate 300 can be adjusted according to actual applications.

[0291] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0292] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; An inverter is arranged on the substrate, and the inverter comprises: A pull-down transistor, comprising a first semiconductor layer extending along a first direction, the first direction being parallel to a top surface of the substrate, the first semiconductor layer comprising a first channel region; A pull-up transistor, comprising a second semiconductor layer extending along the first direction, the second semiconductor layer being spaced above the first semiconductor layer along a second direction perpendicular to the top surface of the substrate, the second semiconductor layer comprising a second channel region; A common gate is arranged on the substrate along the second direction, and the common gate covers the first channel region and the second channel region; A conductive plug is arranged on one side of the common gate along the first direction, the conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer, and an end of the first semiconductor layer and an end of the second semiconductor layer are connected through the conductive plug.

2. The semiconductor structure according to claim 1, characterized in that: Along the first direction, the source of the pull-down transistor and the drain of the pull-down transistor are relatively arranged in the first semiconductor layer on both sides of the first channel region; The source of the pull-up transistor and the drain of the pull-up transistor are arranged oppositely in the second semiconductor layer at two sides of the second channel region; The source of the pull-down transistor and the source of the pull-up transistor are arranged on the same side, and the drain of the pull-down transistor and the drain of the pull-up transistor are arranged on the same side.

3. The semiconductor structure according to claim 2, characterized in that: The conductive plug is disposed on the first semiconductor layer, and the drain of the pull-down transistor and the drain of the pull-up transistor are connected through the conductive plug.

4. The semiconductor structure according to claim 1, characterized in that: Along the first direction, two ends of the second semiconductor layer are retracted relative to the first semiconductor layer.

5. The semiconductor structure according to claim 1, characterized in that: The pull-down transistor is a dual-gate transistor and / or the pull-up transistor is a dual-gate transistor.

6. The semiconductor structure according to claim 5, characterized in that: The pull-down transistor is a double-gate transistor, and the first semiconductor layer includes a bottom first semiconductor layer and a top first semiconductor layer spaced apart along the second direction.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The conductivity type of the first semiconductor layer is opposite to the conductivity type of the second semiconductor layer.

8. A memory, characterized in that: A device comprising a substrate and at least one static random access memory unit arranged on the substrate, each of the static random access memory units comprising a first inverter and a second inverter, the first inverter, the second inverter and the inverter in the semiconductor structure according to any one of claims 1 to 7 having the same structure, an input end of the first inverter and an output end of the second inverter being connected, and an output end of the first inverter and an input end of the second inverter being connected; Each of the static random access memory cells further comprises: A first transmission transistor is disposed above the first inverter, and the first transmission transistor is connected to an input terminal of the first inverter or an output terminal of the first inverter; The second transmission transistor is arranged above the second inverter, and the second transmission transistor is connected to the output terminal of the second inverter or the input terminal of the second inverter.

9. The memory according to claim 8, characterized in that: The first inverter includes a first pull-down transistor, a first pull-up transistor, a first conductive plug, and a first common gate, the first pull-down transistor and the first pull-up transistor share the first common gate, and the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected through the first conductive plug; The second inverter includes a second pull-down transistor, a second pull-up transistor, a second conductive plug and a second common gate. The second pull-down transistor and the second pull-up transistor share the second common gate. The drain of the second pull-down transistor and the drain of the second pull-up transistor are connected through the second conductive plug. The second common gate is connected to the first conductive plug, and the second conductive plug is connected to the first common gate.

10. The memory according to claim 9, characterized in that: The memory also includes: A power supply terminal, a source of the first pull-up transistor, a source of the second pull-up transistor and the power supply terminal are connected; A ground terminal, a source of the first pull-down transistor, a source of the second pull-down transistor and the ground terminal are connected.

11. The memory according to claim 8, characterized in that: The first transfer transistor includes a drain, a channel region, and a source arranged in sequence in a direction away from the first inverter, the first transfer transistor also includes a gate, the gate of the first transfer transistor surrounds and covers the circumference of the channel region of the first transfer transistor, and the drain of the first transfer transistor is connected to the first inverter; The second transfer transistor includes a drain, a channel region and a source which are sequentially arranged in a direction away from the second inverter. The second transfer transistor also includes a gate. The gate of the second transfer transistor surrounds and covers the circumference of the channel region of the second transfer transistor. The drain of the second transfer transistor is connected to the second inverter.

12. The memory according to claim 11, characterized in that: The memory also includes: a first bit line, the first bit line being connected to the source of the first transfer transistor; a first word line, wherein the extending directions of the first word line and the first bit line intersect vertically, and the first word line is connected to the gate of the first transfer transistor; a second bit line, the second bit line being connected to the source of the second transfer transistor; A second word line, wherein the extending directions of the second word line and the second bit line intersect vertically, and the second word line is connected to the gate of the second transfer transistor.

13. A method for manufacturing a memory, characterized in that: The following steps are involved: Providing a composite substrate, the composite substrate comprising a stacked substrate base, at least one first semiconductor material layer and at least one second semiconductor material layer, wherein adjacent first semiconductor material layers and / or second semiconductor material layers are spaced apart, and the first semiconductor material layer and the second semiconductor material layer have opposite conductivity types; Etching the composite substrate to form a plurality of fin-shaped portions, wherein the fin-shaped portions extend along a first direction, and the fin-shaped portions are arranged at intervals along a third direction, wherein the first direction and the third direction are parallel to the top surface of the substrate base, the first semiconductor material layer retained in the fin-shaped portion forms a first semiconductor layer, and the second semiconductor material layer retained in the fin-shaped portion forms a second semiconductor layer, and along a direction away from the substrate base, the lengths of at least one layer of the first semiconductor layer and at least one layer of the second semiconductor layer in the fin-shaped portion in the first direction decrease in sequence; forming a common gate, the common gate extending on the substrate base along a second direction, the second direction being perpendicular to the top surface of the substrate base, the common gate covering the surface of the first semiconductor layer and the surface of the second semiconductor layer located in the middle region of the fin-shaped portion, to form a common-gate pull-down transistor and a pull-up transistor; A conductive plug is formed, and the conductive plug is arranged on one side of the fin-shaped portion along the first direction. The conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer. One end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug. The pull-down transistor and the pull-up transistor are connected through the conductive plug to form an inverter.

14. The method for manufacturing a memory according to claim 13, characterized in that: Before forming the common gate, the following steps are also included: forming a dummy gate, wherein the dummy gate extends along the third direction and covers the middle region of the fin-shaped portion arranged along the third direction; Etching the fin-shaped portion exposed by the dummy gate to remove part of the fin-shaped portion, forming a gap between adjacent first semiconductor layers and / or second semiconductor layers along the second direction, and exposing surfaces of the first semiconductor layer and the second semiconductor layer outside the middle region; An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the first semiconductor layer and the second semiconductor layer outside the middle region and fills a gap between the first semiconductor layer and / or the second semiconductor layer.

15. The method for manufacturing a memory according to claim 14, characterized in that: A common gate is formed, comprising: removing the dummy gate to expose the fin-shaped portion in the middle region; Etching and removing a portion of the fin-shaped portion in the middle region to expose surfaces of the first semiconductor layer and the second semiconductor layer in the middle region; forming a gate dielectric layer, wherein the gate dielectric layer covers surfaces of the first semiconductor layer and the second semiconductor layer in the middle region; The common gate is formed, and the common gate covers the gate dielectric layer and fills the area between the first semiconductor layer and / or the second semiconductor layer in the middle area.

16. The method for manufacturing a memory according to claim 14, characterized in that: Forming a conductive plug, comprising: forming a contact hole in the interlayer dielectric layer, wherein the contact hole exposes a portion of the surface of the first semiconductor layer and the second semiconductor layer located on one side of the middle region; The conductive plug is formed in the contact hole.

17. The method for manufacturing a memory according to claim 13, characterized in that: The method for manufacturing the memory further comprises the following steps: forming a word line, wherein the word line extends along the first direction and the word line is correspondingly arranged above the inverter; forming a transfer transistor, wherein the transfer transistor is disposed above the inverter, a gate of the transfer transistor is connected to the word line, and a drain of the transfer transistor is connected to the common gate of the inverter or the conductive plug; forming a bit line, the bit line extending above the inverter along the second direction, the bit line being connected to a source of the transfer transistor; Along the third direction, the two transfer transistors connected to the two adjacent inverters, the drain of one of the transfer transistors is connected to the common gate of one inverter, and the drain of the other of the transfer transistors is connected to the conductive plug of the other inverter.

18. The method for manufacturing a memory according to claim 13, characterized in that: A composite substrate is provided, comprising: Providing a first substrate and a second substrate, wherein the first substrate and the second substrate include a first semiconductor material, wherein the first substrate includes a first back substrate, a first buried oxide layer and a first top substrate which are arranged in sequence; The second substrate is disposed on the first top substrate, and the second substrate is bonded and connected to the first top substrate; Providing a third substrate, and epitaxially forming an epitaxial substrate layer on the third substrate, wherein the epitaxial substrate layer includes a second semiconductor material; The epitaxial substrate layer is disposed on the second substrate, and the epitaxial substrate layer is bonded to the surface of the second substrate on a side away from the first substrate; The third substrate is removed by etching, and the first substrate, the second substrate and the epitaxial substrate layer together form the composite substrate.

19. The method for manufacturing a memory according to claim 18, characterized in that: Epitaxially forming an epitaxial substrate layer on the third substrate comprises: Placing the third substrate in a reaction chamber, introducing a gas source of the first semiconductor material and a gas source of the second semiconductor material into the reaction chamber, epitaxially growing the epitaxial substrate layer on the top surface of the third substrate, and gradually reducing the content of the gas source of the first semiconductor material introduced into the reaction chamber and gradually increasing the content of the gas source of the second semiconductor material introduced into the reaction chamber during the epitaxial growth of the epitaxial substrate layer; In the process of etching and removing the third substrate, a portion of the epitaxial substrate layer is etched and removed, and a portion of the structure on the top of the epitaxial substrate layer is retained to form the composite substrate.

20. The method for manufacturing a memory according to claim 18, characterized in that: Epitaxially forming an epitaxial substrate layer on the third substrate comprises: epitaxially forming at least one second semiconductor epitaxial layer on the top surface of the third substrate, wherein the concentration of the second semiconductor material in the at least one second semiconductor epitaxial layer increases in a direction away from the top surface of the third substrate; epitaxially forming the epitaxial substrate layer on the top surface of at least one layer of the second semiconductor epitaxial layer; In the process of etching and removing the third substrate, at least one layer of the second semiconductor epitaxial layer is etched and removed.

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