Semiconductor memory device

Abstract

A semiconductor memory device (1) is provided with: a first pull-down N-channel MOS transistor (21), the drain of which is connected to a word line (20), the source of which is connected to a ground line, and the gate of which is connected to a first node (91); a first series-connected N-channel MOS transistor (22), the drain of which is connected to the power supply line and the source of which is connected to the first node (91); and a second series-connected N-channel MOS transistor (23), the drain of which is connected to the first node (91) and the source of which is connected to the ground. An inverted logic signal, which is a signal input to the gate of the second series-connected N-channel MOS transistor (23), is input to the gate of the first series-connected N-channel MOS transistor (22).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly to an SRAM (Static Random Access Memory). Background Art

[0002] Conventionally, as a technique for improving SNM (Static Noise Margin) in SRAM, there is known a technique for pulling down the voltage of an active word line to reduce the voltage.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-262637 Summary of the invention

[0006] Problems to be solved by the invention

[0007] In an SRAM, if the voltage of an active word line is lowered in order to increase SNM, the writing capability to and the reading capability from the memory cell (hereinafter also referred to as “writing / reading capability”) are reduced.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor memory device that can suppress a decrease in write / read capability and achieve a voltage drop of a word line for improving SNM.

[0009] Means for solving problems

[0010] A semiconductor storage device of one embodiment of the present invention comprises: a first pull-down N-channel MOS (Metal Oxide Semiconductor) transistor, whose drain is connected to a first word line connected to one or more first storage cells, whose source is connected to a ground line for supplying a ground voltage, and whose gate is connected to a first node; a first series-connected N-channel MOS transistor, whose drain is connected to a power line for supplying a power voltage, and whose source is connected to the first node; and a second series-connected N-channel MOS transistor, whose drain is connected to the first node, and whose source is connected to the ground line; and an inverted logic signal of a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor.

[0011] A semiconductor storage device of one embodiment of the present invention comprises: a first pull-down N-channel MOS transistor, whose drain is connected to a first word line connected to one or more first storage cells, whose source is connected to a ground line supplying a ground voltage, and whose gate is connected to a first node; a first P-channel MOS transistor, whose source is connected to a power line supplying a power voltage, and whose drain is connected to a second node; a first series-connected N-channel MOS transistor, whose drain is connected to the second node, whose source is connected to the first node, and whose gate is connected to a first control signal input terminal to which a first control signal is input; and a second series-connected N-channel MOS transistor, whose drain is connected to the first node, and whose source is connected to the ground line; a logic signal identical to the signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first P-channel MOS transistor.

[0012] Effects of the Invention

[0013] According to a semiconductor memory device of one embodiment of the present disclosure, there is provided a semiconductor memory device capable of suppressing a decrease in write / read capability and achieving a voltage drop of a word line for improving SNM. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a block diagram showing the structure of a semiconductor storage device according to Embodiment 1.

[0015] Figure 2 This is a circuit diagram showing the structure of a memory cell according to the first embodiment.

[0016] Figure 3 This is a circuit diagram showing the configuration of an auxiliary circuit according to the first embodiment.

[0017] Figure 4 This is a schematic diagram showing a state in which the assist circuit according to the first embodiment pulls down the voltage of the word line in an active state to reduce the voltage.

[0018] Figure 5 This is a block diagram showing the structure of a semiconductor storage device according to a second embodiment.

[0019] Figure 6 This is a circuit diagram showing the configuration of an auxiliary circuit according to the second embodiment.

[0020] Figure 7 This is a block diagram showing the structure of a semiconductor storage device according to a third embodiment.

[0021] Figure 8 This is a circuit diagram showing the configuration of an auxiliary circuit according to the third embodiment.

[0022] Fig. 9 This is a block diagram showing the structure of a semiconductor storage device according to a fourth embodiment.

[0023] Fig.10 This is a circuit diagram showing the structure of an auxiliary circuit according to a fourth embodiment.

[0024] Fig.11 This is a block diagram showing the structure of a semiconductor storage device according to a fifth embodiment.

[0025] Fig.12 This is a circuit diagram showing the structure of an auxiliary circuit according to the fifth embodiment.

[0026] Fig.13 This is a block diagram showing the structure of a semiconductor storage device according to a sixth embodiment.

[0027] Fig.14 This is a circuit diagram showing the structure of an auxiliary circuit according to a sixth embodiment.

[0028] Fig.15 This is a block diagram showing the structure of a semiconductor storage device according to a seventh embodiment.

[0029] Fig.16 This is a circuit diagram showing the structure of an auxiliary circuit according to a seventh embodiment.

[0030] Fig.17 This is a schematic diagram showing the relationship between process variation conditions and voltage drop amounts.

[0031] Fig.18 This is a block diagram showing the structure of a semiconductor storage device according to an eighth embodiment.

[0032] Fig.19 This is a circuit diagram showing the structure of an auxiliary circuit according to an eighth embodiment.

[0033] Fig. 20 This is a block diagram showing the structure of a semiconductor storage device according to a ninth embodiment.

[0034] Fig.21 This is a circuit diagram showing the structure of an auxiliary circuit according to a ninth embodiment.

[0035] Fig. 22 This is a block diagram showing the structure of a semiconductor storage device according to a tenth embodiment.

[0036] Fig.23 This is a circuit diagram showing the structure of an auxiliary circuit according to a tenth embodiment.

[0037] Fig.24 This is a block diagram showing the structure of a semiconductor storage device according to embodiment 11.

[0038] Fig.25 This is a circuit diagram showing the structure of the auxiliary circuit of embodiment 11.

[0039] Fig.26 This is a schematic diagram showing the relationship between process variation conditions and voltage drop amounts.

[0040] Fig. 27 This is a block diagram showing the structure of a semiconductor storage device according to embodiment 12.

[0041] Fig.28 This is a circuit diagram showing the structure of the auxiliary circuit of embodiment 12.

[0042] Fig.29 This is a block diagram showing the structure of a semiconductor storage device according to embodiment 13.

[0043] Fig.30 This is a circuit diagram showing the structure of the auxiliary circuit of embodiment 13. DETAILED DESCRIPTION

[0044] (The process of obtaining one method of the present disclosure)

[0045] Generally, when the temperature condition is a high temperature condition and when the process variation condition is a condition that an N-channel MOS (Metal Oxide Semiconductor) transistor is fast (a threshold voltage of the N-channel MOS transistor is low), the SNM becomes small.

[0046] In addition, generally, when the temperature condition is a low temperature condition and when the process variation condition is a condition where the N-channel MOS transistor is slow (the threshold voltage of the N-channel MOS transistor is high), the write / read capability is reduced.

[0047] Therefore, the inventors believe that in SRAM, if the voltage drop of the word line can be controlled so that when the temperature condition is a low temperature condition, the voltage drop of the word line in the activated state becomes smaller than when the temperature condition is a high temperature condition, and when the process deviation condition is a slow condition of the N-channel MOS transistor, the voltage drop of the word line in the activated state becomes smaller than when the process deviation condition is a fast condition of the N-channel MOS transistor, then the reduction in write and read capabilities can be suppressed without reducing SNM.

[0048] Therefore, based on the above considerations, the inventors have repeatedly conducted intensive experiments and studies on a semiconductor memory device that can suppress a decrease in write / read performance and achieve a voltage drop in a word line for improving SNM.

[0049] As a result, the inventors conceived of the semiconductor memory device of the present disclosure described below.

[0050] A semiconductor storage device of one embodiment of the present invention comprises: a first pull-down N-channel MOS (Metal Oxide Semiconductor) transistor, whose drain is connected to a first word line connected to one or more first storage cells, whose source is connected to a ground line for supplying a ground voltage, and whose gate is connected to a first node; a first series-connected N-channel MOS transistor, whose drain is connected to a power line for supplying a power voltage, and whose source is connected to the first node; and a second series-connected N-channel MOS transistor, whose drain is connected to the first node, and whose source is connected to the ground line; and an inverted logic signal of a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor.

[0051] According to the semiconductor memory device of the above structure, the voltage of the first node, that is, the gate voltage of the first pull-down N-channel MOS transistor becomes a voltage (VDD-Vtn) lower than the power supply voltage (hereinafter also referred to as "VDD") by the threshold voltage (hereinafter also referred to as "Vtn") of the N-channel MOS transistor.

[0052] Generally, Vtn is larger under a low temperature condition than under a high temperature condition, and is larger under a slow N-channel MOS transistor condition than under a fast N-channel MOS transistor condition.

[0053] Therefore, the gate voltage of the first pull-down N-channel MOS transistor is lower when the temperature condition is a low temperature condition than when the temperature condition is a high temperature condition, and is lower when the process variation condition is a slow N-channel MOS transistor condition than when the process variation condition is a fast N-channel MOS transistor condition.

[0054] In the semiconductor memory device having the above structure, the first pull-down N-channel MOS transistor pulls down the voltage of the active first word line according to its gate voltage so that the lower the gate voltage is, the smaller the pull-down voltage amount of the active first word line is.

[0055] Therefore, in the semiconductor memory device of the structure, the voltage drop amount of the first word line in the activated state is controlled so that, when the temperature condition is a low temperature condition, the voltage drop amount of the first word line becomes smaller than that when the temperature condition is a high temperature condition, and when the process deviation condition is a slow condition of the N-channel MOS transistor, the voltage drop amount of the first word line becomes smaller than that when the process deviation condition is a fast condition of the N-channel MOS transistor.

[0056] Therefore, according to the semiconductor memory device having the above structure, it is possible to provide a semiconductor memory device that can suppress a decrease in write / read capability and achieve a voltage drop of a word line for improving SNM.

[0057] In addition, it is also possible that there is also a first P-channel MOS transistor, the drain of which is connected to the drain of the first series-connected N-channel MOS transistor, the source is connected to the power line, and the gate is connected to the first control signal input terminal to which the first control signal is input, and the drain of the first series-connected N-channel MOS transistor is connected to the power line via the first P-channel MOS transistor.

[0058] Thus, by controlling the first control signal, it is possible to control whether the first pull-down N-channel MOS transistor pulls down the voltage of the first word line.

[0059] In addition, it may also be provided with: a second pull-down N-channel MOS transistor, whose drain is connected to the second word line connected to one or more second storage units, whose source is connected to the ground line, and whose gate is connected to the second node; a third series-connected N-channel MOS transistor, whose drain is connected to the drain of the first P-channel MOS transistor, and whose source is connected to the second node; and a fourth series-connected N-channel MOS transistor, whose drain is connected to the second node, and whose source is connected to the ground line; and an inverted logic signal of the signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the third series-connected N-channel MOS transistor.

[0060] According to the semiconductor memory device having the above structure, a P-channel MOS transistor located on a current path from a power supply wiring to a first node and a P-channel MOS transistor located on a current path from a power supply wiring to a second node can be provided as a common first P-channel MOS transistor.

[0061] Thus, compared with the case where a P-channel MOS transistor located on a current path from the power supply wiring to the first node and a P-channel MOS transistor located on a current path from the power supply wiring to the second node are separately formed, the area for forming the P-channel MOS transistor can be reduced.

[0062] In addition, the present invention may further include: a second pull-down N-channel MOS transistor, whose drain is connected to a second word line connected to one or more second storage cells, whose source is connected to the ground line, and whose gate is connected to the first node; a third pull-down N-channel MOS transistor, whose drain is connected to a third word line connected to one or more third storage cells, whose source is connected to the ground line, and whose gate is connected to the second node; a fourth pull-down N-channel MOS transistor, whose drain is connected to a fourth word line connected to one or more fourth storage cells, whose source is connected to the ground line, and whose gate is connected to the second node; a third serially connected N-channel MOS transistor, whose drain is connected to the first P-channel a fourth series-connected N-channel MOS transistor, having a drain connected to the second node and a source connected to the second node; a fourth series-connected N-channel MOS transistor, having a drain connected to the second node and a source connected to the ground line, and inputting an inverted logic signal of a signal input to the gate of the second series-connected N-channel MOS transistor to the gate of the first series-connected N-channel MOS transistor when the first word line and / or the second word line are activated, and inputting an inverted logic signal of a signal input to the gate of the fourth series-connected N-channel MOS transistor to the gate of the third series-connected N-channel MOS transistor when the third word line and / or the fourth word line are activated.

[0063] According to the semiconductor memory device having the above structure, a P-channel MOS transistor located on a current path from a power supply wiring to a first node and a P-channel MOS transistor located on a current path from a power supply wiring to a second node can be provided as a common first P-channel MOS transistor.

[0064] Thus, compared with the case where a P-channel MOS transistor located on a current path from the power supply wiring to the first node and a P-channel MOS transistor located on a current path from the power supply wiring to the second node are separately formed, the area for forming the P-channel MOS transistor can be reduced.

[0065] Furthermore, according to the semiconductor storage device of the above structure, an N-channel MOS transistor located on a current path from a power supply wiring to a gate of a first pull-down N-channel MOS transistor and an N-channel MOS transistor located on a current path from a power supply wiring to a gate of a second pull-down N-channel MOS transistor can be set as a common first series-connected N-channel MOS transistor, and an N-channel MOS transistor located on a current path from the gate of the first pull-down N-channel MOS transistor to a ground wiring and an N-channel MOS transistor located on a current path from the gate of the second pull-down N-channel MOS transistor to a ground wiring can be set as a common second series-connected N-channel MOS transistor.

[0066] Thus, the area used to form the N-channel MOS transistor can be reduced compared to a case where an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor are separately formed, or / and a case where an N-channel MOS transistor located on a current path from the gate of the first pull-down N-channel MOS transistor to the ground wiring and an N-channel MOS transistor located on a current path from the gate of the second pull-down N-channel MOS transistor to the ground wiring are separately formed.

[0067] Furthermore, according to the semiconductor storage device of the above structure, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor can be set as a common third series-connected N-channel MOS transistor, and an N-channel MOS transistor located on a current path from the gate of the third pull-down N-channel MOS transistor to the ground wiring and an N-channel MOS transistor located on a current path from the gate of the fourth pull-down N-channel MOS transistor to the ground wiring can be set as a common fourth series-connected N-channel MOS transistor.

[0068] Thus, the area used to form the N-channel MOS transistor can be reduced compared to a case where an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor are separately formed, or / and a case where an N-channel MOS transistor located on a current path from the gate of the third pull-down N-channel MOS transistor to the ground wiring and an N-channel MOS transistor located on a current path from the gate of the fourth pull-down N-channel MOS transistor to the ground wiring are separately formed.

[0069] In addition, it may also be that it further comprises: a second pull-down N-channel MOS transistor, whose drain is connected to the first word line, whose source is connected to the ground line, and whose gate is connected to the second node; a second P-channel MOS transistor, whose drain is connected to the third node, whose source is connected to the power line, and whose gate is connected to the second control signal input terminal to which the second control signal is input; a third series-connected N-channel MOS transistor, whose drain is connected to the third node, and whose source is connected to the second node; and a fourth series-connected N-channel MOS transistor, whose drain is connected to the second node, and whose source is connected to the ground line, wherein the same logic signal as the signal input to the gate of the third series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor; and the same logic signal as the signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the second series-connected N-channel MOS transistor.

[0070] Thus, it is possible to select whether to use the first pull-down N-channel MOS transistor to pull down the first word line, or to use the second pull-down N-channel MOS transistor to pull down the first word line, or to use the first pull-down N-channel MOS transistor and the second pull-down N-channel MOS transistor to pull down the first word line, or to not pull down the first word line.

[0071] A semiconductor storage device of one embodiment of the present invention comprises: a first pull-down N-channel MOS transistor, whose drain is connected to a first word line connected to one or more first storage cells, whose source is connected to a ground line for supplying a ground voltage, and whose gate is connected to a first node; a first P-channel MOS transistor, whose source is connected to a power line for supplying a power voltage, and whose drain is connected to a second node; a first series-connected N-channel MOS transistor, whose drain is connected to the second node, whose source is connected to the first node, and whose gate is connected to a first control signal input terminal for inputting a first control signal; and a second series-connected N-channel MOS transistor, whose drain is connected to the first node, and whose source is connected to the ground line; a logic signal identical to the signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first P-channel MOS transistor.

[0072] According to the semiconductor memory device having the above configuration, the voltage of the first node when the first P-channel MOS transistor is in the on state, that is, the gate voltage of the first pull-down N-channel MOS transistor becomes VDD-Vtn.

[0073] Generally, Vtn is larger under a low temperature condition than under a high temperature condition, and is larger under a slow N-channel MOS transistor condition than under a fast N-channel MOS transistor condition.

[0074] Therefore, the gate voltage of the first pull-down N-channel MOS transistor is lower when the temperature condition is a low temperature condition than when the temperature condition is a high temperature condition, and is lower when the process variation condition is a slow N-channel MOS transistor condition than when the process variation condition is a fast N-channel MOS transistor condition.

[0075] In the semiconductor memory device having the above structure, the first pull-down N-channel MOS transistor pulls down the voltage of the active first word line according to its gate voltage so that the lower the gate voltage is, the smaller the pull-down voltage amount of the active first word line is.

[0076] Therefore, in the semiconductor memory device of the structure, the voltage drop amount of the first word line in the activated state is controlled so that, when the temperature condition is a low temperature condition, the voltage drop amount of the first word line becomes smaller than that when the temperature condition is a high temperature condition, and when the process deviation condition is a slow condition of the N-channel MOS transistor, the voltage drop amount of the first word line becomes smaller than that when the process deviation condition is a fast condition of the N-channel MOS transistor.

[0077] Therefore, according to the semiconductor memory device having the above structure, it is possible to provide a semiconductor memory device that can suppress a decrease in write / read capability and achieve a voltage drop of a word line for improving SNM.

[0078] Furthermore, according to the semiconductor memory device having the above structure, by controlling the first control signal, it is possible to control whether the first pull-down N-channel MOS transistor pulls down the voltage of the first word line.

[0079] Furthermore, a second pull-down N-channel MOS transistor may be further provided, wherein the drain of the second pull-down N-channel MOS transistor is connected to a second word line connected to one or more second memory cells, the source is connected to the ground line, and the gate is connected to the first node.

[0080] According to the semiconductor storage device of the above structure, an N-channel MOS transistor located on a current path from a power supply wiring to a gate of a first pull-down N-channel MOS transistor and an N-channel MOS transistor located on a current path from a power supply wiring to a gate of a second pull-down N-channel MOS transistor can be set as a common first series-connected N-channel MOS transistor, and an N-channel MOS transistor located on a current path from the gate of the first pull-down N-channel MOS transistor to a ground wiring and an N-channel MOS transistor located on a current path from the gate of the second pull-down N-channel MOS transistor to a ground wiring can be set as a common second series-connected N-channel MOS transistor.

[0081] Therefore, compared with the case where an N-channel MOS transistor located on the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor and an N-channel MOS transistor located on the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor are separately formed, the size of the first series-connected N-channel MOS transistor can be increased.

[0082] This can suppress variations in Vtn of the first series-connected N-channel MOS transistors.

[0083] Furthermore, a second pull-down N-channel MOS transistor may be further provided, wherein a drain of the second pull-down N-channel MOS transistor is connected to the first word line, a source of the second pull-down N-channel MOS transistor is connected to the ground line, and a gate of the second pull-down N-channel MOS transistor is connected to the power line.

[0084] According to the semiconductor memory device having the above structure, the voltage of the first word line is pulled down by the first pull-down N-channel MOS transistor having a gate voltage of VDD-Vtn and the second pull-down N-channel MOS transistor having a gate voltage of VDD.

[0085] Thus, the voltage drop amount of the first word line can be controlled more sensitively.

[0086] Furthermore, a threshold value of the first series-connected N-channel MOS transistor may be lower than threshold values ​​of the first pull-down N-channel MOS transistor and the second series-connected N-channel MOS transistor.

[0087] According to the semiconductor memory device with the above structure, when the power supply voltage is reduced, the gate voltage of the first pull-down N-channel MOS transistor becomes lower than the threshold voltage of the first pull-down N-channel MOS transistor. As a result, the occurrence of the inadequate situation in which the first pull-down N-channel MOS transistor cannot pull down the first word line can be suppressed.

[0088] Therefore, the low voltage operation region of the pull-down operation of the first word line can be expanded.

[0089] In addition, it may also be that it further comprises: a second pull-down N-channel MOS transistor, whose drain is connected to the first word line, whose source is connected to the ground line, and whose gate is connected to the third node; a second P-channel MOS transistor, whose source is connected to the power line, and whose drain is connected to the fourth node; a third series-connected N-channel MOS transistor, whose drain is connected to the fourth node, whose source is connected to the third node, and whose gate is connected to a second control signal input terminal to which a second control signal is input; and a fourth series-connected N-channel MOS transistor, whose drain is connected to the third node, and whose source is connected to the ground line; and a logic signal identical to the signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the second P-channel MOS transistor and the gate of the fourth series-connected N-channel MOS transistor.

[0090] Thus, it is possible to select whether to use the first pull-down N-channel MOS transistor to pull down the first word line, or to use the second pull-down N-channel MOS transistor to pull down the first word line, or to use the first pull-down N-channel MOS transistor and the second pull-down N-channel MOS transistor to pull down the first word line, or to not pull down the first word line.

[0091] Hereinafter, a specific example of a semiconductor storage device of one embodiment of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown here all represent a specific example of the present disclosure. Therefore, the numerical values, shapes, constituent elements, configurations and connection methods of constituent elements, and steps (processes) and the order of steps shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and may not be strictly illustrated. In each figure, the same figure mark is marked for substantially the same structure, and repeated descriptions are omitted or simplified.

[0092] (Implementation Method 1)

[0093] Hereinafter, a semiconductor memory device according to Embodiment 1 will be described. The semiconductor memory device according to Embodiment 1 is an SRAM having a word line, and in order to improve SNM, the voltage of the word line in an active state is pulled down to reduce the voltage.

[0094] <Structure>

[0095] Figure 1 This is a block diagram showing the structure of a semiconductor storage device according to Embodiment 1.

[0096] like Figure 1 As shown, the semiconductor memory device 1 includes a memory cell array 50 , a row decoder 60 , an I / O circuit 70 , a control unit 80 , a plurality of word lines 20 , and a plurality of auxiliary circuits 10 .

[0097] The memory cell array 50 is formed by arranging a plurality of memory cells 40 in a matrix.

[0098] The plurality of memory cells 40 constituting the memory cell array 50 are connected to one common word line 20 for each row. That is, the semiconductor memory device 1 includes word lines 20 as many as the number of rows of the memory cell array 50 .

[0099] The memory cell array 50 further includes a pair of bit lines 28 and inverted bit lines 29 for each column. Moreover, the plurality of memory cells 40 constituting the memory cell array 50 are connected to a common pair of bit lines 28 and inverted bit lines 29 for each column. That is, the memory cell array 50 includes pairs of bit lines 28 and inverted bit lines 29 as many as the number of columns of the memory cell array 50.

[0100] Figure 2 is a circuit diagram showing the structure of the memory cell 40 .

[0101] like Figure 2 As shown, the memory cell 40 is connected to the word line 20, the bit line 28, and the inverted bit line 29, and is composed of six transistors, namely, an access transistor 41 which is an N-channel MOS transistor, an access transistor 42 which is an N-channel MOS transistor, a load transistor 43 which is a P-channel MOS transistor, a load transistor 44 which is a P-channel MOS transistor, a drive transistor 45 which is an N-channel MOS transistor, and a drive transistor 46 which is an N-channel MOS transistor.

[0102] Back again Figure 1 , the semiconductor storage device 1 is further described.

[0103] Each of the plurality of word lines 20 is connected to one or more memory cells 40 forming a row of the memory cell array.

[0104] The row decoder 60 selects a row of the memory cell array 50. More specifically, the row decoder 60 includes a plurality of word line drivers 30 that drive the plurality of word lines 20 in a one-to-one manner, and one of the plurality of word line drivers 30 drives one of the plurality of word lines 20 to be activated, thereby selecting a row consisting of one or more memory cells 40 connected to the one word line 20 that is set to the activated state.

[0105] The I / O circuit 70 writes data to the memory cell array 50 and reads data held in the memory cell array 50 .

[0106] The control unit 80 controls the memory cell array 50 , the row decoder 60 , the I / O circuit 70 , and the plurality of auxiliary circuits 10 .

[0107] The assist circuit 10 pulls down the voltage of the word line 20 in the active state to reduce the voltage.

[0108] Each of the plurality of auxiliary circuits 10 is connected one-to-one to each of the plurality of word lines 20 . That is, the semiconductor memory device 1 includes the auxiliary circuits 10 as many as the number of word lines 20 .

[0109] Figure 3 : is a circuit diagram showing the structure of the auxiliary circuit 10.

[0110] like Figure 3 As shown, the auxiliary circuit 10 comprises: a first pull-down N-channel MOS transistor 21, whose drain is connected to the word line 20, whose source is connected to the ground line for supplying the ground voltage (VSS), and whose gate is connected to the first node 91; a first series-connected N-channel MOS transistor 22, whose drain is connected to the power line for supplying the power voltage (VDD), and whose source is connected to the first node 91; and a second series-connected N-channel MOS transistor 23, whose drain is connected to the first node 91, and whose source is connected to the ground line.

[0111] The auxiliary circuit 10 further includes an inverter 24 connected so that an inverted logic signal of a signal input to a gate of the second series-connected N-channel MOS transistor 23 is input to a gate of the first series-connected N-channel MOS transistor 22 .

[0112] <Inspection>

[0113] Figure 4 This is a schematic diagram showing a state in which the assist circuit 10 pulls down the voltage of the word line 20 in an active state to reduce the voltage.

[0114] In the auxiliary circuit 10, when a logic value of 0 is input to the terminal c0, that is, when the voltage of the terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0115] Thus, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes VDD-Vtn.

[0116] Generally, Vtn is larger under a low temperature condition than under a high temperature condition, and is larger under a slow N-channel MOS transistor condition than under a fast N-channel MOS transistor condition.

[0117] Therefore, if Figure 4 As shown, the voltage VDD-Vtn of the first node 91, i.e., the gate voltage VDD-Vtn of the first pull-down N-channel MOS transistor 21, is lower when the temperature condition is a low temperature condition than when the temperature condition is a high temperature condition, and is lower when the process deviation condition is a slow condition for the N-channel MOS transistor than when the process deviation condition is a fast condition for the N-channel MOS transistor.

[0118] In the assist circuit 10 , the first pull-down N-channel MOS transistor 21 pulls down the voltage of the active word line 20 in accordance with the gate voltage thereof such that the pull-down voltage amount Vpd of the active word line 20 decreases as the gate voltage decreases.

[0119] Therefore, if Figure 4 As shown, in the semiconductor memory device 1, the voltage drop amount of the word line 20 in the activated state is controlled so that, when the temperature condition is a low temperature condition, the voltage drop amount Vpd of the word line 20 becomes smaller than that when the temperature condition is a high temperature condition, and when the process deviation condition is a slow condition of the N-channel MOS transistor, the voltage drop amount Vpd of the word line 20 becomes smaller than that when the process deviation condition is a fast condition of the N-channel MOS transistor.

[0120] Therefore, according to the semiconductor memory device 1 having the above-described structure, it is possible to suppress a decrease in write / read performance and realize a voltage drop of the word line for improving SNM.

[0121] (Implementation Method 2)

[0122] Hereinafter, a semiconductor storage device according to a second embodiment having a configuration partially modified from semiconductor storage device 1 according to the first embodiment will be described.

[0123] Here, regarding the semiconductor storage device of Embodiment 2, components identical to those of semiconductor storage device 1 are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on differences from semiconductor storage device 1 .

[0124] <Structure>

[0125] Figure 5 This is a block diagram showing the structure of a semiconductor memory device 1A according to the second embodiment.

[0126] like Figure 5 As shown, semiconductor memory device 1A is configured by adding a first control signal input terminal CNT0 to semiconductor memory device 1 of Embodiment 1 and changing auxiliary circuit 10 to auxiliary circuit 10A.

[0127] The first control signal input terminal CNT0 is a terminal to which a first control signal is input from outside the semiconductor memory device 1A. The first control signal input terminal CNT0 is connected to a first P-channel MOS transistor 25 (see the following) included in each of the plurality of auxiliary circuits 10A. Figure 6 ) are all gate connections.

[0128] Figure 6 : is a circuit diagram showing the structure of the auxiliary circuit 10A.

[0129] like Figure 6 As shown, the auxiliary circuit 10A is configured by adding a first P-channel MOS transistor 25 between the drain of the first series-connected N-channel MOS transistor 22 and the power line, compared to the auxiliary circuit 10 of Embodiment 1. More specifically, the auxiliary circuit 10A is configured by adding a first P-channel MOS transistor 25 whose drain is connected to the drain of the first series-connected N-channel MOS transistor 22 and whose source is connected to the power line.

[0130] In addition, the gate of the first P-channel MOS transistor 25 is connected to the first control signal input terminal CNT0 via the terminal sel0.

[0131] <Inspection>

[0132] In the auxiliary circuit 10A having the above-described structure, the drain of the first series-connected N-channel MOS transistor 22 is connected to the power supply line via the first P-channel MOS transistor 25 .

[0133] Therefore, when the first control signal having a logic value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive, and thus, similarly to the auxiliary circuit 10 of embodiment 1, in the auxiliary circuit 10A, when a logic value of 0 is input to the terminal c0, that is, when the voltage of the terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0134] Thus, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes VDD-Vtn.

[0135] On the other hand, when the first control signal having a logical value of 1 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0136] Therefore, in the auxiliary circuit 10A, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive, and the voltage of the first node 91 is reset (becomes VSS). Then, the voltage of the first node 91 will not become higher than VSS, that is, the first pull-down N-channel MOS transistor 21 will not pull down the voltage of the activated word line 20 to reduce the voltage.

[0137] As described above, according to the semiconductor memory device 1A having the above configuration, by controlling the first control signal, it is possible to control whether the function of lowering the voltage of the active word line 20 (hereinafter also referred to as “assist function”) is enabled.

[0138] Thus, a user who uses semiconductor storage device 1A can evaluate the characteristics of storage cell 40 in a state where the auxiliary function is not enabled.

[0139] In addition, this allows a user who uses semiconductor storage device 1A to disable the auxiliary function when using semiconductor storage device 1A with relatively high write / read capabilities, such as when using semiconductor storage device 1A with a relatively high power supply voltage.

[0140] In addition, this makes it possible to relatively easily implement power cutoff control for suppressing leakage current.

[0141] (Implementation 3)

[0142] Hereinafter, a semiconductor storage device according to a third embodiment having a configuration partially modified from semiconductor storage device 1A according to the second embodiment will be described.

[0143] Here, regarding the semiconductor storage device of Embodiment 3, components identical to those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on differences from semiconductor storage device 1A.

[0144] <Structure>

[0145] Figure 7 This is a block diagram showing the structure of a semiconductor memory device 1B according to the third embodiment.

[0146] like Figure 7 As shown, semiconductor storage device 1B is configured such that auxiliary circuit 10A is replaced with auxiliary circuit 10B compared to semiconductor storage device 1A of the second embodiment.

[0147] Here, the first control signal input terminal CNT0 is connected to a first series-connected N-channel MOS transistor 22B (see hereinafter) included in each of the plurality of auxiliary circuits 10B. Figure 8 ) are all gate connections.

[0148] Figure 8 : is a circuit diagram showing the structure of the auxiliary circuit 10B.

[0149] like Figure 8 As shown, the auxiliary circuit 10B is configured such that the inverter 24 is deleted from the auxiliary circuit 10 of the first embodiment, the first series-connected N-channel MOS transistor 22 is replaced by a first series-connected N-channel MOS transistor 22B, and the first P-channel MOS transistor 25 is replaced by a first P-channel MOS transistor 25B.

[0150] The same logic signal (here, the same signal) as the signal input to the gate of the second series-connected N-channel MOS transistor 23 is input to the gate of the first series-connected N-channel MOS transistor 22B.

[0151] In addition, the gate of the first series-connected N-channel MOS transistor 22B is connected to the first control signal input terminal CNT0 via the terminal sel0.

[0152] <Inspection>

[0153] In the auxiliary circuit 10B having the above-described structure, the drain of the first series-connected N-channel MOS transistor 22B (ie, the second node 92B) is connected to the power supply line via the first P-channel MOS transistor 25B.

[0154] Therefore, when the first control signal of logic value 1 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, the first series-connected N-channel MOS transistor 22B becomes conductive, and therefore in the auxiliary circuit 10B, when the logic value 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first P-channel MOS transistor 25B becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0155] Thus, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes VDD-Vtn.

[0156] On the other hand, when the first control signal having a logical value of 0 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VSS, the first series-connected N-channel MOS transistor 22B is in a non-conductive state.

[0157] Therefore, in the auxiliary circuit 10B, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive, and the voltage of the first node 91 is reset (becomes VSS). Then, the voltage of the first node 91 will not become higher than VSS, that is, the first pull-down N-channel MOS transistor 21 will not pull down the voltage of the activated word line 20 to reduce the voltage.

[0158] As described above, according to semiconductor storage device 1B having the above configuration, similarly to semiconductor storage device 1A according to the second embodiment, whether or not the auxiliary function is enabled can be controlled by controlling the first control signal.

[0159] (Implementation 4)

[0160] Hereinafter, a semiconductor storage device according to a fourth embodiment having a configuration partially modified from semiconductor storage device 1A according to the second embodiment will be described.

[0161] Here, regarding the semiconductor storage device of Embodiment 4, components identical to those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on differences from semiconductor storage device 1A.

[0162] <Structure>

[0163] Fig. 9 This is a block diagram showing the structure of a semiconductor memory device 1C according to a fourth embodiment.

[0164] like Fig. 9 As shown, semiconductor storage device 1C is configured such that two auxiliary circuits 10A are replaced with one auxiliary circuit 10C compared to semiconductor storage device 1A of the second embodiment.

[0165] That is, each of the plurality of auxiliary circuits 10C is connected to two word lines 20. Therefore, the semiconductor memory device 1C includes auxiliary circuits 10C which are 1 / 2 the number of word lines 20.

[0166] Here, the first control signal input terminal CNT0 is connected to the first P-channel MOS transistor 25 (see the following description) provided in each of the plurality of auxiliary circuits 10C. Fig.10 ) of all gates.

[0167] Fig.10 1 is a circuit diagram showing the structure of the auxiliary circuit 10C. Here, one of the two word lines 20 connected to the auxiliary circuit 10C is referred to as word line 20WL0, and the other is referred to as word line 20WL1. That is, among the two word lines 20 connected to the auxiliary circuit 10C, the word line 20 connected to one or more memory cells 40 forming a row (for example, row 0) of the memory cell array 50 is referred to as word line 20WL0, and the word line 20 connected to one or more memory cells 40 forming another row (for example, row 1) of the memory cell array 50 is referred to as word line 20WL1.

[0168] like Fig.10As shown, the auxiliary circuit 10C is configured by adding a second pull-down N-channel MOS transistor 21C, a third series-connected N-channel MOS transistor 22C, and a fourth series-connected N-channel MOS transistor 23C relative to the auxiliary circuit 10A of embodiment 2, wherein the drain of the second pull-down N-channel MOS transistor 21C is connected to the word line 20 (here, word line 20WL1), the source is connected to the ground line, and the gate is connected to the second node 91C, the drain of the third series-connected N-channel MOS transistor 22C is connected to the drain of the first P-channel MOS transistor 25, the source is connected to the second node 91C, and the drain of the fourth series-connected N-channel MOS transistor 23C is connected to the second node 91C, and the source is connected to the ground line.

[0169] The auxiliary circuit 10C is configured by adding an inverter 24C to the auxiliary circuit 10A. The inverter 24 is connected so that the gate of the third series-connected N-channel MOS transistor 22C receives an inverted logic signal of the signal input to the gate of the fourth series-connected N-channel MOS transistor 23C.

[0170] <Inspection>

[0171] In the auxiliary circuit 10C having the above-described structure, the drain of the third series-connected N-channel MOS transistor 22C is connected to the power supply line via the first P-channel MOS transistor 25 .

[0172] Therefore, when the first control signal of logic value 0 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive, and therefore in the auxiliary circuit 10C, when logic value 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the third series-connected N-channel MOS transistor 22C becomes conductive, and the fourth series-connected N-channel MOS transistor 23C becomes non-conductive.

[0173] As a result, the voltage of the second node 91C, that is, the gate voltage of the second pull-down N-channel MOS transistor 21C becomes VDD-Vtn.

[0174] On the other hand, when the first control signal having a logical value of 1 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0175] Therefore, in the auxiliary circuit 10C, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the fourth series-connected N-channel MOS transistor 23C becomes conductive and the voltage of the second node 91C is reset (becomes VSS). Then, the voltage of the second node 91C will not become higher than VSS, that is, the second pull-down N-channel MOS transistor 21C will not pull down the voltage of the activated word line 20WL1 to reduce the voltage.

[0176] As described above, according to the semiconductor memory device 1C having the above configuration, whether or not to enable the auxiliary function of the word line 20 in the active state can be controlled by controlling the first control signal.

[0177] In the auxiliary circuit 10C having the above configuration, the P-channel MOS transistor located on the current path from the power supply wiring to the first node 91 and the P-channel MOS transistor located on the current path from the power supply wiring to the second node 91C can be provided as a common first P-channel MOS transistor 25 .

[0178] Thus, compared with the case where a P-channel MOS transistor located on the current path from the power supply wiring to the first node 91 and a P-channel MOS transistor located on the current path from the power supply wiring to the second node 91C are separately formed, the area for forming the P-channel MOS transistor can be reduced.

[0179] Furthermore, in Embodiment 4, it is described that the auxiliary circuit 10C is configured by adding a circuit group consisting of a second pull-down N-channel MOS transistor 21C, a third series-connected N-channel MOS transistor 22C, a fourth series-connected N-channel MOS transistor 23C, and an inverter 24C relative to the auxiliary circuit 10A of Embodiment 2, and is capable of controlling whether the auxiliary function of the two word lines 20 (word line 20WL0 and word line 20WL1) in the activated state is enabled.

[0180] In contrast, as another configuration example, the auxiliary circuit 10C can be configured by adding N (N is an integer greater than 2) of the above-mentioned circuit groups to the auxiliary circuit 10A of embodiment 2, and can control whether the auxiliary function of more than N+1 word lines 20 in the activated state is effective.

[0181] In this case, the semiconductor memory device 1C includes 1 / (N+1) auxiliary circuits 10C, which is the number of word lines 20 .

[0182] (Implementation method 5)

[0183] Hereinafter, a semiconductor storage device according to a fifth embodiment having a configuration partially modified from semiconductor storage device 1A according to the second embodiment will be described.

[0184] Here, regarding the semiconductor storage device of Embodiment 5, components identical to those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on differences from semiconductor storage device 1A.

[0185] <Structure>

[0186] Fig.11 This is a block diagram showing the structure of a semiconductor memory device 1D according to a fifth embodiment.

[0187] like Fig.11 As shown, semiconductor memory device 1D is configured such that eight auxiliary circuits 10A are replaced with one auxiliary circuit 10D compared to semiconductor memory device 1A of the second embodiment.

[0188] That is, each of the plurality of auxiliary circuits 10D is connected to eight word lines 20. Therefore, the semiconductor memory device 1D includes auxiliary circuits 10D which are 1 / 8 the number of word lines 20.

[0189] Here, the first control signal input terminal CNT0 is connected to the first P-channel MOS transistor 25 (see the following description) provided in each of the plurality of auxiliary circuits 10D. Fig.12 ) of all gates.

[0190] Fig.128 word lines 20 connected to the auxiliary circuit 10D are referred to as word line 20WL0, word line 20WL1, word line 20WL2, word line 20WL3, word line 20WL4, word line 20WL5, word line 20WL6, and word line 20WL7. That is, among the eight word lines 20 connected to the auxiliary circuit 10D, the word line 20 connected to one or more memory cells 40 forming a certain row (for example, the 0th row) of the memory cell array 50 is referred to as word line 20WL0, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 1st row) of the memory cell array 50 is referred to as word line 20WL1, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 2nd row) of the memory cell array 50 is referred to as word line 20WL2, and the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 3rd row) of the memory cell array 50 is referred to as word line 20WL1. Word line 20WL3, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 4th row) of the memory cell array 50 is called word line 20WL4, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 5th row) of the memory cell array 50 is called word line 20WL5, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 6th row) of the memory cell array 50 is called word line 20WL6, and the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 7th row) of the memory cell array 50 is called word line 20WL7.

[0191] like Fig.12As shown, the auxiliary circuit 10D is configured by adding the following transistors to the auxiliary circuit 10A of the second embodiment: a second pull-down N-channel MOS transistor 21D1, whose drain is connected to the word line 20 (here, word line 20WL1), whose source is connected to the ground line, and whose gate is connected to the first node 91; and a third pull-down N-channel MOS transistor 21D2, whose drain is connected to the word line 20 (here, word line 20WL2), whose source is connected to the ground line, and whose gate is connected to the first node 91; a fourth pull-down N-channel MOS transistor 21D3, whose drain is connected to the word line 20 (here, word line 20WL3), whose source is connected to the ground line, and whose gate is connected to the first node 91; and a fifth pull-down N-channel MOS transistor 21D4, whose drain is connected to the word line 20 (here, word line 20WL4), whose source is connected to the ground line, and whose gate is connected to the second node 91D. a sixth pull-down N-channel MOS transistor 21D5, whose drain is connected to the word line 20 (here, word line 20WL5), whose source is connected to the ground line, and whose gate is connected to the second node 91D; a seventh pull-down N-channel MOS transistor 21D6, whose drain is connected to the word line 20 (here, word line 20WL6), whose source is connected to the ground line, and whose gate is connected to the second node 91D; an eighth pull-down N-channel MOS transistor 21D7, whose drain is connected to the word line 20 (here, word line 20WL7), whose source is connected to the ground line, and whose gate is connected to the second node 91D; a third series-connected N-channel MOS transistor 22D, whose drain is connected to the drain of the first P-channel MOS transistor 25, and whose source is connected to the second node 91D; and a fourth series-connected N-channel MOS transistor 23D, whose drain is connected to the second node 91D, and whose source is connected to the ground line.

[0192] The auxiliary circuit 10D is further configured by deleting the inverter 24 and adding the following circuits relative to the auxiliary circuit 10A: a NAND circuit 26 connected so that when the word line 20WL0, the word line 20WL1, the word line 20WL2 and / or the word line WL3 are activated (here, when a signal of a logic value of 1 is input to the terminal Rdec0), an inverted logic signal of a signal input to the gate of the second series-connected N-channel MOS transistor 23 is input to the gate of the first series-connected N-channel MOS transistor 22; and a NAND circuit 26D connected so that when the word line 20WL4, the word line 20WL5, the word line 20WL6 and / or the word line WL7 are activated (here, when a signal of a logic value of 1 is input to the terminal Rdec1), an inverted logic signal of a signal input to the gate of the fourth series-connected N-channel MOS transistor 23D is input to the gate of the third series-connected N-channel MOS transistor 22D.

[0193] <Inspection>

[0194] In the auxiliary circuit 10D having the above-described structure, the drain of the first series-connected N-channel MOS transistor 22 is connected to the power supply line via the first P-channel MOS transistor 25 .

[0195] Therefore, when a signal with a logic value of 0 is input from the terminal Rdec0, that is, when the voltage of the terminal Rdec0 is VSS, when a first control signal with a logic value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive, and therefore in the auxiliary circuit 10D, when a logic value of 0 is input to the terminal c0, that is, when the voltage of the terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive, and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0196] Thus, the voltage of the first node 91, that is, the gate voltages of the first pull-down N-channel MOS transistor 21D1, the second pull-down N-channel MOS transistor 21D2, and the fourth pull-down N-channel MOS transistor 21D3, becomes VDD-Vtn.

[0197] On the other hand, when the first control signal having a logical value of 1 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0198] Therefore, in the auxiliary circuit 10D, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive, and the voltage of the first node 91 is reset (becomes VSS), then, thereafter, the voltage of the first node 91 will not become higher than VSS, that is, the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21D1, the third pull-down N-channel MOS transistor 21D2 and the fourth pull-down N-channel MOS transistor 21D3 will not pull down the voltages of the activated word lines 20WL0, 20WL1, 20WL2 and 20WL3, respectively.

[0199] Furthermore, when a signal with a logic value of 0 is input from the terminal Rdec1, that is, when the voltage of the terminal Rdec1 is VSS, when a first control signal with a logic value of 0 is input from the first control signal input terminal CNT0, that is, when the voltage of the terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive, and therefore, in the auxiliary circuit 10D, when a logic value of 0 is input to the terminal c0, that is, when the voltage of the terminal c0 becomes VSS, the third series-connected N-channel MOS transistor 22D becomes conductive, and the fourth series-connected N-channel MOS transistor 23D becomes non-conductive.

[0200] Thus, the voltage of the second node 91D, that is, the gate voltages of the fifth pull-down N-channel MOS transistor 21D4 , the sixth pull-down N-channel MOS transistor 21D5 , the seventh pull-down N-channel MOS transistor 21D6 , and the eighth pull-down N-channel MOS transistor 21D7 become VDD-Vtn.

[0201] On the other hand, when the first control signal having a logical value of 1 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0202] Therefore, in the auxiliary circuit 10D, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the fourth series-connected N-channel MOS transistor 23D becomes conductive and the voltage of the second node 91D is reset (becomes VSS). Then, thereafter, the voltage of the second node 91D will not become higher than VSS, that is, the fifth pull-down N-channel MOS transistor 21D4, the sixth pull-down N-channel MOS transistor 21D5, the seventh pull-down N-channel MOS transistor 21D6 and the eighth pull-down N-channel MOS transistor 21D7 will not pull down the voltages of the activated word lines 20WL4, 20WL5, 20WL6 and 20WL7, respectively.

[0203] As described above, according to the semiconductor memory device 1D having the above configuration, whether or not to enable the auxiliary function of the word line 20 in the active state can be controlled by controlling the first control signal.

[0204] In the auxiliary circuit 10D having the above configuration, the P-channel MOS transistor located on the current path from the power supply wiring to the first node 91 and the P-channel MOS transistor located on the current path from the power supply wiring to the second node 91C can be provided as a common first P-channel MOS transistor 25 .

[0205] Thus, compared with the case where a P-channel MOS transistor located on the current path from the power supply wiring to the first node 91 and a P-channel MOS transistor located on the current path from the power supply wiring to the second node 91D are separately formed, the area for forming the P-channel MOS transistor can be reduced.

[0206] Furthermore, in the auxiliary circuit 10D having the above-described structure, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21D1, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21D2, and the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21D3 can be set as a common first series-connected N-channel MOS transistor. The OS transistor 22 can also be used to connect an N-channel MOS transistor located on a current path from the gate of the first pull-down N-channel MOS transistor 21 to the ground wiring, an N-channel MOS transistor located on a current path from the gate of the second pull-down N-channel MOS transistor 21D1 to the ground wiring, an N-channel MOS transistor located on a current path from the gate of the third pull-down N-channel MOS transistor 21D2 to the ground wiring, and an N-channel MOS transistor located on a current path from the gate of the fourth pull-down N-channel MOS transistor 21D3 to the ground wiring to be set as a common second series-connected N-channel MOS transistor 23.

[0207] Thus, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21D, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21D1, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21D2, and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21D3 are formed respectively, or / and N-channel MOS transistors located on a current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21D3 are formed respectively. The area used to form the N-channel MOS transistors can be reduced compared to the case of an N-channel MOS transistor on the current path from the gate of the first pull-down N-channel MOS transistor 21 to the ground wiring, an N-channel MOS transistor on the current path from the gate of the second pull-down N-channel MOS transistor 21D1 to the ground wiring, an N-channel MOS transistor on the current path from the gate of the third pull-down N-channel MOS transistor 21D2 to the ground wiring, and an N-channel MOS transistor on the current path from the gate of the fourth pull-down N-channel MOS transistor 21D3 to the ground wiring.

[0208] Furthermore, in the auxiliary circuit 10D having the above-described structure, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the fifth pull-down N-channel MOS transistor 21D4, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the sixth pull-down N-channel MOS transistor 21D5, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the seventh pull-down N-channel MOS transistor 21D6, and the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the eighth pull-down N-channel MOS transistor 21D7 can be set as a common third series-connected N-channel MOS transistor. S transistor 22D, and an N-channel MOS transistor located on a current path from the gate of the fifth pull-down N-channel MOS transistor 21D4 to the ground wiring, an N-channel MOS transistor located on a current path from the gate of the sixth pull-down N-channel MOS transistor 21D5 to the ground wiring, an N-channel MOS transistor located on a current path from the gate of the seventh pull-down N-channel MOS transistor 21D6 to the ground wiring, and an N-channel MOS transistor located on a current path from the gate of the eighth pull-down N-channel MOS transistor 21D7 to the ground wiring are set to a common fourth series-connected N-channel MOS transistor 23D.

[0209] Thus, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the fifth pull-down N-channel MOS transistor 21D4, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the sixth pull-down N-channel MOS transistor 21D5, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the seventh pull-down N-channel MOS transistor 21D6, and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the eighth pull-down N-channel MOS transistor 21D7 are formed, or / and N-channel MOS transistors located on a current path from the power supply wiring to the gate of the eighth pull-down N-channel MOS transistor 21D7 are formed. Compared with the N-channel MOS transistor on the current path from the gate of the fifth pull-down N-channel MOS transistor 21D4 to the ground wiring, the N-channel MOS transistor on the current path from the gate of the sixth pull-down N-channel MOS transistor 21D5 to the ground wiring, the N-channel MOS transistor on the current path from the gate of the seventh pull-down N-channel MOS transistor 21D6 to the ground wiring, and the N-channel MOS transistor on the current path from the gate of the eighth pull-down N-channel MOS transistor 21D7 to the ground wiring, the area used to form the N-channel MOS transistor can be reduced.

[0210] In the fifth embodiment, the auxiliary circuit 10D is described assuming that the number M of pull-down N-channel MOS transistors whose gates are connected to the first node 91 and the number M of N-channel MOS transistors connected to the second node 91D are four.

[0211] On the other hand, as another configuration example, M may be an integer other than 4 and greater than 2.

[0212] In this case, the semiconductor memory device 1D includes ½M auxiliary circuits 10D, which is the number of word lines 20 .

[0213] (Implementation 6)

[0214] Hereinafter, a semiconductor storage device according to a sixth embodiment having a structure partially modified from semiconductor storage device 1A according to the second embodiment will be described.

[0215] Here, regarding the semiconductor storage device of Embodiment 6, the same components as those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1A.

[0216] Fig.13 This is a block diagram showing the structure of a semiconductor memory device 1E according to the sixth embodiment.

[0217] like Fig.13 As shown, semiconductor storage device 1E is configured such that four auxiliary circuits 10A are replaced with one auxiliary circuit 10E compared to semiconductor storage device 1A of the second embodiment.

[0218] That is, each of the plurality of auxiliary circuits 10E is connected to four word lines 20. Therefore, the semiconductor memory device 1E includes auxiliary circuits 10E, which is 1 / 4 the number of word lines 20.

[0219] Here, the first control signal input terminal CNT0 is connected to the first P-channel MOS transistor 25 (see the following description) provided in each of the plurality of auxiliary circuits 10E. Fig.14 ) of all gates.

[0220] Fig.142 is a circuit diagram showing the structure of the auxiliary circuit 10E. Here, the four word lines 20 connected to the auxiliary circuit 10E are respectively referred to as word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3. That is, among the four word lines 20 connected to the auxiliary circuit 10E, the word line 20 connected to one or more memory cells 40 forming a certain row (for example, the 0th row) of the memory cell array 50 is referred to as word line 20WL0, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 1st row) of the memory cell array 50 is referred to as word line 20WL1, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 2nd row) of the memory cell array 50 is referred to as word line 20WL2, and the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 3rd row) of the memory cell array 50 is referred to as word line 20WL3.

[0221] like Fig.14 As shown, the auxiliary circuit 10E is formed by adding a second pull-down N-channel MOS transistor 21E1, a third pull-down N-channel MOS transistor 21E2, and a fourth pull-down N-channel MOS transistor 21E3 relative to the auxiliary circuit 10A of embodiment 2, wherein the drain of the second pull-down N-channel MOS transistor 21E1 is connected to the word line 20 (here, word line 20WL1), the source is connected to the ground line, and the gate is connected to the first node 91, the drain of the third pull-down N-channel MOS transistor 21E2 is connected to the word line 20 (here, word line 20WL2), the source is connected to the ground line, and the gate is connected to the first node 91, and the drain of the fourth pull-down N-channel MOS transistor 21E3 is connected to the word line 20 (here, word line 20WL3), the source is connected to the ground line, and the gate is connected to the first node 91.

[0222] <Inspection>

[0223] In the auxiliary circuit 10E having the above-described structure, the drain of the first series-connected N-channel MOS transistor 22 is connected to the power supply line via the first P-channel MOS transistor 25 .

[0224] Therefore, when the first control signal of logic value 0 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, the first P-channel MOS transistor 25 becomes conductive, and therefore in the auxiliary circuit 10E, when logic value 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first series-connected N-channel MOS transistor 22 becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0225] Thus, the voltage of the first node 91, that is, the gate voltages of the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21E1, the third pull-down N-channel MOS transistor 21E2, and the fourth pull-down N-channel MOS transistor 21E3, becomes VDD-Vtn.

[0226] On the other hand, when the first control signal having a logical value of 1 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VDD, the first P-channel MOS transistor 25 is in a non-conductive state.

[0227] Therefore, in the auxiliary circuit 10E, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive, and the voltage of the first node 91 is reset (becomes VSS), then, thereafter, the voltage of the first node 91 will not become higher than VSS, that is, the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21E1, the third pull-down N-channel MOS transistor 21E2 and the fourth pull-down N-channel MOS transistor 21E3 will not pull down the voltages of the activated word lines 20WL0, 20WL1, 20WL2 and 20WL3, respectively, to reduce the voltages.

[0228] As described above, according to the semiconductor memory device 1E having the above configuration, whether or not to enable the auxiliary function of the word line 20 in the active state can be controlled by controlling the first control signal.

[0229] In the auxiliary circuit 10E having the above-described structure, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21E1, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21E2, and the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21E3 can be set as a common first series-connected N-channel MOS transistor. The S transistor 22 can also be used to connect the N-channel MOS transistor 21E1 to the ground wiring, and the N-channel MOS transistor 21E2 to the ground wiring can be used to connect the N-channel MOS transistor 21E3 to the ground wiring. The N-channel MOS transistor 21E1 to the ground wiring can be used to connect the N-channel MOS transistor 21E2 to the ground wiring, and the N-channel MOS transistor 21E3 to the ground wiring can be used to connect the N-channel MOS transistor 21E3 to the ground wiring.

[0230] Therefore, compared with the case where an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21E1, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21E2, and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21E3 are respectively formed, the size of the first series-connected N-channel MOS transistor 22 can be increased.

[0231] This can suppress variations in Vtn of the first series-connected N-channel MOS transistors 22 .

[0232] Furthermore, in the sixth embodiment, the auxiliary circuit 10E is described assuming that the number M of pull-down N-channel MOS transistors whose gates are connected to the first node 91 is four.

[0233] On the other hand, as another configuration example, M may be an integer other than 4 and greater than 2.

[0234] In this case, the semiconductor memory device 1E includes 1 / M number of auxiliary circuits 10E which is the number of word lines 20 .

[0235] (Implementation 7)

[0236] Hereinafter, a semiconductor storage device according to a seventh embodiment having a configuration partially modified from semiconductor storage device 1A according to the second embodiment will be described.

[0237] Here, regarding the semiconductor storage device of Embodiment 7, the same components as those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1A.

[0238] <Structure>

[0239] Fig.15 This is a block diagram showing the structure of a semiconductor storage device 1F according to a seventh embodiment.

[0240] like Fig.15 As shown, semiconductor storage device 1F is configured such that auxiliary circuit 10A is replaced with auxiliary circuit 10F compared to semiconductor storage device 1A of the second embodiment.

[0241] Here, the first control signal input terminal CNT0 is connected to the first P-channel MOS transistor 25 (see the following description) provided in each of the plurality of auxiliary circuits 10F. Fig.16 ) of all gates.

[0242] Fig.16 : is a circuit diagram showing the structure of the auxiliary circuit 10F.

[0243] like Fig.16 As shown, the auxiliary circuit 10F is configured by adding a second pull-down N-channel MOS transistor 21F to the auxiliary circuit 10A of the second embodiment. The drain of the second pull-down N-channel MOS transistor 21F is connected to the word line 20, the source is connected to the ground line, and the gate is connected to the power supply line.

[0244] <Inspection>

[0245] In the auxiliary circuit 10F having the above structure, the voltage of the word line 20 is pulled down by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn and the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD.

[0246] Fig.17The schematic diagram shows the relationship between the process variation conditions of the N-channel MOS transistors and the voltage drop amount of the word line 20 in (1) the case where the voltage of the word line 20 is pulled down by two transistors, namely, the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD and the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn, (2) the case where the voltage of the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD, and (3) the case where the voltage of the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0247] exist Fig.17 In FIG. 1 , the horizontal axis represents the degree of variation of the process variation conditions of the N-channel MOS transistor, and the vertical axis represents the voltage drop amount of the word line 20 .

[0248] like Fig.17 As shown, in the case where (1) the voltage of the word line 20 is pulled down by two transistors, namely, the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD and the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn, the voltage drop amount of the word line 20 can be controlled more sensitively than in the case where (2) the voltage of the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21F having a gate voltage of VDD and (3) the voltage of the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0249] As described above, according to the semiconductor memory device 1F having the above-described structure, the voltage drop amount of the word line 20 can be controlled more sensitively.

[0250] (Implementation 8)

[0251] Hereinafter, a semiconductor storage device according to an eighth embodiment in which a part of the structure of semiconductor storage device 1A according to the second embodiment is changed will be described.

[0252] Here, regarding the semiconductor storage device of Embodiment 8, the same components as those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1A.

[0253] <Structure>

[0254] Fig.18 This is a block diagram showing the structure of a semiconductor memory device 1G according to an eighth embodiment.

[0255] like Fig.18As shown, semiconductor storage device 1G is configured such that auxiliary circuit 10A is replaced with auxiliary circuit 10G compared to semiconductor storage device 1A of the second embodiment.

[0256] Here, the first control signal input terminal CNT0 is connected to the first P-channel MOS transistor 25 (see the following description) provided in each of the plurality of auxiliary circuits 10G. Fig.19 ) of all gates.

[0257] Fig.19 : is a circuit diagram showing the structure of the auxiliary circuit 10G.

[0258] like Fig.19 As shown, the auxiliary circuit 10G is configured in comparison with the auxiliary circuit 10A of the second embodiment except that the first series-connected N-channel MOS transistor 22 is replaced with a first series-connected N-channel MOS transistor 22G.

[0259] Here, the first series-connected N-channel MOS transistor 22G has a lower threshold value than the first pull-down N-channel MOS transistor 21 and the second series-connected N-channel MOS transistor 23 .

[0260] <Inspection>

[0261] According to the semiconductor memory device 1G with the above structure, when the power supply voltage is reduced, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes lower than the threshold voltage of the first pull-down N-channel MOS transistor 21. As a result, the occurrence of the inadvertent situation in which the first pull-down N-channel MOS transistor 21 cannot pull down the word line 20 can be suppressed.

[0262] Thus, according to the semiconductor memory device 1G having the above-described structure, the low voltage operation region of the pull-down operation of the word line 20 can be expanded.

[0263] (Implementation method 9)

[0264] Hereinafter, a semiconductor storage device according to an eighth embodiment in which a part of the structure of semiconductor storage device 1A according to the second embodiment is changed will be described.

[0265] Here, regarding the semiconductor storage device of Embodiment 8, the same components as those of semiconductor storage device 1A are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1A.

[0266] <Structure>

[0267] Fig. 20 This is a block diagram showing the structure of a semiconductor memory device 1H according to a ninth embodiment.

[0268] like Fig. 20As shown, the semiconductor memory device 1H is configured by adding a second control signal input terminal CNT1 to the semiconductor memory device 1A of the second embodiment and changing the auxiliary circuit 10A to an auxiliary circuit 10H.

[0269] Here, the first control signal input terminal CNT0 is connected to the first P-channel MOS transistor 25 (see the following description) provided in each of the plurality of auxiliary circuits 10H. Fig.21 ), the second control signal input terminal CNT1 is connected to the second P-channel MOS transistor 25H (see later-described) provided in each of the plurality of auxiliary circuits 10H. Fig.21 ) are all gate connections.

[0270] Fig.21 : is a circuit diagram showing the structure of the auxiliary circuit 10H.

[0271] like Fig.21 As shown, the auxiliary circuit 10H is configured by adding a second pull-down N-channel MOS transistor 21H, a second P-channel MOS transistor 25H, a third series-connected N-channel MOS transistor 22H, and a fourth series-connected N-channel MOS transistor 23H, and further adding an inverter 24H, relative to the auxiliary circuit 10A of the second embodiment. The drain of the second pull-down N-channel MOS transistor 21H is connected to the word line 20, the source is connected to the ground line, and the gate is connected to the second node 91H. The second P-channel MOS transistor 25H is connected to the ground line. The drain of the third series-connected N-channel MOS transistor 22H is connected to the third node 92H, and the source is connected to the power supply line. The drain of the third series-connected N-channel MOS transistor 22H is connected to the third node 92H, and the source is connected to the second node 91H. The drain of the fourth series-connected N-channel MOS transistor 23H is connected to the second node 91H, and the source is connected to the ground line. The inverter 24 is connected so that the gate of the third series-connected N-channel MOS transistor 22H is input with an inverted logic signal of the signal input to the gate of the fourth series-connected N-channel MOS transistor 23H.

[0272] In addition, the gate of the second P-channel MOS transistor 25H is connected to the second control signal input terminal CNT1 via the terminal sel1.

[0273] <Inspection>

[0274] According to the semiconductor memory device 1H of the above structure, by controlling the first control signal, it is possible to control whether the auxiliary function using the first pull-down N-channel MOS transistor 21 is enabled, and by controlling the second control signal, it is possible to control whether the auxiliary function using the second pull-down N-channel MOS transistor 21H is enabled.

[0275] Therefore, according to the semiconductor storage device 1H of the above structure, it is possible to choose whether to use the first pull-down N-channel MOS transistor 21 to pull down the word line 20, or to use the second pull-down N-channel MOS transistor 21H to pull down the word line 20, or to use the first pull-down N-channel MOS transistor 21 and the second pull-down N-channel MOS transistor 21H to pull down the word line 20, or to not pull down the word line 20.

[0276] (Implementation 10)

[0277] Hereinafter, a semiconductor storage device according to a tenth embodiment having a configuration partially modified from semiconductor storage device 1B according to the third embodiment will be described.

[0278] Here, regarding the semiconductor storage device of Embodiment 10, the same components as those of semiconductor storage device 1B are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1B.

[0279] Fig. 22 This is a block diagram showing the structure of a semiconductor memory device 1J according to a tenth embodiment.

[0280] like Fig. 22 As shown, semiconductor memory device 1J is configured such that four auxiliary circuits 10B are replaced with one auxiliary circuit 10J compared to semiconductor memory device 1B of the third embodiment.

[0281] That is, each of the plurality of auxiliary circuits 10J is connected to four word lines 20. Therefore, the semiconductor memory device 1J includes auxiliary circuits 10J, which is 1 / 4 the number of word lines 20.

[0282] Here, the first control signal input terminal CNT0 is connected to a first series-connected N-channel MOS transistor 22B (see the following) included in each of the plurality of auxiliary circuits 10J. Fig.23 ) are all gate connections.

[0283] Fig.232 is a circuit diagram showing the structure of the auxiliary circuit 10J. Here, the four word lines 20 connected to the auxiliary circuit 10J are respectively referred to as word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3. That is, among the four word lines 20 connected to the auxiliary circuit 10J, the word line 20 connected to one or more memory cells 40 forming a certain row (for example, the 0th row) of the memory cell array 50 is referred to as word line 20WL0, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 1st row) of the memory cell array 50 is referred to as word line 20WL1, the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 2nd row) of the memory cell array 50 is referred to as word line 20WL2, and the word line 20 connected to one or more memory cells 40 forming another certain row (for example, the 3rd row) of the memory cell array 50 is referred to as word line 20WL3.

[0284] like Fig.23 As shown, the auxiliary circuit 10J is formed by adding a second pull-down N-channel MOS transistor 21J1, a third pull-down N-channel MOS transistor 21J2, and a fourth pull-down N-channel MOS transistor 21J3 relative to the auxiliary circuit 10B of embodiment 3, wherein the drain of the second pull-down N-channel MOS transistor 21J1 is connected to the word line 20 (here, word line 20WL1), the source is connected to the ground line, and the gate is connected to the first node 91, the drain of the third pull-down N-channel MOS transistor 21J2 is connected to the word line 20 (here, word line 20WL2), the source is connected to the ground line, and the gate is connected to the first node 91, and the drain of the fourth pull-down N-channel MOS transistor 21J3 is connected to the word line 20 (here, word line 20WL3), the source is connected to the ground line, and the gate is connected to the first node 91.

[0285] <Inspection>

[0286] In the auxiliary circuit 10J of the above-described structure, the drain of the first series-connected N-channel MOS transistor 22B (ie, the second node 92B) is connected to the power supply line via the first P-channel MOS transistor 25B.

[0287] Therefore, when the first control signal of logic value 1 is input from the first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, the first series-connected N-channel MOS transistor 22B becomes conductive, and therefore in the auxiliary circuit 10J, when the logic value 0 is input to terminal c0, that is, when the voltage of terminal c0 becomes VSS, the first P-channel MOS transistor 25B becomes conductive and the second series-connected N-channel MOS transistor 23 becomes non-conductive.

[0288] Thus, the voltage of the first node 91, that is, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes VDD-Vtn.

[0289] On the other hand, when the first control signal having a logical value of 0 is input from the first control signal input terminal CNT0 , that is, when the voltage of the terminal sel0 is VSS, the first series-connected N-channel MOS transistor 22B is in a non-conductive state.

[0290] Therefore, in the auxiliary circuit 10J, once a logic value 1 is input to the terminal c0, that is, once the voltage of the terminal c0 becomes VDD, the second series-connected N-channel MOS transistor 23 becomes conductive, and the voltage of the first node 91 is reset (becomes VSS), then, thereafter, the voltage of the first node 91 will not become higher than VSS, that is, the first pull-down N-channel MOS transistor 21, the second pull-down N-channel MOS transistor 21J1, the third pull-down N-channel MOS transistor 21J2 and the fourth pull-down N-channel MOS transistor 21J3 will not pull down the voltages of the activated word lines 20WL0, 20WL1, 20WL2 and 20WL3, respectively.

[0291] As described above, according to the semiconductor memory device 1J having the above-described structure, whether or not to enable the auxiliary function of the word line 20 in the active state can be controlled by controlling the first control signal.

[0292] In the auxiliary circuit 10J having the above-described structure, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21J1, the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21J2, and the N-channel MOS transistor located on the current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21J3 can be set as a common first series-connected N-channel MOS transistor. The transistor 22B can be configured to be a second series-connected N-channel MOS transistor 23 that is capable of setting an N-channel MOS transistor located on a current path from the gate of the first pull-down N-channel MOS transistor 21 to the ground wiring, an N-channel MOS transistor located on a current path from the gate of the second pull-down N-channel MOS transistor 21J1 to the ground wiring, an N-channel MOS transistor located on a current path from the gate of the third pull-down N-channel MOS transistor 21J2 to the ground wiring, and an N-channel MOS transistor located on a current path from the gate of the fourth pull-down N-channel MOS transistor 21J3 to the ground wiring as a common N-channel MOS transistor.

[0293] Therefore, compared with the case where an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the first pull-down N-channel MOS transistor 21, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the second pull-down N-channel MOS transistor 21J1, an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the third pull-down N-channel MOS transistor 21J2, and an N-channel MOS transistor located on a current path from the power supply wiring to the gate of the fourth pull-down N-channel MOS transistor 21J3 are respectively formed, the size of the first series-connected N-channel MOS transistor 22B can be increased.

[0294] This can suppress variations in Vtn of the first series-connected N-channel MOS transistors 22B.

[0295] Furthermore, in the tenth embodiment, the auxiliary circuit 10J is described assuming that the number M of pull-down N-channel MOS transistors whose gates are connected to the first node 91 is four.

[0296] On the other hand, as another configuration example, M may be an integer other than 4 and greater than 2.

[0297] In this case, the semiconductor memory device 1E includes 1 / M number of auxiliary circuits 10E which is the number of word lines 20 .

[0298] (Implementation 11)

[0299] Hereinafter, a semiconductor storage device according to an eleventh embodiment having a structure partially modified from semiconductor storage device 1B according to the third embodiment will be described.

[0300] Here, regarding the semiconductor storage device of Embodiment 11, the same components as those of semiconductor storage device 1B are given the same reference numerals as those already described, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1B.

[0301] <Structure>

[0302] Fig.24 This is a block diagram showing the structure of a semiconductor memory device 1K according to the eleventh embodiment.

[0303] like Fig.24 As shown, the semiconductor memory device 1k is configured such that the auxiliary circuit 10B is replaced with an auxiliary circuit 10K compared to the semiconductor memory device 1B of the third embodiment.

[0304] Here, the first control signal input terminal CNT0 is connected to a first series-connected N-channel MOS transistor 22B (see hereinafter) included in each of the plurality of auxiliary circuits 10K. Fig.25) are all gate connections.

[0305] Fig.25 : is a circuit diagram showing the structure of the auxiliary circuit 10K.

[0306] like Fig.25 As shown, the auxiliary circuit 10K is configured by adding a second pull-down N-channel MOS transistor 21K to the auxiliary circuit 10B of the third embodiment. The drain of the second pull-down N-channel MOS transistor 21K is connected to the word line 20, the source is connected to the ground line, and the gate is connected to the power supply line.

[0307] <Inspection>

[0308] In the auxiliary circuit 10K of the above structure, the voltage of the word line 20 is pulled down by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn and the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD.

[0309] Fig.26 It is a schematic diagram showing the relationship between the process variation conditions of the N-channel MOS transistors and the voltage drop amount of the word line 20 in (1) the case where the voltage of the word line 20 is pulled down by two transistors, namely, the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD and the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn, (2) the case where the voltage of the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD, and (3) the case where the voltage of the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0310] exist Fig.26 In FIG. 1 , the horizontal axis represents the degree of variation of the process variation conditions of the N-channel MOS transistor, and the vertical axis represents the voltage drop amount of the word line 20 .

[0311] like Fig.26 As shown, in the case where (1) the voltage of the word line 20 is pulled down by two transistors, namely, the second pull-down N-channel MOS transistor 21k having a gate voltage of VDD and the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn, the voltage drop amount of the word line 20 can be controlled more sensitively than in the case where (2) the voltage of the word line 20 is pulled down only by the second pull-down N-channel MOS transistor 21K having a gate voltage of VDD and (3) the voltage of the word line 20 is pulled down only by the first pull-down N-channel MOS transistor 21 having a gate voltage of VDD-Vtn.

[0312] As described above, according to the semiconductor memory device 1K having the above-described structure, the voltage drop amount of the word line 20 can be controlled more sensitively.

[0313] (Implementation 12)

[0314] Hereinafter, a semiconductor storage device according to a twelfth embodiment having a structure partially modified from semiconductor storage device 1B according to the third embodiment will be described.

[0315] Here, regarding the semiconductor storage device of Embodiment 12, the same components as those of semiconductor storage device 1B are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1B.

[0316] <Structure>

[0317] Fig. 27 This is a block diagram showing the structure of a semiconductor storage device 1L according to a twelfth embodiment.

[0318] like Fig. 27 As shown, semiconductor storage device 1L is configured such that auxiliary circuit 10B is replaced with auxiliary circuit 10L compared to semiconductor storage device 1B of the third embodiment.

[0319] Here, the first control signal input terminal CNT0 is connected to a first series-connected N-channel MOS transistor 22L (see hereinafter) included in each of the plurality of auxiliary circuits 10L. Fig.28 ) are all gate connections.

[0320] Fig.28 : is a circuit diagram showing the structure of the auxiliary circuit 10L.

[0321] like Fig.28 As shown, the auxiliary circuit 10L is configured such that the first series-connected N-channel MOS transistor 22B is replaced with a first series-connected N-channel MOS transistor 22L compared to the auxiliary circuit 10L of the third embodiment.

[0322] Here, the first series-connected N-channel MOS transistor 22L has a lower threshold value than the first pull-down N-channel MOS transistor 21 and the second series-connected N-channel MOS transistor 23 .

[0323] <Inspection>

[0324] According to the semiconductor memory device 1L with the above structure, when the power supply voltage is reduced, the gate voltage of the first pull-down N-channel MOS transistor 21 becomes lower than the threshold voltage of the first pull-down N-channel MOS transistor 21. As a result, the occurrence of the inadvertent situation in which the first pull-down N-channel MOS transistor 21 cannot pull down the word line 20 can be suppressed.

[0325] Thus, according to the semiconductor memory device 1L having the above-described structure, the low voltage operation region of the pull-down operation of the word line 20 can be expanded.

[0326] (Implementation 13)

[0327] Hereinafter, a semiconductor storage device according to a thirteenth embodiment having a structure partially modified from semiconductor storage device 1B according to the third embodiment will be described.

[0328] Here, regarding the semiconductor storage device of embodiment 13, the same components as those of semiconductor storage device 1B are assumed to have been described and are denoted by the same reference numerals, and detailed description thereof is omitted, and the description will focus on the differences from semiconductor storage device 1B.

[0329] <Structure>

[0330] Fig.29 This is a block diagram showing the structure of a semiconductor storage device 1M according to a thirteenth embodiment.

[0331] like Fig.29 As shown, the semiconductor memory device 1M is configured by adding a second control signal input terminal CNT1 to the semiconductor memory device 1B of the third embodiment and changing the auxiliary circuit 10B to an auxiliary circuit 10M.

[0332] Here, the first control signal input terminal CNT0 is connected to a first series-connected N-channel MOS transistor 22B (see hereinafter) included in each of the plurality of auxiliary circuits 10M. Fig.30 ), the second control signal input terminal CNT1 is connected to the third series-connected N-channel MOS transistor 22M (see the third series-connected N-channel MOS transistor 22M) described later and provided in each of the plurality of auxiliary circuits 10M. Fig.30 ) are all gate connections.

[0333] Fig.30 : is a circuit diagram showing the structure of the auxiliary circuit 10M.

[0334] like Fig.30As shown, the auxiliary circuit 10M is additionally provided with a second pull-down N-channel MOS transistor 21M, a second P-channel MOS transistor 25M, a third series-connected N-channel MOS transistor 22M and a fourth series-connected N-channel MOS transistor 23M relative to the auxiliary circuit 10B of the third embodiment, and furthermore, the same logic signal as the signal input to the gate of the second series-connected N-channel MOS transistor 23 is input to the gate of the second P-channel MOS transistor 25M and the gate of the fourth series-connected N-channel MOS transistor 23M, wherein the drain of the second pull-down N-channel MOS transistor 21M is connected to the word line 20, the source is connected to the ground line, and the gate is connected to the third node 91M, the source of the second P-channel MOS transistor 25M is connected to the power supply line, the drain is connected to the fourth node 92M, the drain of the third series-connected N-channel MOS transistor 22M is connected to the fourth node 92M, the source is connected to the third node 91M, and the drain of the fourth series-connected N-channel MOS transistor 23M is connected to the third node 91M, and the source is connected to the ground line.

[0335] In addition, the gate of the third series-connected N-channel MOS transistor 22M is connected to the second control signal input terminal CNT1 via the terminal sel1.

[0336] <Inspection>

[0337] According to the semiconductor memory device 1M of the above structure, whether the auxiliary function using the first pull-down N-channel MOS transistor 21 is enabled can be controlled by controlling the first control signal, and whether the auxiliary function using the second pull-down N-channel MOS transistor 21M is enabled can be controlled by controlling the second control signal.

[0338] Therefore, according to the semiconductor memory device 1M of the above structure, it is possible to choose whether to use the first pull-down N-channel MOS transistor 21 to pull down the word line 20, or to use the second pull-down N-channel MOS transistor 21M to pull down the word line 20, or to use the first pull-down N-channel MOS transistor 21 and the second pull-down N-channel MOS transistor 21M to pull down the word line 20, or to not pull down the word line 20.

[0339] (Replenish)

[0340] As described above, as an illustration of the technology disclosed in this application, embodiments 1 to 13 are described. However, the present disclosure is not limited to these embodiments. As long as it does not depart from the main purpose of the present disclosure, the various modifications that a person skilled in the art may conceive of to implement the present embodiment, and the methods constructed by combining the constituent elements in different embodiments or modifications may also be included in the scope of one or more methods of the present disclosure.

[0341] Industrial Applicability

[0342] The present disclosure can be widely used in semiconductor memory devices.

[0343] Description of Reference Numerals

[0344] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1J, 1K, 1L, 1M Semiconductor storage device

[0345] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10J, 10K, 10L, 10M Auxiliary circuit

[0346] 20, 20WL0, 20WL1, 20WL2, 20WL3, 20WL4, 20WL5, 20WL6, 20WL7 word lines

[0347] 21 First pull-down N-channel MOS transistor

[0348] 21C, 21D1, 21E1, 21F, 21H, 21J1, 21K, 21M Second pull-down N-channel MOS transistor

[0349] 21D2, 21E2, 21J2 Third pull-down N-channel MOS transistor

[0350] 21D3, 21E3, 23J3 Fourth pull-down N-channel MOS transistor

[0351] 21D4 Fifth pull-down N-channel MOS transistor

[0352] 21D5 Sixth pull-down N-channel MOS transistor

[0353] 21D6 Seventh pull-down N-channel MOS transistor

[0354] 21D7 Eighth pull-down N-channel MOS transistor

[0355] 22, 22B, 22G, 22L First series N-channel MOS transistor

[0356] 22C, 22D, 22H, 22M Third series-connected N-channel MOS transistors

[0357] 23 Second series-connected N-channel MOS transistor

[0358] 23C, 23D, 23H, 23M Fourth series-connected N-channel MOS transistors

[0359] 24, 24C, 24H Inverter

[0360] 25, 25B First P-channel MOS transistor

[0361] 25H, 25M Second P-channel MOS transistor

[0362] 26, 26D AND NOT circuit

[0363] 28 bit lines

[0364] 29 Reverse Phase Line

[0365] 30 Word Line Driver

[0366] 40 storage units

[0367] 41, 42 Access transistor

[0368] 43, 44 Load transistor

[0369] 45, 46 driving transistor

[0370] 50 memory cell array

[0371] 60-line decoder

[0372] 70 I / O circuit

[0373] 80 Control Department

[0374] 91 First Node

[0375] 91C, 91D, 91H, 92B Second node

[0376] 92H Third Node

[0377] 92M Fourth Node

Claims

1. A semiconductor storage device comprising: a first pull-down N-channel MOS transistor, having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line supplying a ground voltage, and a gate connected to a first node, wherein the MOS transistor is a metal oxide semiconductor transistor; a first series-connected N-channel MOS transistor, a drain of which is connected to a power line supplying a power supply voltage, and a source of which is connected to the first node; as well as a second series-connected N-channel MOS transistor, a drain of which is connected to the first node and a source of which is connected to the ground line, An inverted logic signal of a signal input to a gate of the second series-connected N-channel MOS transistor is input to a gate of the first series-connected N-channel MOS transistor.

2. The semiconductor memory device according to claim 1, further comprising a first P-channel MOS transistor having a drain connected to the drain of the first series-connected N-channel MOS transistor, a source connected to the power supply line, and a gate connected to a first control signal input terminal to which a first control signal is input, The drains of the first series-connected N-channel MOS transistors are connected to the power supply line via the first P-channel MOS transistor.

3. The semiconductor memory device according to claim 2, Also available: a second pull-down N-channel MOS transistor, having a drain connected to a second word line connected to at least one second storage unit, a source connected to the ground line, and a gate connected to a second node; a third series-connected N-channel MOS transistor, having a drain connected to the drain of the first P-channel MOS transistor and a source connected to the second node; as well as a fourth series-connected N-channel MOS transistor, a drain of which is connected to the second node and a source of which is connected to the ground line, An inverted logic signal of a signal input to a gate of the fourth series-connected N-channel MOS transistor is input to a gate of the third series-connected N-channel MOS transistor.

4. The semiconductor memory device according to claim 2, Also available: a second pull-down N-channel MOS transistor, having a drain connected to a second word line connected to at least one second storage unit, a source connected to the ground line, and a gate connected to the first node; a third pull-down N-channel MOS transistor, having a drain connected to a third word line connected to at least one third storage unit, a source connected to the ground line, and a gate connected to the second node; a fourth pull-down N-channel MOS transistor, having a drain connected to a fourth word line connected to at least one fourth storage unit, a source connected to the ground line, and a gate connected to the second node; a third serially connected N-channel MOS transistor, having a drain connected to the drain of the first P-channel MOS transistor and a source connected to the second node; as well as a fourth series-connected N-channel MOS transistor, a drain of which is connected to the second node and a source of which is connected to the ground line, When the first word line and / or the second word line is activated, an inverted logic signal of a signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first series-connected N-channel MOS transistor, When the third word line and / or the fourth word line is activated, an inverted logic signal of a signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the third series-connected N-channel MOS transistor.

5. The semiconductor memory device according to claim 2, Also available: a second pull-down N-channel MOS transistor, having a drain connected to the first word line, a source connected to the ground line, and a gate connected to a second node; a second P-channel MOS transistor, a drain of which is connected to the third node, a source of which is connected to the power supply line, and a gate of which is connected to a second control signal input terminal to which a second control signal is input; a third series-connected N-channel MOS transistor having a drain connected to the third node and a source connected to the second node; as well as a fourth series-connected N-channel MOS transistor, a drain of which is connected to the second node and a source of which is connected to the ground line, inputting to the gate of the first series-connected N-channel MOS transistor a same logic signal as the signal input to the gate of the third series-connected N-channel MOS transistor, The same logic signal as the signal input to the gate of the fourth series-connected N-channel MOS transistor is input to the gate of the second series-connected N-channel MOS transistor.

6. A semiconductor storage device comprising: a first pull-down N-channel MOS transistor, having a drain connected to a first word line connected to one or more first memory cells, a source connected to a ground line supplying a ground voltage, and a gate connected to a first node, wherein the MOS transistor is a metal oxide semiconductor transistor; a first P-channel MOS transistor having a source connected to a power line supplying a power supply voltage and a drain connected to the second node; a first series-connected N-channel MOS transistor, a drain of which is connected to the second node, a source of which is connected to the first node, and a gate of which is connected to a first control signal input terminal to which a first control signal is input; as well as a second series-connected N-channel MOS transistor, a drain of which is connected to the first node and a source of which is connected to the ground line, The same logic signal as the signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the first P-channel MOS transistor.

7. The semiconductor memory device according to claim 2 or 6, A second pull-down N-channel MOS transistor is further provided, wherein the drain of the second pull-down N-channel MOS transistor is connected to a second word line connected to one or more second memory cells, the source of the second pull-down N-channel MOS transistor is connected to the ground line, and the gate of the second pull-down N-channel MOS transistor is connected to the first node.

8. The semiconductor memory device according to claim 2 or 6, A second pull-down N-channel MOS transistor is further provided. The drain of the second pull-down N-channel MOS transistor is connected to the first word line, the source is connected to the ground line, and the gate is connected to the power line.

9. The semiconductor memory device according to claim 2 or 6, The threshold value of the first series-connected N-channel MOS transistor is lower than the threshold values ​​of the first pull-down N-channel MOS transistor and the second series-connected N-channel MOS transistor.

10. The semiconductor memory device according to claim 6, Also available: a second pull-down N-channel MOS transistor, having a drain connected to the first word line, a source connected to the ground line, and a gate connected to a third node; a second P-channel MOS transistor, whose source is connected to the power line and whose drain is connected to the fourth node; a third series-connected N-channel MOS transistor, a drain of which is connected to the fourth node, a source of which is connected to the third node, and a gate of which is connected to a second control signal input terminal to which a second control signal is input; as well as a fourth series-connected N-channel MOS transistor, a drain of which is connected to the third node and a source of which is connected to the ground line, The same logic signal as the signal input to the gate of the second series-connected N-channel MOS transistor is input to the gate of the second P-channel MOS transistor and the gate of the fourth series-connected N-channel MOS transistor.

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