Semiconductor device, power device, and power module

Abstract

According to one embodiment, a semiconductor device includes a semiconductor chip (10) and a first conductive layer (12B) provided on a first surface side of the semiconductor chip (10), the first conductive layer (12B) includes an intermetallic compound layer containing copper (Cu), tin (Sn), and silver (Ag), and a concentration of silver relative to tin in the first conductive layer (12B) is 1.0 at% or more and 7.9 at% or less.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, a power device, and a power module. Background Art

[0002] A power device having a structure in which a semiconductor chip is bonded to a copper member via an intermetallic compound is known.

[0003] Prior art literature

[0004] Non-patent literature

[0005] Non-patent document 1: "Evaluation of Ag-sinter and CuSn-TLP base joining technologies on lead frame", A. Otto, et al., Proc. PCIM Europe 2018 (2018), 691-698.

[0006] Non-patent document 2: "Reliability modeling of Sn-Ag transient liquid phasedie-bonds for high-power SiC devices", AABajwa and J.Wilde, MicroelectronicsReliability, 60(2016), 116-125.

[0007] Non-patent document 3: "Formation of Initial Defects in Solid-Liquid ReactionDiffusion Bonding of Cu Using Sn Film", S. Fukumoto, et.al., Proc. MSES2017 (2017), 61-64. Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Improve the reliability of semiconductor devices.

[0010] Means used to solve problems

[0011] A semiconductor device of an embodiment comprises a semiconductor chip and a first conductive layer arranged on a first surface side of the semiconductor chip, the first conductive layer includes an intermetallic compound layer containing copper (Cu), tin (Sn) and silver (Ag), and the concentration of the silver in the first conductive layer relative to the tin is greater than 1.0 at % and less than 7.9 at %. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a cross-sectional view showing a configuration example of a semiconductor device according to an embodiment.

[0013] Figure 2 It is a diagram showing the experimental results of the semiconductor device according to the embodiment.

[0014] Figure 3 It is a cross-sectional view showing a specific example of the semiconductor device according to the embodiment.

[0015] Figure 4 It is a cross-sectional view showing a specific example of the semiconductor device according to the embodiment.

[0016] Figure 5 It is a cross-sectional view showing a specific example of the semiconductor device according to the embodiment.

[0017] Figure 6 It is a cross-sectional view showing a specific example of the semiconductor device according to the embodiment.

[0018] Figure 7 It is a cross-sectional view showing a specific example of the semiconductor device according to the embodiment.

[0019] Figure 8 It is a cross-sectional view showing a specific example of the semiconductor device according to the embodiment.

[0020] Fig. 9 It is a cross-sectional view showing a modification of the semiconductor device according to the embodiment.

[0021] Fig.10 It is a cross-sectional view showing a modification of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In the following description, the same symbols are used for elements having the same function and structure. In addition, in each of the following embodiments, the components (e.g., circuits, wiring, various voltages and signals, etc.) marked with reference symbols with numbers / English letters for distinguishing at the end may also be omitted from the description (reference symbols) at the end when they are not distinguished from each other. The dimensions and ratios of the drawings may not be the same as in reality.

[0023] <Implementation Method>

[0024] Reference Figures 1 to 10 , a semiconductor device according to an embodiment of the present invention is described.

[0025] (1)Basic example

[0026] Reference Figure 1 and Figure 2, a basic example of a semiconductor device according to an embodiment of the present invention is described.

[0027] (structure)

[0028] Figure 1 It is a cross-sectional view for explaining the structure of a basic example of the semiconductor device according to the present embodiment.

[0029] Figure 1 (a) is a cross-sectional view showing a state before the semiconductor device of the present embodiment is bonded to a copper substrate. Figure 1 (b) is a cross-sectional view showing a state where the semiconductor device according to the present embodiment is bonded to a copper substrate.

[0030] like Figure 1 As shown, the semiconductor device 1 of the embodiment is provided on a copper layer (Cu layer) 20 as a copper substrate. The semiconductor device 1 includes a semiconductor chip 10, a conductive layer 11, conductive layers 12 (12A and 12B), and pads (electrodes) 19.

[0031] The semiconductor chip 10 has a cubic or rectangular parallelepiped structure and has a front surface (upper surface) and a back surface (lower surface) extending in the XY plane.

[0032] The semiconductor chip 10 includes a silicon substrate (Si substrate) or a silicon carbide substrate (SiC substrate).

[0033] The semiconductor chip 10 is a chip of a vertical power device. The output current of the vertical power device flows between the front and back surfaces of the semiconductor chip 10. The semiconductor chip 10 includes an element portion 100. The element portion 100 includes a semiconductor element such as a MOS field effect transistor, an IGBT (Insulated gate bipolar transistor) or a diode.

[0034] Furthermore, a chip of a lateral power device may also be used for the semiconductor chip 10. In this case, the current does not flow to the copper substrate side, and the copper substrate functions as a heat sink.

[0035] For example, the power device formed in the semiconductor chip 10 is a Si device having a withstand voltage of 20V to 200V, or a SiC device having a withstand voltage of 600V to 4500V.

[0036] The pads 19 are provided on the surface of the semiconductor chip 10. The pads 19 are electrically connected to the element unit 100 via contacts (not shown) and wirings (not shown) in the semiconductor chip 10.

[0037] The conductive layer 11 and the conductive layer 12 are provided on the back surface side of the semiconductor chip 10 in the Z direction.

[0038] The conductive layer 11 is provided between the semiconductor chip 10 and the conductive layer 12. The conductive layer 11 is provided under the back surface of the semiconductor chip 10. The conductive layer 11 is electrically connected to the element portion 100. The conductive layer 11 includes two metal layers 110 and 111 stacked in the Z direction.

[0039] The metal layer 110 is in contact with the back surface of the semiconductor chip 10. The metal layer 110 is provided to improve the bonding between the semiconductor chip 10 and the conductive layer 12 and to improve the electrical characteristics between the semiconductor chip 10 and the conductive layer 12. The metal layer 110 is, for example, a titanium layer (Ti layer).

[0040] The metal layer 111 is provided between the metal layer 110 and the conductive layer 12. The metal layer 111 functions as a barrier metal that prevents chemical reaction between the conductive layer 12 and the metal layer (Ti layer) 110 and diffusion of constituent components (atoms) between the conductive layer 12 and the metal layer 110. The metal layer 111 is, for example, a nickel layer (Ni layer).

[0041] Hereinafter, the conductive layer 11 is also referred to as a backing metal layer 11 .

[0042] The conductive layer 12 is disposed between the backing metal layer 11 and the Cu layer 20. The conductive layer 12 is in contact with the Cu layer 20.

[0043] like Figure 1 As shown in (a) of FIG. 1 , in a state before the semiconductor device 1 is bonded to the Cu layer 20 , the conductive layer 12A includes metal layers 120 and 121 stacked in the Z direction.

[0044] The metal layer 120 is in contact with the backing metal layer 11. The metal layer 120 is, for example, a silver layer (Ag layer).

[0045] The metal layer 121 is provided between the metal layer (Ag layer) 120 and the Cu layer 20. For example, the metal layer 121 is a tin layer (Sn layer).

[0046] The Ag layer 120 has a film thickness T1. The Sn layer 121 has a film thickness T2. The film thickness T1 is thinner than the film thickness T2. For example, when the area of ​​the surface (and back surface) of the semiconductor chip 10 is 0.8 mm×0.8 mm, the film thickness T2 of the Sn layer 121 is set to about 5.0 μm. When the film thickness T2 of the Sn layer 121 is 5.0 μm, the film thickness T1 of the Ag layer 120 is, for example, greater than 30 nm and less than 100 nm. In this case, the film thickness T1 of the Ag layer 120 is preferably set to, for example, about 60 nm.

[0047] For example, the Ag layer 120 is formed on the Ni layer 111 of the backing metal layer 11 by vacuum evaporation or sputtering.

[0048] For example, the Sn layer 121 is a metal paste and may be formed on the Ag layer 120 by vacuum evaporation or sputtering.

[0049] Figure 1 The semiconductor device 1 of (a) is, for example, a bare chip.

[0050] like Figure 1 As shown in (b), the conductive layer 12B becomes an intermetallic compound layer after the semiconductor device 1 is bonded to the Cu layer 20. The conductive layer 12B is formed by bonding the member constituting the conductive layer 12A to the Cu layer by TLPS (Transient liquid phase sintering), for example.

[0051] In order to bond the semiconductor device 1 to the Cu layer 20, a heat treatment for TLPS is performed on the semiconductor device 1 and the Cu layer 20. Through a chemical reaction based on the heat treatment, Figure 1 The Ag layer 120, the Sn layer 121 and the Cu layer 20 of (a) are combined. For example, the conductive layer 12B after the heat treatment contains a metal compound of Ag, Cu and Sn.

[0052] In this embodiment, the conductive layer 12B is a CuSn layer to which Ag is added. The conductive layer 12B is also referred to as an AgCuSn layer.

[0053] The conductive layer 12B and the Cu layer 20 are integrated by metal bonding through heat treatment. For example, the conductive layer 12B and the Cu layer 20 are continuous.

[0054] Hereinafter, the conductive layer 12 ( 12A, 12B) is also referred to as a mounting layer 12 .

[0055] The film thickness of the AgCuSn layer 12B is 3 μm or more and 50 μm or less. For example, the film thickness of the AgCuSn layer 12B is preferably 5 μm or more and 15 μm or less. When the film thickness of the AgCuSn layer 12B is 5 μm or more and 15 μm or less, the heat dissipation of the semiconductor device 1 and the reliability of the bonding between the mounting layer 12 and the Cu layer 20 can be further ensured.

[0056] When forming the AgCuSn layer 12B, it is preferred to perform a heat treatment at a temperature above the melting point of Sn on the conductive layer (Ag / Sn layer) 12A and the Cu layer 20. This promotes the diffusion of Ag, Sn, and Cu between the conductive layer 12A and the Cu layer 20. As a result, the mounting layer 12 and the Cu layer 20 of the semiconductor device 1 can be integrated by forming an intermetallic compound.

[0057] For example, in the present embodiment, the conductive layer 12B including the CuSn intermetallic compound to which Ag is added as the mounting layer 12 is a layer formed of a hypoeutectic of AgSn and CuSn. For example, the AgCuSn layer 12B includes at least one of Ag3Sn and Ag5Sn. For example, the AgCuSn layer 12B includes at least one of Cu3Sn, Cu6Sn5, and Cu7Sn2.

[0058] In the present embodiment, in the conductive layer 12B formed of the CuSn metal compound containing Ag, the concentration of Ag relative to Sn is 1.0 at % (atomic percentage) or more and 7.9 at % or less. For example, the concentration of Ag relative to Sn is preferably less than 7.9 at %.

[0059] For example, in the present embodiment, the AgCuSn layer 12B can achieve a thermal conductivity of 34 W / mK or more.

[0060] For example, the AgCuSn layer 12B may further contain Ni. It should be noted that the AgCuSn layer 12B as the mounting layer 12 may contain other elements as long as the concentration is a trace amount below the eutectic point of AgCuSn.

[0061] In addition, the Ag layer may remain between the AgCuSn layer 12B and the Ni layer 111 .

[0062] With the above-described structure, the semiconductor device 1 of the present embodiment can improve reliability.

[0063] (Manufacturing method)

[0064] Reference Figure 1 , a method for manufacturing a semiconductor device according to this embodiment is described.

[0065] like Figure 1 As shown in (a), an element portion 100 including a semiconductor element such as a MOSFET or an IGBT is formed on a semiconductor substrate (for example, a Si substrate or a SiC substrate). Then, a pad 19 is formed on the surface side of the semiconductor substrate. Thus, a semiconductor chip 10 is formed.

[0066] The back metal layer 11 formed of a stacked body of the Ti layer 110 and the Ni layer 111 is formed on the back surface of the semiconductor chip 10 by sputtering or vacuum evaporation.

[0067] On the back side of the semiconductor chip 10, the Ag layer 120 is formed on the Ni layer 111 of the backing metal layer 11 by sputtering or vacuum evaporation. The Ag layer 120 has a film thickness of, for example, 60 nm.

[0068] Sn layer 121 is formed on Ag layer 120 by coating of a metal paste, sputtering, or vacuum deposition. Sn layer 121 has a film thickness of, for example, 5 μm.

[0069] Thus, the mounting layer 12 formed of the stacked body of the Ag layer 120 and the Sn layer 121 is formed on the back metal layer 11 on the back surface side of the semiconductor chip 10 .

[0070] Through the above steps, the bare chip semiconductor device 1 is formed.

[0071] The bare chip semiconductor device 1 is mounted on the Cu layer 20 such that the Sn layer 121 of the mounting layer 12 is in contact with the Cu layer (Cu substrate) 20 .

[0072] In a state where the Sn layer 121 is in contact with the Cu layer 20 , heat treatment for bonding the semiconductor device 1 and the Cu layer 20 (hereinafter also referred to as mounting bonding treatment) is performed at a temperature equal to or higher than the melting point of Sn.

[0073] Due to the heat treatment, diffusion of Ag, Sn, and Cu as constituent elements occurs between the mounting layer 12 and the Cu layer 20 .

[0074] Therefore, if Figure 1 As shown in (b), an intermetallic compound layer 12B containing Ag, Cu and Sn is formed between the semiconductor device 1 and the Cu layer 20. The AgCuSn layer 12B as the intermetallic compound layer is partially integrated with the Cu layer 20. The AgCuSn layer 12B and the Cu layer 20 form a continuous layer (region) in which no cracks are generated at the interface.

[0075] The semiconductor device 1 (semiconductor chip 10 ) is bonded to the Cu layer 20 via the AgCuSn layer 12B.

[0076] Through the above steps, the semiconductor device 1 of the present embodiment is completed.

[0077] (experiment)

[0078] Reference Figure 2 Characteristics of the semiconductor device of this embodiment will be described.

[0079] Figure 2 The cross-sectional images when various heat treatments are performed on the semiconductor device of the present embodiment and the semiconductor device of the comparative example are shown.

[0080] Figure 2 (a) is a cross-sectional image of the vicinity of the boundary between the mounting layer and the Cu layer of the semiconductor device of the comparative example. The semiconductor device of the comparative example includes a CuSn-based metal compound layer to which Ag is not added in the mounting layer.

[0081] Figure 2(b) is a cross-sectional image of the semiconductor device of this embodiment near the boundary between the mounting layer and the Cu layer.

[0082] exist Figure 2 (a) and (b) show cross-sectional images of the mounting layer of the experimental sample in the initial state, the experimental sample after pretreatment, the experimental sample after the thermal cycle test, and the experimental sample after the high-temperature storage treatment, respectively.

[0083] In the comparative example and the experimental samples of the present embodiment, the film thickness of the Sn layer of the mounting layer is set to 5.0 μm before the mounting layer is bonded to the Cu layer. In the experimental samples of the present embodiment, the film thickness of the Ag layer of the mounting layer is set to 60 nm before the mounting layer is bonded to the Cu layer. In the experimental samples of the present embodiment, the concentration of Ag in the mounting layer relative to Sn is 1.9 at%.

[0084] In the experimental sample of the semiconductor device of the comparative example, the conductive layer 90 not containing Ag was bonded to the Cu layer at a mounting temperature of 380 degrees. In the experimental sample of the semiconductor device of the present embodiment, the conductive layer 12B containing Ag was bonded to the Cu layer at a mounting temperature of 380 degrees.

[0085] The pre-treatment performed on the experimental samples of the semiconductor devices of the comparative example and the present embodiment is a treatment related to the moisture sensitivity level (MSL).

[0086] The experimental samples of the semiconductor device of the comparative example and the present embodiment were subjected to a thermal cycle test (TCT) of 1000 cycles and a thermal cycle test of 2000 cycles, respectively.

[0087] As high temperature exposure treatment, the experimental samples of the semiconductor device of the comparative example and the present embodiment were subjected to heat treatment at 150 degrees for 1000 hours, heat treatment at 150 degrees for 2000 hours, heat treatment at 175 degrees for 1000 hours, and heat treatment at 175 degrees for 2000 hours, respectively.

[0088] like Figure 2 As shown in (a) of FIG. 1 , in the semiconductor device of the comparative example, a mounting layer (hereinafter referred to as a CuSn layer) 90 made of a CuSn intermetallic compound is formed in the initial state after being bonded to the Cu layer 20X. The CuSn layer 90 is integrated with the Cu layer 20X.

[0089] For example, in the semiconductor device of the comparative example, Kirkendall voids 99X were generated between the CuSn layer 90 and the Cu layer 20X in a 2000-cycle heat cycle test.

[0090] When the semiconductor device of the comparative example is subjected to a high temperature exposure treatment at 150 degrees, Kirkendall voids 99X are generated between the CuSn layer 90 and the Cu layer 20X. In the comparative example, the Kirkendall voids 99X based on the heat treatment under the conditions of 150 degrees and 2000 hours are larger than the Kirkendall voids based on the heat treatment under the conditions of 150 degrees and 1000 hours.

[0091] When the semiconductor device of the comparative example is subjected to a high temperature exposure treatment at 175 degrees, Kirkendall voids 99X are generated between the CuSn layer 90 and the Cu layer 20X. The Kirkendall voids 99X generated by the heat treatment under the conditions of 175 degrees and 2000 hours are larger than the Kirkendall voids 99X generated by the heat treatment under the conditions of 175 degrees and 1000 hours. In addition, the Kirkendall voids 99X generated by the heat treatment at 175 degrees are larger than the Kirkendall voids 99X generated by the heat treatment at 150 degrees.

[0092] As described above, when the semiconductor device of the comparative example is left in a high temperature state of 150 degrees or higher, large Kirkendall voids are generated between the CuSn layer 90 and the Cu layer 20X.

[0093] Therefore, when Ag is not added to the mounting layer 90 formed of the CuSn-based intermetallic compound as in the comparative example, cracks (eg, voids) are generated between the mounting layer 90 and the Cu layer 20X. Therefore, the bonding strength between the semiconductor chip and the Cu substrate of the semiconductor device of the comparative example is deteriorated.

[0094] like Figure 2 As shown in FIG. 2( b ), in the semiconductor device 1 of the present embodiment, in the initial state after bonding, a mounting layer (AgCuSn layer) 12B made of a CuSn intermetallic compound to which Ag is added is formed. The AgCuSn layer 12B is integrated with the Cu layer 20 .

[0095] When a heat cycle test was performed on the semiconductor device 1 of the present embodiment, Kirkendall voids were not generated between the mounting layer 12B and the Cu layer 20 .

[0096] Even when the semiconductor device 1 of the present embodiment is subjected to a heat treatment (high temperature exposure treatment) at 150 degrees for 1000 hours, Kirkendall voids are not generated between the mounting layer 12B and the Cu layer 20 .

[0097] When the heat treatment under the conditions of 150 degrees and 2000 hours is performed on the semiconductor device 1 of the present embodiment, Kirkendall voids 99 are generated between the mounting layer 12B and the Cu layer 20 .

[0098] In addition, when the semiconductor device 1 of the present embodiment is subjected to heat treatment at 175 degrees for 1000 hours and heat treatment at 175 degrees for 2000 hours, Kirkendall voids 99 are generated between the mounting layer 12B and the Cu layer 20 .

[0099] However, regarding each heat treatment under the same conditions, the size of the Kirkendall voids generated in the semiconductor device 1 of the embodiment is smaller than the size of the Kirkendall voids generated in the semiconductor device of the comparative example.

[0100] When a semiconductor device bonded to a Cu layer is placed at high temperature, Cu is supplied from the Cu layer to the mounting layer. As a result, Cu combines with Sn in the mounting layer to form CuSn. Depending on the amount of Cu diffused from the Cu layer to the mounting layer, Kirkendall voids are generated between the Cu layer and the mounting layer.

[0101] When Ag is added to the mounting layer 12 as in the present embodiment, the consumption of Cu (diffusion of Cu) when forming the intermetallic compound is reduced compared to a case where the metal layer serving as the base of the mounting layer is composed of only Sn.

[0102] As a result, Figure 2 As in the experimental sample shown in (b) of FIG. 1 , Kirkendall voids are less likely to occur in the semiconductor device 1 of the present embodiment.

[0103] (Summarize)

[0104] By adding Ag to the CuSn intermetallic compound layer as in the semiconductor device 1 of the present embodiment, the size of Kirkendall voids generated between the mounting layer and the Cu layer which are left at high temperatures can be reduced.

[0105] Therefore, the semiconductor device 1 of the present embodiment can suppress the occurrence of cracks at the boundary between the mounting layer and the Cu layer. Therefore, the semiconductor device 1 of the present embodiment can improve the bonding strength between the mounting layer and the Cu layer.

[0106] As a result, the semiconductor device 1 of the present embodiment can reduce bonding defects between the semiconductor device and the Cu layer.

[0107] In the present embodiment, the AgCuSn layer 12B as the mounting layer includes an AgSn phase and a CuSn phase. The Young's modulus of AgSn is lower than that of CuSn.

[0108] Therefore, in the semiconductor device 1 of the present embodiment, the stress resistance of the mounting layer is improved.

[0109] Therefore, the semiconductor device 1 of the present embodiment can prevent peeling (or breaking) from occurring between the semiconductor chip and the base layer formed of Cu.

[0110] The semiconductor device 1 of this embodiment uses a CuSn-based intermetallic compound in the bonding between the semiconductor device and the Cu material. As a result, the semiconductor device 1 of this embodiment can ensure high heat resistance with a melting point of more than 400 degrees. In addition, the semiconductor device 1 of this embodiment can reduce the cost of the mounting layer bonded to the Cu layer. The semiconductor device 1 of this embodiment can bond the semiconductor device to the Cu material without lead (Pb).

[0111] The semiconductor device 1 of this embodiment controls the film thickness of the AgCuSn mounting layer to 5 μm to 15 μm. This can improve the heat dissipation of the semiconductor device 1 of this embodiment. In addition, the semiconductor device of this embodiment can reduce the thermal resistance by making the mounting layer thinner.

[0112] As described above, the semiconductor device 1 of the present embodiment can improve reliability.

[0113] (2) Specific examples

[0114] Reference Figures 3 to 8 , a specific example (application example) of the semiconductor device of this embodiment is described.

[0115] Figure 3 It is a cross-sectional view showing a specific example of the semiconductor device according to the present embodiment.

[0116] Before the semiconductor device 1 of the present embodiment is mounted on a package, the semiconductor device 1 is provided in a state before the mounting layer 12 forms a metal compound with Cu.

[0117] In this case, the semiconductor device 1 of the embodiment includes a mounting layer 12A, which includes an Ag layer 120 and a Sn layer 121. The mounting layer 12A is a laminate (Ag / Sn layer) of the Ag layer 120 and the Sn layer 121. The Ag layer 120 is in contact with the Ni layer 111 of the backing metal layer 11. The Ag layer 120 is provided between the Ni layer 111 and the Sn layer 121. One surface of the Sn layer 121 is in contact with the Ag layer 120. The surface of the Sn layer 121 opposite to the one surface is exposed.

[0118] In addition, the Ag layer 120 may be provided in the Sn layer 121. In this case, the Ag layer 120 is sandwiched between two parts (Sn parts) in the Sn layer 121. The Sn layer 121 may be provided between the Ag layer 120 and the Ni layer 111.

[0119] The Ag layer 120 is formed by a film forming technique such as a vacuum deposition method or a sputtering method.

[0120] The Sn layer 121 may be a layer formed of a metal paste or may be a layer formed by a film formation technique.

[0121] The film thickness T1 of the Ag layer 120 is thinner than the film thickness T2 of the Sn layer 121. The film thickness T1 of the Ag layer 120 and the film thickness T2 of the Sn layer 121 are preferably set so that the concentration of Ag relative to Sn is 1.0 at% or more and 7.9 at% or less. For example, when the film thickness T2 of the Sn layer 121 is 5.0 μm, the film thickness T1 of the Ag layer 120 is 60 nm.

[0122] Figure 4 It is a cross-sectional view showing a specific example of the semiconductor device according to the present embodiment.

[0123] like Figure 4 As shown, in the mounting layer 12A, the metal layer 123 may also be disposed between the Ag layer 120 and the Sn layer 121 .

[0124] The metal layer 123 is a layer including at least one of gold (Au), palladium (Pd), and Ni.

[0125] The metal layer 123 is an Au layer, a Pd layer, or a Ni layer. The metal layer 123 may be a laminated film including two or more selected from Au, Pd, and Ni, or an intermetallic compound layer including two or more selected from Au, Pd, and Ni.

[0126] The film thickness T3 of the metal layer 123 is less than the film thickness T1 of the Ag layer 120 .

[0127] When the mounting layer 12A and the Cu layer are bonded, the metal layer 123 is melted by heat, and the constituent elements of the metal layer 123 are diffused together with Ag and added into the CuSn layer.

[0128] As a result, Figure 1 The mounting layer 12B of (b) contains elements other than Ag, Cu, and Sn in the AgCuSn layer.

[0129] In addition, at least one of the Ag layer 120 and the Sn layer 121 may include at least one of Au, Pd, and Ni. The metal layer 123 may be provided between the backing metal layer 11 and the Ag layer 120. The Sn layer 121 may be provided between the Ag layer 120 and the metal layer 123.

[0130] Figure 5 It is a cross-sectional view showing a specific example of the semiconductor device according to the present embodiment.

[0131] like Figure 5 As shown, the semiconductor device 1 of the present embodiment can be provided as a packaged power device 5A.

[0132] For example, the semiconductor device 1 is mounted on a lead frame 2A.

[0133] The lead frame 2A includes a mounting portion (bare die mounting portion) 20A and a plurality of lead portions (connection terminals) 21. The mounting portion 20A and the lead portions 21 are Cu layers.

[0134] The semiconductor device 1 is provided on the mounting portion (Cu layer) 20A.

[0135] The pad 19 is electrically connected to the lead portion 21 via a bonding wire 30 .

[0136] The semiconductor device 1 mounted on the lead frame 2A is sealed by a sealing material (insulator) 39. The semiconductor device 1 is covered by the sealing material 39.

[0137] When the semiconductor device 1 is mounted on the lead frame 2, the mounting layer of the semiconductor device 1 is bonded to the mounting portion 20A of the lead frame 2A by heat treatment. By bonding the conductive layer including the Ag layer and the Sn layer to the mounting portion 20A, a mounting layer 12B including an AgCuSn layer is formed on the back side of the semiconductor chip 10. The AgCuSn layer 12B as the mounting layer is integrated with the mounting portion 20A formed of Cu.

[0138] The semiconductor device 1 is bonded to the lead frame 2A via the AgCuSn layer 12B.

[0139] Figure 6 It is a cross-sectional view showing one example of the semiconductor device according to the present embodiment.

[0140] like Figure 6 As shown, in the power device 5B, the conductive layer 12Z formed of AgCuSn may also be provided on the surface side of the semiconductor chip 10 .

[0141] The lead frame 2B includes a lead portion (connection terminal) 23. The lead portion 23 is a Cu layer. The lead portion 23 extends from the bottom surface of the sealing material 39 to the upper surface of the semiconductor chip 10. One end of the lead portion 23 is adjacent to the mounting portion 20A. The other end of the lead portion 23 is arranged above the pad 19 via the conductive layer 12Z.

[0142] When manufacturing the semiconductor device 1, a conductive layer including, for example, an Ag layer and a Sn layer is provided on the pad 19. On the surface side of the semiconductor chip 10, the Ag layer is provided between the Sn layer and the pad 19.

[0143] When the semiconductor device 1 is mounted on the lead frame 2 , the semiconductor device 1 is mounted on the mounting portion 20A, and the other end of the lead portion 23 is provided on the conductive layer (Sn / Ag layer) on the upper surface of the semiconductor chip 10 .

[0144] Through the heat treatment, the AgCuSn layer 12B is formed between the semiconductor chip 10 and the mounting portion 20A, and the AgCuSn layer 12Z is ​​formed between the pad 19 and the lead portion 23 .

[0145] Thus, the AgCuSn layer 12Z is ​​bonded to the lead portion 23 of the Cu layer on the surface side of the semiconductor chip 10. The AgCuSn layer 12Z is ​​integrated with the Cu layer of the lead portion 23. It should be noted that the AgCuSn layer 12Z can be integrated with the pad 19 by bonding the AgCuSn layer 12Z and the pad 19 by heat.

[0146] Figure 7 It is a cross-sectional view showing a specific example of the semiconductor device according to the present embodiment.

[0147] like Figure 7 As shown, a power device 5C including the semiconductor device 1 of the present embodiment may also be provided without being sealed by a sealing material.

[0148] On the surface side of the semiconductor chip 10, external connection terminals 29 are connected to the pads 19. The external connection terminals 29 are conductive bodies containing Sn. The external connection terminals 29 are, for example, solder balls or bumps.

[0149] The Cu layer 20B is provided on the back side of the semiconductor chip 10. The Cu layer 20B is connected to the mounting layer 12B. The mounting layer 12B is an AgCuSn layer. The AgCuSn layer 12B is integrated with the Cu layer 20B.

[0150] For example, the Cu layer 20B functions as an electrode and a heat sink of the power device 5C. Figure 7 The power device 5C may be a lateral power device. When the power device 5C is a lateral power device, the current does not flow to the Cu layer 20B side, and the Cu layer 20B functions as a heat sink.

[0151] Figure 8 It is a cross-sectional view showing a specific example of the semiconductor device according to the present embodiment.

[0152] like Figure 8 As shown, the semiconductor device 1 of this embodiment may also be used in a power module 6 .

[0153] The power module 6 is, for example, a DC-DC converter, an inverter, or a switch.

[0154] In the power module 6 , the semiconductor devices 1 according to the plurality of embodiments are provided on the circuit substrate 3 .

[0155] The circuit board 3 on which the semiconductor device 1 is mounted is provided on the base substrate 50 .

[0156] The housing 51 is provided on the base substrate 50 so as to surround the circuit substrate 3. For example, an insulator (not shown) is provided in a space surrounded by the housing 51 on the base substrate 50. The semiconductor device 1 in the housing 51 is sealed by the insulator.

[0157] The cover 52 is provided on the housing 51 . The cover 52 covers the semiconductor device 1 and the circuit board 3 .

[0158] The external connection terminal 59 is provided in the housing 51. The external connection terminal 59 extends from the housing 51 side toward the circuit substrate 3. One end of the external connection terminal 59 is connected to the wiring 27 (or the Cu layer 20) of the circuit substrate 3. The other end of the external connection terminal 59 protrudes from the cover 52, for example. The other end of the external connection terminal 59 is connected to a device (for example, a control device) outside the power module 6.

[0159] The circuit board 3 includes a metal plate 26 , a ceramic plate 25 , a Cu layer 20 , and wirings 27 .

[0160] The metal plate 26 is a Cu plate. The metal plate 26 functions as a heat sink. The ceramic plate 25 is provided on the metal plate 26. The ceramic plate 25 electrically separates the metal plate 26 from the Cu layer 20 and the wiring 27. The ceramic plate 25 functions as a heat sink.

[0161] The Cu layer 20 and the wiring 27 are provided on the ceramic board 25 .

[0162] The semiconductor device 1 is provided on the Cu layer 20. The semiconductor device 1 is bonded to the Cu layer 20 via a mounting layer (intermetallic compound layer) 12B formed of AgCuSn. The AgCuSn layer 12B is integrated with the Cu layer 20. For example, the Cu layer 20 can also be used as wiring.

[0163] The wiring 27 electrically connects the plurality of semiconductor devices 1 to each other. The wiring 27 is connected to the semiconductor device 1 via the bonding wire 30. The plurality of semiconductor devices 1 on the circuit board 3 are connected to each other via the bonding wire 30. The wiring 27 connects the plurality of semiconductor devices 1 to the external connection terminal 59.

[0164] The output current (or output voltage) of the semiconductor device 1 is output to the outside of the power module 6 via the bonding wires 30 , the wirings 27 , and the external connection terminals 59 .

[0165] like Figures 3 to 8 As shown, the semiconductor device 1 of this embodiment is applied to a device including a Cu component. The semiconductor device 1 of this embodiment is bonded to the Cu component via a mounting layer 12B including AgCuSn.

[0166] Therefore, the reliability of a device including the semiconductor device 1 of this embodiment can be improved.

[0167] (3) Modification

[0168] Reference Fig. 9 and Fig.10 , a modification example of the semiconductor device of this embodiment is described.

[0169] Fig. 9 This is a cross-sectional view showing an example of a modification of the semiconductor device according to the embodiment.

[0170] like Fig. 9 As shown, Sn grains (Sn crystals) 125 may be provided in the AgCuSn layer 12B as the mounting layer. For example, the Sn grains 125 are randomly arranged in the AgCuSn layer 12B.

[0171] Fig.10 This is a cross-sectional view showing an example of a modification of the semiconductor device according to the present embodiment.

[0172] like Fig.10 As shown, the voids 129 may be provided in the AgCuSn layer 12B as the mounting layer. For example, the voids 129 are formed at random positions or according to the positions where the pins abut when heated.

[0173] like Fig. 9 and Fig.10 As shown, even when Sn particles 125 or voids 129 are provided in mounting layer 12B, the semiconductor device according to the modification of the present embodiment can obtain the above-described effects.

[0174] (4) Others

[0175] In the above embodiment, the Ag-doped CuSn layer is used for a power device or a power module, but the Ag-doped CuSn layer can also be used for semiconductor devices other than power devices such as analog circuits and logic circuits.

[0176] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: Semiconductor chips, and A first conductive layer provided on the first surface side of the semiconductor chip, The first conductive layer includes an intermetallic compound layer containing copper (Cu), tin (Sn) and silver (Ag). The concentration of the silver in the first conductive layer relative to the tin is greater than or equal to 1.0 at % and less than or equal to 7.9 at %.

2. The semiconductor device according to claim 1, wherein The first conductive layer is disposed between the semiconductor chip and the copper layer.

3. The semiconductor device according to claim 1, wherein The first conductive layer further includes at least one of nickel (Ni), gold (Au), and palladium (Pd).

4. The semiconductor device according to claim 1, further comprising a second conductive layer provided between the semiconductor chip and the first conductive layer, The second conductive layer includes a nickel layer and a titanium layer between the nickel layer and the semiconductor chip.

5. The semiconductor device according to claim 1, wherein The first conductive layer includes an AgSn phase and a CuSn phase.

6. The semiconductor device according to claim 5, wherein: The AgSn phase includes at least one of Ag3Sn and Ag5Sn, The CuSn phase includes at least one of Cu3Sn, Cu6Sn5 and Cu7Sn2.

7. A power device comprising: The semiconductor device according to claim 1, and A lead frame comprising: a mounting portion bonded to the semiconductor device via the first conductive layer; and a terminal connected to a pad provided on a second surface of the semiconductor device opposite to the first surface. The mounting portion and the terminal each include copper.

8. The power device according to claim 7, wherein: The semiconductor device further comprises a third conductive layer disposed between the pad and the terminal. The third conductive layer includes an intermetallic compound layer containing copper, tin and silver, The concentration of the silver in the third conductive layer relative to the tin is greater than or equal to 1.0 at % and less than or equal to 7.9 at %.

9. A power module comprising: The semiconductor device according to claim 1; and A circuit substrate includes a copper layer bonded to the semiconductor device via the first conductive layer.

10. A semiconductor device comprising: Semiconductor chips, and A first conductive layer provided on the first surface side of the semiconductor chip, The first conductive layer comprises: Tin layer, and a silver layer between the tin layer and the semiconductor chip, The film thickness of the silver layer is thinner than the film thickness of the tin layer.

11. The semiconductor device according to claim 10, wherein: The first conductive layer further comprises a metal layer, The metal layer comprises at least one of nickel, gold and palladium, The thickness of the metal layer is less than the thickness of the silver layer.

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