Semiconductor device

Abstract

A semiconductor device according to an embodiment includes: a tablet (60) having a first surface on which a plurality of pads (618) are provided; a first bonding material disposed on the first surface; and a first metal plate (20) which is provided on the first bonding material, is electrically connected to the plurality of pads (618), and includes a second surface facing the first surface, and a plurality of protrusions (211) provided on the second surface, the plurality of protrusions (211) respectively facing a pad (618A) at one end and a pad (618B) at the other end of the plurality of pads (618) in a direction in which the plurality of pads are arranged.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device. Background Art

[0002] There is known a semiconductor device having a structure in which the upper surface and the lower surface of a pellet are connected to a conductor via a bonding material.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 5807221

[0006] Patent Document 2: Japanese Patent Application Publication No. 2010-87395

[0007] Patent Document 3: Japanese Patent Application Publication No. 2013-89849

[0008] Patent Document 4: Japanese Patent Application Publication No. 2013-16603

[0009] Patent Document 5: Japanese Patent No. 6314433 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] Suppressing semiconductor device defects.

[0012] Technical solutions for solving technical problems

[0013] A semiconductor device of an embodiment comprises: a pressing sheet having a first surface on which a plurality of solder pads are provided; a first bonding material provided on the first surface; and a first metal plate provided on the first bonding material and electrically connected to the plurality of solder pads, comprising a second surface opposite to the first surface and a plurality of protrusions provided on the second surface, the plurality of protrusions being respectively opposite to a solder pad at one end and a solder pad at the other end of the plurality of solder pads in a direction in which the plurality of solder pads are arranged. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a bird's-eye view showing an example of the appearance of a semiconductor device according to an embodiment.

[0015] Figure 2 This is an exploded view showing an example of the internal structure of the semiconductor device according to the embodiment.

[0016] Figure 3 It is a plan view showing an example of a planar layout of a semiconductor device according to an embodiment.

[0017] Figure 4 It is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to an embodiment.

[0018] Figure 5 It is a cross-sectional view showing an example of an element structure of a semiconductor device according to an embodiment.

[0019] Figure 6 It is a plan view showing an example of the structure of the metal plate of the semiconductor device according to the embodiment.

[0020] Figure 7 It is a cross-sectional view showing an example of the structure of the metal plate of the semiconductor device according to the embodiment.

[0021] Figure 8 It is a cross-sectional process diagram showing one step of the method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0022] Reference Figures 1 to 8 , a semiconductor device of an embodiment is described. In the following description, components having substantially the same function and configuration are marked with the same reference numerals. In the case of distinguishing between components having the same configuration, sometimes different characters or numbers are added to the end of the same reference numeral. The dimensions and proportions of the drawings may not be the same as those in reality.

[0023] (Implementation Method)

[0024] (a) Construction example

[0025] Reference Figures 1 to 7 , a structural example of a semiconductor device according to an embodiment is described.

[0026] Figure 1 This is a bird's-eye view showing an example of the appearance of a semiconductor device according to an embodiment.

[0027] Figure 1 The semiconductor device 1 of the embodiment is a power device. The semiconductor device 1 has, for example, a thin rectangular parallelepiped shape. Hereinafter, the thickness direction of the semiconductor device 1 is referred to as the up-down direction. In addition, when the component of the semiconductor device 1 has two surfaces facing each other in the up-down direction, the two surfaces are referred to as the lower surface and the upper surface, respectively.

[0028] Semiconductor device 1 includes metal plate 10, two metal plates 20, two leads 30, and packaging material 40. Metal plate 10, two metal plates 20, and two leads 30 each have a portion exposed to the outside of packaging material 40 as a terminal for electrically connecting semiconductor device 1 to other devices.

[0029] The metal plate 10 and the two metal plates 20 are respectively disposed in a manner of being exposed on the lower surface and the upper surface of the packaging material 40. For example, the height of the exposed surface of the metal plate 10 is consistent with the height of the lower surface of the packaging material 40. For example, the height of the exposed surface of each metal plate 20 is consistent with the height of the upper surface of the packaging material 40. When viewed from a direction perpendicular to the upper surface (and lower surface) of the semiconductor device 1, the exposed surface of each metal plate 20 is included in the region of the exposed surface of the metal plate 10.

[0030] Hereinafter, the metal plate 10 on the lower surface side of the semiconductor device 1 is referred to as a lower metal plate 10 , and the metal plate 20 on the upper surface side of the semiconductor device 1 is referred to as an upper metal plate 20 .

[0031] The two lead portions 30 are provided so as to be exposed on the side surface of the sealing material 40. For example, the two lead portions 30 protrude from the side surface of the sealing material 40.

[0032] The packaging material 40 is an insulating member that physically and electrically protects the internal structure of the semiconductor device 1 from the outside. The packaging material 40 forms the outer shape of the semiconductor device 1.

[0033] Figures 2 to 4 It is a diagram for explaining the internal structure of the semiconductor device 1 according to the present embodiment. Figure 2 FIG. 1 is an exploded view showing an example of the internal structure of the semiconductor device 1 according to the embodiment. Figure 2 , the internal structure of the semiconductor device 1 exploded in the thickness direction is schematically shown. Figure 3 It is a plan view showing an example of the internal plan layout of the semiconductor device 1 according to the embodiment. Figure 4 An example of the internal cross-sectional structure of the semiconductor device 1 according to the embodiment is shown along Figure 3 A cross-sectional view of the IV-IV line. Figure 2 , Figure 3 as well as Figure 4 In the figure, the packaging material 40 is omitted.

[0034] like Figures 2 to 4 As shown, as an internal structure, the semiconductor device 1 includes two bonding materials 50 , two pressing sheets 60 , two bonding materials 70 , and two wires 80 in addition to the lower metal plate 10 , two upper metal plates 20 , and two lead portions 30 .

[0035] The lower metal plate 10 is a plate-shaped conductor. One surface of the lower metal plate 10 is opposite to one surface (lower surface) of the pressing sheet 60. The surface of the lower metal plate 10 opposite to the pressing sheet 60 is called the upper surface of the lower metal plate 10. In the lower metal plate 10, the other surface parallel to the upper surface of the lower metal plate 10 is called the lower surface of the lower metal plate 10. The lower surface of the lower metal plate 10 corresponds to the exposed surface of the lower metal plate 10 from the packaging material 40. The entire upper surface and the entire lower surface of the lower metal plate 10 are flat. In addition, a protrusion protruding toward the pressing sheet 60 side may also be provided on the upper surface of the lower metal plate 10. In this case, a depression may also be provided at a position on the lower surface of the lower electrode plate 10 corresponding to the protrusion provided on the upper surface of the lower electrode plate 10.

[0036] The upper metal plate 20 is a plate-shaped conductor. The upper metal plate 20 has a surface S1 opposite to the other surface (upper surface) of the pressing sheet 60. The surface S1 of the upper metal plate 20 opposite to the pressing sheet 60 is called the lower surface S1 of the upper metal plate 20. In the upper metal plate 20, the other surface parallel to the lower surface S1 of the upper metal plate 20 is called the upper surface of the upper metal plate 20. The upper surface of the upper metal plate 20 corresponds to the exposed surface of the upper metal plate 20 from the packaging material 40. In the present embodiment, the upper metal plate 20 includes a plurality of protrusions 211 arranged on the side of the lower surface S1 of the upper metal plate 20. The upper surface of the upper metal plate 20 can be, for example, flat throughout. Alternatively, a depression can be provided at a portion of the upper surface of the upper metal plate 20, for example, at a position of the upper surface corresponding to the protrusion 211 provided on the lower surface S1. The details of the structure of the upper metal plate 20 will be described later.

[0037] The lower metal plate 10 and the upper metal plate 20 are each made of, for example, a copper plate. The copper plate of the lower metal plate 10 and the copper plate of the upper metal plate 20 have a thickness of about 1.5 mm.

[0038] Two bonding materials 50 are disposed separately from each other on the upper surface of the lower metal plate 10. The corresponding pressing sheet 60 is disposed on the upper surface of the bonding material 50. Each bonding material 50 is disposed between the lower metal plate 10 and the corresponding pressing sheet 60. The bonding material 50 bonds the lower metal plate 10 to the pressing sheet 60. The bonding material 50 contacts the flat lower surface of the pressing sheet 60. The bonding material 50 is a conductor. The bonding material 50 is, for example, a plate-shaped solder layer (e.g., a solder sheet).

[0039] A pressing sheet (semiconductor chip, semiconductor substrate, semiconductor element) 60 is provided between the lower metal plate 10 and the upper metal plate 20. For example, the area of ​​the lower surface of the pressing sheet 60 is smaller than the area of ​​the upper surface of the lower metal plate 10. For example, the area of ​​the upper surface of the pressing sheet 60 is larger than the area of ​​the lower surface of the upper metal plate 20.

[0040] The pressing piece 60 is a chip including a semiconductor element such as a power semiconductor device. The power semiconductor device of the pressing piece 60 is, for example, a device using silicon (Si) or silicon carbide (SiC). As an example of a power semiconductor device, when silicon is used for the pressing piece 60, the pressing piece 60 is an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor). As another example of a power semiconductor device, when silicon carbide is used for the pressing piece 60, the pressing piece 60 is a MOS field effect transistor (MOSFET: Metal-Oxide-Silicon Field Effect Transistor). The pressing piece 60 includes an element portion 600. The element portion 600 includes a plurality of components of the semiconductor element. In addition, a terminal structure (not shown) is provided in a region between the end of the pressing piece 60 in a direction parallel to the upper surface of the pressing piece 60 and the element portion 600.

[0041] A plurality of pads 618 and 619 are provided on the upper surface (the surface of the upper metal plate 20) of the pressing piece 60. Each of the pads 618 and 619 is electrically connected to a component on the semiconductor substrate included in the element portion 600 and / or a component in the semiconductor substrate.

[0042] The insulating layer 629 is provided between adjacent pads 618. The insulating layer 629 is, for example, a polyimide layer. For example, the upper surfaces of the pads 618 and 619 are exposed through an opening provided in the insulating layer 629. The position of the upper surface of the insulating layer 629 in the third direction is higher than the position of the upper surface of the pads 618 and 619 in the third direction. Therefore, a step 699 is generated between the upper surfaces of the pads 618 and 619 and the upper surface of the insulating layer 629.

[0043] Figure 5 It is a cross-sectional view showing an example of the element structure of an IGBT which is the semiconductor device 1 according to the present embodiment. Figure 5 Indicates along Figure 3 The cross section of the VV line.

[0044] like Figure 5 As shown, when the semiconductor element formed on the pressing piece 60 is an IGBT, the semiconductor layer 610, the semiconductor layer 611, the plurality of semiconductor layers 612, the plurality of semiconductor layers 613, the plurality of gate electrodes 614, the plurality of gate insulating layers 615, the gate wiring 616, the semiconductor layer 617, the plurality of pads (conductive patterns) 618 and 619, the electrode 650 and the insulating layer 620 are provided in the pressing piece 60 as components of the element part 600. The terminal structure (not shown) is provided at the end of the pressing piece 60 in a direction parallel to the upper surface of the pressing piece 60.

[0045] The semiconductor layer 610 is provided on the lower surface side of the pressing piece 60. The semiconductor layer 610 is a diffusion layer (impurity semiconductor region) formed in the semiconductor substrate of the pressing piece 60. The semiconductor layer 610 is electrically connected to the lower metal plate 10 via the bonding material (solder layer) 50. The lower surface of the semiconductor layer 610 is substantially flat. The semiconductor layer 610 is a semiconductor layer serving as a collector of the IGBT.

[0046] For example, the electrode 650 is provided between the semiconductor layer 610 and the solder layer 50. The electrode 650 improves the wettability of the solder and the bonding between the solder layer 50 and the pressing piece 60. The electrode 650 functions as a barrier film for suppressing the intrusion (diffusion) of the solder material into the pressing piece 60. For example, the electrode 650 is a laminated film including a titanium film (Ti film), a nickel film (Ni film), and a silver film (Ag film).

[0047] The semiconductor layer 611 is provided in a semiconductor region partitioned by an element isolation layer (not shown) in a semiconductor substrate. The semiconductor layer 611 is, for example, a semiconductor layer serving as a drift layer of an IGBT.

[0048] A plurality of semiconductor layers 612 are provided in the semiconductor layer 611. Each semiconductor layer 612 is a semiconductor layer serving as a base of the IGBT.

[0049] A plurality of semiconductor layers 613 are provided in the semiconductor layer 612. Each semiconductor layer 613 is a semiconductor layer serving as an emitter of the IGBT.

[0050] The gate electrode 614 is a trench gate. The gate electrode 614 is disposed in the pressing sheet 60 via a gate insulating layer 615. The gate insulating layer 615 is disposed between the gate electrode 614 and the semiconductor layers 611, 612, and 613. The gate electrode 614 is sandwiched between two semiconductor layers 612 and between two semiconductor layers 613. The side of the gate electrode 614 is opposite to the semiconductor layer 612 and the semiconductor layer 613 via the gate insulating layer 615. The gate electrode 614 is a conductive layer that serves as the gate electrode 614 of the IGBT.

[0051] The gate wiring 616 is arranged in a region between two pads 618 adjacent to each other in the second direction. The gate wiring 616 is provided on the insulating layer 620. The semiconductor layer 617 is provided in a semiconductor region below the gate wiring 616 via the insulating layer 620.

[0052] The conductivity type of semiconductor layers 610, 611, 612, 613, 617 is set to N type or P type according to the driving type of IGBT. Semiconductor layers other than semiconductor layers 610, 611, 612, 613, 617 may be provided in the sheet 60 according to the functions and characteristics required of the IGBT.

[0053] The pads 618 and 619 are provided on the upper surface side of the pressing sheet 60. The pads 618 and 619 are conductive bodies.

[0054] A plurality of pads 618 are provided on an insulating layer 620 on the upper surface of the semiconductor substrate covering the pressing sheet 60. Each pad 618 contacts the semiconductor layers 612 and 613 via an opening (contact hole) in the insulating layer 620. The pad 618 is electrically connected to the semiconductor layers 612 and 613. The pad 618 is a pad for electrically connecting the emitter of the IGBT to the upper metal plate 20. Each pad 618 has, for example, a rectangular pattern. When viewed from the upper surface of the pressing sheet 60, the pad 618 extends in a first direction parallel to the upper surface of the pressing sheet 60. A plurality of pads 618 are arranged in a second direction intersecting the first direction and parallel to the upper surface of the pressing sheet 60. Hereinafter, the pad 618 is also referred to as an emitter pad 618.

[0055] The pads 618 and 619 are laminated films including an aluminum film (Al film), a nickel film (Ni film), and a gold film (Au film). The gold film prevents oxidation of the nickel film on the aluminum film of the pads 618 and 619. The nickel film ensures bonding between the bonding material (e.g., solder layer) 70 and the pressing sheet 60.

[0056] The insulating layer 629 is provided on the gate wiring 616. The insulating layer 629 overlaps with the end of the pad 618. The step 699 is provided between the insulating layer 629 and the pad 618.

[0057] return Figure 3 and Figure 4 For example, the plurality of emitter pads 618 include emitter pads 618A, 618B, and 618C. Emitter pad 618A is arranged on the side closest to one end in the arrangement direction (second direction) of the plurality of emitter pads 618. Emitter pad 618B is arranged on the side closest to the other end in the arrangement direction of the plurality of emitter pads 618. Emitter pad 618B is adjacent to pad 619 in the extension direction (first direction) of emitter pad 618. A dimension (length) LB in the extension direction of emitter pad 618B is smaller than a dimension LA in the extension direction of emitter pad 618A. Emitter pad 618C is arranged in a region between emitter pad 618A and emitter pad 618B. A portion of emitter pad 618C is adjacent to pad 619 in the arrangement direction of emitter pad 618. The dimension of the emitter pad 618C in the extending direction is the same as the dimension LA of the emitter pad 618A in the extending direction.

[0058] A step 699 is generated between an upper portion of the emitter pad 618 and an upper portion of the insulating layer 620. Due to the step 699, a groove is formed above the emitter pad 618.

[0059] A pad 619 is provided on the insulating layer 620. The pad 619 is electrically connected to the gate electrode 614 via a gate wiring (not shown) in the pressing sheet 60 and a contact plug (not shown) in the insulating layer 620. For example, the pad 619 is arranged in a certain corner region in the region PA where the pads 618 and 619 are provided. The pad 619 has, for example, a square pattern. Hereinafter, the pad 619 connected to the gate electrode 614 is referred to as the gate pad 619.

[0060] Hereinafter, a region on the upper surface of the pressing piece 60 where a plurality of emitter pads 618 and gate pads 619 are arranged is referred to as a pad arrangement region PA.

[0061] When the pressing piece 60 is an IGBT, the lower metal plate 10 is a collector electrode (collector terminal), and the upper metal plate 20 is an emitter electrode (emitter terminal). In addition, when the pressing piece 60 is a MOSFET, for example, the lower metal plate 10 is a drain electrode and the upper metal plate 20 is a source electrode.

[0062] The two bonding materials 70 are separated from each other. The two bonding materials 70 are respectively arranged on the upper surface (pad configuration area PA) of the pressing sheet 60, including the emitter pad 618 and excluding the gate pad 619. The corresponding upper metal plate 20 is arranged on the upper surface of the bonding material 70. Each bonding material 70 is arranged between the corresponding upper metal plate 20 and the corresponding pressing sheet 60. The bonding material 70 bonds the upper metal plate 20 to the pressing sheet 60. The bonding material 70 contacts the undulating upper surface of the pressing sheet 60. The bonding material 70 is a conductor. The bonding material 70 is, for example, a plate-shaped solder layer (solder sheet).

[0063] The bonding material 70 is disposed on the upper surface of the pressing sheet 60 in a manner covering the emitter pad 618. The bonding material 70 is in contact with the emitter pad 618. Thus, the upper metal plate 20 is electrically connected to the plurality of emitter pads 618 via the bonding material 70. The bonding material 70 is not in contact with the gate pad 619. For example, the bonding material 70 does not extend in the region between the end of the pad configuration region PA and the end of the pressing sheet 60.

[0064] One end of a corresponding wire 80 is provided on the gate pad 619 on the upper surface of the pressing piece 60. The wire 80 is a bonding wire. The other end of the wire 80 is connected to the corresponding lead portion 30. The lead portion 30 is a gate electrode (gate terminal).

[0065] With the above-described structure, inside the semiconductor device 1, the three terminals for input and output of the pressing piece 60 are electrically connected to the collector electrode 10, the emitter electrode 20, and the gate electrode 30. The bonding material 50 and the bonding material 70 are responsible for the electrical connection between the pressing piece 60 and the metal plates (electrodes) 10 and 20, and have the function of dissipating the heat generated in the pressing piece 60 in the upward and downward directions.

[0066] In addition, Figures 1 to 5 In the above description, the case where two pressing pieces 60 are provided in the semiconductor device 1 is described, but the present invention is not limited thereto. The number of pressing pieces 60 provided in the semiconductor device 1 may be one, or may be three or more.

[0067] In the semiconductor device 1 of the present embodiment, the upper metal plate 20 includes a plurality of protrusions 211 provided on the lower surface S1 of the upper metal plate 20 .

[0068] Thus, the semiconductor device 1 of the present embodiment can prevent poor bonding and poor electrical connection between the upper metal plate 20 and the pressing piece 60 .

[0069] <Upper Metal Plate>

[0070] Figure 6 and Figure 7 This is a diagram for explaining a structural example of the upper metal plate 20 of the semiconductor device 1 according to the present embodiment. Figure 6 It is a plan view showing a structural example of the upper metal plate 20 in the semiconductor device 1 according to the present embodiment. Figure 7 It is a cross-sectional view showing a structural example of the upper metal plate 20 in the semiconductor device 1 according to the present embodiment. Figure 7 (a) is along Figure 6 Cross-sectional view along line VIIa-VIIa.

[0071] Figure 7 (b) is along Figure 6 A cross-sectional view of line VIIb-VIIb. Figure 7 In order to show the positional relationship between the protrusion 211 of the upper metal plate 20 and the pad 618 of the pressing piece 60 , a part of the structure of the pressing piece 60 is schematically shown.

[0072] As described above, when the semiconductor device 1 is an IGBT, the upper metal plate 20 is the emitter electrode.

[0073] like Figure 6 and Figure 7 As shown, the upper metal plate 20 includes a plate portion 210 and a plurality of protrusions 211 .

[0074] The plate portion 210 is a plate-shaped conductor. The plate portion 210 has two surfaces S1 and S2. The two surfaces S1 and S2 are parallel to each other. The surface S1 is the surface of the upper metal plate 20 that is opposite to the pressing piece 60. The surface S2 is the surface exposed from the packaging material 40. The surface S1 is called the lower surface, and the surface S2 is called the upper surface.

[0075] The lower surface S1 of the upper metal plate 20 has a plurality of protrusions 211 (211A, 211B, 211C, 211D, 211E). On the lower surface S1 of the upper metal plate 20, for example, four or more protrusions 211 are provided on the plate portion 210. In the lower surface S1 of the upper metal plate 20, the portion of the plate portion 210 other than the protrusions 211 is flat.

[0076] The upper surface S2 of the upper metal plate 20 (plate portion 210 ) is, for example, flat. However, as described above, the recess 299 may be provided at a position corresponding to the protrusion 211 on the upper surface S2 of the upper metal plate 20 .

[0077] When viewed from a direction perpendicular to the lower surface S1, the protrusion 211 is provided in a region 219 near a corner of the plate portion 210. Hereinafter, the region 219 is referred to as a corner region.

[0078] The protrusion 211 has, for example, a hemispherical or semi-ellipsoidal shape. Alternatively, the protrusion 211 may have a cube, a rectangular parallelepiped, a triangular pyramid, or a quadrangular pyramid shape.

[0079] The plurality of protrusions 211 have the same height (dimension in a direction perpendicular to the lower surface S1). For example, each protrusion 211 has a height H1. The height H1 of the protrusion 211 is a dimension in a direction perpendicular to the lower surface S1 from a flat portion of the surface S1 on one side of the plate 210 where the protrusion 211 is provided to the top of the protrusion 211 (the position most protruding from the surface S1).

[0080] The plurality of protrusions 211 are arranged in the lower surface S1 of the upper metal plate 20 in such a manner that they overlap vertically with the positions of the corners of the region where the plurality of emitter pads 618 are arranged. When viewed from the direction perpendicular to the lower surface S1, the protrusions 211 are provided at positions opposite to the emitter pads 618 on the outer peripheral side of the pressing sheet 60. The protrusions 211 overlap vertically with the ends of the emitter pads 618 in the extending direction of the pattern of the emitter pads 618 in the direction perpendicular to the lower surface S1.

[0081] For example, five protrusions 211A, 211B, 211C, 211D, and 211E are provided on the upper metal plate 20 .

[0082] Two protrusions 211 ( 211A, 211B) out of the five protrusions 211 are provided at positions vertically overlapping with an emitter pad 618A located closest to one end in the direction (second direction) in which the emitter pads 618 are arranged among the plurality of emitter pads 618 .

[0083] The other two protrusions 211 (211C, 211D) are provided at positions vertically overlapping with the emitter pad 618B which is closest to the other end side in the direction in which the emitter pads 618 are arranged among the plurality of emitter pads 618. The emitter pad 618B on the other end side is adjacent to the gate pad 619 in the extending direction of the emitter pad 618 (the first direction).

[0084] One of the two protrusions 211 (protrusions 211A, 211C) overlapping with a certain emitter pad 618 (618A, 618B) vertically overlaps with one end of the emitter pad 618 in the extending direction of the emitter pad 618. The other of the two protrusions 211 (protrusions 211B, 211D) overlapping with a certain emitter pad 618 (618A, 618B) vertically overlaps with the other end of the emitter pad 618 in the extending direction of the emitter pad 618.

[0085] The interval between two protrusions 211 facing a certain emitter pad 618 is smaller than the dimension (length) in the extending direction of the emitter pad 618. For example, the interval DA between the two protrusions 211A and 211B in the first direction is smaller than the length LA in the first direction of the emitter pad 618A. The interval DA is the dimension between the top of the protrusion 211A and the top of the protrusion 211B. For example, the interval DB between the two protrusions 211C and 211D in the first direction is smaller than the length LB in the first direction of the emitter pad 618B. The interval DB is the dimension between the top of the protrusion 211C and the top of the protrusion 211D.

[0086] The interval between two protrusions 211 overlapping different emitter pads 618 is substantially equal to the interval between two emitter pads 618A and 618B provided at one end and the other end of the periphery of the pad configuration area PA. For example, the interval D1 between the protrusion 211A and the protrusion 211C in the second direction and the interval D2 between the emitter pad 618A on one end side and the emitter pad 618B on the other end side in the second direction are substantially equal. For example, the interval D1 is the dimension between the top of the protrusion 211A and the top of the protrusion 211D. For example, the interval D2 is the dimension between the center line of the emitter pad 618A on one end side along the first direction and the center line of the emitter pad 618B on the other end side along the first direction.

[0087] For example, the interval D1a between the protrusion 211B and the protrusion 211D in the second direction is substantially equal to the interval D1 between the protrusion 211A and the protrusion 211C in the second direction. For example, the interval D3 between the protrusion 211B and the protrusion 211E in the second direction is smaller than the interval D1 between the protrusion 211A and the protrusion 211C in the second direction.

[0088] One of the five protrusions 211E is provided at a position vertically overlapping with one end of the emitter pad 618C adjacent to the gate pad 619 in the arrangement direction of the pads 618. The protrusion 211E is adjacent to one corner of the gate pad 619. For example, the protrusion 211 is not provided at a position vertically overlapping with the other end of the emitter pad 618C. Therefore, the other end of the emitter pad 618C does not vertically overlap with the protrusion 211. However, the protrusion 211 may be provided on the lower surface S1 of the upper metal plate 20 at a position vertically overlapping with the other end of the emitter pad 618C. In addition, the protrusion 211E may not be provided.

[0089] As long as it is in the area where the corner portion is formed in the upper metal plate 20, other protrusions 211 may be provided on the metal plate 20 at a position opposite to the portion other than the end portion of the emitter pad 618C. The portion other than the end portion of the emitter pad 618C (including the portion opposite to the position of other protrusions 211) is arranged at other corners on the side of the gate pad 619 adjacent to the emitter pad 618C.

[0090] A space is formed between the plate portion 210 and the upper surface of the pressing sheet 60 by the protrusion 211 having the height H1.

[0091] As described above, the solder layer 70 is provided between the upper metal plate 20 and the pressing piece 60. For example, the solder layer 70 is interposed between the protrusion 211 and the emitter pad 618, between the plate portion 210 and the emitter pad 618, and between the plate portion 210 and the insulating layer 620. The corners of the solder layer 70 overlap the protrusion 211 of the upper metal plate 20 in a direction perpendicular to the upper surface of the solder layer 70 (the upper surface of the pressing piece 60 or the lower surface S1 of the upper metal plate 20). In addition, the protrusion 211 may also directly contact the emitter pad 618 without passing through the solder layer 70.

[0092] The protrusion 211 functions as a melting base of the solder when the solder melts in the manufacturing process of the semiconductor device 1. The protrusion 211 can suppress curling and / or shrinkage of the solder layer (solder sheet) in the manufacturing process of the semiconductor device 1.

[0093] (b) Manufacturing method

[0094] Reference Figure 8 , a method for manufacturing the semiconductor device 1 according to the present embodiment will be described. Figure 8 It is a cross-sectional process diagram showing one process of the method for manufacturing the semiconductor device 1 according to the present embodiment.

[0095] like Figure 8 As shown, in the manufacturing process of the semiconductor device 1 of this embodiment, the pressing piece 60 including the power device is stacked on the lower metal plate 10 via the solder sheet 50A. The solder sheet 50A is in contact with the flat lower surface of the pressing piece 60. The solder sheet 50A is a component for forming a solder layer (joining material) between the lower metal plate 10 and the pressing piece 60.

[0096] On the upper surface of the pressing sheet 60, a step 699 is generated between the patterns of the emitter pad 618. In the portion of the step 699, the insulating layer (for example, a polyimide layer) 629 protrudes. On the upper surface of the pressing sheet 60, portions of the pad 618 made of metal and portions of the insulating layer 629 are alternately arranged. A groove is formed in the space surrounded by the insulating layer 629 above the emitter pad 618.

[0097] The solder sheet 70A is laminated on the upper surface of the pressing sheet 60. The solder sheet 70A is in contact with the upper surface having the undulations of the pressing sheet 60. The solder sheet 70A is a member for forming a solder layer (joining material) between the upper metal plate 20 and the pressing sheet 60.

[0098] The upper metal plate 20 is stacked on the pressing sheet 60 via the solder sheet 70A. The protrusion 211 of the upper metal plate 20 is arranged above the pad 618 on the outer peripheral side of the pressing sheet 60 in a direction perpendicular to the upper surface of the pressing sheet 60 via the solder sheet 70A.

[0099] After laminating the upper metal plate 20, in order to melt the solder sheets 50A and 70A, heat (or ultrasonic waves) 999 is supplied to the laminated body including the pressing sheet 60 sandwiched by the metal plates 10 and 20. The solder sheets 50A and 70A are melted by the supply of heat. For example, the heat 999 is supplied to the pressing sheet 60 from the lower metal plate 10 side.

[0100] In the initial stage of heat supply in the soldering process (solder reflow process), the supplied heat is transferred from the protrusion 211 of the upper metal plate 20 to the solder sheet 50A. At this time, the solder sheet 70A on the upper surface of the pressing sheet 60 melts with the plurality of protrusions 211 provided on the upper metal plate 20 as the base point. Thus, in the present embodiment, the melting of the solder sheet 70A starts from the outer peripheral side in the pad configuration area PA. In addition, the end of the solder sheet 70A is pressed against the emitter pad 618 on the outer periphery of the pad configuration area PA by the protrusion 211 of the upper metal plate 20.

[0101] Therefore, in the present embodiment, the curling and / or shrinkage of the solder on the outer peripheral side of the pad configuration area PA can be suppressed. Therefore, the molten solder wets and spreads on the entire upper surface of the pressing piece 60 without the adverse effect of the step 699 between the pads 618. The pressing piece 60 having a plurality of emitter pads on the upper surface is bonded to the upper metal plate 20 via a solder layer 70 having a relatively uniform thickness.

[0102] As described above, the upper metal plate (emitter electrode) 20 is bonded to the plurality of pads 618 of the pressing piece 60 via the solder layer formed by the solder sheet 70A. The lower metal plate (collector electrode) 10 is also bonded to the flat lower surface of the pressing piece 60 via the solder layer formed by melting the solder sheet 50A in a simultaneous process.

[0103] After the pressing piece 60 is bonded to the metal plates 10 and 20 , the gate pad 619 is connected to the lead portion 30 via the wire 80 by wire bonding in the pressing piece 60 sandwiched between the metal plates 10 and 20 .

[0104] After the wire bonding process, the pressing sheet 60 sandwiched between the metal plates 10 and 20 is sealed with the sealing material 40 .

[0105] Through the above steps, the semiconductor device 1 of the present embodiment is completed.

[0106] (c) Summary

[0107] In the present embodiment, the upper metal plate 20 is joined to the upper surface of the pressing piece 60 on which the plurality of pads 618 are arranged by melting the solder (solder sheet).

[0108] In a general method for manufacturing a semiconductor device, during the welding process of a pressing sheet and a metal plate, when heat is supplied to the pressing sheet from the lower metal plate side, the temperature of the central portion of the pressing sheet tends to rise. When the solder sheet melts from the central portion of the pressing sheet, the solder of the unmelted portion (for example, the portion on the outer peripheral side of the pressing sheet) is pulled toward the central side of the pressing sheet by the molten solder in the central portion of the pressing sheet. In addition, due to the steps between the pads, the flow of the molten solder is hindered and / or the solder is condensed (contracted), etc. As a result, the solder melted with the central portion of the pressing sheet as the base point may not wet and spread from the central portion of the pressing sheet to the pad pattern on the outer peripheral portion of the pressing sheet.

[0109] In addition, if the solder sheet for forming the solder layer has deformation due to bending of the sheet, the pressing of the solder sheet against the pressing sheet may become insufficient. In this case, the solder may shrink at the outer periphery of the pressing sheet.

[0110] Therefore, in a general semiconductor device, there is a possibility that a defect may occur in the semiconductor device due to unevenness of the solder layer between the pressing piece and the upper metal plate.

[0111] In the semiconductor device 1 of the present embodiment, the upper metal plate 20 stacked on the upper surface of the pressing sheet 60 has a protrusion 211 in a corner region 219 of the surface S1 of the upper metal plate 20 that is opposite to the pressing sheet 60. The protrusion 211 of the upper metal plate 20 overlaps with the pads 618 arranged on the periphery among the plurality of pads 618 of the pressing sheet 60 in a direction perpendicular to the upper surface of the pressing sheet 60. In the present embodiment, the protrusion 211 of the upper metal plate 20 is opposite to the pattern of the pads 618 on the periphery of the pressing sheet 60 at the corner of the upper metal plate 20 and the pad arrangement area PA.

[0112] A space is formed between the upper metal plate 20 and the pressing piece 60 by the protrusion 211. A solder layer 70 is provided between the upper metal plate 20 and the pressing piece 60.

[0113] In the present embodiment, the solder between the upper metal plate 20 and the pressing sheet 60 melts with the protrusion 211 provided on the upper metal plate 20 as a base point. As a result, the solder melts and flows from the outer periphery of the region PA where the plurality of pads are provided toward the central portion. The molten solder wets and spreads relatively uniformly on the upper surface of the pressing sheet 60 having undulations caused by the step 699 between the pad 618 and the insulating layer 629. Therefore, the semiconductor device 1 of the present embodiment can suppress the occurrence of cracks and shrinkage of the solder layer 70 caused by poor solder wetting.

[0114] As a result, the semiconductor device 1 of this embodiment can form a solder layer 70 with relatively uniform film thickness and film quality between the upper metal plate 20 and the pressing piece 60. Therefore, the semiconductor device 1 of this embodiment can suppress semiconductor device defects caused by uneven solder layer 70.

[0115] For example, in the present embodiment, the solder sheet is used to form the solder layer 70. In the semiconductor device 1 of the present embodiment, even if the shape of the solder sheet is deformed, the solder sheet can be pressed against the pads 618 on the outer periphery of the pressing sheet 60 by the protrusions 211 provided on the upper metal plate 20. Therefore, the semiconductor device 1 of the present embodiment can suppress the curling and / or shrinkage of the solder layer 70 on the pads 618 on the outer periphery in the region PA where the plurality of pads 618 are provided.

[0116] As a result, the semiconductor device 1 of the present embodiment can reduce electrical connection defects between the upper metal plate 20 and the pressing piece 60 in the pads 618 ( 618A, 618B, 618C) on the outer peripheral side of the region PA where the plurality of pads 618 are arranged.

[0117] The stress tends to concentrate on the thin film thickness of the solder layer. Due to the concentration of stress, there is a possibility of generation of defects in the solder layer and / or breakage of the pressed piece.

[0118] In the present embodiment, by forming a relatively uniform solder layer 70, the number of thin portions of the solder layer 70 decreases. As a result, the semiconductor device 1 of the present embodiment can suppress the concentration of stress caused by the thin film thickness of the solder layer 70. As a result, the semiconductor device 1 of the present embodiment can reduce the damage of the pressing piece 60.

[0119] Due to the above-mentioned effects, the semiconductor device 1 of the present embodiment can improve the manufacturing yield.

[0120] As described above, the semiconductor device of the present embodiment can suppress defects in the semiconductor device 1 .

[0121] (d) Others

[0122] The semiconductor device 1 of the embodiment is not limited to a power device as long as it has a structure in which a die (semiconductor chip) is sandwiched between two metal plates. For example, the semiconductor device 1 of the embodiment may be an analog circuit, a logic circuit, a processor, a communication circuit, or a storage device.

[0123] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: A pressing sheet having a first surface provided with a plurality of pads; A first bonding material disposed on the first surface; and a first metal plate, disposed on the first bonding material, electrically connected to the plurality of pads, comprising a second surface opposite to the first surface and a plurality of protrusions disposed on the second surface; The plurality of protrusions are respectively opposed to the pads at one end and the pads at the other end of the plurality of pads in the direction in which the plurality of pads are arranged.

2. The semiconductor device according to claim 1, wherein: The plurality of protrusions are respectively arranged in corner regions of the first metal plate within the second surface.

3. The semiconductor device according to claim 1, wherein: The plurality of protrusions each have a first height.

4. The semiconductor device according to claim 1, wherein: The plurality of pads extend respectively in a first direction parallel to the first surface, The plurality of pads are arranged on the insulating layer covering the pressing sheet along a second direction intersecting the first direction and parallel to the first surface, The plurality of pads include a first pad disposed at one end of the second direction and a second pad disposed at the other end of the second direction. One end of the first pad in the first direction is opposite to a first protrusion among the plurality of protrusions, and the other end of the first pad in the first direction is opposite to a second protrusion among the plurality of protrusions. One end of the second pad in the first direction faces a third protrusion among the plurality of protrusions, and the other end of the second pad in the first direction faces a fourth protrusion among the plurality of protrusions.

5. The semiconductor device according to claim 4, wherein: The plurality of pads include: a third pad disposed between the first pad and the second pad; and a fourth pad adjacent to the second pad in the first direction and adjacent to the third pad in the second direction, A portion of the third pad adjacent to the fourth pad faces a fifth protrusion among the plurality of protrusions.

6. The semiconductor device according to claim 4, wherein: An interval between the first protrusion and the third protrusion in the second direction is equal to an interval between the first pad and the second pad in the second direction.

7. The semiconductor device according to claim 6, wherein: A distance between the first protrusion and the second protrusion in the first direction is smaller than a size of the first pad in the first direction.

8. The semiconductor device according to claim 1, wherein: The first bonding material is a solder sheet.

9. The semiconductor device according to claim 1, wherein: Also available: A second metal plate is disposed on a third surface of the pressing sheet that is opposite to the first surface; and a second bonding material between the pressing sheet and the second metal plate, The first metal plate is an emitter electrode of an insulated gate bipolar transistor (IGBT). The second metal plate is a collector electrode of the IGBT.

10. The semiconductor device according to claim 1, wherein: Also available: A second metal plate is disposed on a third surface of the pressing sheet that is opposite to the first surface; and a second bonding material between the pressing sheet and the second metal plate, The first metal plate is a source electrode of a metal oxide semiconductor field effect transistor (MOSFET). The second metal plate is a drain electrode of the MOSFET.

Images