Semiconductor device

Abstract

A semiconductor device according to an embodiment is provided with: a substrate (10); a housing (20) provided on the substrate (10) and including a resin layer (200) and a terminal (210); and a circuit board (100) that is provided on the substrate (10) and includes a semiconductor chip (110) and a wiring (109) that is electrically connected to the semiconductor chip (110) and the terminal (210). The terminal (210) includes a first portion (211) extending from the resin layer (200) toward the circuit board (100), a second portion (212) bonded to the wiring (109), and a third portion (213) between the first portion (211) and the second portion (212). The third portion (213) is recessed further toward the opposite side of the substrate (100) than the second portion (212).

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device. Background Art

[0002] As a semiconductor device that realizes high output, a power module is known. The power module is configured as a single package in which a plurality of power semiconductors are integrated.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 5972172

[0006] Patent Document 2: Japanese Patent No. 6189798

[0007] Patent Document 3: Japanese Patent No. 6805776 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] Reduce semiconductor device defects.

[0010] Technical solutions for solving technical problems

[0011] A semiconductor device according to an embodiment comprises: a substrate; a housing, which is arranged on the substrate and includes a resin layer and terminals; and a circuit substrate, which is arranged on the substrate and includes a semiconductor chip and wiring electrically connected to the semiconductor chip and the terminals, wherein the terminal includes a first portion extending from the resin layer toward the circuit substrate, a second portion joined to the wiring, and a third portion between the first portion and the second portion, wherein the third portion is recessed toward the side opposite to the substrate side than the second portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a bird's-eye view showing the appearance of a semiconductor device according to an embodiment.

[0013] Figure 2 It is a plan view showing the internal structure of the semiconductor device according to the embodiment.

[0014] Figure 3 It is a cross-sectional view showing the internal structure of the semiconductor device according to the embodiment.

[0015] Figure 4 It is a cross-sectional view showing a structural example of a signal terminal and a case of a semiconductor device according to an embodiment.

[0016] Figure 5It is a cross-sectional view showing a structural example of a signal terminal and a case of a semiconductor device according to an embodiment.

[0017] Figure 6 It is a cross-sectional view showing an example of the structure of a signal terminal of the semiconductor device according to the embodiment.

[0018] Figure 7 It is a cross-sectional process diagram showing one step of the method for manufacturing a semiconductor device according to the embodiment.

[0019] Figure 8 It is a cross-sectional process diagram showing one step of the method for manufacturing a semiconductor device according to the embodiment.

[0020] Fig. 9 It is a cross-sectional view showing a modification of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0021] Reference Figures 1 to 9 , a semiconductor device of an embodiment is described. In the following description, elements having the same function and structure are marked with the same symbols. In addition, in each of the following embodiments, the components (for example, circuits, wiring, various voltages and signals, etc.) marked with reference symbols with numbers / English letters for distinction at the end may also be recorded (reference symbols) without omitting the numbers / English letters at the end when they are not distinguished from each other. The sizes and ratios of the components in the drawings may not be the same as in reality.

[0022] <Implementation Method>

[0023] (1) Example of configuration

[0024] Reference Figures 1 to 6 , a configuration example of a semiconductor device according to an embodiment is described.

[0025] Figure 1 It is a bird's-eye view showing the appearance of the semiconductor device 1 according to the present embodiment.

[0026] like Figure 1 As shown, the semiconductor device 1 of the embodiment includes a base substrate 10 , a housing 20 , lids 30A and 30B, and a plurality of connectors 219 and 319 ( 319A, 319B, and 319C).

[0027] The base substrate 10, the housing 20, and the covers 30A and 30B form a container of the semiconductor device 1. A structure including a semiconductor element is provided in the container of the semiconductor device 1.

[0028] The base substrate 10 is a support body of the semiconductor device 1. The base substrate 10 has a flat plate shape. The base substrate 10 corresponds to the bottom of the container of the semiconductor device 1. The base substrate 10 has, for example, a threaded hole. The base substrate 10 can be fixed to a device outside the semiconductor device 1 via the threaded hole. The base substrate 10 functions as, for example, a heat sink. For example, the base substrate 10 includes copper and / or ceramics.

[0029] The housing 20 is provided on the upper surface of the base substrate 10. The housing 20 is an insulator having a square cylindrical shape. The housing 20 corresponds to the side of the container of the semiconductor device 1. The housing 20 is fixed to the base substrate 10. For example, the housing 20 is bonded to the base substrate 10 by an adhesive (resin). The housing 20 is a resin component. For example, the housing 20 contains polyphenylene sulfide (PPS: Poly-Phenylene Sulfide).

[0030] The covers 30A and 30B are provided on the upper surface of the housing 20. The cover 30 is an insulator having a plate-like shape. The covers 30A and 30B correspond to the upper part of the container of the semiconductor device 1. The cover 30 is fixed to the housing 20. For example, the covers 30A and 30B are made of PPS.

[0031] By assembling the above-mentioned base substrate 10, housing 20, and lids 30A and 30B, a space for arranging components (e.g., semiconductor elements) is formed inside the container of the semiconductor device 1. Hereinafter, a plane parallel to the contact surface between the base substrate 10 and the housing 20 is referred to as an XY plane. In the XY plane, the direction of one side of the base substrate 10 is referred to as an X direction, and the direction of the other side intersecting with the one side of the base substrate 10 is referred to as a Y direction. The direction perpendicular to the XY plane is referred to as a Z direction.

[0032] The semiconductor device 1 includes a plurality of connectors 219, 319 (319A, 319B, 319C). The plurality of connectors 219, 319 are electrically connected to devices outside the semiconductor device 1. The plurality of connectors 219, 319 are electrically connected to semiconductor elements in the container of the semiconductor device 1. The connectors 219, 319 are ends of each terminal (bus bar) in the container of the semiconductor device 1.

[0033] The connector 319 is used to input and output voltage and / or current to the semiconductor device 1. The connector 319 supplies a voltage (or current) from a device outside the semiconductor device 1 to a semiconductor element in a container of the semiconductor device 1, or supplies a voltage (or current) generated by the semiconductor device 1 to an external device.

[0034] For example, two connectors 319A are arranged in the Y direction on the upper portion of the semiconductor device 1 (eg, the upper surface of the housing 20 ). The two connectors 319A correspond to input terminals of P (Positive) polarity. The two connectors 319A are electrically connected to each other.

[0035] For example, two connectors 319B are arranged in the Y direction on the upper part of the semiconductor device 1 (eg, the upper surface of the cover 30B). The two connectors 319B correspond to input terminals of N (Negative) polarity. The two connectors 319B are electrically connected to each other.

[0036] For example, three connectors 319C are arranged in the Y direction on the upper portion of the semiconductor device 1 (eg, the upper surface of the housing 20 ). The three connectors 319C correspond to output terminals. The three connectors 319C are electrically connected to each other.

[0037] The connector 219 is used to monitor the operating state of the semiconductor device 1. The connector 219 supplies a signal indicating a monitoring result corresponding to the operating state of the semiconductor element in the container of the semiconductor device 1 to a device outside the semiconductor device 1. In addition, the connector 219 can also be used to supply a signal for controlling the semiconductor device 1. For example, the control connector 219 supplies a control signal from a device outside the semiconductor device 1 to the semiconductor element in the container of the semiconductor device 1.

[0038] For example, three connectors 219 are arranged in the X direction on the upper portion of the semiconductor device 1 (for example, the upper surfaces of the housing 20 and the cover 30 ). The three connectors 219 are electrically separated from each other.

[0039] One or more semiconductor chips constituting the semiconductor element are provided in a space surrounded by the base substrate 10 , the housing 20 , and the cover 30 .

[0040] The semiconductor device 1 of the present embodiment is a power module and is, for example, an inverter, a converter, a regulator, or a switch.

[0041] Reference Figure 2 and Figure 3 , the internal structure of the semiconductor device 1 of this embodiment is described.

[0042] Figure 2 It is a plan view showing an example of the internal structure of the semiconductor device 1 according to the present embodiment. Figure 3 2 is a cross-sectional view schematically showing an example of the internal structure of the semiconductor device 1 according to the present embodiment. Figure 2 In FIG. 1 , the connector 319 disposed above the base substrate 10 is indicated by a dotted line, a dotted line, a dashed line, or the like.

[0043] like Figure 2 and Figure 3 As shown, the case 20 surrounds the space on the upper surface of the base substrate 10. The case 20 includes a rectangular tube-shaped resin layer 200. For example, an insulator (sealing material) 90 is filled in the space surrounded by the case 20 on the base substrate 10.

[0044] The semiconductor device 1 of the present embodiment includes a plurality of semiconductor chips 110 provided on a circuit substrate 100. The number of semiconductor chips 110 in one semiconductor device 1 is, for example, ten or more.

[0045] For example, four circuit boards 100 are provided on the base substrate 10. Each circuit board 100 is fixed to the base substrate 10 via solder (not shown) or an adhesive (not shown). The circuit board 100 and the semiconductor chip 110 are sealed by an insulator (sealing material) 90.

[0046] The circuit substrate 100 includes two wiring layers 101, 103 and an insulating layer 102. The insulating layer 102 is sandwiched between the two wiring layers 101, 103. The wiring layers 101, 103 include a plurality of wirings 109. The wirings 109 are copper layers (Cu layers). The insulating layer 102 is a ceramic layer. For example, the wiring layer 103 is electrically separated from the wiring layer 101 by the ceramic layer 102. However, the wiring layer 103 on the upper surface side of the insulating layer 102 may also be electrically connected to the wiring layer 101 on the lower surface side of the insulating layer 102 via a through electrode (or plug) not shown in the insulating layer 102.

[0047] For example, two wirings 109 in the circuit substrate 100 are electrically connected to each other via the bonding wire 115. For example, two wirings 109 in adjacent circuit substrates 100 are electrically connected to each other via the bonding wire 115.

[0048] A plurality of semiconductor chips 110 are provided on each circuit substrate 100 . For example, 16 semiconductor chips 110 are provided on one circuit substrate 100 .

[0049] The semiconductor chip 110 includes a plurality of nodes 111. Each node 111 is connected to a node 111 of another semiconductor chip 110 or a corresponding one of the plurality of wirings 109 on the circuit board 100 via a bonding wire 119. The node 111 is, for example, a pad or an electrode.

[0050] For example, the semiconductor chip 110 includes an IGBT-FRD (Insulated gate bipolar transistor-fast recovery diode).

[0051] The circuit substrate 100 and the plurality of semiconductor chips 110 on the circuit substrate 100 form a semiconductor circuit. In the present embodiment, the circuit substrate 100 and the semiconductor chips 110 connected to the circuit substrate 100 are also referred to as a semiconductor circuit.

[0052] A plurality of terminals (bus bars) 210 and 310 are provided in the container of the semiconductor device 1 .

[0053] Each terminal 210, 310 is a plate-shaped conductor. Each terminal 210, 310 includes copper. One end (lower end) of each terminal 210, 310 is electrically connected to the semiconductor chip 110 via the wiring 109 of the circuit substrate 100. The other end (upper end) of each terminal 210, 310 is electrically connected to a corresponding one of the plurality of connectors 219, 319.

[0054] The terminals 310 (310A, 310B, and 310C) are terminals for inputting or outputting voltage or current to and from the semiconductor chip 110. Hereinafter, the terminals 310 are referred to as input / output terminals.

[0055] The input / output terminal 310A is electrically connected to the connector 319A. The input / output terminal 310A is a P-polarity input terminal. The input / output terminal 310B is electrically connected to the connector 319B. The input / output terminal 310B is an N-polarity input terminal. The input / output terminal 310C is electrically connected to the connector 319C. The input / output terminal 310C is an output terminal.

[0056] Each input / output terminal 310 is electrically connected to a corresponding one of the plurality of wirings 109 on the circuit board 100. The ends (upper ends) of the input / output terminals 310 on the cover 30 side are arranged above the ends (upper ends) of the terminals 210 on the cover 30 side in the Z direction.

[0057] The terminal 210 is a terminal for monitoring or controlling the semiconductor device 1. Hereinafter, the terminal 210 is referred to as a signal terminal. Each signal terminal 210 is electrically connected to a corresponding connector 219. The signal terminal 210 is a conductor insert-molded in the housing 20 (resin layer 200). For example, the signal terminal 210 is connected to a wiring 109 connected to a control terminal (e.g., a gate) and / or a current path (e.g., a source / drain, an emitter, or a collector) of a transistor included in the semiconductor device 1.

[0058] The ends (lower ends, front ends) of the signal terminals 210 on the circuit board 100 side are bonded to the wirings 109 of the wiring layer 103 . Thus, the signal terminals 210 are electrically connected to the semiconductor chip 110 via the wirings 109 and the bonding wires 119 .

[0059] In the semiconductor device 1 of the present embodiment, the surface (bottom surface) of the signal terminal 210 that is in contact with the wiring 109 includes a step (recess) 290 .

[0060] Reference Figure 4 and Figure 5 , the structures of the housing 20 and the signal terminals 210 of the semiconductor device 1 according to the present embodiment will be described.

[0061] Figure 4 It is a cross-sectional view schematically showing a basic configuration of the structure of the housing 20 and the signal terminal 210 in the extending direction (first direction) of the signal terminal 210 in the semiconductor device 1 of the present embodiment. Figure 5 2 is a cross-sectional view schematically showing the basic structure of the housing 20 and the signal terminal 210 in the direction (second direction) intersecting the extending direction of the signal terminal 210 in the semiconductor device 1 of the present embodiment. Figure 5 , a cross section of an opening of the resin layer 200 at a portion of the housing 20 where the signal terminal is embedded is shown. Figure 4 as well as Figure 5 , a base substrate 10 and a circuit substrate 100 are schematically shown.

[0062] like Figure 4 and Figure 5 As shown, the housing 20 includes a slit 201 between a portion 214 of the signal terminal 210 and the resin layer 200 in a region near an opening 209 in the resin layer 200 for leading the signal terminal 210 from the resin layer 200 to the interior of the container.

[0063] The slit 201 has a wedge-shaped cross-sectional shape. In addition, the cross-sectional shape of the slit 201 is not limited to a wedge-shaped shape, and may also be a quadrilateral shape. Due to the slit 201, the dimension of the opening 209 in the third direction (Z direction) is larger than the thickness (dimension in the third direction) of the plate-shaped portion of the signal terminal 219 in the resin layer 200.

[0064] The slits 201 in the resin layer 200 increase the movable range of the signal terminal 210 toward the base substrate 10 when pressure toward the base substrate 10 is applied to the signal terminal 210. In addition, the elasticity of the signal terminal 210 in the portion extending from the resin layer 200 is improved.

[0065] The signal terminal 210 extends from the housing 20 toward the circuit substrate 100. The signal terminal 210 includes a plurality of portions 211, 212, 213, and 214. Hereinafter, the portion 214 of the signal terminal 210 inside the resin layer 200 of the housing 20 is referred to as an embedded portion (or buried portion). The portion 212 of the signal terminal 210 that is bonded to the wiring 109 of the circuit substrate 100 is referred to as a bonding portion (or bottom portion). The portion 211 of the signal terminal 210 that extends from the embedded portion 214 to the bonding portion 212 is referred to as a leg portion (or lead portion). The portion 213 of the signal terminal 210 that is connected to the lower end of the leg portion 211 and between the leg portion 211 and the bonding portion 212 is referred to as a heel portion.

[0066] The leg portion 211 , the joint portion 212 , the heel portion 213 , and the embedded portion 214 are a single plate-shaped continuous conductor.

[0067] The embedded portion 214 is covered by the resin layer 200. One end of the embedded portion 214 is connected to the leg portion 211. The other end of the embedded portion 214 is connected to the connector 219. The bottom of the embedded portion 214 does not contact the resin layer 200 due to the formation of the slit 201. For example, in the assembled semiconductor device 1, the insulator 90 is filled in the slit 201 between the bottom of the embedded portion 214 and the resin layer 200.

[0068] Parts 211 , 212 , and 213 of the signal terminal 210 extend from the opening 209 of the resin layer 200 to the space (insulator 90 ) in the container of the semiconductor device 1 . The leg portion 211 , the joint portion 212 , and the heel portion 213 are exposed from the resin layer 200 .

[0069] The heel portion 213 is provided between the leg portion 211 and the joint portion 212. The joint portion 212 is connected to the leg portion 211 via the heel portion 213.

[0070] The joint portion 212 is disposed above the circuit substrate 100 in a direction (third direction) perpendicular to the upper surface of the base substrate 10. For example, the width W2 of the joint portion 212 in the width direction of the terminal 210 is greater than the width W1 of the leg portion 211 in the width direction of the terminal 210.

[0071] In the semiconductor device 1 of the present embodiment, a step 290 is provided between the bonding portion 212 and the heel portion 213 on the base substrate 10 side surfaces of the bonding portion 212 and the heel portion 213 (surfaces in contact with the wiring 109 , bottom surfaces of the signal terminals 210 ).

[0072] Due to the step 290 , the bottom surface of the heel portion 213 (the surface facing the wiring 109 , the surface on the base substrate 10 side) is recessed toward the cover 30 (the upper portion of the semiconductor device 1 ) more than the bottom surface of the bonding portion 212 .

[0073] The signal terminal 210 has elasticity at a portion between the leg portion 211 and the engagement portion 212 due to the step 290 of the heel portion 213 .

[0074] The provision of the step 290 at the bottom (bottom surface) of the signal terminal 210 prevents the bottom of the signal terminal 210 from making one-sided contact with the circuit substrate 100 .

[0075] have Figure 4 and Figure 5 The terminal of the shape can also be used as the terminal 310 for inputting and outputting voltage / current to the semiconductor chip 110.

[0076] In addition, depending on the layout and shape of the signal terminal 210, the joint portion 212 may be led out from the leg portion 211 (and the heel portion 213) in a direction (e.g., the second direction) that intersects the extension direction (e.g., the first direction) of the leg portion 211. In this case, the joint portion 212 is also connected to the leg portion 211 via the heel portion 213 at the lower end of the leg portion 211. There is also a case where the leg portion 211 extends along the second direction.

[0077] <Example of terminal structure>

[0078] Figure 6 1 is a schematic diagram showing a specific example of the shape of the signal terminal 210 in the semiconductor device 1 according to the present embodiment.

[0079] Figure 6 (a) is a cross-sectional view showing an example of a specific structure of the signal terminal 210 in the semiconductor device 1 of the present embodiment before being bonded to the wiring 109 . Figure 6 (b) is a cross-sectional view showing an example of a specific structure of the signal terminal 210 in the semiconductor device 1 of the present embodiment in a state where the signal terminal 210 is bonded to the wiring 109 .

[0080] like Figure 6 As shown in FIG. 2 (a), the signal terminal 210 includes a leg portion 211 , a joint portion 212 and a heel portion 213 .

[0081] The leg portion 211 is a plate-shaped conductor and includes a portion extending in a substantially vertical direction from the housing 20 (embedded portion 214 ) toward the base substrate 10 . The leg portion 211 may be inclined relative to a direction perpendicular to the upper surface of the base substrate 10 .

[0082] The joint portion 212 is a plate-shaped conductor. The joint portion 212 extends in a direction parallel to the upper surface of the base substrate 10. The joint portion 212 is connected to the leg portion 211 via the heel portion 213. The joint portion 212 is a portion of the signal terminal 210 that is joined to the wiring 109. The joint portion 212 corresponds to the front end area of ​​the contact surface of the signal terminal 210 with the wiring 109.

[0083] The dimension (length) of the bonding portion 212 in the direction from the heel portion 213 toward the bonding portion 212 (the length direction of the bonding portion 212) is "L1". The dimension (thickness) of the bonding portion 212 in the direction perpendicular to the surface of the base substrate 10 (the thickness direction of the bonding portion 212) is "t1".

[0084] The heel portion 213 is a plate-shaped conductor. The heel portion 213 is located at the lower end of the leg portion 211. The heel portion 213 connects the joint portion 212 to the leg portion 211. The bottom surface of the heel portion 213 is located closer to the upper side (cover 30 side) of the semiconductor device 1 than the bottom surface of the joint portion 211. The heel portion 213 corresponds to the root area of ​​the contact surface of the signal terminal 210 with the wiring 109. In addition, the heel portion 213 can be regarded as the lower end of the leg portion 211.

[0085] The dimension (length) of the heel portion 213 in the direction from the heel portion 213 toward the joint portion 212 is “L2.” For example, the dimension L2 of the heel portion 213 is smaller than the dimension L1 of the joint portion 212. For example, the dimension L2 is less than or equal to half of the dimension L1.

[0086] The dimension (thickness) of the heel portion 213 in the direction perpendicular to the surface of the base substrate 10 (the thickness direction of the heel portion) is "t2". The dimension t2 of the heel portion 213 is smaller than the dimension t1 of the bonding portion 212. For example, the dimension t2 is a dimension within a range of more than one third of the dimension t1 and less than one half of the dimension t1.

[0087] The step 290 is provided in the region (boundary portion) between the joint portion 212 and the heel portion 213. The size of the step 290 is "D1". The size D1 of the step corresponds to the difference (t1-t2) between the thickness t1 and the thickness t2.

[0088] As a result, in the semiconductor device 1 of the present embodiment, the signal terminal 210 has a structure in which the heel portion 213 of the signal terminal 210 is recessed toward the cover 30 of the semiconductor device 1 relative to the bonding portion 212 .

[0089] For example, the step 290 between the engagement portion 212 and the heel portion 213 is formed by striking the heel portion 213 with a die or grinding a component of the heel portion 213 .

[0090] like Figure 6 As shown in (b), the signal terminal 210 and the wiring 109 are bonded by applying ultrasonic waves and pressure. When the signal terminal 210 and the wiring 109 are respectively formed of copper, the bonding portion 212 and the wiring 109 are bonded by Cu-Cu bonding based on the application of ultrasonic waves and pressure.

[0091] When the signal terminal 210 is bonded to the wiring 109 on the circuit board 100 by Cu-Cu bonding using ultrasonic waves, the bonding portion 212 is integrated with the wiring 109. Due to the high-speed vibration of the applied ultrasonic waves, interatomic bonding occurs between the bonding portion 212 and the wiring 109. Therefore, the bonding portion 212 and the wiring 109 become conductors in which the boundary (interface) B1 between the bonding portion 212 and the wiring 109 is unclear (substantially no boundary exists). However, depending on the difference between the composition ratio of the components of the signal terminal 210 and the composition ratio of the components of the wiring 109, the boundary B1 between the signal terminal 210 and the wiring 109 can sometimes be determined.

[0092] For example, the bottom (bottom surface) of the joint portion 212 sinks into the wiring 109 by the pressure during ultrasonic bonding. According to the sinking of the joint portion 212, the upper surface of the wiring 109 is recessed in the area where the joint portion 212 contacts the wiring 109. In addition, in the area where the joint portion 212 contacts the wiring 109, the position of the upper surface of the wiring 109 is sometimes maintained, and the joint portion 212 is flattened. When the joint portion 212 is flattened, the size of the lower surface (bottom surface, contact surface) side of the joint portion 212 is larger than the width of the upper surface side of the joint portion 212.

[0093] For example, the influence of ultrasound and pressure in the heel 213 is smaller than that in the joint 212. In this case, the heel 213 is not integrated with the wiring 109. The heel 213 is only in contact with the wiring 109. For example, there is a boundary (interface) B2 between the heel 213 and the wiring 109. An insulating layer 295 such as an oxide may be provided between the heel 213 and the wiring 109. However, similarly to the joint 212, there is also a case where the heel 213 and the wiring 109 become an integrated conductor.

[0094] As described above, in the semiconductor device 1 of the present embodiment, the signal terminal 210 having the step 290 on the bonding surface with the wiring 109 can bond the tip portion (bonding portion) 212 of the signal terminal 210 to the wiring 109 of the circuit board 100 .

[0095] (2) Manufacturing method

[0096] Reference Figure 7 and Figure 8 , a method for manufacturing the semiconductor device 1 according to the present embodiment will be described. Figure 7 and Figure 8 It is a cross-sectional process diagram showing one step of the method for manufacturing the semiconductor device 1 according to the present embodiment.

[0097] like Figure 7As shown, in the assembly process of the semiconductor device (power module) 1 , the circuit substrate 100 including a plurality of semiconductor chips 110 is disposed on the base substrate 10 . The housing 20 including the insert-molded signal terminals 210 is disposed on the base substrate 10 .

[0098] In order to connect the signal terminals 210 of the housing 20 to the wirings 109 of the circuit board 100 , the base substrate 10 on which the circuit board 100 and the housing 20 are arranged is mounted in the ultrasonic device 5 .

[0099] The bonding portion 212 of the signal terminal 210 is arranged on the wiring 109 so that the position of the bonding portion 212 matches the position of the corresponding wiring 109 of the circuit board 100 .

[0100] At this time, as in the present embodiment, the heel portion 213 of the signal terminal 210 is recessed, thereby suppressing the occurrence of one-sided contact of the heel portion 213 of the signal terminal 210 .

[0101] Thus, in the present embodiment, the bottom surface of the bonding portion 212 of the signal terminal 210 is in contact with the wiring 109 in a substantially parallel manner.

[0102] In the ultrasonic device 5, an ultrasonic capillary 51 connected to an ultrasonic horn 50 abuts against the signal terminal 210. The ultrasonic horn 50 generates ultrasonic waves of a certain amplitude and frequency. The ultrasonic capillary 51 supplies ultrasonic waves from the ultrasonic horn 50 to the signal terminal 210 and applies pressure to the signal terminal 210.

[0103] like Figure 8 As shown, the ultrasonic capillary 51 is pressed against the bonding portion 212 of the signal terminal 210 to supply ultrasonic waves to the signal terminal 210. The bonding portion 212 of the signal terminal 210 is bonded to the wiring 109 by the vibration of the ultrasonic waves and the pressurization of the ultrasonic capillary 51.

[0104] When the ultrasonic capillary 51 is pressed against the signal terminal 210 , the signal terminal 210 moves downward toward the base substrate 10 .

[0105] In the present embodiment, the wedge-shaped slit 201 is provided between the resin layer 200 and the bottom (bottom surface) of the embedding portion 214 of the signal terminal 210 in the opening portion 209 on the signal terminal 210 side of the housing 20. As a result, the movable range of the signal terminal 210 is expanded, and the elasticity of the signal terminal 210 is improved. As a result, in the present embodiment, the deflection of the signal terminal 210 toward the base substrate side is larger than when the slit 201 is not provided.

[0106] Therefore, when the signal terminal 210 is pressed toward the base substrate 10 by the ultrasonic capillary 51, the signal terminal 210 insert-molded in the housing 20 is sufficiently pressed against the wiring 109. As a result, in this embodiment, the bonding portion 212 of the signal terminal 210 can be reliably bonded to the wiring 109.

[0107] Therefore, in the present embodiment, the occurrence of poor bonding between the signal terminal 210 and the wiring 109 due to the one-sided contact of the bottom of the signal terminal 210 with the circuit board 100 is suppressed.

[0108] When the signal terminal 210 is bent toward the base substrate 10 due to the pressure of the ultrasonic capillary 51, a gap 99 may be generated between the upper portion of the embedded portion 214 and the resin layer 200. The gap 99 may remain in the semiconductor device 1 even after the manufacturing process of the semiconductor device 1 is completed.

[0109] like Figure 6 As shown in (b) , the bonding portion 212 of the signal terminal 210 and the wiring 109 are integrated by Cu-Cu bonding based on application of ultrasonic waves and pressure.

[0110] After each signal terminal 210 is bonded to the corresponding wiring 109, a plurality of input / output terminals 310 are arranged on the housing 20. The input / output terminals 310 are bonded to the corresponding wiring 109 on the circuit board 100, for example, by ultrasonic bonding. After the input / output terminals 310 are bonded to the wiring 109, the cover 30 is connected to the housing 20. The insulator 90 is filled in the housing 20.

[0111] Through the above steps, the semiconductor device 1 of the present embodiment is completed.

[0112] (3) Modification

[0113] Fig. 9 It is a cross-sectional view showing a modification of the semiconductor device according to the present embodiment.

[0114] like Fig. 9 As shown, the gap 299 may be provided between the heel 213 of the signal terminal 210 and the wiring 109 of the circuit substrate 100. For example, after the semiconductor device 1 is assembled, the insulator 90 is filled into the gap 299. The insulator 90 is provided between the heel 213 and the wiring 109.

[0115] In this case as well, the semiconductor device 1 according to the modified example can suppress the bonding failure between the signal terminal 210 and the wiring 109 .

[0116] (4) Summary

[0117] In a semiconductor device such as a power module, terminals insert-molded in a case are joined to wirings of a circuit board on a base substrate.

[0118] When the housing is bonded to the base substrate, if the signal terminal (or housing) is deformed by an external force, the junction between the signal terminal and the wiring may float above the wiring. When the junction floats above the wiring, the bottom of the signal terminal with a flat contact surface may contact one side of the wiring.

[0119] When ultrasonic bonding of the signal terminal and the wiring is performed in a state where the bottom of the signal terminal is in contact with one side of the wiring, bonding failure between the signal terminal and the wiring may occur due to a small contact area between the bottom of the signal terminal and the wiring.

[0120] In the semiconductor device 1 of the present embodiment, the heel portion 213 of the bottom of the signal terminal 210 is recessed. Due to the recess of the heel portion 213, a step 290 is provided between the heel portion 213 on the bottom surface of the signal terminal 210 and the bonding portion 212 bonded to the wiring 109.

[0121] By means of the step 290, in the semiconductor device 1 of the present embodiment, a space for avoiding one-sided contact of the signal terminal 210 can be provided between the wiring 109 and the heel portion 213 of the signal terminal 210. Therefore, in the present embodiment, it is difficult for the lower end (heel portion 213) of the leg portion 211 of the signal terminal 210 to contact the wiring 109 before the joint portion 212 of the signal terminal 210.

[0122] Therefore, the semiconductor device 1 of the present embodiment can suppress the occurrence of one-sided contact at the heel portion 213 (the lower end of the leg portion 211 ) of the signal terminal 210 .

[0123] The signal terminal of the housing that is close to the resin layer has relatively high rigidity. When the signal terminal has high rigidity, the signal terminal is not easily bent.

[0124] In the semiconductor device 1 of the present embodiment, the wedge-shaped slit 201 is provided in the region between the bottom of the embedded portion 214 in the resin layer 200 and the resin layer 200 in the signal terminal 210. As a result, the spring characteristics of the signal terminal 210 near the opening 209 of the resin layer 200 (near the boundary between the leg portion 211 and the embedded portion 214) are improved. In addition, by disposing the slit 201, the movable range of the signal terminal 210 toward the base substrate 10 side is expanded. Therefore, in the present embodiment, during the ultrasonic bonding process, the signal terminal 210 can be greatly bent toward the base substrate side.

[0125] As a result, the semiconductor device 1 of the present embodiment can make the contact surface of the signal terminal 210 with respect to the wiring 109 (for example, the bottom surface of the bonding portion 212) contact the wiring 109 in parallel. Therefore, the semiconductor device 1 of the present embodiment can perform ultrasonic bonding between the signal terminal 210 and the wiring 109 while ensuring a large contact surface between the signal terminal 210 and the wiring 109.

[0126] Therefore, the semiconductor device 1 of the present embodiment can suppress bonding defects between the signal terminal 210 and the wiring 109 .

[0127] In this embodiment, when the signal terminal expands due to heat, the slit 201 can reduce the stress generated between the resin layer 200 and the signal terminal 210. Thus, the semiconductor device 1 of this embodiment can suppress deformation and degradation of the shape of the signal terminal due to stress.

[0128] As described above, the semiconductor device of the present embodiment can suppress defects in the semiconductor device, and accordingly, the semiconductor device of the present embodiment can improve the manufacturing yield of the semiconductor device.

[0129] (5) Others

[0130] The semiconductor device of this embodiment can be any device in which a terminal insert-molded in a housing is joined to a conductor on a substrate by ultrasonic bonding, and is not limited to a power module. In addition, the device of this embodiment can be any device in which a terminal insert-molded in a housing is joined to a conductor on a substrate by ultrasonic bonding, and is not limited to a semiconductor device.

[0131] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: substrate; a housing, disposed on the substrate, comprising a resin layer and terminals; and a circuit substrate, disposed on the substrate, comprising a semiconductor chip and wiring electrically connected to the semiconductor chip and the terminals, The terminal includes a first portion extending from the resin layer toward the circuit substrate, a second portion bonded to the wiring, and a third portion between the first portion and the second portion. The third portion is recessed toward the side opposite to the substrate side relative to the second portion.

2. The semiconductor device according to claim 1, wherein: The terminal includes a step between the second portion and the third portion.

3. The semiconductor device according to claim 1, wherein: The terminal further includes a fourth portion disposed in the resin layer, The housing further includes a slit disposed between the fourth portion and the resin layer.

4. The semiconductor device according to claim 3, wherein: further comprising an insulator covering the circuit substrate, The insulator is disposed in the slit.

5. The semiconductor device according to claim 1, wherein: A size of the third portion in a first direction perpendicular to an upper surface of the substrate is smaller than a size of the second portion in the first direction.

6. The semiconductor device according to claim 1, wherein: A size of the second portion in a second direction parallel to an upper surface of the substrate is greater than a size of the third portion in the second direction.

7. The semiconductor device according to claim 1, wherein: A size of the second portion in a third direction parallel to an upper surface of the substrate is larger than a size of the first portion in the third direction.

8. The semiconductor device according to claim 1, wherein: The second portion is continuous with the wiring.

9. The semiconductor device according to claim 1, wherein: The third portion is in contact with the wiring and is not continuous with the wiring.

10. The semiconductor device according to claim 1, wherein: further comprising an insulator covering the circuit substrate, The insulator is provided between the third portion and the wiring.

11. The semiconductor device according to claim 1, wherein: The terminal is a conductor that is insert-molded in the resin layer.

12. A semiconductor device, characterized in that: have: substrate; A housing, disposed on the substrate, comprising a resin layer, a terminal, and a slit between a portion of the terminal disposed in the resin layer and the resin layer; as well as The circuit board is provided on the substrate and includes a semiconductor chip and wiring electrically connected to the semiconductor chip and the terminals.

13. The semiconductor device according to claim 12, wherein: The terminal is a conductor that is insert-molded in the resin layer.

Images